NEL MD-01-4-43-75-482 May 8, 2002 Preliminary MC740-430E 47-Gb/s 4:1 Multiplexer The MC740-430E is an engineering sample of 47-Gb/s signal generator. It consists of a 4:1 multiplexer (MUX), D-type flipflop (D-FF), and clock distribution unit based on 0.1-µm InP-HEMT devices. Four-parallel data inputs are multiplexed to 47-Gb/s data by using 47- and 11.75-GHz clock signals. At the output stage, the D-FF regenerates the muliplexed data with the 47-GHz clock signal and offers symmetrical eye openings. The MC740-430E has SCFL (Source Coupled FET Logic) I/O and can be directly connected to a pulse pattern generator. FEATURES Operating range: 38 to 47 Gb/s (min.) (note) Signal regeneration with full-rate clock signal Large output amplitude: SCFL I/O (VOHD = 0V, VOLD = -0.9V, typ.) Single power supply voltage: DC -6 V (note) 50-Gb/s operation is optional. APPLICATIONS Parallel-to-serial converters, Test equipments FUNCTION DIAGRAM 20Gb/s (mon.) 2 DATA 3, 2, 1, 0 4 40Gb/s (mon.) 10-dB ATT Latching stage 75 Ω 50 Ω 4:1 MUX CLK10 50 Ω DATA D-FF 75 Ω DATA 75 Ω φshifter 50 Ω CLK10 2 CLK40 CLK40 Clock Distributor 65 Ω Fig. 1. Function diagram. -1- 50 Ω NEL MC740-430E TIMING CHARTS (1) Data and Clock Input Signals DATA3 D30 D31 DATA2 D20 D21 DATA1 D10 D11 DATA0 D00 D01 CLK10 (2) Multiplexed 20 Gb/s Data Output Signals (Monitor) 20 Gb/s Odd ch. D30 D10 D31 D11 20 Gb/s Even ch. D20 D00 D21 D01 (3) Multiplexed 40 Gb/s Data Output Signals 40 Gb/s (4:1 MUX output) D30 D20 D10 D00 D3 1 D2 1 D11 D0 1 DATA D30 D20 D10 D00 D31 D21 D1 1 D01 DATA D30 D20 D10 D00 D31 D21 D1 1 D01 Fig. 2. Timing charts. -2- NEL MC740-430E CONNECTION TABLE TERMINAL FUNCTION 20G Monitor K(f) (2) 1 Front Switch Front Switch - 13 2 φshifter Clock Phase Shifter for D-FF - 14 3 DATA Data Output V(f) (1) 15 CLK10 1/4 Clock Output SMA(f) 4 /DATA Data Output (complement) V(f) (1) 16 40Gb/s 40G Monitor (4:1 MUX Output) V(f) (1) 5 CLK10 SMA(f) 17 PWR Power Supply (-6.0 V) - 18 GND Ground (0.0 V) - 19 Main Switch Main Switch - (1) 6 CLK40 Clock Output 7 CLK10 1/4 Clock Input SMA(f) 8 CLK40 Clock Input V(f) (1) 9 DATA3 Data Input 3 SMA(f) 10 DATA1 Data Input 1 SMA(f) 11 DATA2 Data Input 2 SMA(f) 12 DATA0 Data Input 0 SMA(f) notes) V(f) NAME TERMINAL NAME 1/4 Clock Output No. FUNCTION No. 20Gb/s Even 20Gb/s Odd (Even ch., DATA2 and 0) 20G Monitor (Odd ch., DATA3 and 1) (1) V: Anritsu panel adaptor V232 (2) K: Anritsu panel adaptor K232B CONNECTION DIAGRAM FRONT PANEL 2 1 3 5 7 9 11 4 6 8 10 12 REAR PANEL MONITOR 13 15 14 19 17 20Gb/s Odd -6V DC CLK10 Even 16 18 OFF GND Fig. 3. Front and rear panels. Case dimension (without connectors) height: 95 mm width: 370 mm depth: 235 mm -3- ON 40Gb/s K(f) (2) NEL MC740-430E ABSOLUTE MAXIMUM RATINGS GENERAL SYMBOL VPWR Tstor PARAMETER Ratings Power Supply Voltage Storage Temperature TBD TBD DATA and CLOCK INPUT SIGNALS PARAMETER SYMBOL Applied Voltage at DATA3 to 0 DATA3 to 0 Applied Voltage at CLK40 VICLK40 Applied Voltage at CLK10 VICLK10 DATA and CLOCK OUTPUT SIGNALS PARAMETER SYMBOL Applied Voltage at DATA, /DATA VDATA, /DATA Applied Voltage at CLK40 VOC40 Applied Voltage at CLK10 VOC10 MONITOR OUTPUT SIGNALS PARAMETER SYMBOL 40-Gb/s Monitor Output Interface 40Gb/s 20-Gb/s Monitor Output Interface 20Gb/s (odd, even) 10-GHz Clock Output Interface CLK10 -4- Ratings -1.9 to 0 V -1.6 to +1.6 V (DC), 1.6 Vpp (AC) -1.6 to +1.6 V (DC), 1.6 Vpp (AC) Ratings TBD -1.2 to 1.2 V (DC), No RF Input -1.75 to +0.2 V Conditions TBD -1.75 to +0.2 V -1.75 to +0.2 V NEL MC740-430E RECOMMENDED OPERATING CONDITIONS GENERAL SYMBOL (note1) VPWR Ta (note2) PARAMETER MIN. TYP. MAX. UNITS 30 V ℃ -6.0 Power Supply Voltage Operating Temperature 20 - (note1) NEL recommends a DC power supply with an output current capacity of 10 A and an output voltage ripple less than 10 mV rms. (note2) The MC740-430E should be protected from condensation. DATA and CLOCK INPUT SIGNALS PARAMETER SYMBOL Data Input Interface DATA3 to 0 CLK40 CLK10 Conditions 40-GHz Clock Input Interface (with an internal DC blocking capacitor) 10-GHz Clock Input Interface DATA and CLOCK OUTPUT SIGNALS PARAMETER SYMBOL Data Output Interface DATA, /DATA 40-GHz Clock Output Interface CLK40 (with an internal DC blocking capacitor) CLK10 10-GHz Clock Output Interface MONITOR OUTPUT SIGNALS PARAMETER SYMBOL 40-Gb/s Monitor Output Interface 40Gb/s (with an internal 10-dB attenuator) 20 Gb/s (odd, even) CLK10 20-Gb/s Monitor Output Interface 10-GHz Clock Output Interface -5- DC coupling (see DC and AC characteristics) AC coupling (see AC characteristics) AC or DC coupling (see AC characteristics) Conditions DC coupling, Terminate with 50 Ω to GND AC coupling, Terminate with 50 Ω AC or DC coupling, Terminate with 50 Ω Conditions DC coupling, Terminate with 50 Ω to GND DC coupling, Terminate with 50 Ω to GND AC or DC coupling, Terminate with 50 Ω NEL MC740-430E DC CHARACTERISTICS (VPWR = -6.0 V, GND = 0.0V, Ta = 25℃) SYMBOL PARAMETER MIN. TYP. VIH Data Input Voltage, High (DATA3 to 0) -0.2 0.0 VIL Data Input Voltage, Low (DATA3 to 0) VOHD Data Output Voltage, High (DATA, /DATA) VOLD Data Output Voltage, Low (DATA, /DATA) -0.9 TBD V IPWR Power Supply Current 7.0 TBD A Pd Power Dissipation 42 TBD W TYP. MAX. UNITS 38 GHz -0.9 TBD MAX. UNITS V -0.8 0.0 V V AC CHARACTERISTICS (VPWR = -6.0 V, GND = 0.0V, Ta = 25℃) DATA and CLOCK INPUT SIGNALS SYMBOL PARAMETER MIN. fMIN Minimum Clock Frequency for CLK40 fMAX Maximum Clock Frequency for CLK40 Maximum Skew Among Four Data and CLK10 Inputs CI40 Clock Input Amplitude for CLK40 CI10 Clock Input Amplitude for CLK10 47 (note) 10 (TBD) 0.6 (TBD) 0.7 Vcenter Center Voltage of CLK40 and 10 -0.5 0.0 0.5 MIN. TYP. MAX. TBD 0.9 Skew GHz pspp 0.9 0.9 1.2 Vpp Vpp V (note) 50-Gb/s operation is optional. DATA and CLOCK OUTPUT SIGNALS SYMBOL PARAMETER UNITS VampD Output Voltage Amplitude (DATA, /DATA) tr Output Rise Time (DATA, /DATA) 10 TBD ps tf Output Fall Time (DATA, /DATA) 10 TBD ps CO40 Output Voltage Amplitude of CLK40 CO10 Output Voltage Amplitude of CLK10 VOHC10 Output Voltage, High (CLK10) VOLC10 Output Voltage, Low (CLK10) -6- 0.5 (TBD) 0.5 (TBD) TBD Vpp 0.7 Vpp 0.7 Vpp -0.2 V -0.9 TBD V NEL MC740-430E MONITOR OUTPUT SIGNALS SYMBOL PARAMETER Output Voltage Amplitude of 4:1 MUX VampM40 (with an internal 10-dB attenuator) Output Voltage Amplitude of 20 Gb/s Data, VampM20 (Odd, Even) CM10 Output Voltage Amplitude of CLK10 VOHM10 Output Voltage, High (CLK10) VOLM10 Output Voltage, Low (CLK10) -7- MIN. TYP. - 0.3 Vpp - 0.9 Vpp 0.7 Vpp -0.2 V 0.5 (TBD) TBD -0.9 MAX. TBD UNITS V NEL MC740-430E DEFINITIONS of SYMBOLS (1) Data and Clock Input Signals CI40 Vcenter 50% CLK40 DIH DATA3 to 1 DIL 50% CLK10 CI10 Vcenter Skew (2) Data and Clock Output Signals DATA, .DATA 80% VampD 80% 20% 20% tr VOHD VOLD tf CO40 CLK40 CO10 CLK10 VOHC10 VOLC10 (3) Monitor Output Signals VampM40 40Gb/s VampM20 20Gb/s odd, even CM10 CLK10 VOHM10 VOLM10 Fig. 4. Definitions of symbols. -8- NEL MC740-430E EXAMPLE WAVEFORMS (47-Gb/s OUTPUT) INPUT SIGNALS DATA3 DATA2 DATA1 DATA0 CLK10 CLK40 1 V/div, 20 ps/div OUTPUT SIGNALS DATA DATA CLK40 300 mV/div, 5 ps/div Fig. 5. Example input and output waveforms (47-Gb/s operation). Measurement conditions Ta = 25℃, VPWR = -6.0 V DATA3 to 0: 11.75-Gb/s (223-1) pseudo-random binary sequence Sampling Oscilloscope: Agilent digital communication analyzer (86100A) and plug-in module (83484A) Cable: SUHNER SUCOFLEX102 (30 cm) -9- NEL MC740-430E OPERATION CAUTION The MC740-430E is very sensitive to electrostatic discharge (ESD). ESD preventive measures must be employed at customer’s working desk. Before operating the MC740-430E, please read the handling precautions on page 14. Before connecting any cables to the input and output terminals, short the center and outer conductors of the cable together. Mechanical shock can damage or destroy the MC740-430E. Please handle carefully. Do not remove the warranty seals and/or open the cover. Turn-on procedure Connect a DC power supply, signal sources (a pulse pattern generator, PPG, and a synthesizer), an oscilloscope, and a device under test (see the sample implementation, Fig. 9). Here, outputs from the equipments should be turned-off. If customer connects an AC coupled circuit to the DATA and/or /DATA output terminals, terminate the terminals with 50-ohm resistors via a bias-tee (see Fig. 9). Output terminals unused should be terminated with 50-ohm resistors. Power supply sequence is shown in table 1. Table 1 Turn-on sequence Step 1 Step 2 Step 3 Step 4 Turn-On Procedure Procedure Make sure the output voltage of the DC supply has been set to be - (minus) 6 V. The DC -6 V on. Main switch (rear panel) on. A current of 1 A is observed at the DC supply. Wait until the current becomes (approximately 10 sec). Front switch on. A current of 7 A is observed at the DC supply. Wait until the current becomes (approximately 10 sec). RF input on. power power stable power stable Delay adjustment To operate the MC740-430E normally, the following delay adjustments are needed (refer to the function diagram, Fig. 1, and sample implementation, Fig. 9). (1) CLK10 output: Adjust the timing between the input data (after latching) and the internal clock at the 4:1 MUX. (2) Clock delay for the DFF (“φshifter” on front panel): Adjust the timing between the output signal from the 4:1 MUX and the clock signal for the DFF. - 10 - NEL MC740-430E Step 1 CLK10 output Insert a phase shifter between CLK10 output terminal and the PPG. Phase shift range of the phase shifter should be 100 pspp. Observe the 20 Gb/s monitor outputs by using the oscilloscope. If the CLK10 delay is not optimum, the monitor outputs will be similar to Fig. 6(a). Adjust the CLK10 delay until the monitor output becomes clear (see Fig. 6(b)). When the 20G monitor outputs become clear, the 40G monitor output automatically becomes clear. 20Gb/s odd 500 mV/div 20Gb/s even 500 mV/div 40Gb/s 150 mV/div 20 psV/div (a) with an unsuitable delay 20Gb/s odd 500 mV/div 20Gb/s even 500 mV/div 40Gb/s 150 mV/div Fig. 6. 20 psV/div (b) after delay adjustment 20G and 40G monitor output waveforms. Informally, similar adjustment could be done by shifting the delay of CLK10 input (clock delay time from PPG). The output timing from the latching stage, or input data timing for the 4:1 MUX, can be controlled by CLK10 input as shown in Fig. 7. However, this method cannot be applicable for all situations because the clock phase margin of the latching stage is smaller than 360 degree. latched data DATA 3, 2, 1, 0 4 CLK10 input Latching stage 4 4:1 MUX internal clock Fig. 7. Delay adjustment by CLK10 input. - 11 - NEL MC740-430E Step 2 Clock delay for DFF If the CLK10 delay is not optimum, the monitor output will be similar to Fig. 8(a). Adjust the clock delay for DFF by using “φshifter” dial with monitoring the DFF output signals. /DATA 300 mV/div DATA 300 mV/div 10 ps/div (a) with an unsuitable delay /DATA 300 mV/div DATA 300 mV/div 10 ps/div (b) after delay adjustment at ”φshifter” Fig. 8. DFF output waveforms. Turn-off procedure Turn-off sequence is shown in Table. 2. Table 2 Turn-off sequence Step 1 Turn-off sequence Procedure RF inputs off. Step 2 Step 3 Step 4 Front switch off. Main switch (rear panel) off. DC -6 V off. - 12 - NEL MC740-430E SAMPLE IMPLEMENTATION 2 φShifter CI40 = 0.9 Vpp Vcenter = 0 V MC740-430E 70 Ω 50 Ω 8 CLK40 (input) Zo = 50 Ω 50 Ω DATA, DATA 50 Ω synthesizer CLK40 (output) PPG V IH = 0.0 V V IH = -0.9 V CI10 = 0.9 Vpp Vcenter = 0 V 7 70 Ω 50 Ω 40Gb/s (mon.) CLK10 (input) Zo = 50 Ω 5 75 Ω 65 Ω 20Gb/s (mon.) CLK10 (output) Zo = 50 Ω 10-dB ATT 50 Ω 2 Zo = 50 Ω 6 50 Ω Zo = 50 Ω 15 50 Ω CLK10 (monitor) DATA3 to 0 Zo = 50 Ω 50 Ω 65 Ω 50 Ω 9, 10, 11, 12 3, 4 Zo = 50 Ω 16 50 Ω 13, 14 2 50 Ω STAND BY 18 phase shifter for CLK10 output 17 1 PWR Fig. 9. Notes: 19 Sample implementation. Each number corresponds to a connector or a dial shown in the connection diagram on page 3. Power supply sequence is shown on pages 10 -12. - 13 - NEL MC740-430E HANDLING PRECAUTIONS BEFORE OPERATING THE INP HEMT/GaAs MESFET/Si-Bipolar IC MODULES, PLEASE READ THIS HANDLING INSTRUCTION TO PREVENT DAMAGE FROM ELECTRIC SURGES SUCH AS POWER LINE LEAK AND ELECTROSTATIC DISCHARGE. 1. Determine the standard GND on the working desk. The Standard GND should be connected to the highest quality GND in the room. Connect commonly all of GND terminals of all the equipment to the standard GND on the working desk. The working desk should be conductive and should be connected to the standard GND. Connection cables are preferred to be as short as possible and as thick as possible. 2. Put on a conductive wrist–strap connected to the standard GND on the desk through a 1-Mohm resistor. 3. Confirm that the voltages of all surrounding materials including human body which touch the modules are less than 0.2 V. Please measure these voltages using an oscilloscope (Do not use DC and AC voltmeters). 4. Make sure that there is no abnormal spike on the power supply voltage. 5. Ground all soldering iron tips. Leak voltage should be less than 0.2 V. - 14 - Caution 1. In order to improve products and technology, specifications are subject to change without notice. 2. When using the products, be sure the latest information and specifications are used. 3. Circuit drawings etc. shall be provided for the purpose of information only on application examples not for actual installation of equipment. NTT Electronics Corp. shall not assume any liability for damage that may result from the use of these circuit drawings etc. NTT Electronics Corp. shall not assent to or guarantee any rights of execution for patent rights of the third parties and other rights that may be raised for use of these circuit drawings. 4. To make a design, the products shall be used within the assured ranges with respect to maximum ratings, voltage, and radiation. NTT Electronics Corp. shall not take any responsibility for damage caused by neglecting the assured values or improper usage. 5. Though NTT Electronics Corp. makes every effort to improve quality and reliability, there is a risk that failure or malfunction may occur in semiconductors. It is therefore necessary that the purchasers should take responsibility for making a design that allows the products to operate safely on equipment and systems without any direct threat to the human body and/or property, should such failures or malfunction occur. 6. NTT Electronics Corp.'s semiconductor device products are designed to be used with multimedia networks communication equipment and related measuring equipment. They have not been developed for such equipment that may affect people's lives. Those who intend to use the products for special purposes that may affect human life as a result of failure or malfunction in the equipment using the products or that require extremely high reliability (e.g. life support, aircraft and space rockets, control in nuclear power facilities, submarine relays, control of operations, etc.) shall contact NTT Electronics Corp. before using the products. NTT Electronics Corp. shall not assume any liability for damage that may occur during operation of the products without prior consultation. 7. This products is controlled under the 'Foreign Exchange and Foreign Trade Law'. In the case of exporting this product, it is requested that you take necessary procedures to obtain prior approval from the Japanese Minister of Economy, Trade and Industry. 8. Some of the products use GaAs (gallium arsenide). GaAs powder and vapor are dangerous for humans. Do not break, cut, crush or chemically destroy the products. To dispose of the products, follow the relevant regulations and laws; do not mix with general industrial waste and domestic garbage. 9. Any questions should be directed to the Sales Department of NTT Electronics Corp. Copyright 2002 NTT Electronics Corp. NTT Electronics Corporation reserves the right to make change in designs, specifications and other information at any time without prior notice. These products or technologies are subject to Japanese strategic restrictions. - 15 -