MC74ACT564 Octal D−Type Flip−Flop with 3−State Outputs The MC74ACT564 is a high−speed, low power octal flip−flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs is stored in the flip−flops on the LOW−to−HIGH Clock (CP) transition. The MC74ACT564 device is functionally indentical to the MC74ACT574, but with inverted outputs. http://onsemi.com Features PDIP−20 N SUFFIX CASE 738 • Inputs and Outputs on the Opposite Sides of the Package Allowing • • • • • • Easy Interface with Microprocessors Useful as Input or Output Port for Microprocessor Functionally Indentical to the MC74ACT574 but with Inverted Outputs 3−State Outputs for Bus−Oriented Applications Outputs Source/Sink 24 mA TTL Compatible Inputs Pb−Free Packages are Available* 1 SOIC−20W DW SUFFIX CASE 751D 1 VCC O0 O1 O2 O3 O4 O5 O6 O7 CP 20 19 18 17 16 15 14 13 12 11 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. DEVICE MARKING INFORMATION 1 2 3 4 5 6 7 8 9 10 OE D0 D1 D2 D3 D4 D5 D6 D7 GND See general marking information in the device marking section on page 5 of this data sheet. Figure 1. Pinout: 20−Lead Packages Conductors (Top View) D0 D1 D2 D3 D4 D5 D6 D7 CP PIN ASSIGNMENT PIN FUNCTION D0−D7 Data Inputs CP Clock Pulse Input OE 3−State Output Enable Input O0−O7 3−State Outputs OE O0 O1 O2 O3 O4 O5 O6 O7 Figure 2. Logic Symbol *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 December, 2006 − Rev. 3 1 Publication Order Number: MC74ACT564/D MC74ACT564 D0 D1 D2 D3 D4 D5 D6 D7 CP C D C C D D C D C D C D C D C Q Q Q Q Q Q Q Q O0 O1 O2 O3 O4 O5 O6 O7 D OE Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 3. Logic Diagram FUNCTION TABLE Inputs Internal Outputs Function OE CP D Q O H H L NC Z Hold H H H NC Z Hold H L H Z Load H H L Z Load L L H H Data Available L H L L Data Available L H L NC NC No Change in Data L H H NC NC No Change in Data H L X Z = = = = = NC = HIGH Voltage Level LOW Voltage Level Immaterial High Impedance LOW−to−HIGH Transition No Change FUNCTIONAL DESCRIPTION meet the setup and hold times requirements on the LOW−to−HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip−flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip−flops. The MC74ACT564 consists of eight edge−triggered flip−flops with individual D−type inputs and 3−state complementary outputs. The buffered clock and buffered Output Enable are common to all flip−flops. The eight flip−flops will store the state of their individual D inputs that http://onsemi.com 2 MC74ACT564 MAXIMUM RATINGS Symbol VCC Parameter Value Unit *0.5 to )7.0 V *0.5 v VI v VCC )0.5 V *0.5 v VO v VCC )0.5 V DC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current $20 mA IOK DC Output Diode Current $50 mA (Note 1) IO DC Output Sink/Source Current $50 mA ICC DC Supply Current per Output Pin $50 mA IGND DC Ground Current per Output Pin $50 mA TSTG Storage Temperature Range *65 to )150 _C 260 _C )150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds TJ Junction Temperature under Bias qJA Thermal Resistance PDIP SOIC 67 96 _C/W PD Power Dissipation in Still Air at 85_C PDIP SOIC 750 500 mW MSL Moisture Sensitivity FR Flammability Rating VESD ILatchup Level 1 Oxygen Index: 30% − 35% UL 94−V0 @ 0.125 in ESD Withstand Voltage Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) > 2000 > 200 > 1000 V Latchup Performance $100 mA Above VCC and Below GND at 85_C (Note 5) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. IO absolute maximum rating must be observed. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter Min DC Input Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Typ Max Unit 4.5 5.5 V 0 VCC V −40 25 +85 °C 0 0 10 8.0 10 8.0 ns/V Junction Temperature (PDIP) 140 °C IOH Output Current − High −24 mA IOL Output Current − Low 24 mA TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Note 7) TJ VCC = 4.5 V VCC = 5.5 V 6. Unused Inputs may not be left open. All inputs must be tied to a high voltage level or low logic voltage level. 7. Vin from 0.8 V to 2.0 V; refer to individual Data Sheets for devices that differ from the typical input rise and fall times. http://onsemi.com 3 MC74ACT564 DC CHARACTERISTICS Symbol Parameter TA = +255C VCC (V) Typ TA = −405C to +855C Guaranteed Limits Unit Conditions VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 V V VOUT = 0.1 V or VCC − 0.1 V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 V V VOUT = 0.1 V or VCC − 0.1 V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 V V IOUT = −50 mA 3.86 4.86 3.76 4.76 V V *VIN = VIL or VIH IOH 0.1 0.1 0.1 0.1 V V IOUT = 50 mA 4.5 5.5 0.36 0.36 0.44 0.44 V V *VIN = VIL or VIH IOL Maximum Input Leakage Current 5.5 ±0.1 ±1.0 mA VI = VCC, GND Additional Max. ICC/Input 5.5 1.5 mA VI = VCC − 2.1 V Maximum 3−State Current 5.5 ±5.0 mA VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND IOLD IOHD †Minimum Dynamic Output Current 5.5 5.5 75 −75 mA mA VOLD = 1.65 V Max VOHD = 3.85 V Min ICC Maximum Quiescent Supply Current 5.5 80 mA VIN = VCC or GND 4.5 5.5 VOL IIN DICCT IOZ Maximum Low Level Output Voltage 4.5 5.5 0.001 0.001 0.6 ±0.5 8.0 −24 mA −24 mA 24 mA 24 mA *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. AC CHARACTERISTICS tr = tf = 3.0 ns (For Figures and Waveforms, See Figures 4, 5, and 6.) Symbol VCC* (V) Parameter TA = +25°C CL = 50 pF Min Typ TA = −40°C to +85°C CL = 50 pF Max Min Unit Max fmax Maximum Clock Frequency 5.0 85 − − 75 − MHz tPLH Propagation Delay CP to Qn 5.0 2.0 − 10.5 1.5 11.5 ns tPHL Propagation Delay CP to Qn 5.0 1.5 − 9.5 1.5 10.5 ns tPZH Output Enable Time 5.0 1.5 − 9.0 1.5 9.5 ns tPZL Output Enable Time 5.0 1.5 − 8.5 1.0 9.5 ns tPHZ Output Disable Time 5.0 1.5 − 10.5 1.5 11.5 ns tPLZ Output Disable Time 5.0 1.5 − 8.0 1.0 8.5 ns *Voltage Range 5.0 V is 5.0 V ±0.5 V http://onsemi.com 4 MC74ACT564 AC OPERATING REQUIREMENTS Symbol TA = +25°C CL = 50 pF VCC* (V) Parameter Typ TA = −40°C to +85°C CL = 50 pF Unit Guaranteed Minimum ts Setup Time, HIGH or LOW Dn to CP 5.0 − 2.5 3.0 ns th Hold Time, HIGH or LOW Dn to CP 5.0 − 1.0 1.0 ns tw CP Pulse Width HIGH or LOW 5.0 − 3.0 3.5 ns *Voltage Range 3.3 V is 3.3 V ±0.3 V. *Voltage Range 5.0 V is 5.0 V ±0.5 V. CAPACITANCE Symbol Parameter Value Typ Unit Test Conditions CIN Input Capacitance 4.5 pF VCC = 5.0 V CPD Power Dissipation Capacitance 50 pF VCC = 5.0 V ORDERING INFORMATION Device Shipping † Package MC74ACT564N PDIP−20 MC74ACT564NG PDIP−20 (Pb−Free) MC74ACT564DWR2 SOIC−20 MC74ACT564DWR2G SOIC−20 (Pb−Free) 18 Units / Rail 1000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MARKING DIAGRAMS PDIP−20 SOIC−20W 20 20 ACT564 AWLYYWWG MC74ACT564N AWLYYWWG 1 1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package http://onsemi.com 5 MC74ACT564 SWITCHING WAVEFORMS tr tf 3.0 V CP 3.0 V 50% OE GND tw 50% ts 1/fmax tPLH Q th 3.0 V tPHL CP 50% GND 50% Figure 4. Figure 5. VALID 3.0 V DATA 50% GND tsu th VCC CP 50% GND Figure 6. 450 W INPUT OUTPUT DEVICE UNDER TEST 50 W SCOPE TEST POINT CL* *Includes all probe and jig capacitance Figure 7. Test Circuit http://onsemi.com 6 MC74ACT564 PACKAGE DIMENSIONS PDIP−20 N SUFFIX PLASTIC DIP PACKAGE CASE 738−03 ISSUE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. −A− 20 11 1 10 B L C −T− K SEATING PLANE M N E G F J D 0.25 (0.010) 20 PL 0.25 (0.010) 20 PL M T A M http://onsemi.com 7 M T B M DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 MC74ACT564 PACKAGE DIMENSIONS SOIC−20W DW SUFFIX CASE 751D−05 ISSUE G 20 11 X 45 _ h H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. q A B M D 1 10 20X B B 0.25 M T A S B S L A 18X e A1 DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ SEATING PLANE C T ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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