ONSEMI 74HC245DTR2G

74HC245
Octal 3−State Noninverting
Bus Transceiver
High−Performance Silicon−Gate CMOS
The 74HC245 is identical in pinout to the LS245. The device inputs
are compatible with standard CMOS outputs; with pull−up resistors,
they are compatible with LSTTL outputs.
The HC245 is a 3−state noninverting transceiver that is used for
2−way asynchronous communication between data buses. The device
has an active−low Output Enable pin, which is used to place the I/O
ports into high−impedance states. The Direction control determines
whether data flows from A to B or from B to A.
Features
•
•
•
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 308 FETs or 77 Equivalent Gates
This is a Pb−Free Device
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MARKING
DIAGRAMS
20
HC
245
ALYW G
G
TSSOP−20
DT SUFFIX
CASE 948E
20
1
1
HC245
A
L
Y
W
G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
March, 2007 − Rev. 1
1
Publication Order Number:
74HC245/D
74HC245
DIRECTION
A1
A2
20
1
2
19
3
18
VCC
OUTPUT ENABLE
A2
A3
B1
A3
4
17
B2
A4
5
16
B3
A5
6
15
B4
A6
7
14
B5
A7
8
13
B6
A8
9
12
B7
10
11
B8
GND
A1
A
DATA
PORT
A4
A5
A6
A7
A8
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
B1
B2
B3
B4
B5
B
DATA
PORT
B6
B7
B8
1
DIRECTION
19
OUTPUT ENABLE
PIN 10 = GND
PIN 20 = VCC
Figure 1. Pin Assignment
Figure 2. Logic Diagram
FUNCTION TABLE
Control Inputs
Output
Enable
Direction
L
L
Data Transmitted from Bus B to Bus A
L
H
Data Transmitted from Bus A to Bus B
H
X
Buses Isolated (High−Impedance State)
Operation
X = don’t care
ORDERING INFORMATION
Device
74HC245DTR2G
Package
Shipping †
TSSOP−20*
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
74HC245
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
VCC
DC Supply Voltage
VIN
DC Input Voltage
VOUT
DC Output Voltage
(Note 2)
Value
Unit
*0.5 to )7.0
V
*0.5 to VCC )0.5
V
*0.5 to VCC )0.5
V
IIK
DC Input Diode Current
$20
mA
IOK
DC Output Diode Current
$35
mA
IOUT
DC Output Sink Current
$35
mA
ICC
DC Supply Current per Supply Pin
$75
mA
IGND
DC Ground Current per Ground Pin
$75
mA
TSTG
Storage Temperature Range
*65 to )150
_C
260
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature Under Bias
)150
_C
qJA
Thermal Resistance
TSSOP
128
_C/W
PD
Power Dissipation in Still Air at 85_C
TSSOP
450
mW
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ILATCHUP
Level 1
Oxygen Index: 30% to 35%
UL 94 V−0 @ 0.125 in
Human Body Model (Note 3)
Machine Model (Note 4)
u2000
u200
V
Above VCC and Below GND at 85_C (Note 5)
$300
mA
ESD Withstand Voltage
Latchup Performance
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 20 ounce copper trace with no air flow.
2. IO absolute maximum rating must observed.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 3)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
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3
Min
Max
Unit
2.0
6.0
V
0
VCC
V
–55
+125
_C
0
0
0
1000
500
400
ns
74HC245
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
–55 to
25_C
Symbol
Parameter
v 85_C
v 125_C
Unit
VIH
Minimum High−Level Input Voltage
Vout = VCC – 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum Low−Level Input Voltage
Vout = 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
VOH
Minimum High−Level Output
Voltage
Vin = VIH
|Iout| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH |Iout| v 2.4 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
Vin = VIL
|Iout| v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIL |Iout| v 2.4 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
VOL
Test Conditions
VCC
V
Maximum Low−Level Output
Voltage
V
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
±0.1
±1.0
±1.0
mA
IOZ
Maximum Three−State Leakage
Current
Output in High−Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
±0.5
±5.0
±10
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 mA
6.0
4.0
40
40
mA
6. Information on typical parametric values and high frequency or heavy load considerations can be found in the ON Semiconductor
High−Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
–55 to
25_C
v 85_C
v 125_C
Unit
tPLH,
tPHL
Maximum Propagation Delay,
A to B, B to A
(Figures 1 and 3)
2.0
3.0
4.5
6.0
75
55
15
13
95
70
19
16
110
80
22
19
ns
tPLZ,
tPHZ
Maximum Propagation Delay,
Direction or Output Enable to A or B
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
90
22
19
140
110
28
24
165
130
33
28
ns
tPZL,
tPZH
Maximum Propagation Delay,
Output Enable to A or B
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
90
22
19
140
110
28
24
165
130
33
28
ns
tTLH,
tTHL
Maximum Output Transition Time,
Any Output
(Figures 1 and 3)
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
Symbol
Parameter
Cin
Maximum Input Capacitance (Pin 1 or Pin 19)
−
10
10
10
pF
Cout
Maximum Three−State I/O Capacitance
(I/O in High−Impedance State)
−
15
15
15
pF
7. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
40
CPD
Power Dissipation Capacitance (Per Transceiver Channel) (Note 8)
pF
8. Used to determine the no−load dynamic power consumption: P D = CPD VCC2 f + ICC VCC . For load considerations, see the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
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4
74HC245
DIRECTION
tf
tr
INPUT
A OR B
tPLH
OUTPUT
B OR A
VCC
90%
50%
10%
tPHL
90%
50%
10%
GND
OUTPUT
ENABLE
A OR B
tTLH
tTHL
A OR B
GND
tPZL
GND
tPLZ
50%
tPHZ
50%
HIGH
IMPEDANCE
10%
VOL
90%
VOH
HIGH
IMPEDANCE
Figure 4. Switching Waveform
TEST POINT
TEST POINT
OUTPUT
OUTPUT
CL*
VCC
VCC
50%
tPZH
Figure 3. Switching Waveform
DEVICE
UNDER
TEST
50%
DEVICE
UNDER
TEST
*Includes all probe and jig capacitance
1 kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 5. Test Circuit
Figure 6. Test Circuit
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5
74HC245
A1
2
18
A2
3
17
A3
A
DATA
PORT
OUTPUT ENABLE
B7
9
11
DIRECTION
B6
8
12
A8
B5
7
13
A7
B4
6
14
A6
B3
5
15
A5
B2
4
16
A4
B1
1
19
Figure 7. Expanded Logic Diagram
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6
B8
B
DATA
PORT
74HC245
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
2X
L
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K
K1
S
J J1
11
B
−U−
PIN 1
IDENT
SECTION N−N
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
−−− 0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
74HC245
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
74HC245/D