MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Product Preview Freescale Semiconductor, Inc... 256K x 36 and 512K x 18 Bit Flow–Through BurstRAM Synchronous Fast Static RAM The MCM63F837 and MCM63F919 are 8M–bit synchronous fast static RAMs designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. The MCM63F837 (organized as 256K words by 36 bits) and the MCM63F919 (organized as 512K words by 18 bits) are fabricated in Motorola’s high performance silicon gate CMOS technology. Synchronous design allows precise cycle control with the use of an external clock (K). Addresses (SA), data inputs (DQx), and all control signals except output enable (G), sleep mode (ZZ), and linear burst order (LBO) are clock (K) controlled through positive–edge–triggered noninverting registers. Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally by the MCM63F837 and MCM63F919 (burst sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin. Write cycles are internally self–timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off–chip write pulse generation and provides increased timing flexibility for incoming signals. Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable (SW) are provided to allow writes to either individual bytes or to all bytes. The bytes are designated as “a”, “b”, etc. SBa controls DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte writes SBx are asserted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted. For read cycles, a flow–through SRAM allows output data to simply flow freely from the memory array. The MCM63F837 and MCM63F919 operate from a 3.3 V core power supply and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC standard JESD8–A and JESD8–5 compatible. Order this document by MCM63F837/D MCM63F837 MCM63F919 TQ PACKAGE TQFP CASE 983A–01 ZP PACKAGE PBGA CASE 999–02 • MCM63F837/MCM63F919–7 = 7 ns Access/8.5 ns Cycle (117 MHz) MCM63F837/MCM63F919–8 = 8 ns Access/10 ns Cycle (100 MHz) MCM63F837/MCM63F919–8.5 = 8.5 ns Access/11 ns Cycle (90 MHz) • 3.3 V ±5% Core Power Supply, 2.5 V or 3.3 V I/O Supply • ADSP, ADSC, and ADV Burst Control Pins • Selectable Burst Sequencing Order (Linear/Interleaved) • Single–Cycle Deselect Timing • Internally Self–Timed Write Cycle • Byte Write and Global Write Control • Sleep Mode (ZZ) • Simplified JTAG • JEDEC Standard 100–Pin TQFP and 119–Bump PBGA Packages The PowerPC name is a trademark of IBM Corp., used under license therefrom. This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. REV 1 8/23/99 Motorola, Inc. 1999 MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63F837•MCM63F919 1 Freescale Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM LBO ADV K ADSC BURST COUNTER K2 2 18/19 256K x 36 / 512K x 18 ARRAY CLR ADSP 2 SA SA1 SA0 ADDRESS REGISTER 18/19 16/17 SGW Freescale Semiconductor, Inc... SW SBa SBb WRITE REGISTER a 36/18 36/18 WRITE REGISTER b 4/2 SBc* SBd* WRITE REGISTER c* DATA–IN REGISTER K WRITE REGISTER d* K2 SE1 SE2 SE3 ENABLE REGISTER G DQa – DQd/ DQa – DQb ZZ * Valid only for MCM63F837. MCM63F837•MCM63F919 2 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. DQc DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQd 100 99 98 97 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 3738 39 40 41 42 43 44 4546 47 48 49 50 A DQb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQa B C D 1 2 3 4 5 6 7 VDDQ SA SA ADSP SA SA VDDQ NC SE2 SA ADSC SA SA NC NC SA SA VDD SA SA NC DQc DQc VSS NC VSS DQb DQb DQc DQc VSS SE1 VSS DQb DQb VDDQ DQc VSS G VSS DQb VDDQ DQc DQc SBc ADV SBb DQb DQb DQc DQc VSS SGW VSS DQb DQb VDDQ VDD NC VDD NC VDD VDDQ E F G H J K DQd DQd VSS K VSS DQa DQa DQd DQd SBd NC SBa DQa DQa VDDQ DQd VSS SW VSS DQa VDDQ L M N P R DQd DQd VSS SA1 VSS DQa DQa DQd DQd VSS SA0 VSS DQa DQa NC SA LBO VDD NC SA NC NC NC SA SA SA NC ZZ VDDQ TMS TDI TCK T U TDO TRST VDDQ LBO SA SA SA SA SA1 SA0 NC NC VSS VDD NC SA SA SA SA SA SA SA SA Freescale Semiconductor, Inc... SA SA SE1 SE2 SBd SBc SBb SBa SE3 VDD VSS K SGW SW G ADSC ADSP ADV SA SA MCM63F837 PIN ASSIGNMENTS 100–PIN TQFP TOP VIEW 119–BUMP PBGA TOP VIEW Not to Scale MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63F837•MCM63F919 3 Freescale Semiconductor, Inc. MCM63F837 TQFP PIN DESCRIPTIONS Pin Locations Symbol Type 85 ADSC Input Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. 84 ADSP Input Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a new READ, WRITE, or chip deselect (exception — chip deselect does not occur when ADSP is asserted and SE1 is high). 83 ADV Input Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). DQx I/O 86 G Input Asynchronous Output Enable Input: Low — enables output buffers (DQx pins). High — DQx pins are high impedance. 89 K Input Clock: This signal registers the address, data in, and all control signals except G, LBO, and ZZ. 31 LBO Input Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low — linear burst counter (68K/PowerPC). High — interleaved burst counter (486/i960/Pentium). 32, 33, 34, 35, 43, 44, 45, 46, 47, 48, 49, 50, 81, 82, 99, 100 SA Input Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. 36, 37 SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. 93, 94, 95, 96 (a) (b) (c) (d) SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte a, b, c, d). SGW overrides SBx. 98 SE1 Input Synchronous Chip Enable: Active low to enable chip. Negated high — blocks ADSP or deselects chip when ADSC is asserted. 97 SE2 Input Synchronous Chip Enable: Active high for depth expansion. 92 SE3 Input Synchronous Chip Enable: Active low for depth expansion. 88 SGW Input Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. 87 SW Input Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. 64 ZZ Input Sleep Mode: This active high asynchronous signal places the RAM into the lowest power mode. The ZZ pin disables the RAMs internal clock when placed in this mode. When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation. 15, 41, 65, 91 VDD Supply Core Power Supply. 4, 11, 20, 27, 54, 61, 70, 77 VDDQ Supply I/O Power Supply. 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VSS Supply Ground. 14, 16, 38, 39, 42, 66 NC — Freescale Semiconductor, Inc... (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29, 30 MCM63F837•MCM63F919 4 Description Synchronous Data I/O: “x” refers to the byte being read or written (byte a, b, c, d). No Connection: There is no connection to the chip. For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. MCM63F837 PBGA PIN DESCRIPTIONS Pin Locations Symbol Type 4B ADSC Input Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. 4A ADSP Input Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a new READ, WRITE, or chip deselect (exception — chip deselect does not occur when ADSP is asserted and SE1 is high). 4G ADV Input Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). DQx I/O 4F G Input Asynchronous Output Enable Input: Low — enables output buffers (DQx pins). High — DQx pins are high impedance. 4K K Input Clock: This signal registers the address, data in, and all control signals except G, LBO, and ZZ. 3R LBO Input Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low — linear burst counter (68K/PowerPC). High — interleaved burst counter (486/i960/Pentium). 2A, 3A, 5A, 6A, 3B, 5B, 6B, 2C, 3C, 5C, 6C, 2R, 6R, 3T, 4T, 5T SA Input Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. 4N, 4P SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. 5L, 5G, 3G, 3L (a) (b) (c) (d) SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte a, b, c, d). SGW overrides SBx. 4E SE1 Input Synchronous Chip Enable: Active low to enable chip. Negated high — blocks ADSP or deselects chip when ADSC is asserted. 2B SE2 Input Synchronous Chip Enable: Active high for depth expansion. 4H SGW Input Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. 4M SW Input Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. 4U TCK Input Boundary Scan Pin, Test Clock: If boundary scan is not used, TCK must be tied to VDD or VSS. 3U TDI Input Boundary Scan Pin, Test Data In. 5U TDO Output 2U TMS Input Boundary Scan Pin, Test Mode Select. 6U TRST Input Boundary Scan Pin, Asynchronous Test Reset: If boundary scan is not used, TRST must be tied to VSS. 7T ZZ Input Sleep Mode: This active high asynchronous signal places the RAM into the lowest power mode. The ZZ pin disables the RAMs internal clock when placed in this mode. When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation. 4C, 2J, 4J, 6J, 4R VDD VDDQ VSS Supply Core Power Supply. Supply I/O Power Supply. Supply Ground. NC — Freescale Semiconductor, Inc... (a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P (b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H (c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H (d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P 1B, 7B, 1C, 7C, 4D, 3J, 5J, 4L, 1R, 5R, 7R, 1T, 2T, 6T MOTOROLA FAST SRAM Description Synchronous Data I/O: “x” refers to the byte being read or written (byte a, b, c, d). Boundary Scan Pin, Test Data Out. No Connection: There is no connection to the chip. For More Information On This Product, Go to: www.freescale.com MCM63F837•MCM63F919 5 Freescale Semiconductor, Inc. NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQb NC VSS VDDQ NC NC NC 100 99 98 97 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 3738 39 40 41 42 43 44 4546 47 48 49 50 1 2 3 4 5 6 7 VDDQ SA SA ADSP SA SA VDDQ NC SE2 SA ADSC SA SA NC NC SA SA VDD SA SA NC DQb NC VSS NC VSS DQa NC NC DQb VSS SE1 VSS NC DQa VDDQ NC VSS G VSS DQa VDDQ NC DQb SBb ADV VSS NC DQa DQb NC VSS SGW VSS DQa NC VDDQ VDD NC VDD NC VDD VDDQ A SA NC NC VDDQ VSS NC DQa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC B C D E F G H J K NC DQb VSS K VSS NC DQa DQb NC VSS NC SBa DQa NC VDDQ DQb VSS SW VSS NC VDDQ L M N P R DQb NC VSS SA1 VSS DQa NC NC DQb VSS SA0 VSS NC DQa NC SA LBO VDD NC SA NC NC SA SA NC SA SA ZZ TDI TCK T U VDDQ TMS TDO TRST VDDQ LBO SA SA SA SA SA1 SA0 NC NC VSS VDD NC SA SA SA SA SA SA SA SA Freescale Semiconductor, Inc... SA SA SE1 SE2 NC NC SBb SBa SE3 VDD VSS K SGW SW G ADSC ADSP ADV SA SA MCM63F919 PIN ASSIGNMENTS 100–PIN TQFP TOP VIEW 119–BUMP PBGA TOP VIEW Not to Scale MCM63F837•MCM63F919 6 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. MCM63F919 TQFP PIN DESCRIPTIONS Pin Locations Symbol Type 85 ADSC Input Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. 84 ADSP Input Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a new READ, WRITE, or chip deselect (exception — chip deselect does not occur when ADSP is asserted and SE1 is high). 83 ADV Input Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). DQx I/O 86 G Input Asynchronous Output Enable Input: Low — enables output buffers (DQx pins). High — DQx pins are high impedance. 89 K Input Clock: This signal registers the address, data in, and all control signals except G, LBO, and ZZ. 31 LBO Input Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low — linear burst counter (68K/PowerPC). High — interleaved burst counter (486/i960/Pentium). 32, 33, 34, 35, 43, 44, 45, 46, 47, 48, 49, 50, 80, 81, 82, 99, 100 SA Input Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. 36, 37 SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. 93, 94 (a) (b) SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte a, b). SGW overrides SBx. 88 SGW Input Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. 98 SE1 Input Synchronous Chip Enable: Active low to enable chip. Negated high — blocks ADSP or deselects chip when ADSC is asserted. 97 SE2 Input Synchronous Chip Enable: Active high for depth expansion. 92 SE3 Input Synchronous Chip Enable: Active low for depth expansion. 87 SW Input Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. 64 ZZ Input Sleep Mode: This active high asynchronous signal places the RAM into the lowest power mode. The ZZ pin disables the RAMs internal clock when placed in this mode. When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation. 15, 41, 65, 91 VDD Supply Core Power Supply. 4, 11, 20, 27, 54, 61, 70, 77 VDDQ Supply I/O Power Supply. 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 VSS Supply Ground. 1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38, 39, 42, 51, 52, 53, 56, 57, 66, 75, 78, 79, 95, 96 NC — Freescale Semiconductor, Inc... (a) 58, 59, 62, 63, 68, 69, 72, 73, 74 (b) 8, 9, 12, 13, 18, 19, 22, 23, 24 MOTOROLA FAST SRAM Description Synchronous Data I/O: “x” refers to the byte being read or written (byte a, b). No Connection: There is no connection to the chip. For More Information On This Product, Go to: www.freescale.com MCM63F837•MCM63F919 7 Freescale Semiconductor, Inc. MCM63F919 PBGA PIN DESCRIPTIONS Pin Locations Symbol Type 4B ADSC Input Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. 4A ADSP Input Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a new READ, WRITE, or chip deselect (exception — chip deselect does not occur when ADSP is asserted and SE1 is high). 4G ADV Input Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). DQx I/O 4F G Input Asynchronous Output Enable Input: Low — enables output buffers (DQx pins). High — DQx pins are high impedance. 4K K Input Clock: This signal registers the address, data in, and all control signals except G, LBO, and ZZ. 3R LBO Input Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low — linear burst counter (68K/PowerPC). High — interleaved burst counter (486/i960/Pentium). 2A, 3A, 5A, 6A, 3B, 5B, 6B, 2C, 3C, 5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T SA Input Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. 4N, 4P SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. 5L, 3G (a) (b) SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte a, b). SGW overrides SBx. 4E SE1 Input Synchronous Chip Enable: Active low to enable chip. Negated high — blocks ADSP or deselects chip when ADSC is asserted. Freescale Semiconductor, Inc... (a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P (b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P Description Synchronous Data I/O: “x” refers to the byte being read or written (byte a, b). 2B SE2 Input Synchronous Chip Enable: Active high for depth expansion. 4H SGW Input Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. 4M SW Input Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. 4U TCK Input Boundary Scan Pin, Test Clock: If boundary scan is not used, TCK must be tied to VDD or VSS. Boundary Scan Pin, Test Data In. 3U TDI Input 5U TDO Output 2U TMS Input Boundary Scan Pin, Test Mode Select. 6U TRST Input Boundary Scan Pin, Asynchronous Test Reset: If boundary scan is not used, TRST must be tied to VSS. 7T ZZ Input Sleep Mode: This active high asynchronous signal places the RAM into the lowest power mode. The ZZ pin disables the RAMs internal clock when placed in this mode. When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation. 4C, 2J, 4J, 6J, 4R VDD VDDQ VSS Supply Core Power Supply. Supply I/O Power Supply. Supply Ground. NC — 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P 1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E, 2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K, 2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R, 5R, 7R, 1T, 4T MCM63F837•MCM63F919 8 Boundary Scan Pin, Test Data Out. No Connection: There is no connection to the chip. For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. TRUTH TABLE (See Notes 1 Through 5) Address Used SE1 SE2 SE3 ADSP ADSC ADV G3 DQx Write 2, 4 Deselect None 1 X X X 0 X X High–Z X Deselect None 0 X 1 0 X X X High–Z X Deselect None 0 0 X 0 X X X High–Z X Deselect None X X 1 1 0 X X High–Z X X Next Cycle Freescale Semiconductor, Inc... Deselect None X 0 X 1 0 X X High–Z Begin Read External 0 1 0 0 X X 0 High–Z X Begin Read External 0 1 0 1 0 X 0 High–Z READ Continue Read Next X X X 1 1 0 1 High–Z READ Continue Read Next X X X 1 1 0 0 DQ READ Continue Read Next 1 X X X 1 0 1 High–Z READ Continue Read Next 1 X X X 1 0 0 DQ READ Suspend Read Current X X X 1 1 1 1 High–Z READ Suspend Read Current X X X 1 1 1 0 DQ READ Suspend Read Current 1 X X X 1 1 1 High–Z READ Suspend Read Current 1 X X X 1 1 0 DQ READ Begin Write External 0 1 0 1 0 X X High–Z WRITE Continue Write Next X X X 1 1 0 X High–Z WRITE Continue Write Next 1 X X X 1 0 X High–Z WRITE Suspend Write Current X X X 1 1 1 X High–Z WRITE Suspend Write Current 1 X X X 1 1 X High–Z WRITE NOTES: 1. X = don’t care. 1 = logic high. 0 = logic low. 2. Write is defined as either 1) any SBx and SW low or 2) SGW is low. 3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low. 4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must also remain negated at the completion of the write cycle to ensure proper write data hold times. ASYNCHRONOUS TRUTH TABLE Operation ZZ G I/O Status Read L L Data Out (DQx) Read L H High–Z Write L X High–Z Deselected L X High–Z Sleep H X High–Z LINEAR BURST ADDRESS TABLE (LBO = VSS) 1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal) X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X10 X . . . X11 X . . . X00 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X00 X . . . X01 X . . . X10 INTERLEAVED BURST ADDRESS TABLE (LBO = VDD) 1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal) X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X00 X . . . X11 X . . . X10 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X10 X . . . X01 X . . . X00 MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63F837•MCM63F919 9 Freescale Semiconductor, Inc. WRITE TRUTH TABLE SGW SW SBa SBb SBc (See Note 1) SBd (See Note 1) Read H H X X X X Read H L H H H H Write Byte a H L L H H H Write Byte b H L H L H H Write Byte c (See Note 1) H L H H L H Write Byte d (See Note 1) H L H H H L Write All Bytes H L L L L L Write All Bytes L X X X X X Cycle Type Freescale Semiconductor, Inc... NOTE: 1. Valid Only for MCM63F837. ABSOLUTE MAXIMUM RATINGS (See Note 1) Rating Symbol Value Unit VDD VSS – 0.5 to 4.6 V VDDQ VSS – 0.5 to VDD V 2 Vin, Vout VSS – 0.5 to VDD + 0.5 V 2 Input Voltage (Three–State I/O) VIT VSS – 0.5 to VDDQ + 0.5 V 2 Output Current (per I/O) Iout ±20 mA Package Power Dissipation PD 1.6 W Tbias –10 to 85 °C Tstg –55 to 125 °C Power Supply Voltage I/O Supply Voltage Input Voltage Relative to VSS for Any Pin Except VDD Temperature Under Bias Storage Temperature Notes This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. 3 NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. This is a steady–state DC parameter that is in effect after the power supply has achieved its nominal operating level. Power sequencing is not necessary. 3. Power dissipation capability is dependent upon package characteristics and use environment. See Package Thermal Characteristics. PACKAGE THERMAL CHARACTERISTICS Rating Symbol Max Unit Notes RθJA 40 25 °C/W 1, 2 Junction to Board (Bottom) RθJB 17 °C/W 3 Junction to Case (Top) RθJC 9 °C/W 4 RθJA 38 22 °C/W 1, 2 RθJB 14 °C/W 3 TQFP Junction to Ambient (@ 200 lfm) Single–Layer Board Four–Layer Board PBGA Junction to Ambient (@ 200 lfm) Junction to Board (Bottom) Single–Layer Board Four–Layer Board Junction to Case (Top) RθJC 5 °C/W 4 NOTES: 1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. Per SEMI G38–87. 3. Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1). MCM63F837•MCM63F919 10 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. DC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V ±5%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS AND DC CHARACTERISTICS (Voltages Referenced to VSS = 0 V) Parameter Symbol Min Typ Max Unit VDD 3.135 3.3 3.465 V I/O Supply Voltage VDDQ 2.375 2.5 2.9 V Input Low Voltage VIL –0.3* — 0.7 V Input High Voltage VIH 1.7 — VDD + 0.3** V Input High Voltage I/O Pins VIH2 1.7 — VDDQ + 0.3** V Output Low Voltage (IOL = 2 mA) VOL — — 0.7 V Output High Voltage (IOH = –2 mA) VOH 1.7 — — V VDD 3.135 3.3 3.465 V I/O Supply Voltage VDDQ 3.135 3.3 VDD V Input Low Voltage VIL –0.5* — 0.8 V Input High Voltage VIH 2 — VDD + 0.5** V Input High Voltage I/O Pins VIH2 2 — VDDQ + 0.5** V Output Low Voltage (IOL = 8 mA) VOL — — 0.4 V Output High Voltage (IOH = –4 mA) VOH 2.4 — — V 2.5 V I/O SUPPLY Supply Voltage Freescale Semiconductor, Inc... 3.3 V I/O SUPPLY Supply Voltage * Undershoot: VIL ≤ – 1.5 V for t < 20% tKHKH. ** Overshoot: VIH/VIH2 ≤ VDD/VDDQ + 1.0 V (not to exceed 4.6 V) for t < 20% tKHKH. SUPPLY CURRENTS Symbol Min Typ Max Unit Notes Input Leakage Current (0 V ≤ Vin ≤ VDD) Parameter Ilkg(I) — — ±1 µA 1 Output Leakage Current (0 V ≤ Vin ≤ VDDQ) Ilkg(O) — — ±1 µA IDDA — — TBD mA 2, 3, 4 CMOS Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, All Inputs Static at CMOS Levels) ISB2 — — TBD mA 5, 6 Sleep Mode Supply Current (Device Deselected, Freq = Max, VDD = Max, All Other Inputs Static at CMOS Levels, ZZ ≥ VDD – 0.2 V) IZZ — — TBD mA 1, 5, 6 TTL Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, All Inputs Static at TTL Levels) ISB3 — — TBD mA 5, 7 Clock Running (Device Deselected, Freq = Max, VDD = Max, All Inputs Toggling at CMOS Levels) MCM63F837/919–7 MCM63F837/919–8 MCM63F837/919–8.5 ISB4 — — TBD mA 5, 6 Static Clock Running (Device Deselected, Freq = Max, VDD = Max, All Inputs Static at TTL Levels) MCM63F837/919–7 MCM63F837/919–8 MCM63F837/919–8.5 ISB5 — — TBD mA 5, 7 AC Supply Current (Device Selected, All Outputs Open, Freq = Max) Includes VDD Only MCM63F837/919–7 MCM63F837/919–8 MCM63F837/919–8.5 NOTES: 1. LBO and ZZ pins have an internal pull–up and pull–down, and will exhibit leakage currents of ±5 µA. 2. Reference AC Operating Conditions and Characteristics for input and timing. 3. All addresses transition simultaneously low (LSB) then high (MSB). 4. Data states are all zero. 5. Device is deselected as defined by the Truth Table. 6. CMOS levels for I/Os are VIT ≤ VSS + 0.2 V or ≥ VDDQ – 0.2 V. CMOS levels for other inputs are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V. 7. TTL levels for I/Os are VIT ≤ VIL or ≥ VIH2. TTL levels for other inputs are Vin ≤ VIL or ≥ VIH. MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63F837•MCM63F919 11 Freescale Semiconductor, Inc. CAPACITANCE (f = 1.0 MHz, TA = 0 to 70°C, Periodically Sampled Rather Than 100% Tested) Symbol Min Typ Max Unit Input Capacitance Parameter Cin — 2 4 pF Input/Output Capacitance CI/O — 3 5 pF AC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V ±5%, TA = 0 to 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . 1.0 V/ns (20% to 80%) Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted READ/WRITE CYCLE TIMING (See Notes 1 and 2) MCM63F837–7 MCM63F919–7 MCM63F837–8 MCM63F919–8 Symbol S b l Min Max Min Max Min Max Unit U i Cycle Time tKHKH 8.5 — 10 — 11 — ns Clock High Pulse Width tKHKL 3.4 — 4 — 4.5 — ns Clock Low Pulse Width tKLKH 3.4 — 4 — 4.5 — ns Clock Access Time tKHQV — 7 — 8 — 8.5 ns Output Enable to Output Valid tGLQV — 3.5 — 3.5 — 3.5 ns Clock High to Output Active tKHQX1 2 — 2 — 2 — ns 3, 4, 5 Clock High to Output Change tKHQX2 2 — 2 — 2 — ns 3, 4 Output Enable to Output Active tGLQX 0 — 0 — 0 — ns 3, 4 Output Disable to Q High–Z tGHQZ — 3.5 — 3.5 — 3.5 ns 3, 4 Clock High to Q High–Z 3, 4, 5 Freescale Semiconductor, Inc... Parameter P MCM63F837–8.5 MCM63F919–8.5 tKHQZ 2 3.5 2 3.5 2 3.5 ns Sleep Mode Standby tZZS — 2 — 2 — 2 cycles Sleep Mode Recovery tZZREC — 2 — 2 — 2 cycles tZZQZ — 15 — 15 — 15 ns Sleep Mode to Q High–Z Setup Times: Address ADSP, ADSC, ADV Data In Write Chip Enable tADKH tADSKH tDVKH tWVKH tEVKH 1.5 — 1.5 — 1.5 — ns Hold Times: Address ADSP, ADSC, ADV Data In Write Chip Enable tKHAX tKHADSX tKHDX tKHWX tKHEX 0.5 — 0.5 — 0.5 — ns Notes N NOTES: 1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP or ADSC is asserted. 2. All read and write cycle timings are referenced from K or G. 3. Measured at ±200 mV from steady state. 4. This parameter is sampled and not 100% tested. 5. At any given voltage and temperature, tKHQZ max is less than tKHQX1 min for a given device and from device to device. OUTPUT Z0 = 50 Ω RL = 50 Ω 1.5 V Figure 1. AC Test Load MCM63F837•MCM63F919 12 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. CLOCK ACCESS TIME DELAY (ns) 5 OUTPUT CL 4 3 TBD 2 1 0 0 20 40 60 80 100 LUMPED CAPACITANCE, CL (pF) Freescale Semiconductor, Inc... Figure 2. Lumped Capacitive Load and Typical Derating Curve OUTPUT LOAD OUTPUT BUFFER TEST POINT UNLOADED RISE AND FALL TIME MEASUREMENT INPUT WAVEFORM OUTPUT WAVEFORM 2.4 2.4 0.6 0.6 2.4 2.4 0.6 0.6 tr tf NOTES: 1. Input waveform has a slew rate of 1 V/ns. 2. Rise time is measured from 0.6 to 2.4 V unloaded. 3. Fall time is measured from 2.4 to 0.6 V unloaded. Figure 3. Unloaded Rise and Fall Time Characterization MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63F837•MCM63F919 13 MCM63F837•MCM63F919 14 For More Information On This Product, Go to: www.freescale.com Q(n) A SINGLE READ tKHQX1 Q(A) tKHQV B tKHKL NOTE: E low = SE2 high and SE3 low. W low = SGW low and/or SW and SBx low. DESELECTED tKHQZ DQx G W E SE1 ADV ADSC ADSP SA K tKHKH tKHQX2 Q(B) Q(B+2) BURST READ Q(B+1) tGHQZ Q(B+3) BURST WRAPS AROUND tKLKH Q(B) ADSP, SA SE2, SE3 IGNORED READ/WRITE CYCLES D(C) C D(C+2) BURST WRITE D(C+1) Freescale Semiconductor, Inc... D(C+3) SINGLE READ tGLQX tGLQV D Q(D) Freescale Semiconductor, Inc. MOTOROLA FAST SRAM MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com DQ G W E SE1 ADV ADSC ADSP SA K DESELECT Q (A) A SINGLE READ Q (A) B Q (C) D SINGLE DESELECT SINGLE READ READ Q (B) C SINGLE READ Q (D) E Q (E) Q(E+1) Q(E+3) BURST READ Q(E+2) READ CYCLES Q (E) Freescale Semiconductor, Inc... F Q (F) Q(F+2) BURST READ Q(F+1) DESELECT Q(F+3) Freescale Semiconductor, Inc. MCM63F837•MCM63F919 15 MCM63F837•MCM63F919 16 For More Information On This Product, Go to: www.freescale.com DQ G W E SE1 ADV ADSC ADSP SA K DESELECT A SINGLE WRITE D (A) SINGLE WRITE D (B) B DESELECT C SINGLE WRITE D (C) D (D) D SINGLE WRITE E D (E) D (E+2) BURST WRITE D (E+1) WRITE CYCLES D (E+3) D (F) F DESELECT Freescale Semiconductor, Inc... D (F+2) D (F+3) BURST WRITE D (F+1) DESELECT Freescale Semiconductor, Inc. MOTOROLA FAST SRAM tZZREC NO READS OR WRITES ALLOWED MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com IDD ZZ DQ G W E ADV ADDR ADS K NORMAL OPERATION tZZS tZZQZ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ NOTE: ADS low = ADSC low or ADSP low. ADS high = both ADSC, ADSP high. E low = SE1 low, SE2 high, SE3 low. IZZ (max) specifications will not be met if inputs toggle. I ZZ IN SLEEP MODE ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ NO NEW READS OR WRITES ALLOWED SLEEP MODE TIMING Freescale Semiconductor, Inc... NORMAL OPERATION Freescale Semiconductor, Inc. MCM63F837•MCM63F919 17 Freescale Semiconductor, Inc. APPLICATION INFORMATION Freescale Semiconductor, Inc... SLEEP MODE A sleep mode feature, the ZZ pin, has been implemented on the MCM63F837 and MCM63F919. It allows the system designer to place the RAM in the lowest possible power condition by asserting ZZ. The sleep mode timing diagram shows the different modes of operation: Normal Operation, No READ/WRITE Allowed, and Sleep Mode. Each mode has its own set of constraints and conditions that are allowed. Normal Operation: All inputs must meet setup and hold times prior to sleep and t ZZREC nanoseconds after recovering from sleep. Clock (K) must also meet cycle, high, and low times during these periods. Two cycles prior to sleep, initiation of either a read or write operation is not allowed. No READ/WRITE: During the period of time just prior to sleep and during recovery from sleep, the assertion of either ADSC, ADSP, or any write signal is not allowed. If a write operation occurs during these periods, the memory array may be corrupted. Validity of data out from the RAM can not be guaranteed immediately after ZZ is asserted (prior to being in sleep). Sleep Mode: The RAM automatically deselects itself. The RAM disconnects its internal clock buffer. The external clock may continue to run without impacting the RAMs sleep current (IZZ). All inputs are allowed to toggle — the RAM will not be selected and perform any reads or writes. However, if inputs toggle, the IZZ (max) specification will not be met. Note: It is invalid to go from stop clock mode directly into sleep mode. NON–BURST SYNCHRONOUS OPERATION Although this BurstRAM has been designed for PowerPC and other high end MPU–based systems, these SRAMs can be used in other high speed L2 cache or memory applications that do not require the burst address feature. Most L2 caches designed with a synchronous interface can make use of the MCM63F837 and MCM63F919. The burst counter feature of the BurstRAM can be disabled, and the SRAM can be configured to act upon a continuous stream of addresses. See Figure 4. CONTROL PIN TIE VALUES EXAMPLE (H ≥ VIH, L ≤ VIL) Non–Burst ADSP ADSC ADV SE1 SE2 LBO Sync Non–Burst, Flow–Through SRAM H L H L H X NOTE: Although X is specified in the table as a don’t care, the pin must be tied either high or low. K ADDR A B C D E F G D(E) D(F) D(G) H SE3 W G DQ Q(A) Q(B) Q(C) Q(D) READS D(H) WRITES Figure 4. Example Configuration as Non–Burst Synchronous SRAM MCM63F837•MCM63F919 18 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION OVERVIEW The serial boundary scan test access port (TAP) on this RAM is designed to operate in a manner consistent with IEEE Standard 1149.1–1990 (commonly referred to as JTAG), but does not implement all of the functions required for IEEE 1149.1 compliance. Certain functions have been modified or eliminated because their implementation places extra delays in the RAMs critical speed path. Nevertheless, the RAM supports the standard TAP controller architecture (the TAP controller is the state machine that controls the TAPs operation) and can be expected to function in a manner that does not conflict with the operation of devices with IEEE Standard 1149.1 compliant TAPs. The TAP operates using a 3.3 V tolerant logic level signaling. DISABLING THE TEST ACCESS PORT It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with normal operation of the device, TRST should be tied low and TCK, TDI, and TMS should be pulled through a resistor to 3.3 V. TDO should be left unconnected. TAP DC OPERATING CHARACTERISTICS Freescale Semiconductor, Inc... (TA = 0 to 70°C, Unless Otherwise Noted) Parameter Symbol Min Max Unit Input Logic Low VIL1 –0.5 0.8 V Input Logic High VIH1 2 3.6 V Ilkg — ±10 µA 1 Output Logic Low VOL1 — 0.4 V 2 Output Logic High VOH1 2.4 — V Input Leakage Current Notes NOTES: 1. 0 V ≤ Vin ≤ VDDQ for all logic input pins. 2. For VOL = 0.4 V, 14 mA ≤ IOL ≤ 28 mA. TAP AC OPERATING CONDITIONS AND CHARACTERISTICS (TA = 0 to 70°C, Unless Otherwise Noted) AC TEST CONDITIONS Parameter Value Unit 1.5 V 0 to 3.0 V 1 V/ns Output Timing Reference Level 1.5 V Output Load (See Figure 1 Unless Otherwise Noted) — — Input Timing Reference Level Input Pulse Levels Input Rise/Fall Time (20% to 80%) MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63F837•MCM63F919 19 Freescale Semiconductor, Inc. TAP CONTROLLER TIMING Parameter Symbol Min Max Unit tTHTH 60 — ns TCK Clock High Time tTH 25 — ns TCK Clock Low Time tTL 25 — ns TDO Access Time tTLQV 1 10 ns TRST Pulse Width tTSRT 40 — ns TCK Cycle Time Notes Setup Times Capture TDI TMS tCS tDVTH tMVTH 5 5 5 — ns 1 Hold Times Capture TDI TMS tCH tTHDX tTHMX 13 14 14 — ns 1 Freescale Semiconductor, Inc... NOTE: 1. tCS and tCH define the minimum pauses in RAM I/O transitions to assure accurate pad data capture. TAP CONTROLLER TIMING DIAGRAM tTHTH tTLTH TEST CLOCK (TCK) tTHTL tTHMX tMVTH TEST MODE SELECT (TMS) tTHDX tDVTH TEST DATA IN (TDI) tTLQV TEST DATA OUT (TDO) MCM63F837•MCM63F919 20 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. TEST ACCESS PORT PINS TCK — TEST CLOCK (INPUT) Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS — TEST MODE SELECT (INPUT) The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will not produce the same result as a logic 1 input level (not IEEE 1149.1 compliant). Freescale Semiconductor, Inc... TDI — TEST DATA IN (INPUT) The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction register (see Figure 6). An undriven TDI pin will not produce the same result as a logic 1 input level (not IEEE 1149.1 compliant). TDO — TEST DATA OUT (OUTPUT) Output that is active depending on the state of the TAP state machine (see Figure 6). Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TRST — TAP RESET The TRST is an asynchronous input that resets the TAP controller and preloads the instruction register with the IDCODE command. This type of reset does not affect the operation of the system logic. The reset affects test logic only. TEST ACCESS PORT REGISTERS BOUNDARY SCAN REGISTER The boundary scan register is identical in length to the number of active input and I/O connections on the RAM (not counting the TAP pins). This also includes a number of place holder locations (always set to a logic 0) reserved for density upgrade address pins. There are a total of 70 bits in the case of the x36 device and 51 bits in the case of the x18 device. The boundary scan register, under the control of the TAP controller, is loaded with the contents of the RAMs I/O ring when the controller is in capture–DR state and then is placed between the TDI and TDO pins when the controller is moved to shift–DR state. The Bump/Bit Scan Order table describes which device bump connects to each boundary scan register location. The first column defines the bit’s position in the boundary scan register. The shift register bit nearest TDO (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the input or I/O at the bump and the third column is the bump number. IDENTIFICATION (ID) REGISTER The ID register is a 32–bit register that is loaded with a device and vendor specific 32–bit code when the controller is put in capture–DR state with the IDCODE command loaded in the instruction register. The code is loaded from a 32–bit on–chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into shift–DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. ID Register Presence Indicator Bit No. 0 Value 1 Motorola JEDEC ID Code (Compressed Format, per IEEE Standard 1149.1–1990 OVERVIEW The various TAP registers are selected (one at a time) via the sequences of 1s and 0s input to the TMS pin as the TCK is strobed. Each of the TAPs registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on subsequent falling edge of TCK. When a register is selected it is “placed” between the TDI and TDO pins. Bit No. 11 10 9 8 7 6 5 4 3 2 1 Value 0 0 0 0 0 0 0 1 1 1 0 Reserved For Future Use Bit No. 17 16 15 14 13 12 Value x x x x x x Device Width INSTRUCTION REGISTER The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run test/idle or the various data register states. The instructions are 3 bits long. The register can be loaded when it is placed between the TDI and TDO pins. The parallel outputs of the instruction register are automatically preloaded with the IDCODE instruction when TRST is asserted or whenever the controller is placed in the test–logic–reset state. The two least significant bits of the serial instruction register are loaded with a binary “or” pattern in the capture–IR state. BYPASS REGISTER The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be MOTOROLA FAST SRAM passed through the RAMs TAP to another device in the scan chain with as little delay as possible. Bit No. 22 21 20 19 18 256K x 36 0 0 1 0 0 512K x 18 0 0 0 1 1 Bit No. 27 26 25 24 23 256K x 36 0 0 1 1 0 512K x 18 0 0 1 1 1 Device Depth Revision Number Bit No. 31 30 29 28 Value 0 0 0 1 Figure 5. ID Register Bit Meanings For More Information On This Product, Go to: www.freescale.com MCM63F837•MCM63F919 21 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MCM63F837 BOUNDARY SCAN ORDER Bit No. Signal Name Bump ID Bit No. Signal Name Bump ID 1 SA TBD 35 K TBD 2 SA TBD 36 SE3 TBD 3 SA TBD 37 SBa TBD 4 SA TBD 38 SBb TBD 5 SA TBD 39 SBc TBD 40 SBd TBD 41 SE2 TBD 42 SE1 TBD 43 SA TBD 44 SA TBD 45 DQc TBD 46 DQc TBD 6 SA TBD 7 SA TBD 8 DQa TBD 9 DQa TBD 10 DQa TBD 11 DQa TBD 12 DQa TBD 47 DQc TBD 13 DQa TBD 48 DQc TBD 14 DQa TBD 49 DQc TBD 15 DQa TBD 50 DQc TBD 16 DQa TBD 51 DQc TBD 17 ZZ TBD 52 DQc TBD 18 DQb TBD 53 DQc TBD 19 DQb TBD 54 VSS TBD 20 DQb TBD 55 DQd TBD 21 DQb TBD 56 DQd TBD 22 DQb TBD 57 DQd TBD 58 DQd TBD 59 DQd TBD 60 DQd TBD 61 DQd TBD 62 DQd TBD 63 DQd TBD 64 LBO TBD 65 SA TBD 23 DQb TBD 24 DQb TBD 25 DQb TBD 26 DQb TBD 27 SA TBD 28 SA TBD 29 ADV TBD 30 ADSP TBD 66 SA TBD 31 ADSC TBD 67 SA TBD 32 G TBD 68 SA TBD 33 SW TBD 69 SA1 TBD 34 SGW TBD 70 SA0 TBD MCM63F837•MCM63F919 22 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MCM63F919 BOUNDARY SCAN ORDER Bit No. Signal Name Bump ID Bit No. Signal Name Bump ID 1 SA TBD 26 SGW TBD 2 SA TBD 27 K TBD 3 SA TBD 28 SE3 TBD 4 SA TBD 29 SBa TBD 5 SA TBD 30 SBb TBD 31 SE2 TBD 32 SE1 TBD 33 SA TBD 34 SA TBD 35 DQb TBD 36 DQb TBD 37 DQb TBD 38 VSS TBD 39 DQb TBD 40 DQb TBD 41 DQb TBD 42 DQb TBD 43 DQb TBD 6 SA TBD 7 SA TBD 8 DQa TBD 9 DQa TBD 10 DQa TBD 11 DQa TBD 12 ZZ TBD 13 DQa TBD 14 DQa TBD 15 DQa TBD 16 DQa TBD 17 DQa TBD 18 SA TBD 44 DQb TBD 19 SA TBD 45 LBO TBD 20 SA TBD 46 SA TBD 21 ADV TBD 47 SA TBD 22 ADSP TBD 48 SA TBD 23 ADSC TBD 49 SA TBD 24 G TBD 50 SA1 TBD 25 SW TBD 51 SA0 TBD MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63F837•MCM63F919 23 Freescale Semiconductor, Inc. TAP CONTROLLER INSTRUCTION SET Freescale Semiconductor, Inc... OVERVIEW There are two classes of instructions defined in the IEEE Standard 1149.1–1990; the standard (public) instructions and device specific (private) instructions. Some public instructions, are mandatory for IEEE 1149.1 compliance. Optional public instructions must be implemented in prescribed ways. Although the TAP controller in this device follows the IEEE 1149.1 conventions, it is not IEEE 1149.1 compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor all input and I/O pads, but can not be used to load address, data, or control signals into the RAM or to preload the I/O buffers. In other words, the device will not perform IEEE 1149.1 EXTEST, INTEST, or the preload portion of the SAMPLE/PRELOAD command. When the TAP controller is placed in capture–IR state, the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the shift–IR state the instruction register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to update–IR state. The TAP instruction sets for this device are listed in the following tables. STANDARD (PUBLIC) INSTRUCTIONS BYPASS The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift–DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is an IEEE 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the Instruction register, moving the TAP controller out of the capture–DR state loads the data in the RAMs input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK), it is MCM63F837•MCM63F919 24 possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results can not be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving the controller to shift–DR state then places the boundary scan register between the TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the update–DR state with the SAMPLE/PRELOAD instruction loaded in the instruction register has the same effect as the pause–DR command. This functionality is not IEEE 1149.1 compliant. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic 0s. EXTEST is not implemented in this device. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture–DR mode and places the ID register between the TDI and TDO pins in shift–DR mode. The IDCODE instruction is the default instruction loaded in at TRST assertion and any time the controller is placed in the test–logic–reset state. THE DEVICE SPECIFIC (PUBLIC) INSTRUCTION SAMPLE–Z If the SAMPLE–Z instruction is loaded in the instruction register, all DQ pins are forced to an inactive drive state (High–Z) and the bypass register is connected between TDI and TDO when the TAP controller is moved to the shift–DR state. THE DEVICE SPECIFIC (PRIVATE) INSTRUCTION NO OP Do not use these instructions; they are reserved for future use. For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. STANDARD AND DEVICE SPECIFIC (PUBLIC) INSTRUCTION CODES Instruction Code* Description IDCODE 001** Preloads ID register and places it between TDI and TDO. Does not affect RAM operation. HIGH–Z 010 Captures I/O ring contents. Places the bypass register between TDI and TDO. Forces all DQ pins to High–Z. NOT IEEE 1149.1 COMPLIANT. BYPASS 011 Places bypass register between TDI and TDO. Does not affect RAM operation. NOT IEEE 1149.1 COMPLIANT. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect RAM operation. Does not implement IEEE 1149.1 Preload function. NOT IEEE 1149.1 COMPLIANT. * Instruction codes expressed in binary, MSB on left, LSB on right. ** Default instruction automatically loaded when TRST asserted or in test–logic–reset state. STANDARD (PRIVATE) INSTRUCTION CODES Freescale Semiconductor, Inc... Instruction Code* Description NO OP 000 Do not use these instructions; they are reserved for future use. NO OP 101 Do not use these instructions; they are reserved for future use. NO OP 110 Do not use these instructions; they are reserved for future use. NO OP 111 Do not use these instructions; they are reserved for future use. * Instruction codes expressed in binary, MSB on left, LSB on right. 1 TEST–LOGIC RESET 0 0 RUN–TEST/ IDLE 1 SELECT DR–SCAN SELECT IR–SCAN 1 0 1 1 CAPTURE–DR CAPTURE–IR 0 0 SHIFT–DR SHIFT–IR 0 0 1 1 EXIT1–DR 1 0 PAUSE–DR PAUSE–IR 0 1 0 1 EXIT2–DR 0 EXIT2–IR 1 1 UPDATE–DR 1 1 EXIT1–IR 0 0 1 0 0 UPDATE–IR 1 0 NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK. Figure 6. TAP Controller State Diagram MOTOROLA FAST SRAM For More Information On This Product, Go to: www.freescale.com MCM63F837•MCM63F919 25 Freescale Semiconductor, Inc. ORDERING INFORMATION (Order by Full Part Number) MCM 63F837 63F919 XX X X Motorola Memory Prefix Blank = Trays, R = Tape and Reel Part Number Speed (7 = 7 ns, 8 = 8 ns, 8.5 = 8.5 ns) Package (TQ = TQFP, ZP = PBGA) MCM63F837TQ8 MCM63F837TQ8R MCM63F837ZP8 MCM63F837ZP8R MCM63F837TQ8.5 MCM63F837TQ8.5R MCM63F837ZP8.5 MCM63F837ZP8.5R MCM63F919TQ7 MCM63F919TQ7R MCM63F919ZP7 MCM63F919ZP7R MCM63F919TQ8 MCM63F919TQ8R MCM63F919ZP8 MCM63F919ZP8R MCM63F919TQ8.5 MCM63F919TQ8.5R MCM63F919ZP8.5 MCM63F919ZP8.5R Freescale Semiconductor, Inc... Full Part Numbers — MCM63F837TQ7 MCM63F837TQ7R MCM63F837ZP7 MCM63F837ZP7R MCM63F837•MCM63F919 26 For More Information On This Product, Go to: www.freescale.com MOTOROLA FAST SRAM Freescale Semiconductor, Inc. PACKAGE DIMENSIONS TQ PACKAGE TQFP CASE 983A–01 e 4X 0.20 (0.008) H A–B D 2X 30 TIPS e/2 0.20 (0.008) C A–B D –D– 80 51 B 50 81 –A– –X– B E/2 X=A, B, OR D –B– VIEW Y E1 E BASE METAL PLATING Freescale Semiconductor, Inc... c 31 100 1 30 D1/2 0.13 (0.005) 0.20 (0.008) C A–B D A q 2 0.10 (0.004) C –H– –C– SEATING PLANE q 3 VIEW AB S S q 1 A2 L2 L L1 GAGE PLANE q VIEW AB DIM A A1 A2 b b1 c c1 D D1 E E1 e L L1 L2 S R1 R2 q 1 2 q3 q q MOTOROLA FAST SRAM C A–B S D S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE –C–. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS D1 AND B1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE b DIMENSION TO EXCEED 0.45 (0.018). 0.25 (0.010) R2 R1 M SECTION B–B 2X 20 TIPS A1 c1 b D/2 D1 D 0.05 (0.002) ÉÉÉÉ ÇÇÇÇ ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ b1 E1/2 For More Information On This Product, Go to: www.freescale.com MILLIMETERS MIN MAX ––– 1.60 0.05 0.15 1.35 1.45 0.22 0.38 0.22 0.33 0.09 0.20 0.09 0.16 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.65 BSC 0.45 0.75 1.00 REF 0.50 REF 0.20 ––– 0.08 ––– 0.08 0.20 0_ 7_ 0_ ––– 11 _ 13 _ 11 _ 13 _ INCHES MIN MAX ––– 0.063 0.002 0.006 0.053 0.057 0.009 0.015 0.009 0.013 0.004 0.008 0.004 0.006 0.866 BSC 0.787 BSC 0.630 BSC 0.551 BSC 0.026 BSC 0.018 0.030 0.039 REF 0.020 REF 0.008 ––– 0.003 ––– 0.003 0.008 0_ 7_ 0_ ––– 11 _ 13 _ 11 _ 13 _ MCM63F837•MCM63F919 27 Freescale Semiconductor, Inc. ZP PACKAGE PBGA CASE 999–02 0.20 4X 119X E C B D Freescale Semiconductor, Inc... E2 e 6X M A B C A A B C D E F G H J K L M N P R T U D1 16X M 0.15 7 6 5 4 3 2 1 D2 b 0.3 DIM A A1 A2 A3 D D1 D2 E E1 E2 b e e E1 TOP VIEW NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. ALL DIMENSIONS IN MILLIMETERS. 3. DIMENSION b IS THE MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. BOTTOM VIEW MILLIMETERS MIN MAX ––– 2.40 0.50 0.70 1.30 1.70 0.80 1.00 22.00 BSC 20.32 BSC 19.40 19.60 14.00 BSC 7.62 BSC 11.90 12.10 0.60 0.90 1.27 BSC 0.25 A A3 0.35 A 0.20 A A A2 A1 SIDE VIEW SEATING PLANE A Motorola reserves the right to make changes without further notice to any products herein. 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