MOTOROLA Order this document by MCM6706BR/D SEMICONDUCTOR TECHNICAL DATA MCM6706BR Product Preview 32K x 8 Bit Static Random Access Memory The MCM6706BR is a 262,144 bit static random access memory organized as 32,768 words of 8 bits. Static design eliminates the need for external clocks or timing strobes. Output enable (G) is a special control feature that provides increased system flexibility and eliminates bus contention problems. The MCM6706BR meets JEDEC standards and is available in a revolutionary pinout 300 mil, 32–lead surface–mount SOJ package. • • • • • Single 5.0 V ± 10% Power Supply Fully Static — No Clock or Timing Strobes Necessary All Inputs and Outputs Are TTL Compatible Three State Outputs Fast Access Times: MCM6706BR–6 = 6 ns MCM6706BR–7 = 7 ns MCM6706BR–8 = 8 ns • Center Power and I/O Pins for Reduced Noise BLOCK DIAGRAM A VCC VSS A A A A MEMORY MATRIX 512 ROWS x 64 x 8 COLUMNS ROW DECODER A A J PACKAGE 300 MIL SOJ CASE 857–02 PIN ASSIGNMENT A 1 32 NC A 2 31 A A 3 30 A A 4 29 A E 5 28 G DQ 6 27 DQ DQ 7 26 DQ VCC 8 25 VSS VSS 9 24 VCC DQ 10 23 DQ DQ 11 22 DQ W 12 21 A A 13 20 A A 14 19 A A 15 18 A A 16 17 NC A A PIN NAMES D0 COLUMN I/O COLUMN DECODER INPUT DATA CONTROL DQ A A A A A A A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address W . . . . . . . . . . . . . . . . . . . . . . . . . Write Enable E . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable G . . . . . . . . . . . . . . . . . . . . . . . Output Enable DQ . . . . . . . . . . . . . . . . . . . Data Input/Output VCC . . . . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . . . . . . . No Connection E W G This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. REV 1 10/9/96 Motorola, Inc. 1996 MOTOROLA FAST SRAM MCM6706BR 1 TRUTH TABLE E G W Mode I/O Pin Cycle H L L L X H L X X H H L Not Selected Read Read Write High–Z High–Z Dout Din — — Read Cycle Write Cycle ABSOLUTE MAXIMUM RATINGS (See Note) Symbol Value Unit VCC – 0.5 to + 7.0 V Vin, Vout – 0.5 to VCC + 0.5 V Output Current Iout ± 30 mA Power Dissipation PD 2.0 W Temperature Under Bias Tbias – 10 to + 85 °C Operating Temperature TA 0 to + 70 °C Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained. Storage Temperature — Plastic Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Supply Voltage (Operating Voltage Range) VCC 4.5 5.0 5.5 V Input High Voltage VIH 2.2 — VCC + 0.3* V Input Low Voltage VIL – 0.5** — 0.8 V Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC) Ilkg(I) — ± 1.0 µA Output Leakage Current (E = VIH or G = VIH, Vout = 0 to VCC) Ilkg(O) — ± 1.0 µA Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V * VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA. ** VIL (min) = – 0.5 V dc @ 30.0 mA; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA. DC CHARACTERISTICS Parameter POWER SUPPLY CURRENTS Parameter Symbol –6 –7 –8 Unit Notes AC Active Supply Current (Iout = 0 mA, VCC = max, f = fmax) ICCA 215 205 195 mA 1, 2, 3 AC Standby Current (E = VIH, VCC = max, f = fmax) ISB1 95 85 75 mA 1, 2, 3 CMOS Standby Current (VCC = max, f = 0 MHz, E ≥ VCC – 0.2 V, Vin ≤ VSS, or ≥ VCC – 0.2 V) ISB2 20 20 20 mA NOTES: 1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V). 2. All addresses transition simultaneously low (LSB) and then high (MSB). 3. Data states are all zero. MCM6706BR 2 MOTOROLA FAST SRAM CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Symbol Max Unit Address Input Capacitance Cin 5 pF Control Pin Input Capacitance (E, G, W) Cin 6 pF Cout 6 pF Parameter I/O Capacitance AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1a READ CYCLE (See Notes 1 and 2) 6706BR–6 Parameter Symbol Min Max 6706BR–7 Min Max 6706BR–8 Min Max Unit Notes 3 Read Cycle Time tAVAV 6 — 7 — 8 — ns Address Access Time tAVQV — 6 — 7 — 8 ns Chip Enable Access Time tELQV — 6 — 7 — 8 ns Output Enable Access Time tGLQV — 4 — 4 — 4 ns Output Hold from Address Change tAXQX 3 — 3 — 3 — ns Chip Enable Low to Output Active tELQX 3 — 3 — 3 — ns 4 ,5, 6 Chip Enable High to Output High–Z tEHQZ — 3 — 3.5 — 3.5 ns 4, 5, 6 Output Enable Low to Output Active tGLQX 0 — 0 — 0 — ns 4, 5, 6 Output Enable High to Output High–Z tGHQZ — 3 — 3.5 — 3.5 ns 4, 5, 6 NOTES: 1. W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All read cycle timing is referenced from the last valid address to the first transitioning address. 4. At any given voltage and temperature, tEHQZ max < tELQX min, and tGHQZ max < tGLQX min, both for a given device and from device to device. 5. Transition is measured 200 mV from steady–state voltage with load of Figure 1b. 6. This parameter is sampled and not 100% tested. 7. Device is continuously selected (E = VIL, G = VIL). 8. Addresses valid prior to or coincident with E going low. TIMING LIMITS +5 V 480 Ω OUTPUT Z0 = 50 Ω RL = 50 Ω OUTPUT 255 Ω 5 pF VL = 1.5 V (a) (b) The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. Figure 1. AC Test Loads MOTOROLA FAST SRAM MCM6706BR 3 READ CYCLE 1 (See Note 7) tAVAV A (ADDRESS) tAXQX Q (DATA OUT) DATA VALID PREVIOUS DATA VALID tAVQV READ CYCLE 2 (See Note 8) tAVAV A (ADDRESS) tELQV E (CHIP ENABLE) tEHQZ tELQX G (OUTPUT ENABLE) tGHQZ tGLQV tGLQX Q (DATA OUT) DATA VALID tAVQV MCM6706BR 4 MOTOROLA FAST SRAM WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) 6706BR–6 Parameter 6706BR–7 6706BR–8 Symbol Min Max Min Max Min Max Unit Notes tAVAV 6 — 7 — 8 — ns 3 Address Setup Time tAVWL 0 — 0 — 0 — ns Address Valid to End of Write tAVWH 6 — 7 — 8 — ns Write Pulse Width tWLWH, tWLEH 6 — 7 — 8 — ns Data Valid to End of Write tDVWH 3 — 3.5 — 3.5 — ns Data Hold Time tWHDX 0 — 0 — 0 — ns Write Low to Data High–Z tWLQZ — 3.5 — 3.5 — 3.5 ns 4, 5, 6 Write High to Output Active tWHQX 3 — 3 — 3 — ns 4, 5, 6 Write Cycle Time Write Recovery Time tWHAX 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All write cycle timings are referenced from the last valid address to the first transitioning address. 4. Transition is measured 200 mV from steady–state voltage with load of Figure 1b. 5. Parameter is sampled and not 100% tested. 6. At any given voltage and temperature, tWLQZ max is < tWHQX min both for a given device and from device to device. WRITE CYCLE 1 tAVAV A (ADDRESS) tAVWH tWHAX E (CHIP ENABLE) tWLEH tWLWH W (WRITE ENABLE) tAVWL tDVWH D (DATA IN) tWHDX DATA VALID tWLQZ Q (DATA OUT) HIGH–Z HIGH–Z tWHQX MOTOROLA FAST SRAM MCM6706BR 5 WRITE CYCLE 2 (E Controlled, See Notes 1 and 2) 6706BR–6 Parameter 6706BR–7 6706BR–8 Symbol Min Max Min Max Min Max Unit Notes tAVAV 6 — 7 — 8 — ns 3 Address Setup Time tAVEL 0 — 0 — 0 — ns Address Valid to End of Write tAVEH 6 — 7 — 8 — ns Chip Enable to End of Write tELWH, tELEH 5 — 6 — 6 — ns Data Valid to End of Write tDVEH 3 — 3.5 — 3.5 — ns Data Hold Time tEHDX 0 — 0 — 0 — ns Write Recovery Time tEHAX 0 — 0 — 0 — ns Write Cycle Time 4,5 NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All write cycle timing is referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition. 5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition. WRITE CYCLE 2 tAVAV A (ADDRESS) tAVEH tELEH E (CHIP ENABLE) tELWH tAVEL tEHAX W (WRITE ENABLE) tDVEH D (DATA IN) tEHDX DATA VALID HIGH–Z Q (DATA OUT) ORDERING INFORMATION (Order by Full Part Number) MCM 6706BR X X XX Motorola Memory Prefix Shipping Method (R = Tape and Reel, Blank = Rails) Part Number Speed (6 = 6 ns, 7 = 7 ns, 8 = 8 ns) Package (J = 300 mil SOJ) Full Part Numbers — MCM6706BRJ6 MCM6706BRJ6R MCM6706BR 6 MCM6706J7 MCM6706BRJ7R MCM6706BRJ8 MCM6706BRJ8R MOTOROLA FAST SRAM PACKAGE DIMENSIONS 32–LEAD 300 MIL SOJ CASE 857–02 F 32 PL 0.17(0.007) 32 17 1 M D 32 PL 0.17(0.007) P 0.17(0.007) S B 16 -AL G DETAIL Z A S S NOTE 5 S A S -B-X- K S NOTE 4 NOTE 3 E C 0.10 (0.004) -T- SEATING PLANE R 0.25 (0.010) S RADIUS S B S NOTE 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DATUM PLANE -X- LOCATED AT TOP OF MOLD PARTING LINE AND COINCIDENT WITH TOP OF LEAD, WHERE LEAD EXITS BODY. 4. TO BE DETERMINED AT PLANE -X-. 5. TO BE DETERMINED AT PLANE -T-. 6. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 7. 857-01 IS OBSOLETE, NEW STANDARD 857-02. DIM A B C D E F G K L N P R S MILLIMETERS MIN MAX 20.83 21.08 7.50 7.74 3.26 3.75 0.41 0.50 2.24 2.48 0.67 0.81 1.27 BSC 0.89 1.14 0.64 BSC 0.76 1.14 8.38 8.64 6.60 6.86 0.77 1.01 INCHES MIN MAX 0.820 0.830 0.295 0.305 0.128 0.148 0.016 0.020 0.088 0.098 0.026 0.032 0.050 BSC 0.035 0.045 0.025 BSC 0.030 0.045 0.330 0.340 0.260 0.270 0.030 0.040 Motorola reserves the right to make changes without further notice to any products herein. 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