Revised February 1999 MM74HC148 8-3 Line Priority Encoder General Description The MM74HC148 priority encoder utilizes advanced silicon-gate CMOS technology. It has the high noise immunity and low power consumption typical of CMOS circuits, as well as the speeds and output drive similar to LB-TTL. This priority encoder accepts 8 input request lines 0–7 and outputs 3 lines A0–A2. The priority encoding ensures that only the highest order data line is encoded. Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry. All data inputs and outputs are active at the low logic level. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Features ■ Typical propagation delay: 13 ns ■ Wide supply voltage range: 2V–6V Ordering Code: Order Number MM74HC148M MM74HC148MTC MM74HC148N Package Number M16A MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Inputs Pin Assignments for DIP, SOIC and TSSOP Outputs EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO H X X X X X X X X H H H H L H H H H H H H H H H H H H L L X X X X X X X L L L L L H L X X X X X X L H L L H L H L X X X X X L H H L H L L H L X X X X L H H H L H H L H L X X X L H H H H H L L L H L X X L H H H H H H L H L H L X L H H H H H H H H L L H L L H H H H H H H H H H L H H = HIGH L = LOW X = Irrelevant © 1999 Fairchild Semiconductor Corporation DS009390.prf www.fairchildsemi.com MM74HC148 8-3 Line Priority Encoder October 1987 MM74HC148 Schematic Diagram www.fairchildsemi.com 2 MM74HC148 Logic Diagram 3 www.fairchildsemi.com MM74HC148 Absolute Maximum Ratings(Note 1) Recommended Operation Conditions (Note 2) −0.5 to +7.0V Supply Voltage (VCC ) DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT) −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK) ±20 mA DC Output Current, per pin (IOUT) ±25 mA (VIN, VOUT) Operating Temperature Range (TA) Power Dissipation (PD) 600 mW S.O. Package only 500 mW Max Units 2 6 V 0 VCC V −40 +85 °C Input Rise or Fall Times −65°C to +150°C (Note 3) Min DC Input or Output Voltage ±50 mA DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Supply Voltage (VCC) (tr, tf) VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Lead Temperature (TL) (Soldering 10 seconds) 260°C Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating—plastic “N” package: −12 mW/°C from 65°C to 85°C. DC Electrical Characteristics Symbol VIH VIL VOH Parameter Conditions (Note 4) VCC TA = 25°C Typ TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Units Minimum HIGH Level 2.0V 1.5 1.5 1.5 V Input Voltage 4.5V 3.15 3.15 3.15 V 6.0V 4.2 4.2 4.2 V Maximum LOW Level 2.0V 0.5 0.5 0.5 V Input Voltage 4.5V 1.35 1.35 1.35 V 6.0V 1.8 1.8 1.8 V Minimum HIGH Level VIN = V IH or VIL Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V |IOUT| ≤ 4.0 mA 4.5V 4.7 3.96 3.84 3.7 V |IOUT| ≤ 5.2 mA 6.0V 5.2 5.48 5.34 5.2 V VIN = V IH or VIL VOL Maximum LOW Level VIN = V IH or VIL Output Voltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V V VIN = V IH or VIL IIN |IOUT| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 |IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V VIN = V CC or GND 6.0V ±0.1 ±1.0 ±1.0 µA Maximum Quiescent VIN = V CC or GND 6.0V 8.0 80 160 µA Supply Current IOUT = 0 µA Maximum Input Current ICC Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. www.fairchildsemi.com 4 MM74HC148 AC Electrical Characteristics Symbol tPHL, tPLH Parameter Conditions Typ Maximum Propagation Delay, Guaranteed Limits 14 Units ns Any Input to Any Output AC Electrical Characteristics VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol Parameter Conditions tPHL, tPLH Inputs 0–7 2.0V to Outputs 4.5V A0, A1, A2 6.0V tPHL, tPLH Inputs 0–7 4.5V Output EO 6.0V 4.5V Output GS 6.0V 4.5V A0, A1, A2 6.0V tf, tr Cpd 17 17 2.0V to 4.5V Output GS 6.0V tPHL, tPLH Input EI 15 2.0V to Outputs tPHL, tPLH Input EI 14 2.0V to tPHL, tPLH Input EI Typ 2.0V to tPHL, tPLH Inputs 0–7 TA = 25°C VCC 12 2.0V to 4.5V Output EO 6.0V Maximum 2.0V Output Rise 4.5V and Fall Time 6.0V 12 7 Power Dissipation TA = −40°C to +85°C TA = −55°C to +125°C Guaranteed Limits Units 140 175 210 28 35 42 ns 24 30 36 ns 140 175 210 ns 28 35 42 ns 24 30 36 ns 160 200 240 ns 32 40 48 ns 27 34 41 ns 160 200 240 ns 32 40 48 ns 27 34 41 ns 100 125 150 ns 20 25 30 ns 17 21 26 ns 100 125 150 ns 20 25 30 ns 17 21 26 ns 75 95 110 ns 15 19 22 ns 13 16 19 52 ns ns pF Capacitance (Note 5) Cin Maximum Input 5 10 10 10 pF Capacitance Note 5: Cpd determines the no load dynamic power consumption, and the no load dynamic current consumption. 5 www.fairchildsemi.com MM74HC148 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A www.fairchildsemi.com 6 MM74HC148 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 7 www.fairchildsemi.com MM74HC148 8-3 Line Priority Encoder Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.