MP6400 Low Quiescent Current Programmable-Delay Supervisory Circuit The Future of Analog IC Technology DESCRIPTION FEATURES The MP6400 family is the microprocessor (µP) supervisory circuit which can monitor and provide reset function for system voltages from 0.4V. When either the SENSE voltage falls below its threshold (VIT) or the voltage of manual reset ( ) is pulled to a logic low, the signal will be asserted. The reset voltage can be factory-set for standard voltage rails from 0.9V to 5V, while the MP6400DG(J)01 reset voltage is adjustable with an external resistor divider. When SENSE voltage and is driven to a exceed their thresholds, logic high after a user-programmable delay time. • R M • • T E S E R T R E M S E R R M • • • • • • T E S E R Fixed Threshold Voltages for Standard Voltage Rails From 0.9V to 5V and Adjustable Voltage From 0.4V are Available Low Quiescent Current: 1.6uA typ Power-On Reset Generator with Adjustable Delay Time: 2.1ms to 10s High Threshold Accuracy: ±1% typ Manual Reset ( ) Input Open-Drain Output Immune to Short Negative SENSE voltage Guaranteed Reset Valid to VCC=0.8V 6 Pin TSOT23 and 2mm×2mm QFN APPLICATIONS The MP6400 has a very low quiescent current of 1.6μA typically, which makes it ideal suitable for battery-powered applications. It provides a precision reference to achieve ±1% threshold accuracy. The reset delay time can be selected by a capacitor which is connected between CDELAY and GND, allowing the user to select any delay time from 2.1ms to 10s. 380ms delay time is selected by connecting the CDELAY pin to VCC, while 24ms delay time by leaving the CDELAY pin float. MP6400 is available in TSOT23 and 2mm×2mm 6-pin QFN packages. • • • • • DSP or Micro controller Applications Laptop/Desktop Computers PDAs/Hand-Held Products Portable/Battery-Powered Products FPGA/ASIC Applications All MPS parts are lead-free and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION VCC R1 VCC Microprocessor SENSE R3 MP6400 C1 Microcontroller C2 R2 MR GND DSP RESET CDELAY C3 RESET GND CDELAY MP6400 Rev. 1.0 9/7/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 1 TM MP6400 -- LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT ORDERING INFORMATION Part Number* MP6400DG-01 MP6400DG-09 MP6400DG-12 MP6400DG-15 MP6400DG-25 MP6400DG-30 MP6400DG-33 MP6400DJ-01 MP6400DJ-09 MP6400DJ-12 MP6400DJ-15 MP6400DJ-25 MP6400DJ-30 MP6400DJ-33 Package QFN6 (2x2mm) TSOT23-6 Top Marking Free Air Temperature (TA) 5B AD AC 6V 4V 9S 9R 4B AAG AAF 6V 4V 8S 3S –40°C to +85°C *For Tape & Reel, add suffix –Z (e.g. MP6400DG–XX-Z); For RoHS compliant packaging, add suffix –LF (e.g. MP6400DG–XX-LF–Z). * For other versions, contact factory for availability. PACKAGE REFERENCE TOP VIEW TOP VIEW VCC 1 6 RESET SENSE 2 5 GND CDELAY 3 4 MR QFN6 (2mm x 2mm) MP6400 Rev. 1.0 9/7/2012 RESET 1 6 VCC GND 2 5 SENSE MR 3 4 CDELAY TSOT23-6 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 2 TM MP6400 -- LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT ABSOLUTE MAXIMUM RATINGS (1) Recommended Operating Conditions Supply Voltage VCC ......................... -0.3 to 6.5 V CDELAY Voltage VCDELAY ....... –0.3V to VCC + 0.3V SENSE Voltage VSENSE ....................–0.3V to 6V All Other Pins ..............................–0.3V to +6.5V RESET Current IRESET ................................ 5mA Thermal Resistance Continuous Power Dissipation (TA = +25°C) (2) QFN6 (2mmx2mm) .................................... 2.5W TSOT23-6 ................................................ 0.57W Junction Temperature ...............................150°C Lead Temperature ....................................260°C Storage Temperature.............. –65°C to +150°C MP6400 Rev. 1.0 9/7/2012 (3) Supply Voltage VCC ............................1.8V to 6V Operating Junct. Temp (TJ)..... –40°C to +125°C (4) θJA θJC QFN6 (2mmx2mm) ................50 ...... 12 ... °C/W TSOT23-6 ..............................220 .... 110 .. °C/W Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7 4-layer board. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 3 TM MP6400 -- LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT ELECTRICAL CHARACTERISTICS 1.8V≤VCC≤6V, R3 = 100kΩ, C3 = 47pF, TA= -40°C to +85°C, Typical values are at TA=+25°C, unless otherwise noted. Parameters Symbol Condition VCC Supply Current (current into VCC pin) VCC = 3.3V, asserted. , CDELAY open Low-level Output Voltage not , T E S T E E R S ER RM ICC IR = Units 6 V 1.6 3.5 µA 1.85 12 µA 0.3 V 0.4 V 0.8 V ±1.0 ±2.0 % 1.5 3.5 VIT% T E S E Power-up Reset Voltage(5) Max A u 5 1 not VCC = 6V, asserted. , , CDELAY open 1.3V ≤ VCC < 1.8V, IOL = 0.4mA 1.8V ≤ VCC ≤ 6V, IOL = 1.0mA VOL (max) = 0.2V, VOL Typ 1.8 T E T S E E S R E RR M Input Supply Range Min Trise(Vcc)≥15µs/V Threshold VSENSE falling slowly VIT R VHYS Internal Pull-up Resistance Input Current at SENSE Pin ISENSE T E S E = 6V, R R M M VIH = 1.05 VIT, VIL = 0.95 VIT CDELAY = Open tw T E S E R CDELAY = VCC td (6) CDELAY = 150pF CDELAY = 10nF T E S E R R M Propagation Delay (6) nA µA not 300 nA 0.25VCC V V 17.5 µs 15 24 34 ms 230 380 530 ms 1.3 2.1 3 ms 61 102 142 ms tpHL1 VIH = 0.7 VCC, VIL = 0.25 VCC 160 ns tpHL2 VIH = 1.05 VIT, VIL = 0.95 VIT 17.5 µs T E S E R T E S E R Delay, T E S E R Note: 5) The lowest supply voltage (VCC) at which 6) Guaranteed by design. MP6400 Rev. 1.0 9/7/2012 2.4 0.7VCC VIH Transient kΩ +25 VIL Delay Time High to Low Level SENSE to -25 asserted Logic Low Input to 110 T E S E R MP6400DJ-01 VSENSE = VIT Fixed versions VSENSE = 6V VR T E S E R Leakage Current Logic High Input SENSE Maximum Duration 50 R M R M Negative-going Input Accuracy Hysteresis on VIT Pin becomes active. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 4 TM MP6400 -- LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT STANDARD VERSIONS (7) Product MP6400DG-01 MP6400DJ-01 MP6400DG-09 MP6400DJ-09 MP6400DG-12 MP6400DJ-12 MP6400DG-125 MP6400DJ-125 MP6400DG-15 MP6400DJ-15 MP6400DG-18 MP6400DJ-18 MP6400DG-25 MP6400DJ-25 MP6400DG-30 MP6400DJ-30 MP6400DG-33 MP6400DJ-33 MP6400DG-50 MP6400DJ-50 Package QFN TSOT23 QFN TSOT23 QFN TSOT23 QFN TSOT23 QFN TSOT23 QFN TSOT23 QFN TSOT23 QFN TSOT23 QFN TSOT23 QFN TSOT23 Top Mark 5B 4B AD AAG AC AAF Contact Factory Contact Factory 6V 6V Contact Factory Contact Factory 4V 4V 9S 8S 9R 3S Contact Factory Contact Factory Nominal Supply Voltage Threshold Voltage (VIT) Adjustable 0.4V 0.9V 0.84V 1.2V 1.12V 1.25V 1.16V 1.5V 1.40V 1.8V 1.67V 2.5V 2.33V 3.0V 2.79V 3.3V 3.07V 5.0V 4.65V Note: 7) In “MP6400DG(J)- _ _”, the “_ _” are placeholders for the monitored voltage levels of the devices. Desired monitored voltages are set by the suffix found in ordering information. MP6400 Rev. 1.0 9/7/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 5 TM MP6400 -- LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT PIN FUNCTIONS QFN Pin # TSOT Pin # Name Description T E S E R 4 3 3 4 2 5 1 6 R M 2 T E S E R 5 T E S E R 1 T E S E R 6 is an open drain signal which will be asserted when the SENSE voltage drops below a preset threshold or when the manual reset ( ) pin drops to a logic delay time is programmable from 2.1ms to 10s by using external low. The capacitors. A pull-up resistor bigger than 10k should be connected this pin to outputting a higher voltage than VCC is allowable. supply line, and the Ground. T E S E R ) can introduce another logic signal to control the . It is The manual reset ( internally connected to VCC through a 90kΩ resistor. Programmable reset delay time pin. When CDELAY connected to VCC through a resistor between 50kΩ and 200kΩ, a 380ms delay time is selected. When CDELAY CDELAY floated, the delay time is 24ms. A capacitor bigger than 150pF connected CDELAY to GND could be used to get the user’s programmable time from 2.1ms to 10s. SENSE pin is connected to the monitored system voltage. When the monitored SENSE is asserted. voltage is below desired threshold, VCC Supply voltage. A 0.1uF decoupling ceramic capacitor should be put close to this pin. T E S E R DETAIL DESCRIPTION R M T E S E R output remains asserted for a user’s programmable delay time. Two fixed delay times are user-selectable: 380ms delay time by connecting the CDELAY pin to VCC, and 24ms delay time by leaving the CDELAY pin float. Any delay time from 2.1ms to 10s could be gotten by connecting a capacitor between CDELAY and GND. The wide monitor voltage and programmable reset delay time make MP6400 product family suitable for a broad array of applications. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. T E S E R R M The MP6400 product family asserts a signal when either the SENSE pin voltage is lower than VIT or the manual reset ( ) is driven low. The MP6400 family can be monitored a fixed voltage from 0.9V to 5.0V, while the MP6400DG(J)-01 can monitor any voltage above 0.4V by adjusting the external resistor divider. ) and SENSE After both the manual reset ( voltages exceed their thresholds, the MP6400 Rev. 1.0 9/7/2012 T E S E R R M R M GND 6 TM MP6400 -- LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT TYPICAL PERFORMANCE CHARACTERISTICS VCC=3.3V, R3 = 100kΩ, C3 = 47pF, TA= -40°C to +85°C, Typical values are at TA=+25°C, unless otherwise noted. Supply Current vs. VCC Reset Delay Time vs. CDELAY 3 +85 OC 2 1 +25 OC -40 C O 2.5 3.5 4.5 10 1 0.1 0.01 0.001 0.0001 0.001 0.01 0 1.5 MAXIMUM SENSE TRANSIENT DURATION(us) 100 RESET DELAY TIME(s) SUPPLY CURRENT(uA) 4 5.5 V CC(V) 0.1 1 Reset Delay vs.Temperature (CDELAY=VCC) 26 24 22 20 0.401 440 0.4 420 60 80 380 30 40 50 0.398 0.397 360 -40 20 0.399 400 0.396 0.395 320 40 10 VIT vs. Temperature 460 340 20 0 VIT(V) RESET DELAY(ms) 28 0 1 SENSE THRESHOLD OVERDRIVE(%) (CDELAY=open) -20 10 10 Reset Delay vs.Temperature -40 100 CDELAY(uF) 30 RESET DELAY(ms) Maximum SENSE Transient Duration vs.SENSE Threshold Overdrive Voltage -20 0 20 40 60 80 -40 -20 0 20 40 60 80 IRESET vs. Low Level RESET Voltage 0.8 LOW LEVEL RESET VOLTAGE(V) 0.7 VCC=1.8V 0.6 0.5 0.4 VCC=3.3V 0.3 0.2 VCC=6V 0.1 0 0 5 10 15 IRESET(mA) MP6400 Rev. 1.0 9/7/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 7 TM MP6400 -- LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT FUNCTIONAL BLOCK DIAGRAM VCC VCC VCC VCC MP6400DJ-01 Adjustable Voltage 90k MR 0.4V SENSE RESET MR SENSE -- R1 Reset Logic Timer + MP6400DJ-XX 90k RESET Reset Logic Timer + R2 0.4V -CDELAY CDELAY GND GND Adjustable Voltage Version Fixed Voltage Version Figure 1—Functional Block Diagram TIMING DIAGRAM VCC 0.8V 0.0V RESET tD tD tD tD=Reset Delay =Undefined State SENSE VIT+VHYS VIT MR 0.7VCC 0.25VCC Time Figure 2—MP6400 Timing Diagram MP6400 Rev. 1.0 9/7/2012 T E S E R R M L L H H TRUTH TABLE SENSE > VIT 0 1 0 1 L L L H www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 8 TM MP6400 -- LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT APPLICATION INFORMATION T E S E R Reset Output Function The MP6400 output is typically connected to the input of a microprocessor, as shown in Figure 3. When is not asserted, a pull up resistor must be connected to hold this signal high. The voltage of reset signal is allowed to be higher than VCC (up to 6V) through a resistor pulling up from supply line. If the voltage is below 0.8V, output is undefined. This condition can be ignored generally because that most microprocessors do not function at this state. are higher than their When both SENSE and threshold voltage, output holds logic high. Once either of the two drops below their threshold, will be asserted. T E S E R connects to the SENSE pin. The circuit can be used to monitor any voltage higher than 0.4V. T E S E R VSEN VOUT VCC VIT = (1+ R1 R1 )0.4 R2 MP6400DJ-01 T E S E R RESET SENSE R M 1nF R2 GND T E S E R T E S E R VCC RESET GND CDELAY RESET 47pF GND R M MR T E S E R Microcontroller 1nF T E S E DSP 100k RR M Microprocessor SENSE R2 R M T E S E R R1 0.1uF Monitor Multiple System Voltages The manual reset ( ) can introduce another logic signal to control the . When is a will be asserted. After logic low (0.25VCC), are above their thresholds, both SENSE and will be driven to a logic high after a reset is internally connected to VCC delay time. The through a 90kΩ resistor so this pin can float. See how multiple system voltages are monitored by in Figure 5. If the signal on isn’t up to VCC, there will be an additional current through internal 90kΩ pull up resistor. A logic-level FET can be used to minimize the leakage, as shown in Figure 6. R M VCC Figure 4—MP6400DJ-01 Monitoring a UserDefined Voltage R M Figure 3—Typical Application of MP6400 with Microprocessor 3.3V 1.2V T E S E R From the point that is again logic high and SENSE is above VIT + VHYS (the threshold hysteresis), will be driven to a logic high after a reset delay time. The reset delay time is programmable by CDELAY pin. Due to the finite impedance of pin, the pull up resistor should be bigger than 10kΩ. R M R M CDELAY T E S E R MP6400DJ-12 RESET CDELAY GND SENSE VCC MP6400DJ-33 MR RESET CDELAY GND VI/O VCORE DSP RESET GND T E S E R Monitor a Voltage The SENSE input pin is connected to the monitored system voltage directly or through a resistor network (on MP6400DJ-01). When the voltage on the pin is below VIT, is asserted. A threshold hysteresis will prevent the chip from responding perturbation on SENSE pin. A 1nF to 10nF bypass capacitor should be put on this pin to increase its immunity to noise. A typical application of the MP6400DJ-01 is shown in Figure 4. Two external resistors form a voltage divider from monitored voltage to GND. Its tap SENSE VCC MP6400 Rev. 1.0 9/7/2012 Figure 5— MP6400 Family Monitoring Multiple System Voltages www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 9 TM MP6400 -- LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT 3.3V R M VCC The reset delay time is determined by the charge time of external capacitor. While SENSE is above VIT and is a logic high, the internal 140nA current source is enabled and starts to charge the capacitor to set the delay time. When the capacitor voltage rises to 1.13V, the is deasserted. The capacitor will be discharged when is again asserted. Stray capacitance the may cause errors of the delay time. A ceramic capacitor with low leakage is strongly recommended. SENSE T E S E R MR RESET T E S E R GND Figure 6—Minimizing ICC When MR Signal isn’t over VCC by External MOSFET 3.3V 3.3V SENSE SENSE VCC VCC MP6400DJ-33 MP6400DJ-33 RESET RESET 50k CDELAY CDELAY GND GND 24ms Delay (b) 380ms Delay (a) 3.3V SENSE Voltage Transients Immunity The MP6400 can be immune to SENSE pin short negative transient. The maximum immune duration is 17us while overdrive is 5%. A shorter negative transient can not assert the output. The effective duration is relative to the threshold overdrive, as shown in Figure 8. T E S E R Programmable Reset Delay Time The reset delay time can be programmed by CDELAY configure. When CDELAY is connected to VCC through a resistor between 50kΩ and 200kΩ, the delay time is 380ms. When CDELAY floated, the delay time is 24ms. In addition, a capacitor connected CDELAY to GND could be used to get the user’s programmable delay time from 2.1ms to 10s. The three configures can be found in Figure 7(a)(b)(c). Maximum SENSE Transient Duration vs.SENSE Threshold Overdrive Voltage MAXIMUM SENSE TRANSIENT DURATION(us) MP6400DJ-33 100 10 1 0 10 20 30 40 50 SENSE THRESHOLD OVERDRIVE(%) SENSE VCC MP6400DJ-33 Figure 8—Maximum Transient Duration vs. Sense Threshold Overdrive Voltage RESET CDELAY CDELAY GND (c) Figure 7—Programmable Configurations to the Reset Delay Time The external capacitor CDELAY must be larger than 150pF. For a given delay time, the capacitor value can be calculated using the following equation: C DELAY (nF) = [t D (s) − 4.99 × 10 −4 (s)] × 107 MP6400 Rev. 1.0 9/7/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 10 TM MP6400 -- LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT PACKAGE INFORMATION QFN6 (2mm x 2mm) PIN 1 ID MARKING 1.90 2.10 0.30 0.40 0.20 0.30 1.90 2.10 PIN 1 ID INDEX AREA 0.65 0.85 PIN 1 ID SEE DETAIL A 1 6 1.25 1.45 0.65 BSC 3 4 TOP VIEW BOTTOM VIEW 0.80 1.00 0.20 REF PIN 1 ID OPTION A 0.30x45º TYP. PIN 1 ID OPTION B R0.20 TYP. 0.00 0.05 SIDE VIEW DETAIL A NOTE: 1.90 0.70 0.70 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX. 4) JEDEC REFERENCE IS MO-229, VARIATION VCCC. 5) DRAWING IS NOT TO SCALE. 0.25 1.40 0.65 RECOMMENDED LAND PATTERN MP6400 Rev. 1.0 9/7/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 11 TM MP6400 -- LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT TSOT23-6 NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP6400 Rev. 1.0 9/7/2012 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. 12