MP7226 BiCMOS Fixed, Quad, Voltage Output, Single or Dual Supply 8-Bit Digital-to-Analog Converter FEATURES • • • • • • • • • • • APPLICATIONS MPS Pioneered Segmented DAC Approach • Function Generators Four 8-Bit DACs with Buffer Amplifiers • Automatic Test Equipment Bipolar Amplifier Inputs for Low Noise and Drift • Process Controls Operates with Single or Dual Supplies BENEFITS µP Compatible (95ns WR) No External Adjustments Required • Reduced Board Space; Lower System Cost Power-on-Reset Function • Reduced System Errors due to Excellent DAC-to-DAC Specified for 5 to 15 V Operation Matching and Tracking ESD Protection: 2000 Volts Minimum • Easy to Design with Microprocessors Latch-Up Proof • Stable, High Reliability through Advanced Processing Octal Available: MP7228 • Lower 1/f Noise Increases Useful Dynamic Range The MP7226 is manufactured using advanced thin film resistors on a double metal BiCMOS process. The MP7226 incorporates a unique bit decoding technique yielding lower glitch, higher speed and excellent accuracy over temperature and time. The MP7226 maintains 8-Bit accuracy over the full operating temperature range without laser trim or external adjustments. GENERAL DESCRIPTION The MP7226 contains four 8-bit voltage-output Digital-toAnalog Converters, with BiCMOS output buffer amplifiers and interface logic on a monolithic chip. Separate on-chip latches are provided for each of the four D/A converters. The control logic is speed compatible with most 8-bit microprocessors. All digital inputs are TTL/CMOS(5V) compatible. SIMPLIFIED BLOCK DIAGRAM VREF MSB DATA (8 BIT) LSB D A T A B U S VDD LATCH 1 DAC 1 – 1 + VOUT1 LATCH 2 DAC 2 – 2 + VOUT2 LATCH 3 DAC 3 – 3 + VOUT3 LATCH 4 DAC 4 – + 4 VOUT4 WR A1 A0 CONTROL LOGIC VSS Rev. 2.00 1 AGND DGND MP7226 ORDERING INFORMATION Package Type Temperature Range Part No. INL (LSB) DNL (LSB) Full Scale Error (LSB) Plastic Dip –40 to +85°C MP7226KN 1 1/2 1 Plastic Dip –40 to +85°C MP7226LN* 1/2 –40 to +85°C 1/2 1/2 PLCC MP7226KP 1 1 PLCC –40 to +85°C 1/2 MP7226LP* 1/2 1/2 SOIC –40 to +85°C 1/2 MP7226KS 1 1 SOIC –40 to +85°C 1/2 MP7226LS* 1/2 1/2 1/2 *Contact factory for availability. PIN CONFIGURATIONS See Packaging Section for Package Dimensions 3 VOUT2 VOUT1 VSS VREF AGND DGND DB7 (MSB) DB6 DB5 DB4 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VOUT3 VOUT4 VDD A0 A1 WR DB0 (LSB) DB1 DB2 DB3 20 Pin PDIP (0.300”) N20 1 20 2 19 3 4 5 6 17 See Pin Out at Far Left 6 15 8 13 9 12 10 11 19 5 16 14 20 18 17 7 1 4 18 See Pin Out at Left 2 7 15 8 14 9 20 Pin SOIC (Jedec, 0.300”) S20 16 10 11 12 13 20 Pin PLCC P20 PIN OUT DEFINITIONS PIN NO. NAME DESCRIPTION PIN NO. NAME DESCRIPTION 1 VOUT2 DAC 2 Voltage Output 11 DB3 Data Input Bit 3 2 VOUT1 DAC 1 Voltage Output 12 DB2 Data Input Bit 2 3 VSS Negative Power Supply (0 V to –5 V) 13 DB1 Data Input Bit 1 4 VREF Reference Input Voltage 14 DB0 Data Input Bit 0 (LSB) 5 AGND Analog Ground 15 WR Write (Active Low) 6 DGND Digital Ground 16 A1 DAC Address Bit 1 7 DB7 Data Input Bit 7 (MSB) 17 A0 DAC Address Bit 0 8 DB6 Data Input Bit 6 18 VDD Positive Power Supply (+5 to +15 V) 9 DB5 Data Input Bit 5 19 VOUT4 DAC 4 Voltage Output 10 DB4 Data Input Bit 4 20 VOUT3 DAC 3 Voltage Output Rev. 2.00 2 MP7226 ELECTRICAL CHARACTERISTICS Single or Dual Supply Operation (VDD = +10.8 V to 16.5 V, VSS = 0 V or –5 V 10%, AGND = 0 V, DGND = 0 V, VREF = +2 V to +10 V, RL = 2kΩ, CL = 100pF unless otherwise noted) Parameter Symbol Min N 8 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments STATIC PERFORMANCE Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) K L 8 Bits INL LSB 1 1/2 1 1/2 1/2 1/2 3/4 3/4 2 1 2 1 Full Scale Error3 K L 1 1/2 1 1/2 Zero Code Error K L 20 15 30 20 Differential Non-Linearity K L DNL Total Unadjusted Error2 K L Output Load Resistance 2 2 End Point Linearity Spec LSB All grades monotonic over full temperature range. LSB VDD = 15 V 10%, VREF = +10 V LSB VREF = +10 V typ. Tempco is 5 ppm/°C mV TA = 25°C typ. Tempco is 30µV/°C kΩ VOUT = +10 V DYNAMIC PERFORMANCE4 Voltage Output Slew Rate Voltage Output Settling Time 2 4 2 4 5 V/µs µs Digital Feedthrough 25 nVs Digital Crosstalk5 25 nVs VREF = +10 V; Settling Time to 1/2 LSB Code transition all 0s to all 1s VREF = 0 V, WR = VDD Code transition all 0s to all 1s VREF = +10 V, WR = 0 V REFERENCE INPUT Reference Input Range1 Reference Input Resistance Reference Input Capacitance4 RIN 1 2 AC Feedthrough 10 1 2 10 500 V kΩ pF –70 dB Limitation: VREF – VSS < 11 V Min RIN at Code 14910 Occurs when all DACs are loaded with all 1s VREF = 10 kHz, 5 V p-p sinewave DIGITAL INPUTS Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance4 Input Coding VINH VINL ILKG 2.4 2.4 0.8 1 8 0.8 1 8 V V µA pF VIN = 0 V or VDD Binary Rev. 2.00 3 MP7226 ELECTRICAL CHARACTERISTICS (CONT’D) Parameter Symbol Min 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments POWER SUPPLY VDD Range VSS Range (Dual Supplies)8 IDD 10.8 0 ISS (Dual Supplies) 16.5 –5.5 12 10.8 0 10 16.5 –5.5 14 V V mA 12 For specified performance For specified performance Outputs unloaded; VIN=VINL or VINH Outputs unloaded; VIN=VINL or VINH SWITCHING CHARACTERISTICS4, 6, 7 Address to WR Setup Time, t1 Address to WR Hold Time, t2 Data Valid to WR Setup Time, t3 Data Valid to WR Hold Time, t4 WR Pulse Width, t5 tAS tAH tDS tDH tWR 0 0 70 10 95 0 0 95 10 120 ns ns ns ns NOTES: 1 VOUT must be less than VDD by 3.5 V to ensure correct operation. 2 Total Unadjusted Error includes zero code error, relative accuracy and full-scale error. 3 Calculated after zero code error has been adjusted out. 4 Sample tested at 25°C to ensure compliance. 5 The glitch impulse transferred to the output of one converter (not adjusted) due to a change in the digital input code to another addressed converter. 6 All input rise and fall times are measured from 10% to 90% of +5 V, tR = tF = 5 ns. 7 Timing measurement reference level is (VINH + VINL)/2. Specifications are subject to change without notice Rev. 2.00 4 MP7226 ELECTRICAL CHARACTERISTICS Single & Dual 5 V Supply Operation (VDD = +5 V 5%, VSS = 0 V to –5 V 10%, VREF = +1.25 V, AGND = 0 V, DGND = 0 V, RL = 2kΩ, CL = 100pF unless otherwise noted) Parameter Symbol Min N 8 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments STATIC PERFORMANCE Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) K L Differential Non-Linearity K L 8 Bits INL LSB 2 1 2 1 1 1 1 1 DNL Total Unadjusted Error2 4 Full Scale Error3 K L 4 2 Zero Code Error 20 Output Load Resistance End Point Linearity Spec LSB All grades monotonic over full temperature range. LSB VDD = 5 V 5%, VREF = 1.25 V LSB VREF = +1.25 V 4 2 mV 2 kΩ VOUT = +10 V DYNAMIC PERFORMANCE4 Voltage Output Slew Rate Voltage Output Settling Time 2 4 V/µs µs 4 Digital Feedthrough 25 nVs Digital Crosstalk5 25 nVs VREF = +1.25 V; Settling Time to 1/2 LSB Code transition all 0s to all 1s VREF = 0 V, WR = VDD Code transition all 0s to all 1s VREF = +1.25 V, WR = 0 V REFERENCE INPUT Reference Input Range Reference Input Resistance Reference Input Capacitance4 RIN 1 2 AC Feedthrough 1.6 1 2 1.6 500 V kΩ pF –70 dB VOUT must be < VDD by 3.2V Occurs when all DACs are loaded with all 1s VREF = 10 kHz, 1/2 V p-p sinewave DIGITAL INPUTS Input High Voltage Input Low Voltage Input Leakage Current Input Capacitance4 Input Coding VINH VINL ILKG 2.4 2.4 0.8 1 8 0.8 1 8 V V µA pF VIN = 0 V or VDD Binary Rev. 2.00 5 MP7226 ELECTRICAL CHARACTERISTICS (CONT’D) Parameter Symbol Min 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments POWER SUPPLY VDD Range IDD 4.75 ISS (Dual Supplies) 5.25 8 4.75 6 5.25 8 V mA 6 For specified performance Outputs unloaded; VIN=VINL or VINH Outputs unloaded; VIN=VINL or VINH SWITCHING CHARACTERISTICS4, 6, 7 Address to WR Setup Time, t1 Address to WR Hold Time, t2 Data Valid to WR Setup Time, t3 Data Valid to WR Hold Time, t4 WR Pulse Width, t5 tAS tAH tDS tDH tWR 0 0 70 0 95 0 0 95 ns ns ns 120 ns NOTES: 1 VOUT must be less than VDD by 3.5 V to ensure correct operation. 2 Total Unadjusted Error includes zero code error, relative accuracy and full-scale error. 3 Calculated after zero code error has been adjusted out. 4 Sample tested at 25°C to ensure compliance. 5 The glitch impulse transferred to the output of one converter (not adjusted) due to a change in the digital input code to another addressed converter. 6 All input rise and fall times are measured from 10% to 90% of +5 V, tR = tF = 5 ns. 7 Timing measurement reference level is (VINH + VINL)/2. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2 VDD to AGND, DGND . . . . . . . . . . . . . . . . . . . . . . 0 to +17 V Digital Input Voltage to DGND . . . . . . . . –0.5 to VDD +0.5 V VREF to AGND, DGND . . . . . . . . . . . . . . –0.5 to VDD +0.5 V VSS to AGND, DGND . . . . . . . . . . . . . . . . . . . . . +0.5 to –7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V (Functionality Guaranteed +0.5 V) Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 seconds) . . . . . . +300°C Package Power Dissipation Rating to 75°C PDIP, SOIC, PLCC . . . . . . . . . . . . . . . . . . . . . . . . 900mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 12mW/°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. Rev. 2.00 6 MP7226 Decoding two bits to three, a 1% change in any one of the converter’s three decoded current sources affects the output by no more than 0.25% of full scale, compared with 0.5% in a conventional R-2R type CMOS DAC. D/A CONVERTER SECTION The MP7226 contains four matched, 8-bit, voltage-mode Digital-to-Analog Converters (DACs) which incorporate an MPS pioneered unique bit decoding technique. This decoding scheme reduces the maximum binary weight carried by any resistor switch, reducing the accuracy required of the switches and resistor network. The output voltages have the same polarity as the reference voltage, allowing single supply operation. The voltage reference range is from +2V to +10V. Each DAC uses a highly-stable, thin-film, ladder network and high-speed NMOS switches. Figure 1. shows a simplified circuit diagram for one channel. In the MP7226, the first three MSBs are decoded into three equal current sources, each contributing 25% of the full scale output current. – 2R 4R 4R 2R VOUT 2R 4R + 4R 4R 4R VREF AGND 2 to 3 Decoder Switch Drivers Shown for all 1s on DAC Figure 1. Simplified D/A Circuit Diagram VREF Input Output Buffer Amp The VREF and AGND are common to all four DACs and set the full-scale output. The input impedance of the VREF pin is the parallel combination of the four individual DAC reference impedances and is code dependent. This impedance varies from 2kΩ to 500kΩ. Therefore, it is very important that the external reference source output impedance is low enough so that its output voltage will not be affected by the varying digital code. Due to transient currents at the VREF input during digital code changes, a 0.1µF or greater decoupling capacitor on that VREF input is recommended. The input capacitance at the VREF pin is also code dependent and typically varies from less than 120pF to 350pF. Each D/A converter output is buffered by a unity gain noninverting BiCMOS amplifier which has slew rate greater than 2 V/ µs . The output buffer settles to 1/2 LSB in less than 4µs when driving a load of 2kΩ in parallel with 100pF with a full scale transition from 0V to +10V or from +10V to 0V . The buffers can drive 2kΩ and 500pF to 10V levels without oscillation. A simplified circuit diagram of the output buffer is shown in Figure 2. The Input stage is provided by BiCMOS PNP transistors with resulting lower input offset voltage, offset voltage drift over time and noise when compared to MOS process . The amplifier output stage uses a substrate NPN bipolar device to provide a low output impedance, high-output current capability. The MP7226 is specified for single or dual power supply operation, with only the buffer amplifier outputs using VSS supply current . Operating the MP7226 from dual supplies will improve the negative going output settling time near ground. In dual supply voltage operation , the output amplifier can sink 500µA when VOUT = 0 V. Each VOUT voltage can be represented by a digitally programmable voltage source using the following expression : VOUT = Dn X VREF/256 where Dn is the decimal equivalent to the digital input code and can vary from 0 to 255. Rev. 2.00 7 MP7226 VDD To DAC1 Latch Enable A0 To DAC2 Latch Enable 1 of 4 Decoder To DAC3 Latch Enable A1 To DAC4 Latch Enable VIN Output WR VSS AGND Figure 3. Input Control Logic Figure 2. Simplified Output Buffer Amplifiers The amplifiers outputs may be shorted to ground. However, the power dissipation of the package should not exceed the maximum limit. Digital Inputs All of the digital inputs to this DAC maintain TTL level interface compatibility and can also be driven directly with 5V CMOS logic inputs. The digital inputs are ESD protected to a rating of 2000 volts. WR A1 A0 Operation H X X L L L No Operation; Device Not Selected DAC 1 Transparent L L DAC 1 Latched L L H DAC 2 Transparent L H L DAC 3 Transparent L H H DAC 4 Transparent Table 1. Truth Table Digital Interface Logic The MP7226 allows direct interface to most microprocessor buses without additional interface circuitry. tAS Figure 3. shows the input control logic circuit diagram and Table 1. shows the control logic truth table and operation for WR, A1, A0. The address lines A0, and A1 determine which DAC will accept the input data. The WR input determines whether the selected DAC is transparent (output follows the input), latched, or no operation. The WR input will also inhibit power on reset of the DAC latches to 0, if its initial state = 0 after 5 µs of power. tAH 5V Address 0V WR tWR 5V 0V tDS Data Figure 4. shows the write cycle timing diagram. When the WR signal is low, the input latch of the selected DAC is transparent, and the DAC’s output corresponds to the value present on the data bus. On some data buses, data is not always valid for the entire period that the WR signal is low and can cause unwanted data at the output. Ensuring that the write pulse (WR) conforms to the data hold time, (t4) spec will prevent this problem. tDH VINH VINL 5V 0V NOTE: When the WR signal is low, the input latch of the selected DAC is transparent and any invalid data at this time will cause erroneous output. Figure 4. Write Cycle Timing Diagram Rev. 2.00 8 MP7226 APPLICATIONS INFORMATION Digital Input Power On Reset 1 1 1 1 1 1 1 1 At power up, all inputs are reset to 0 V if WR = 1. For WR = 0, the addressed DAC will receive input data. 1 0 0 0 0 0 0 1 Power Supply 1 0 0 0 0 0 0 0 The MP7226 can operate with either a single or dual power supply. Improved zero-code settling error can be obtained by using dual power supplies. The dual power supply specifications are a positive supply (VDD) range of +10.5V to +16.5V, and a –5V supply (VSS) . The single power supply specifications are a positive supply (VDD) range of +10.5V to +16.5V, or range of +4.75V to 5.5V . The specified reference voltage (VREF) range under these conditions is from +2V to VDD –4V. For those applications requiring +10V at the output (VREF = +10V), VDD must be +14V minimum to meet data sheet limits . 8-bit performance is guaranteed for single supply operation (VSS = 0V); however, zero code output sink capability is improved with VSS = –5V. For adequate DAC and Buffer operation, VREF must always be below VDD by at least 3.5V. 0 1 1 1 1 1 1 1 Analog Output, VOUT 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Table 2. Unipolar Code Table Digital Input Power Supply Decoupling 11111111 The Power Supplies used with the MP7226 should be well regulated and filtered. Local power supply decoupling consisting of a 10µF tantalum capacitor in parallel with a 0.01µF ceramic is recommended. The decoupling capacitors should be connected between the VDD and AGND, and between VSS and AGND if VSS = –5V. 10000001 10000000 01111111 Unipolar Output Operation 00000001 In this configuration, the reference voltage is the same polarity as the output voltage. Since the reference voltage must always be positive with respect to GND, the output can only be 0 or positive. 00000000 Analog Output 0V Table 3. Bipolar Code Table Table 2. shows the code relationship for the part in unipolar operation Rev. 2.00 9 MP7226 Bipolar Binary Operation VREF R1 The Bipolar Mode configuration for each DAC requires one external op-amp and two resistors per channel. R2 VREF DAC VOUT – + Figure 5. shows a typical Bipolar Operation circuit using the MP7226. Table 3. shows the code relationship for the circuit of Figure 5. assuming R1 = R2 . VOUT – + AC Reference Signal VSS An AC signal can be applied to the reference of the MP7226 for multiplying capability within the upper (+10V) and lower (+2V) limits of the reference voltage input, with either single or dual supplies . This signal must be level shifted or AC coupled with proper bias level before being applied to the reference input. Figure 6. shows techniques for applying an AC signal to the MP7226. Since all four DACs share a common reference, they will all share this AC modulated reference. Input frequencies up to 50kHz will typically be distorted less than 0.1% . AGND VOUT = Dn X VREF X (1+R2/R1) – VREF X R2/R1 if R1 = R2 VOUT = VREF X (2Dn – 1) Where Dn is the digital input code and can vary from 0 to 255 Figure 5. Bipolar Output Circuit +15 V +10 V +4 V C AC Reference Input R1 DC Offset + R2 +2 V VREF – VDD –4 V DAC VOUT – + DCOFFSET = VDD (+15) X R2/R1+R2 VSS –5 V or GND Figure 6. AC Reference Input Signal Circuit (AC Couple) Rev. 2.00 10 AGND MP7226 R R – R DAC Output VOUT VOUT = Dn X VREF + VOFFSET where Dn is the digital input code and can vary 0 to 255 VOUT VOUT = Dn1 X VREF + Dn2 X VREF where Dn is the digital input code and can vary 0 to 255 + R VOFFSET R R – DAC Output1 R DAC Output2 R + Figure 7. Digitally Programmable Offset Adjustment Circuits +15 V AC Reference Input + VREF – DAC VDD – + VOUT DAC or DC Voltage VSS –5 V or GND AGND Figure 8. Digitally Programmable AC Reference Input Signal Circuit (DC Couple) buffer, the DAC output will begin to increment in a normal operation. Offsetting DAC Outputs Figure 7. shows examples of offset circuits. 5V Operation DAC offset effects The MP7226 can be operated with a single power supply (VDD = +5V ) or dual power supplies ( VDD = +5V and VSS = –5V) . The reference voltage range is reduced along with Some performance parameter degradation. However the DNL of each DAC remains at 1 LSB guaranteeing monotonicity. When using the device in single supply applications, and minimum reference voltage, there is a possibility that the DAC output will not change when the code is incremented from 0. Once the DAC has reached the offset voltage of the output Rev. 2.00 11 MP7226 PERFORMANCE CHARACTERISTICS Graph 1. Power Supply Current vs. Temperature Graph 2. Relative Accuracy vs. Digital Code Rev. 2.00 12 MP7226 20 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) N20 S 20 11 1 10 Q1 E1 E D A1 Seating Plane A L B e B1 α MILLIMETERS INCHES SYMBOL A MIN MAX MIN MAX –– 0.200 –– 5.08 A1 0.015 –– 0.38 –– B 0.014 0.023 0.356 0.584 B1 (1) 0.038 0.065 0.965 1.65 C 0.008 0.015 0.203 0.381 D 0.945 1.060 24.0 26.92 E 0.295 0.325 7.49 8.26 E1 0.220 0.310 5.59 7.87 e 0.100 BSC 2.54 BSC L 0.115 0.150 2.92 3.81 α 0° 15° 0° 15° Q1 0.055 0.070 1.40 1.78 S 0.040 0.080 1.02 2.03 Note: (1) The minimum limit for dimensions B1 may be 0.023” (0.58 mm) for all four corner leads only. Rev. 2.00 13 C MP7226 20 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S20 D 20 11 E H 10 h x 45° C A Seating Plane B e α A1 L INCHES SYMBOL MILLIMETERS MIN MAX MIN A 0.097 0.104 2.464 A1 0.0050 0.0115 0.127 0.292 B 0.014 0.019 0.356 0.483 C 0.0091 0.0125 0.231 0.318 D 0.500 0.510 12.70 12.95 E 0.292 0.299 7.42 7.59 e 0.050 BSC MAX 2.642 1.27 BSC H 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.406 L 0.016 0.035 0.406 0.889 α 0° 8° 0° 8° Rev. 2.00 14 MP7226 20 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) P20 D D1 Seating Plane A2 1 D B D1 D2 e1 C D3 A1 A INCHES SYMBOL MILLIMETERS MIN MAX MIN MAX A 0.165 0.180 4.19 4.57 A1 0.100 0.110 2.54 2.79 A2 0.148 0.156 3.76 3.96 B 0.013 0.021 0.330 0.533 C 0.008 0.012 0.203 0.305 D 0.385 0.395 9.78 10.03 D1 (1) 0.350 0.354 8.89 8.99 D2 0.290 0.330 7.37 8.38 D3 0.200 Ref 5.08 Ref. e1 0.050 BSC 1.27 BSC Note: (1) Dimension D1 does not include mold protrusion. Allowed mold protrusion is 0.254 mm/0.010 in. Rev. 2.00 15 MP7226 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1993 EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 2.00 16