MPT57202 160-CHANNEL LCD GATE DRIVER FOR DOT MATRIX STN SGLS093 – MARCH 1997 D D D D D D Duty Cycle for LCD Driver is Over 1/400 Recommended VEE Voltage Range for LCD Driver: 20 V to 42 V (45 V Max) 160 Channel Outputs Power Supply Voltage . . . 5 V ± 10% High-Voltage CMOS SI Gate Technology TAB (Tape Automated Bonding) Packaging description The MPT57202 is a CMOS integrated circuit designed to drive an LCD (liquid crystal display) for a dot matrix STN (super twisted nematic). The outputs can be configured as one set of 160 output channels or as two sets of 80 output channels. The duty cycle is over 1/400, and the output bias voltage range (VEE) is from 20 V to 42 V (45 V maximum). The outputs can be configured as one set of 160 output channels or as 2 sets of 80 output channels. This high-voltage CMOS SI gate device is available in a custom TAB (tape automated bonding) package. OUT160 OUT158 OUT152 OUT150 OUT11 OUT9 OUT3 OUT1 The MPT57202 is characterized for operation over the full military temperature range of –55°C to 125°C. OUT1 VL2 VL4 VL3 VL1 V EE2 VSS2 TEST 80CH BS L/R MODE DISP OFF M DST SCK VSS3 EIO1 EIO2 EIO3 EIO4 VCC D7 D6 D5 D4 D3 D2 D1 D0 VL1 VL3 V EE1 VL4 VL3 VSS1 OUT160 MPT57202 IC Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MPT57202 160-CHANNEL LCD GATE DRIVER FOR DOT MATRIX STN SGLS093 – MARCH 1997 function table SIGNAL COMMON (ROW) MODE BS Not Used (tie low) D7-D0 Not Used (tie low) DISP OFF† TEST VL2 (display off): L DST Data shift on falling edge 80 CH L = 160-channel EIO1 Serial I/O H=80-channel x 2 (parallel) 1 CH Serial I/O EIO2 See Note 1 80 CH Serial I/O EIO3 See Note 1 81 CH Serial I/O EIO4 Serial I/O 160 CH Serial I/O L/R = L (left shift) EIO1 ← <R1> ← <R2> ← <R3>...← <R160> ← EIO4 L/R M L/R = H (right shift) EIO1 → <R1> → <R2> → <R3>...→ <R160> → EIO4 M, data combination Selects level 0,1 , 1,0 0,0 1,1 11 VL1 VL3 VL4 VL2 MODE L SCK Not used (tie low) TEST Test pin = L or open † This terminal should be low at power up for logic resetting. NOTE 1: This terminal is not used in this configuration. Although the pin produces a low output level, it should be left open. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MPT57202 160-CHANNEL LCD GATE DRIVER FOR DOT MATRIX STN SGLS093 – MARCH 1997 functional block diagram DST MODE SCK Control EIO1 80CH EIO4 BS L/R Data Bus 20-Bit / 40-Bit Latch Select Bit Bus 4 D7 20 / 40 8-Bit Data Latch 4/8 D0 40 / 8 20 Data Latch VCC VSS3 160 160 160 1 Data Latch 1 Bidirectional Data Shifter EIO2 EIO3 160 Logic M 160-Bit Level Shifter VEE1, VEE2 160 VL1 VL3 VL4 VL2 TEST 160-Channel LCD Driver DISP OFF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 OUT160 OUT159 OUT158 OUT157 OUT156 OUT155 OUT154 OUT153 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 VSS1, VSS2 3 MPT57202 160-CHANNEL LCD GATE DRIVER FOR DOT MATRIX STN SGLS093 – MARCH 1997 power supply circuit 42 V 5V VR VCC R3 R1 R1 VEE1 , VEE2 VL1 + _ R3 + _ R3 VL3 VL4 MPT57202 (Common) R1 VL2 VSS1, VSS2 VSS3 GND (0 V) GND (0 V) NOTE A. Separation between high voltage GND (VSS1, VSS2) line and logic GND (VSS3) line is recommended to avoid noise problems. schematics of inputs and outputs ALL INPUTS VCC EIO1, EIO2, EIO3, AND EIO4 OUTPUT VCC VCC Input Output VSS3 TYPICAL OF ALL OUTn OUTPUTS VSS3 VL1 OUTn VL3 OUTn VL4 OUTn VL3 OUTn VSS 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MPT57202 160-CHANNEL LCD GATE DRIVER FOR DOT MATRIX STN SGLS093 – MARCH 1997 Terminal Functions common (row) driver mode TERMINAL NAME I/O 80CH I 80CH is the 160-channel/80-channel mode select L = 160-channel data shift mode; H = 80-channel-×-2 data shift mode DESCRIPTION BS I Not used (tie low) D7–D0 I Not used (tie low) DISP OFF I Display off. A low level on DISP OFF disables normal operation, turning the display off (0V) and enabling the test mode. DISP OFF must be tied high for normal operation. DST I Data strobe. DST is the data strobed input. EIO1 I/O Serial I/O 1. When L/R is high, EIO1 is an active-high serial input. When L/R is low (left-shift mode), EIO1 is an active-high serial output. EIO2 I/O Serial I/O 2: When the device is configured in 160-channel data shift mode (80CH = L), EIO2 is not used and should be left open. When the device is configured in 80-channel-×-2 data shift mode (80CH = H) and L/R is low; this EIO2 is an active-high serial input for the first 80-channel output section. L/R is high; EIO2 is an active-high serial output for the first 80-channel output section. EIO3 I/O Serial I/O 3: When MPT57202 is configured in 160-channel data shift mode (80 CH = L), EIO3 is not used and should be left open. When the device is configured in 80-channel-×-2 data shift mode (80CH = H) and L/R is low; EIO3 is an active-high serial output for the first 80-channel output section. L/R is high; EIO3 is an active-high serial input for the first 80-channel output section. EIO4 I/O Serial I/O 4: When L/R = H: EIO4 is an active-high serial output When L/R = L: EIO4 is an active-high serial input L/R I Select left or right shift When the MPT57202 is in 160-channel data shift mode (80CH = L) and L/R = H, data is right shifted into EIO1 and out from EIO4 EIO1 → <R1> → <R2> → <R3>...→ <R160> → EIO4 When the MPT57202 is in 160-channel data shift mode (80CH = L) and L/R = L, data is left shifted into EIO4 and out from EIO1 EIO1 ← <R1> ← <R2> ← <R3>...← <R160> ← EIO4 When the MPT57202 is in 80-channel-×-2 data shift mode with two parallel 80-channel output sections (80CH = H) and L/R = H, data is right shifted into EIO1 and EIO3 and out from EIO2 and EIO4 EIO1 → <R1> → <R2> → <R3>...→ <R80> → EIO2 EIO3 → <R81> → <R82> → <R83>...→ <R160> → EIO4 When the MPT57202 is in 80-channel-×-2 data shift mode with two parallel 80-channel output sections (80CH = H) and L/R = L, data is left shifted into EIO2 and EIO4 and out from EIO1 and EIO3 EIO1 ← <R1> ← <R2> ← <R3>...← <R80> ← EIO2 EIO3 ← <R81> ← <R82> ← <R83>...← <R160> ← EIO4 In all cases, R<1> → OUT1, e.g., R<1> → OUT1, R<76> → OUT76, etc. See Table 1 for the cascade configuration. M I Frame signal input MODE I Common/segment mode select. MODE should be tied low. OUT1–OUT160 O Common (row) driver output channels (see Table 2) SCK I Not used (tie low) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 MPT57202 160-CHANNEL LCD GATE DRIVER FOR DOT MATRIX STN SGLS093 – MARCH 1997 Terminal Functions (continued) TERMINAL NAME I/O DESCRIPTION TEST I TEST is used for factory testing only. For normal operation tie TEST low or leave it open. TEST has an internal pulldown resistor. VCC VEE1 5-V supply terminal VEE2 VL1 Output logic bias Output buffer bias VL1 is the on-level of the LCD driver output VL2 VL2 is the off-level of the LCD driver output VL3 VL3 is the on-level of the LCD driver output VL4 VL4 is the off-level of the LCD driver output VSS1 VSS2 Ground terminal with respect to VEE1 VSS3 Ground terminal with respect to VCC Ground terminal with respect to VEE2 Table 1. Cascade Configurations - Common-Driver Mode (MODE = L) EIO1 EIO2 EIO3 EIO4 NUMBER OF CHANNELS/ SHIFT DIRECTION H Input - - Output 160/right L Output - - Input 160/left H H Input Output Input Output 80 x 2/right H L Output Input Output Input 80 x 2/left INPUTS 6 I/O 80 CH L/R L L POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MPT57202 160-CHANNEL LCD GATE DRIVER FOR DOT MATRIX STN SGLS093 – MARCH 1997 absolute maximum ratings over free-air temperature range† Supply voltage range, VCC (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Supply voltage (VSS1, VSS2, VSS3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V Input voltage range, VI (DST, SCK, M, MODE, 80CH, L/R, BS, EIO1-EIO4, D0-D7, DISP OFF, TEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V Output voltage range, VO (EIO1, EIO2, EIO3, EIO4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V Output bias voltage range for LCD (VEE1, VEE2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 45 V Supply voltage range for LCD (VL1, VL2, VL3, VL4) (see Note 3) . . . . . . . . . . . . . . . – 0.3 V to VEE + 0.3 V Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 10 mA Output current, IO: EIO1 to EIO4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA OUT1 to OUT160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 2. Voltage values are with respect to VSS1, VSS2, and VSS3. 3. The following conditions must be met: VEE1 and VEE2 ≥ VL1 ≥ VL3 ≥ VEE - 7 V, and 7 V ≥ VL4 ≥ VL2 ≥ VSS1, VSS2, VSS3 VEE1 and VEE2 > VL1 > VL3 > VEE - ∆ V, and ∆ V > VL4 > VL2 > VSS1, VSS2, VSS3 (See Figure 1 for a graphic representation of ∆ V). VEE1, VEE2 VL1 ∆V VL3 VL4 VL2 ∆V VSS 6.7 ∆V (V) 3.2 2.3 14 20 42 VEE – Output Bias Voltage Range – V Figure 1. VLn Voltage Range POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 MPT57202 160-CHANNEL LCD GATE DRIVER FOR DOT MATRIX STN SGLS093 – MARCH 1997 recommended operating conditions (see Figure 2) MIN Supply voltage, VCC See Notes 4 and 5 NOM 4.5 Supply voltage, VSS 5 MAX UNIT 5.5 0 Supply voltage for LCD drive See Notes 4 and 5 High-level input voltage, VIH VEE1, VEE2, VL1, VL3, VL4, VL2 80CH, BS, D7–D0, DISP OFF, DST, EIO1-EIO4, L/R, M, MODE, SCK, TEST Low-level input voltage, VIL 80CH, BS, D7–D0, DISP OFF, DST, EIO1-EIO4, L/R, M, MODE, SCK, TEST Clock frequency, fCLK DST V V 20 42 V 0.8 VCC VCC V VSS 0.2 VCC V 1 Operating free-air temperature, TA – 55 NOTES: 4. VLn voltage range should be under the following conditions: VEE1 and VEE2 ≥ VL1 ≥ VL3 ≥ VEE - 7 V, and 7 V ≥ VL4 ≥ VL2 ≥ VSS1, VSS2 VSS3 VEE1 and VEE2 > VL1 > VL3 > VEE - ∆ V, and ∆ V > VL4 > VL2 > VSS1, VSS2 VSS3 5. Power-up and power-down sequences are as follows: Power-up sequence: VCC → Input → VEE1, VEE2, VEE3 Power-down sequence: VEE1, VEE2, VEE3 → Input → VCC 125 MHz °C electrical characteristics over full range of recommended operating conditions (unless otherwise noted) PARAMETER VOH High-level output voltage VOL Low-level output voltage IIH High-level input current TEST CONDITIONS MIN TYP VCC = 5 V ± 10%, IOH = -0.4 MA VCC- 0.4 VCC EIO1-EIO4 VCC = 5 V ± 10%, IOL = -0.4 MA VSS 0.4 80CH, BS, D7–D0, DISP OFF, DST, EIO1-EIO4, L/R, M, MODE, SCK VIH = VCC Low-level input current 80CH, BS, D7–D0, DISP OFF, DST, EIO1-EIO4, L/R, M, MODE, SCK 500 VIL = VSS Output impedance OUT1 to OUT160 VEE = 14 V, VLn = ∆V, IO = 150 µA, ∆ZO II Output impedance variance OUT1 to OUT160 See Note 6 Input current VL1, VL2, VL3, VL4 ICC IEE Supply current VCC VEE1, VEE2 VI = VEE, VSS 1/480 duty operation, See Note 7 ICC IEE Supply current VCC VEE1, VEE2 1/480 duty operation II(standby) Standby current VCC See Note 8 NOTES: 6. ∆ZO = (1-Xn/Xaverage) x 100 Xn = impedance or OUTn, Xaverage = impedance of average OUTn 7. fDST = 36 kHz, VIH = VCC, VIL = VSS, and no output load. 8. Voltage level at EIO1 input = VCC 8 V µA -5 µA ZO Supply current V µA TEST Supply current UNIT 5 TEST IIL MAX EIO1-EIO4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ±10% -5 µA 3 kΩ ±30% ±100 µA 1 mA 0.5 mA 5 mA 2 mA 500 µA MPT57202 160-CHANNEL LCD GATE DRIVER FOR DOT MATRIX STN SGLS093 – MARCH 1997 timing requirements over full range of recommended operating conditions (unless otherwise noted) PARAMETER tc tw1(L) Cycle time tw1(H) tsu1 Pulse duration, high pulse width TEST CONDITIONS DST Pulse duration, low pulse width DST Setup time, EIOn valid to DST↓ th1 Hold time, EIOn valid to DST↓ td Frame delay tolerance time NOTE 9: This parameter is not production tested. See Figure 2 See Figure 2 MIN MAX UNIT 1 µs 970 ns 30 ns 100 ns 30 ns ± 300 See Note 10 ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER TEST CONDITIONS tpd1 tpd2 Propagation delay time, DST↓ to EIO1 valid tpd3 Propagation delay time, DST↓ to OUTn valid Propagation delay time, M valid to OUTn valid POST OFFICE BOX 655303 CL = 30 pF, CL = 45 pF, pF • DALLAS, TEXAS 75265 See Figure 2 See Figure 2 MIN MAX UNIT 110 ns 1.5 µs 0.7 µs 9 MPT57202 160-CHANNEL LCD GATE DRIVER FOR DOT MATRIX STN SGLS093 – MARCH 1997 PARAMETER MEASUREMENT INFORMATION tw1(H) tc tr tf VCC DST VSS tw1(L) tsu1 th1 VCC EIOn (IN) VSS tpd1 VCC EIOn (OUT) VSS td VCC M See Note A VSS tpd2 tpd3 VOH OUTn VOL NOTES: A. tr and tf ≤ 30ns for input pulses B. VIH = 0.8 VCC, VIL = 0.2 VCC Figure 2. Clock Timing Waveforms for Common-Driver Mode 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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