FEDL1200V-03 FEDL1200V-03 This version: Sep. 2000 MSC1200-01/1200V-01 Previous version: Nov. 1997 ¡ Semiconductor MSC1200-01/1200V-01 ¡ Semiconductor 30-Bit Duplex Controller/Driver with Digital/Analog Dimming and Keyscan Functions GENERAL DESCRIPTION The MSC1200-01/1200V-01 is a Bi-CMOS display driver for 1/2-duty vacuum fluorescent display tube. This device consists of a 64-bit shift register, latches, an analog dimming circuit, a digital dimming circuit, a keyscan circuit, and drivers. The interface with a microcomputer can be done only with four signal lines (CS, DATA I/O, CLOCK, and INT). Also, the DATA I/O and CLOCK signal lines can be shared with other peripherals by using the chip select function. FEATURES • Power supply voltage : 8V to 18V (built-in 5V regulator for logic) • Operating temperature range : –40°C to +85°C • 30-segment driver outputs (IOH = –6mA at VOH = VDD – 0.8V) • Built-in analog dimming circuit (PWM: 12.5% Max at 6-bit resolution) • Built-in digital dimming circuit (11-bit resolution) • Built-in 5 x 6 keyscan circuit • Built-in RC oscillation circuit (external R and C) • Built-in power-on-reset circuit. • The product name differs depending on the bonding option pin selected: PWM OUT/BLANK IN : MSC1200-01 DATA OUT : MSC1200V-01 • Package : 56-pin plastic QFP (QFP56–P–910-0.65–2K) (Product name: MSC1200-01GS-2K/MSC1200V-01GS-2K) 1/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 BLOCK DIAGRAM GRID1 SEG30 SEG1 GRID2 5V VDD GND 5V Regulator &POR 30 Segment Drivers POR Grid Driver PLA (32 ¥ 32 Matrix) TEST1 Multiplexer S1 S2 S3 S4 S5 S6 S7 S8 S9 SA Bit Latch D CK Mode Selector 64-Bit Shift Register R M3 M2 M1 M0 DATA OUT (Optional) Selector PWM OUT/ BLANK IN (Optional) S1, S6, S7, S8 OSC0 R/C OSC OSC1 VPARK VDIM Timing Generator R Analog Dimming R Digital Dimming R S4 CS DATAI/O CLOCK S2, S7, S3, S8 S9 Control Circuit SA 5 ¥ 6 Keyscan Circuit INT R S5, S6, S9 0 1 2 34 5 0 1 2 34 COLUMN ROW 2/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 INPUT AND OUTPUT CONFIGURATION • Schematic Diagrams of Logic Portion Input Circuit VDD (5V Reg.) INPUT GND GND • Schematic Diagrams of Logic Portion Input • Schematic Diagrams of Logic Portion Input/ Circuit 2 Output Circuit VDD (5V Reg.) VDD (5V Reg.) (5V Reg.) TEST1 COLn DATAI/O GND GND GND GND GND GND • Schematic Diagrams of Logic Portion Output • Schematic Diagrams of Driver Output Circuit Circuit (5V Reg.) (5V Reg.) VDD OUTPUT OUTPUT GND GND VDD GND GND 3/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 43 SEG20 44 SEG21 45 SEG22 46 SEG23 47 SEG24 48 SEG25 49 GND 50 SEG26 51 SEG27 52 SEG28 53 SEG29 54 SEG30 55 GRID1 56 GRID2 PIN CONFIGURATION (TOP VIEW) VDD 1 42 SEG19 VPARK 2 41 SEG18 VDIM 3 40 SEG17 CS 4 39 SEG16 31 SEG8 COLUMN3 13 30 SEG7 COLUMN4 14 29 SEG6 SEG5 28 COLUMN2 12 SEG4 27 32 SEG9 SEG3 26 COLUMN1 11 SEG2 25 33 SEG10 SEG1 24 COLUMN0 10 OSC1 23 34 SEG11 OSC0 22 *1 9 GND 21 35 SEG12 ROW4 20 TEST1 8 ROW3 19 36 SEG13 ROW2 18 INT 7 ROW1 17 37 SEG14 ROW0 16 38 SEG15 COLUMN5 15 CLOCK 5 DATA I/O 6 56-Pin Plastic QFP *1 Bonding option pin (DATA OUT or PWM OUT/BLANK IN) 4/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 PIN DESCRIPTIONS Pin Symbol Type 1 VDD — 2 3 VPARK VDIM Description Power Supply I Day/night switching pin. When the high level is input, the IC enters the night mode and the value determined by the analog or digital dimming circuit is used as the output duty. When the low level is input, the IC enters the day mode and the output duty is about 100%. I Analog voltage input for determining the analog dimming value. When the analog dimming circuit is used, the output duty is determined by the analog voltage to be input to this pin. When only the digital dimming circuit is used, pull down this pin to GND. 4 CS I Chip select input. Only when the high level is input to this pin, interfacing with a microcomputer is available through "CLOCK" and "DATA I/O" pins. Therefore, 2 signal lines of "CLOCK" and "DATA I/O" can be shared with other peripherals. 5 CLOCK I Serial clock input. Data is input-output through "DATA I/O" pin at the rising edge of the serial clock. 6 DATA I/O I/O Serial data input-output. This pin enters output mode only when the keyscan mode is selected. It enters input mode when other mode is selected. O Interrupt signal output to microcomputer. When any key is pressed or released, key scanning is started. After the completion of the one cycle, this pin goes to the high level and keeps the high level until keyscan stop mode is selected. I Test signal input. As this pin has a built-in pull-up resistor, it must be left open or pulled up in the normal operation mode. When the low level is input to this pin, SEG1-30 go to the high level, and GRID1 and GRID2 go to the low level. (All segments go on.) O Serial data output. Selecting this pin specifies the MSC1200V-01. The data from DATA I/O is shifted out on the rising edge of the shift clock with a delay of 64 bits in the shift register. This pin can be used for connecting the IC with a LED driver in series. I/O When the VPARK pin is at the high level, the pulse with the duty ratio determined by the analog or digital dimming circuit is output through this pin. When this pin is at the low level, the pulse with the duty ratio determined by external circuit is input to this pin. This pin has an internal active pull-up resistor, which becomes active only when the VPARK pin is at the low level. When the VPARK pin is at the low level, this pin receives blanking signal from external circuits, so that output duty cycle can be controlled. Selecting this pin specifies the MSC1200-01. 7 INT 8 TEST1 9 DATA OUT (Option) 9 PWM OUT/ BLANK IN (Option) 5/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 Pin Symbol Type Description 10-15 COLUMN 0-5 I Return inputs from key matrix switch. A pull-up resistor is internally connected to each of these pins so that they are at the high level except when the low level is input by depression of a key. These pins are "L" active. 16-20 ROW0-4 O Key switch scanning outputs. Normally the low level is output through these pins. When any key is depressed or released, keyscanning is started and is continued until keyscan stop mode is selected. When the keyscan stop mode is selected and then keyscanning is stopped, all outputs of ROW0-4 go back to the low level. 21, 49 GND — Ground 22, 23 OSC0 OSC1 I/O Connecting pins for RC oscillation circuit. Connect a resistor between OSC1 and OSC0, and a capacitor between OSC0 and ground. 24-48, 50-54 SEG1-30 O Segment signal output. Signals for driving VF display tube are output through these pins. O Grid signal output. Signals for driving VF display tube are output through these pins. Signals inverted with respect to grid signals are output. Normally, these pins are connected to the external grid driver (PNP transistor etc.) inputs. 55, 56 GRID1,2 6/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 ABSOLUTE MAXIMUM RATINGS Symbol Condition Rating Unit Supply Voltage Parameter VDD — –0.3 to +20 V Input Voltage (1) VIN1 All inputs except VPARK –0.3 to +6 V Input Voltage (2) VIN2 VPARK –0.3 to VDD +0.3 V Storage Temperature TSTG — –65 to +150 °C PD Ta = 85°C 400 mW Power Dissipation RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Min. Typ. Max. Unit Supply Voltage VDD — 8 — 18 V High Level Input Voltage (1) VIH1 All inputs except VPARK & OSC0 3.8 — 5.5 V High Level Input Voltage (2) VIH2 VPARK 3.8 — VDD V High Level Input Voltage (3) VIH3 OSC0 4.5 — 5.5 V Low Level Input Voltage (1) VIL1 All inputs except OSC0 0 — 0.8 V Low Level Input Voltage (2) VIL2 OSC0 0 — 0.5 V Clock Frequency fC — — — 250 kHz OSC Frequency fOSC R = 4.7kW, C=10pF — 3.3 — MHz Frame Frequency fFR fOSC=3MHz — 201 — Hz Operating Temperature Top — –40 — +85 °C 7/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 ELECTRICAL CHARACTERISTICS DC Characteristics (Ta = –40 to +85°C, VDD = 8 to 18V) Parameter Symbol Condition Min. Max. Unit High Level Input Voltage (1) *1 VIH1 — 3.8 5.5 V High Level Input Voltage (2) *9 VIH2 — 3.8 VDD V High Level Input Voltage (3) *2 VIH3 — 4.5 5.5 V Low Level Input Voltage (1) *10 VIL1 — 0 0.8 V Low Level Input Voltage (2) *2 VIL2 — 0 0.5 V High Level Input Current (1) *3 IIH1 VIH1 = 5.0V –5 5 mA High Level Input Current (2) *4 IIH2 VIH2 = 5.0V –30 30 mA High Level Input Current (3) *5 IIH3 VIH3 = 5.0V –80 80 mA Low Level Input Current (1) *3 IIL1 VIL1 = 0V –5 –5 mA Low Level Input Current (2) *4 IIL2 VIL2 = 0V –160 –15 mA Low Level Input Current (3) *5 IIL3 VIL3 = 0V –0.6 0.1 mA Input Leakage Current IIL VI = 0 to 5.5V –10 10 mA VOH1 VDD = 9.5V, IOH1 = –6mA — V VOH2-1 VDD = 9.5V, IOH2 = –200mA VDD –0.8 4 6 V VOH2-2 VDD = 9.5V, Output Open 4.5 6 V VOL1-1 VDD = 9.5V, IOL1-1 = 500mA — 2 V VOL1-2 VDD = 9.5V, IOL1-2 = 200mA — 1 V VOL1-3 VDD = 9.5V, IOL1-3 = 2mA — 0.3 V 0.8 V 20 mA *6 High Level Output Voltage (1) *7 High Level Output Voltage (2) *8 Low Level Output Voltage (1) *7 Low Level Output Voltage (2) *8 VOL2 VDD = 9.5V, IOL2 = 200mA — Power Supply Current IDD fOSC = 3.3MHz, No load — *1 *2 *3 *4 *5 *6 *7 *8 Applicable to all input pins (except VPARK and OSC0 pins) Applicable to OSC0 pin Applicable to CLOCK, DATA I/O, CS, and VPARK pins Applicable to COLUMN0 to COLUMN5 and PWM OUT/BLANK IN pins Applicable to TEST1 pin Applicable to VDIM pin Applicable to SEG1 to SEG30, GRID1, and GRID2 pins Applicable to ROW0 to ROW4, DATA I/O, PWMOUT/BLANK IN, DATAOUT, and INT pins. *9 Applicable to VPARK pin *10 Applicable to all input pins (except OSC0) 8/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 AC Characteristics (Ta = –40 to +85°C, VDD = 8 to 18V) Parameter Symbol Condition Min. Max. Unit Oscillation Frequency fOSC R = 4.7kW±1%, C = 10pF±5% 2 4.66 MHz Input Frequency to OSC0 from Outside fOSCI External input only 2.4 3.7 MHz fFR — 122 284 Hz fPWM — 244 568 Hz fC — — 250 kHz Clock Pulse Width tCW — 1.3 — ms Data Setup Time tDS — 1 — ms Data Hold Time tDH — 200 — ns CS Pulse Width tCSW — 68 — ms CS Off Time tCSL — 30 — ms CS Setup Time CS – Clock Time tCSH — 2 — ms CS Hold Time Clock – CS Time tCSH — 2 — ms Data Output Delay Clock – Data output Time tPD — — 1 ms SEG & GRID Output Delay from CS tODS CI = 100pF — 8 ms Slew Rate (All Drivers) tR CI = 100pF, t = 20% to 80% or 80% to 20% of VDD — 5 ms CS Time at Power-on tPCS — 300 — ms Hold Time at Power-off tPOF When mounted on the unit VDD=0.0V 5 — ms Rise Time at Power-on tPRZ When mounted on the unit — 100 ms Frame Frequency PWM OUT Frequency Clock Frequency 9/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 Dimming Characteristics • DC characteristics (Ta = –40 to +85°C, VDD = 8 to 18V) Parameter Condition Min. Typ. Max. Unit — — — ±3 % Note 1 — — ±6 % D/A Output Voltage Error Reference Voltage Accuracy Note: 1. Reference voltage is 6.6V typical. Keyscan Characteristics (Ta = –40 to +85°C, VDD = 8 to 18V) Condition Min. Typ. Max. Unit Keyscan Cycle Time Parameter fOSC=3.3 MHz 275 390 640 ms Keyscan Pulse Width fOSC=3.3 MHz 55 78 128 ms 10/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 TIMING DIAGRAM tCSW tCSL 3.8V CS 0.8V tCSS fC tCW CLOCK tCSH tCW 3.8V 0.8V tDS tDS tDH 3.8V DATA I/O (INPUT) 0.8V VALID tDH VALID Figure 1 Data Input Timing CS 3.8V 0.8V CLOCK tCSH tCSS 3.8V 0.8V tPD tPD DATA I/O 3.8V (OUTPUT) DATA OUT 0.8V Figure 2 Data Output Timing 11/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 TIMING DIAGRAM (Continued) 8V VDD tPRZ 0V tPOF tPCS CS 3.8V Figure 3 Power-On Timing tCSW CS 3.8V tODS tODS tR SEG1-30 GRID1, 2 tR 80% 20% Figure 4 SEG & GRID Output Timing 12/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 FUNCTIONAL DESCRIPTION Power-on Reset The IC is initialized by the built-in power-on reset circuit at power-on. The status of the internal circuit after initialization is as follows; 1) Shift registers and latches are reset. 2) Analog dimming is selected. 3) Digital dimming data register is reset. 4) Display data input mode is selected. Data Input Data input is valid only when the high level is applied to the "CS" pin. Input data is input into the shift register through "DATA I/O" pin at the rising edge of CLOCK. The data is automatically loaded to latches at the falling edge of "CS" signal. [Data Format] 1) Display Data Input Mode Input data : 64 bits VF display data : 60 bits Mode select data : 4 bits First In Bit 64 63 D59 D58 62 D57 Display Data (12 bits) ... 53 52 51 50 49 48 D48 M3 M2 M1 M0 D47 ... Mode Data (4 bits) 3 2 1 D2 D1 D0 Display Data (48 bits) 2) Correspondence between segment outputs and shift register bits 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SEGn 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GRID1 Bit 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 GRID2 13/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 3) Digital Dimming Data Input Mode Input data : 16 bits Digital dimming data : 11 bits Mode select data : 4 bits Bit 64 xx 63 11 62 10 61 9 60 8 59 7 58 6 57 5 56 4 55 3 54 2 53 1 MSB 52 M 3 51 M 2 50 M 1 49 First In M 0 LSB Dimming Data (MSB) Mode Data (LSB) DUTY CYCLE X 0 0 0 0 INPUT DATA 0 0 0 0 0 0 0 0/2048 X 0 0 0 0 0 0 0 0 0 0 1 1/2048 X 1 1 1 1 1 1 1 0 0 0 0 2032/2048 X 1 1 1 1 1 1 1 1 1 1 1 2032/2048 14/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 4) Function Mode Mode M3 S1 0 0 0 0 Display Data Input S2 0 0 1 1 Analog Dimming Select S3 0 1 0 1 Digital Dimming Select S4 0 0 0 1 Digital Dimming Data Input & Digital Dimming Select S5 0 1 1 1 Keyscan Data Output S6 0 1 1 0 Display Data Input & Keyscan Data Output S7 0 0 1 0 Display Data Input & Analog Dimming Select S8 0 1 0 0 Display Data Input & Digital Dimming Select S9 1 0 0 0 Keyscan Data Output & Keyscan Stop SA 1 0 0 1 Keyscan STOP M2 M1 M0 Function Note: Other combinations are used for test modes. 5) Analog Dimming Mode Analog dimming is automatically selected when the VPARK pin is set to the high level after power-on. Therefore, when digital dimming is used, mode setting is required before the VPARK pin is set to the high level. The output duty ratio for analog dimming is 12.5% maximum. The correspondence between threshold voltage and output duty ratio is shown in VDIN Threshold Dimming Voltage VS. PWM Duty Cycle. 15/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 Keyscan Keyscanning is started only when depression or release of any key is detected in order to minimize noise caused by scanning signal. Then, keyscanning is continued until the keyscan stop mode signal is sent from a microcomputer. The INT pin goes to the high level at the completion of 1-cycle scanning after the keyscan start, so the (high level) signal sent from the INT pin can be used as an interrupt signal. [Keyscan Timing] ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 1 Cycle INT Depress/Release Keyscan stop mode is selected. Note: Keyscanning cannot be stopped by selecting the keyscan stop mode only once if: - keyscanning is started after depression or release of any key is detected, and then - a key is depressed or released again before the keyscan stop mode is selected. To stop keyscanning, it is required to select the keyscan stop mode once again. 16/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 [Example] A) When Key Input Status is Changed Depress Release Keyscan stop Keyscan INT CS SA S5 Keyscan stop Keyscan stop Keyscan SA Keyscan data output Keyscan stop S5 Keyscan data output B) When Key Input Status is Changed before Keyscan Stop Mode Select Depress Release *1 INT Keyscan Keyscan Keyscan Stop SA CS Keyscan stop S5 Keyscan data output SA Keyscan stop S5 Keyscan data output *1: Keyscanning resumes after short period of keyscan stop. 17/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 Keyscan Data Output When keyscan data output mode is selected, "DATA I/O" pin is changed to an output mode. Then, 30 bits of keyscan data come out from "DATA I/O" pin synchronizing with the rising edge of the clock. After the completion of 30 bits data output, the IC returns to the display data input mode synchronizing with the falling edge of CS. [Data Format] 1) Keyscan Data Stop Mode Since the DATA I/O pin goes to the output mode after the keyscan stop mode signal is received, be sure to output the keyscan data. Input data : 16 bits Mode select data : 4 bits Bit 64 xx 63 xx 62 xx 61 xx 60 xx 59 xx 58 xx 57 xx 56 xx 55 xx 54 xx 53 xx 52 M 3 51 M 2 50 M 1 49 First In M 0 Mode Data 2) Keyscan Data Output Mode Input data : 30 bits Output data : 30 bits CLOCK 30 S 45 29 S 44 28 S 43 ..... ..... 9 S 12 8 S 11 7 S 10 6 S 05 5 S 04 4 S 03 3 S 02 2 S 01 1 First Out S Keyscan Data 00 S x x ↑ ↑ ROW COLUMN 3) Key switch matrix for COLUMN input and ROW output ROW0 ROW1 ROW2 ROW3 ROW4 S00 S10 S20 S30 S40 S01 S11 S21 S31 S41 S02 S12 S22 S32 S42 S03 S13 S23 S33 S43 S04 S14 S24 S34 S44 S05 S15 S25 S35 S45 COLUMN0 COLUMN1 COLUMN2 COLUMN3 COLUMN4 COLUMN5 = 18/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 GRID/SEG Driver Operation and Digital/Analog Dimming Operation Figure 5 shows the output timing of the GRID and SEG driver when the VPARK is the "H" level. Figure 6 shows the output timing of the GRID and SEG drivers for the digital diming mode operation. Figure 7 shows the output timing of the GRID and SEG drivers for the analog dimming mode operation. 1 Frame 4096 bit times GRID1 16 bit times GRID2 2032 bit times 6 bit times SEG1-30 2038 bit times 10 bit times Figure 5 GRID and SEG Output Timing (VPARK="H") Note: 1 bit time = TOSC (4/fOSC) = 1.2ms (typ.) 1 Frame 4096 bit times GRID1 16 bit times GRID2 2032 bit times 6 bit times SEG1-30 2038 bit times 10 bit times Figure 6 GRID and SEG Output Timing (Digital Dimming Mode) Notes: 1. Shown above is the timing in the digital dimming mode with the duty cycle of 2032/ 2048 at VPARK = "L". 2. The length of time that the grids and the segments are turned on is specified with respect to 11 bits of the ditigal dimming data. 3. 1 bit time = TOSC (4/fOSC) = 1.2ms (typ.) 19/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 1 Frame 4096 bit times GRID1 2048 bit times GRID2 Max. 256 bit times SEG1-30 Figure 7 GRID and SEG Output Timing (Analog Dimming Mode) Notes: 1. Shown above is the timing for the GRID and SEG Drivers in the analog dimming mode at VPARK = "L". 2. 1 bit time = TOSC (4/fOSC) = 1.2ms (typ.) 20/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 PLA Code Table 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 BIT 1, BIT 2, BIT 3, BIT 4, BIT 5, BIT 6, BIT 7, BIT 8, BIT 9, BIT10, BIT11, BIT12, BIT13, BIT14, BIT15, BIT16, BIT17, BIT18, BIT19, BIT20, BIT21, BIT22, BIT23, BIT24, BIT25, BIT26, BIT27, BIT28, BIT29, BIT30, 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG PIN NAME OUTPUT PIN NAME OUTPUT PIN NAME OUTPUT SEG1 BIT 1, 31 SEG11 BIT 11, 41 SEG21 BIT 21, 51 SEG2 BIT 2, 32 SEG12 BIT 12, 42 SEG22 BIT 22, 52 SEG3 BIT 3, 33 SEG13 BIT 13, 43 SEG23 BIT 23, 53 SEG4 BIT 4, 34 SEG14 BIT 14, 44 SEG24 BIT 24, 54 SEG5 BIT 5, 35 SEG15 BIT 15, 45 SEG25 BIT 25, 55 SEG6 BIT 6, 36 SEG16 BIT 16, 46 SEG26 BIT 26, 56 SEG7 BIT 7, 37 SEG17 BIT 17, 47 SEG27 BIT 27, 57 SEG8 BIT 8, 38 SEG18 BIT 18, 48 SEG28 BIT 28, 58 SEG9 BIT 9, 39 SEG19 BIT 19, 49 SEG29 BIT 29, 59 SEG10 BIT 10, 40 BIT 20, 50 SEG30 BIT 30, 60 SEG20 21/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 VDIM Threshold Dimming Voltage VS. PWM Duty Cycle PWM Duty Cycle Pulse Step Number Pulse Count 52 256/2048 % 12.5 51 240/2048 11.7 50 224/2048 10.9 49 208/2048 10.2 48 192/2048 9.38 47 184/2048 8.98 46 176/2048 8.59 45 168/2048 8.20 44 160/2048 7.81 43 152/2048 7.42 42 144/2048 7.03 41 136/2048 6.64 40 6.25 39 128/2048 120/2048 38 112/2048 5.47 37 104/2048 5.08 36 96/2048 4.69 35 92/2048 4.49 34 88/2048 4.30 33 84/2048 4.10 32 80/2048 3.91 31 76/2048 3.71 30 72/2048 3.52 29 68/2048 3.32 28 64/2048 3.13 27 60/2048 2.93 5.86 Threshold Pulse Step PWM Duty Cycle Voltage Number Pulse Count % Vref 26 56/2048 2.73 4.200 25 52/2048 2.54 4.130 24 48/2048 2.34 4.070 23 46/2048 2.25 4.000 22 44/2048 2.15 3.930 21 42/2048 2.05 3.890 20 40/2048 1.95 3.850 19 38/2048 1.86 3.810 18 36/2048 1.76 3.770 17 1.66 34/2048 3.725 16 1.56 32/2048 3.680 15 1.46 30/2048 3.625 14 28/2048 1.37 3.580 26/2048 13 1.27 3.525 12 24/2048 1.17 3.460 11 23/2048 1.12 3.400 10 22/2048 1.07 3.340 9 21/2048 1.03 3.305 8 20/2048 0.98 3.270 7 19/2048 0.93 3.240 6 18/2048 0.88 3.200 5 17/2048 0.83 3.160 4 16/2048 0.78 3.120 3 15/2048 0.73 3.080 2 14/2048 0.68 3.040 1 13/2048 0.63 2.93 0 VDD=12.8V Threshold Voltage 3.000 2.950 2.900 2.850 2.820 2.800 2.770 2.740 2.710 2.680 2.650 2.615 2.580 2.540 2.500 2.470 2.450 2.430 2.410 2.390 2.370 2.340 2.320 2.295 2.270 2.245 0.000 Note: A threshold voltage more than 5V cannot be set. 22/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 APPLICATION CIRCUITS (A) Digital Dimming 1/2-Duty VF Display Tube Driver SEG1 Microcomputer INT CS CLOCK OSC1 OSC0 G1 G2 COLUMN5 COLUMN4 COLUMN3 COLUMN2 COLUMN1 COLUMN0 VDD GND DATAI/O Luminance Control Small Parking Resistor Lamp SW SEG30 MSC1200-01 ROW0 ROW1 ROW2 ROW3 2R VPARK VDIM ROW4 Keyboard R 23/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 (B) Analog Dimming 1/2-Duty VF Display Tube Driver SEG1 Microcomputer INT CS CLOCK Small Parking Lamp SW OSC1 OSC0 G1 G2 COLUMN5 COLUMN4 COLUMN3 COLUMN2 COLUMN1 COLUMN0 VDD GND DATAI/O Luminance Control Resistor SEG30 MSC1200-01 ROW0 ROW1 ROW2 ROW3 2R VPARK ROW4 Keyboard R VDIM 2R Dashboard Lamp R The setting voltage must not exceed 5V. 24/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 PACKAGE DIMENSIONS (Unit : mm) QFP56-P-910-0.65-2K Mirror finish Oki Electric Industry Co., Ltd. Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5 mm) 0.43 TYP. 4/Vov. 28, 1996 Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 25/26 FEDL1200V-03 ¡ Semiconductor MSC1200-01/1200V-01 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. MS-DOS is a registered trademark of Microsoft Corporation. Copyright 2000 Oki Electric Industry Co., Ltd. Printed in Japan 26/26