oH V SC AV ER OM AI SIO PL LA N IA BL S NT E *R Features ■ ■ ■ ■ ■ Applications Lead free versions available RoHS compliant (lead free version)* ESD protection Protects four lines Low capacitance 15 pF ■ ■ ■ Cell phones PDAs and notebooks MP3 players 2DAD-C5R - Integrated Passive & Active Device using CSP General Information The 2DAD-C5R device, manufactured using Thin Film on Silicon technology, provides ESD protection for the external ports of portable electronic devices such as cell phones, modems and PDAs. SOLDER BUMPS The ESD protection provided by the component enables a data port to withstand a minimum ±8 KV Contact / ±15 KV Air Discharge per the ESD test method specified in IEC 61000-4-2. The device measures 1.00 mm x 1.33 mm and is available in a 5 bump CSP package intended to be mounted directly onto an FR4 printed circuit board. The CSP device meets typical thermal cycle and bend test specifications without the use of an underfill material. SILICON DIE Electrical & Thermal Characteristics Electrical Characteristics (TA = 25 °C unless otherwise noted) Symbol Minimum C 12 Capacitance @ 2.5 V 1 MHz Rated Standoff Voltage VWM Breakdown Voltage @ 1 mA VBR Forward Voltage @ 10 mA VF Leakage Current @ 3.3 V IR ESD Protection: IEC 61000-4-2 Contact Discharge Air Discharge Nominal Maximum Unit 15 18 pF 5.0 V 0.8 V 6.0 V 0.1 ±8 ±15 µA kV kV Thermal Characteristics (TA = 25 °C unless otherwise noted) DC Power Rating Operating Temperature Range Storage Temperature Range *RoHS Directive 2002/95/EC Jan 27 2003 including Annex Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. P 200 mW TJ -40 25 +85 °C TSTG -55 25 +150 °C 2DAD-C5R - Integrated Passive & Active Device using CSP Mechanical Characteristics This is a silicon-based device and is packaged using chip scale packaging technology. Solder bumps, formed on the silicon die, provide the interconnect medium from die to PCB. The bumps are arranged on the die in a regular grid formation. The grid pitch is 0.5 mm and the dimensions for the packaged device are shown below. 0.432 - 0.559 (0.017 - 0.022) 0.3 DIA. (0.012) A1 C1 0.435 (0.017) B2 1.285 - 1.375 (0.051 - 0.054) 0.435 (0.017) A3 0.330 - 0.457 (0.013 - 0.018) C3 0.180 - 0.280 (0.007 - 0.011) 0.180 - 0.280 (0.007 - 0.011) 0.50 (0.020) 0.971 - 1.001 (0.038 - 0.039) DIMENSIONS = MILLIMETERS (INCHES) Reliability Data Reliability data is gathered on an ongoing basis for Bourns® Integrated Passive and Active Devices. “Package level” testing of the integrity of the solder joint is carried out on an independent Daisy-Chain test device. A 25-Pin Daisy Chain component is available from Bourns for this purpose (part number 2TAD-C25R). This is a 5 x 5 array featuring 0.5 mm pitch solder bumps. The Distance to Neutral Point (DNP) on that component is larger than that of the 2DAD-C5R and is thus deemed suitable for Thermal Cycle testing. “Silicon level” reliability performance is based on similarity to other integrated passive CSP devices from Bourns. Overshoot and Clamping Voltage Response 5 Volts per Division 35 25 15 5 -5 -90,000 ns 10,000 ns 110,000 ns ESD Test Pulse - 25 kilovolt, 1/30 ns (waveshape) Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. 2DAD-C5R - Integrated Passive & Active Device using CSP PCB Design and SMT Processing Block Diagram The CSP device block diagram below includes the pin names and basic electrical connections associated with each channel. EXT1 Please consult the “Bourns Design Guide Using CSP” for notes on PCB design and SMT Processing. EXT2 How to Order 2 DAD - C5R ____ GND Thinfilm Model Chipscale No. of Solder Bumps EXT4 EXT3 Packaging Option R = Tape and Reel Packaged 3000 pcs. / 7 ” reel Terminations LF = Sn/Ag/Cu (lead free) Blank = Sn/Pb Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. 2DAD-C5R - Integrated Passive & Active Device using CSP Device Pin Out The pin-out for the device is shown below with the bumps facing up. 1 EXT2 2 3 C EXT3 Pin Out A1 C1 B2 B EXT1 EXT4 A Function EXT1 EXT2 GND Pin Out A3 C3 Function EXT4 EXT3 GND Packaging The surface mount product is packaged in an 8 mm x 4 mm Tape and Reel format per EIA-481 standard. TOP SIDE VIEW (INTO COMPONENT POCKET) DIMENSIONS = MILLIMETERS (INCHES) 4.0 ± 0.1 (.16 ± .004) 0.3 ± 0.05 (.01 ± .002) 1.5 ± 0.1/-0 (.06 ± .004/-0) DIA. 2.0 ± 0.05 (.08 ± .002) R 1.75 ± 0.1 (.07 ± .004) 0.3 MAX. (0.01) 0.76 ± 0.1 (.03 ± .004) 8.0 ± 0.3 (.31 ± .01) 1.52 ± 0.1 (.06 ± .004) 3.5 ± 0.05 (.14 ± .002) 1.18 ± 0.1 (.05 ± .004) 4.0 ± 0.1 (.16 ± .004) ORIENTATION OF COMPONENT IN POCKET R 0.25 TYP. (0.010) BACKSIDE FACING UP Reliable Electronic Solutions Asia-Pacific: TEL +886- (0)2 25624117 • FAX +886- (0)2 25624116 Europe: TEL +41-41 768 5555 • FAX +41-41 768 5510 The Americas: TEL +1-951 781-5492 • FAX +1-951 781-5700 www.bourns.com COPYRIGHT© 2004, BOURNS, INC. LITHO IN U.S.A. 06/05 e/IPA0507 2DAD-C5R REV. B, 1/05 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.