OKI MSM54V12222A

MSM54V12222A
OKI Semiconductor
OKI Semiconductor
MSM54V12222A
REVISION-1 1997. 9 . 30
262,214 Words ¥ 12 Bits FIELD MEMORY
GENERAL DESCRIPTION
The OKI MSM54V12222A is a high performance 3M bits, 256K X 12 bits, Field Memory especially designed for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital
movies and Multi-media systems. MSM54V12222A is a FRAM for wide or low end use as general commodity TVs and VTRs, exclusively. MSM54V12222A is not designed for the other use or high end use as
medical systems, professional graphics systems require long time picture storage, data storage systems
and others. More than two MSM54V12222As can be cascaded directly without any delay devices among
the MSM54V12222As. ( Cascading of MSM54V12222A provides larger storage depth or a longer delay.)
Each of the 12-bits planes has separate serial write and read ports that employ independent control clocks
to support asynchronous read and write operations. Different clock rates are also supported that allow
alternate data rates between write and read data streams.
The MSM54V12222A provides high speed FIFO, First-In First-Out, operation without external refreshing:
MSM54V12222A refreshes its DRAM storage cells automatically, so that it appears fully static to the
users.
Moreover, fully static type memory cells and decoders for serial access enable the serial access operation
refresh free, so that serial read and/or write control clock can be halted high or low for any time as long as
the power is on. Internal conflicts of any memory access and refreshing operation are prevented by
special arbitration logic.
The MSM54V12222A's function is simple like that of a digital delay device whose delay-bit-length is easily
set by reset timing. The delay length, number of read delay clocks between write and read, is determined
by externally controlled write and read reset timings.
Additional SRAM serial registers, or line buffers, for the initial access of 256X12 bits enable high speed
first-bit-access with no clock delay just after the write or read reset timings.
In addition to cascade capability, MSM54V12222A has write mask function or input enable function (IE),
and read- data skipping function or output enable function(OE). The differences between write enable
(WE) and input enable (IE), and between read enable (RE) and output enable (OE) are that WE and RE
can stop serial write/read address increments but IE and OE can not stop the increment when write/read
clocking is continuously applied to MSM54V12222A. The input enable (IE) function allows the user to
write into selected locations of the memory only, leaving the rest of the memory contents unchanged. This
facilitates data processing as "picture in picture" on a TV screen simply.
The MSM54V12222A is similar in operation and functionality to OKI 1M bits Field memory MSM51V4222C
and 2M bits Field memory MSM51V8222A. Three MSM51V4222Cs or one MSM51V4222C plus one
MSM51V8222A can be replaced simply by one MSM54V12222A.
1
OKI Semiconductor
MSM54V12222A
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Signale power supply : 3.3V±0.3V
512 Rows X 512 Column X 12 bits
Fast FIFO (First-In First-Out) Operation
High Speed Asynchronous Serial Access
Read/Write Cycle Time
30 ns/40 ns
Access Time
30 ns/35 ns
Direct Cascading Capability
Write Mask Function (Input Enable Control)
Data Skipping Function (Output Enable Cotrol)
Self Refresh (No refresh control is required)
Packageoptions:
44Pin 400mil plastic TSOP (Type II ) (TSOP II 44-P-400-0.80-K) (Product:MSM54V12222A-xxTS-K)
40Pin 400mil Plastic SOJ
(SOJ40-P-400-1.27)
(Product:MSM54V12222A-xxJS)
xx indicates speed rank.
PRODUCT FAMILIES
Family
Access Time (Max.)
Cycle Time (Min.)
MSM54V12222A-30-TS-K
30 ns
30 ns
MSM54V12222A-40-TS-K
35 ns
40 ns
MSM54V12222A-30JS
30 ns
30 ns
MSM54V12222A-40JS
35 ns
40 ns
2
Package
400 mil 44-pin TSOP (II)
400 mil 40-pin SOJ
MSM54V12222A
OKI Semiconductor
PIN CONFIGURATION (TOP VIEW)
VSS 1
44 VSS
VSS 1
40 VSS
NC 2
39 VCC
DIN11 2
43 DOUT11
DIN10 3
42 DOUT10 DIN11 3
38 DOUT11
NC 4
37 DOUT10
DIN8 6
41 NC
DIN10 4
40 DOUT9
DIN9 5
39 DOUT8
DIN8 6
DIN7 7
38 DOUT7
DIN7 7
34 DOUT7
DIN6 8
NC 9
37 DOUT6
DIN6 8
DIN5 9
33 DOUT6
DIN5 10
35 DOUT5
DIN4 10
31 DOUT4
DIN4 11
DIN3 12
34 DOUT4
DIN3 11
30 DOUT3
33 DOUT3
32 DOUT2
DIN2 12
DIN1 13
29 DOUT2
DIN2 13
DIN0 14
27 DOUT0
DIN9 5
36 VCC
NC 14
31 VSS
DIN1 15
30 DOUT1
DIN0 16
29 DOUT0
SWCK 17
28 SRCK
RSTW 18
27 RSTR
NC 19
26 NC
VWE 20
25 RE
IE 21
24 OE
VCC 22
SWCK 15
RSTW 16
WE 17
35 DOUT8
32 DOUT5
28 DOUT1
26 SRCK
25 RSTW
24 RE
IE 18
23 OE
NC 19
22 VSS
VCC 20
21 VCC
23 VCC
40PIn Plastick SOJ
44PIN Plastic TSOP (II)
(K Type)
Pin Name
SRCK
SWCK
WE
RE
IE
OE
RSTW
RSTR
Din0-11
Dout0-11
Vcc
Vss
NC
36 DOUT9
Function
Serial Read Clock
Serial Write Clock
Write Enable
Read Enable
Input Enable
Output Enable
Write Reset Clock
Read Reset Clock
Data Input
Data Output
Power Supply(3.3V)
Ground (0V)
No Connection
3
Data - out
Buffer (X12)
Serial
RE
RSTR
Read
SRCK
Controller
MSM54V12222A
OE
BLOCK DIAGRAM
Dout (X12)
512 Word Serial Read Register (X12)
Read line buffer
Low-Half (X12)
Read line buffer
High-Half (X12)
256 (X12)
71Words
Sub-Register (X12)
256 (X12)
X
Memory
Deco-
4
256K (X12)
Array
71 Words
Sub-Register (X12)
der
256 (X12)
Write line buffer
Low-Half (X12)
256 (X12)
Read/Write
and Refresh
Controller
Clock
Oscillator
Write line Buffer
High-Half (X12)
512 Word Serial Write Register (X12)
Data-in
Buffer (X12)
Serial
Read
Din (X12)
IE
WE
Controller
RSTW
SWCK
OKI Semiconductor
VBB
Generator
MSM54V12222A
OKI Semiconductor
OPERATION
Write Operation
The write operation is controlled by tree clocks, SWCK, RSTW, and WE. Write operation is accomplished
by cycling SWCK and holding WE high after write address pointer reset operation or RSTW.
Each write operation, which begins after RSTW, must contain at least 80 active write cycles, i.e. SWCK
cycles while WE is high. To transfer the last data, which at that time are stored in the serial data registers
attached to DRAM array, to the DRAM array, an RSTW operation is required after the last SWCK cycle.
Note that every write timing of MSM54V12222A is delayed by one clock compared wih read timings for
easy cascading without any interface delay devices.
Write Reset : RSTW
The first positive transition of SWCK after RSTW going high resets the write address counters to zero.
RSTW setup and hold times are referenced to the rising edge of SWCK. Because the write reset function
is solely controlled by SWCK rising edge after high level of RSTW, the states of WE and IE are don't care
in the write reset cycle.
Before RSTW may be brought high again for a further reset operation, it must have been low for at least
two SWCK cycles.
Data Inputs : Din0-11
Write Clock : SWCK
The SWCK latches the input data on chip when WE is high and also increments the internal write address
pointer. Data-in setup time, tDS and hold time, tDH, are referenced to the rising edge of SWCK.
Write Enable : WE
WE is used for data write enable/disable control. WE high level enables the input, and WE low level
disables the input and holds the internal write address pointer. There are no WE disable time (low) and
WE enable time (high) restrictions because MSM54V12222A is fully static operation as long as power is
on. Note that WE setup and hold times are referenced to the rising edge of SWCK.
Input Enable : IE
IE is used to enable/disable writing into memory. IE high level enables writing. The internal write address
pointer is always incremented by cycling SWCK regardless of IE level. Note that IE setup and hold times
are referenced to the rising edge of SWCK.
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OKI Semiconductor
MSM54V12222A
Read Operation
The read operation is controlled by tree clocks, SRCK, RSTR, and RE. Read operation is accomplished
by cycling SRCK and holding RE high after read address pointer reset operation or RSTR. Each read
operation, which begins after RSTR, must contain at least 80 active read cycles, i.e. SRCK cycles while
RE is high.
Read Reset : RSTR
The first positive transition of SRCK after RSTR going high resets the read address counters to zero.
RSTR setup and hold times are referenced to the rising edge of SRCK. Because the read reset function
is solely controlled by SRCK rising edge after high level of RSTR, the states of RE and RE are don't care
in the read reset cycle.
Before RSTR may be brought high again for a further reset operation, it must have been low for at least
*two SRCK cycles.
Data Out : Dout0-11
Read Clock : SRCK
Data is shifted out of the data registers triggered by the rising edge of SRCK when RE is high during a
read operation. The SRCK input increments the internal read address pointer when RE is high.
The three-state output buffer provides direct TTL compatibility ( no pullup resistor required). Data out is
the same polarity as data in. The output becomes valid after the access time interval tAC that begins with
the rising edge of SRCK. *There are no output valid time restriction on MSM54V12222A.
Read Enable : RE
The function of RE is gating of the SRCK clock, for incrementing the read pointer. When RE is high
before the rising edge of SRCK, the read pointer is incremented. When RE is low, the read pointer is not
incremented. RE setup times (tRENS and tRDSS) and RE hold times (tRENH and tRDSH) are referenced to the rising edge of the SRCK clock.
Output Enable : OE
OE is used to enable/disable the outputs. OE high level enables the outputs. The internal read address
pointer is always incremented by cycling SRCK regardless of OE level. Note that OE setup and hold times
are referenced to the rising edge of SRCK.
6
MSM54V12222A
OKI Semiconductor
Power-up and Initialization
On Powering up, the device is designed to begin proper operation after at least 100 us after VCC has
stabilized to a value within the range of recommended operating conditions. After this 100 us stabilization
interval, the following initialization sequence must be performed.
Because the read and write address counters are not valid after power-up, a minimum of 80 dummy write
operations (SWCK cycles) and read operations (SRCK cycles) must be performed, followed by an RSTW
operation and an RSTR operation, to properly initialize the write and the read address pointer. Dummy
write cycles/RSTW and dummy read cycles/RSTR may occur simultaneously.
If these dummy read and write operations start while VCC and/or the substrate voltage have not stabilized, it is required to perform an RSTR operation plus a minimum of 80 SRCK cycles plus another RSTR
operation, and an RSTW operation plus a minimum of 80 SRCK cycles plus another RSTW operation to
properly initialize read and write address pointers.
Old/New Data Access
There must be minimum delay of 600 SWCK cycles between writing into memory and reading out from
memory if reading from the first field starts with an RSTR operation, before the start of writing the second
field, (before the next RSTW operation), then the data just written in will be read out.
The start of reading out the first field of data may be delayed past the beginning of writing in the second
field of data for as many as 70 SWCK cycles. If the RSTR operation for the first field read-out occurs less
than 70 SWCK cycles after the RSTW operation for the second field write-in, then the internal buffering of
the device assures that the first field will still be read out. The first field of data that is read out while the
second field of data is written is called "old data".
In order to read out "new data", i.e., the second field written in, the delay between an RSTW operation and
an RSTR operation must be at least 600 SRCK cycles. If the delay between RSTW and RSTR operations
is more than 71 but less than 600 cycles, then the data read out will be undetermined. It may be "old data"
or "new" data or a combination of old and new data. Such a timing should be avoided.
Cascade Operation
The MSM5412222A has been designed to allow easy cascading of multiple memory devices, in order to
obtain a higher storage depth or a longer delay than can be achieved with only one memory device.
7
OKI Semiconductor
MSM54V12222A
ELECTRICAL CHARACTERISTICS
- Absolute Maximum Rating
Parameter
Symbol
Input Output Voltage
VT
Output Current
Power Dissipation
Operating Temperature
Storage Temperature
I OS
PD
T opr
T stg
Rating
Conditions
Unit
V
–1.0~4.6
50
1
0~70
at Ta = 25°C, Vss
Ta = 25°C
Ta = 25°C
—
—
mA
W
°C
–55~150
°C
- Recommended /peration Condition
Parameter
Symbol
MIN
TYP
MAX
Unit
VCC
VSS
3.0
0
2.4
3.3
0
Vcc
3.6
0
Vcc+0.3
–0.3
0
0.8
V
V
V
V
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
VIH
VIL
- DC Characteristics
Parameter
Input Leakage Current
Output Leakage Current
Output "H" Level Voltage
Output "L" Level Voltage
Operating Current
Standby Current
Symbol
Condition
Min
Max
Unit
ILI
0<Vi<+0.3,Other Pins Tested at V=0V
0<Vo<Vcc
IOH=-1mA
IOL=2mA
-10
10
mA
-10
2.4
10
0.4
60
mA
V
V
mA
3
mA
ILO
VOH
VOL
ICC1
ICC2
Minimum Cycle Time,Output Open
Input Pin=VIH/VIL
- Capacitance
(Ta = 25°C, f = 1 MHz)
Parameter
Input Capacitance (Din, SWCK, SRCK, RSTW, RSTR, WE, RE, IE, OE)
Output Capacitance (Dout)
8
Symbol
MAX
Unit
Ci
Co
7
10
pF
pF
MSM54V12222A
OKI Semiconductor
AC CHARACTERISTICS
(Vcc = 3.3V±0.3V, Ta = 0~70°C)
Parameter
Symbol
Access Time from SRCK
Dout Hold Time from SRCK
t AC
t DDCK
Dout Enable Time from SRCK
SWCK "H" Pulse Width
SWCK "L" Pulse Width
t DECK
t WSWH
t WSWL
Input Data Setup Time
Input Data Hold Time
WE Enable Setup Time
WE Enable Hold Time
WE Disable Setup Time
WE Disable Hold Time
IE Enable Setup Time
IE Enable Hold Time
IE Disable Setup Time
IE Disable Hold Time
t DS
t DH
t WENS
t WENH
WE "H" Pulse Width
WE "L" Pulse Width
IE "H" Pulse Width
IE "L" Pulse Width
RSTW Setup Time
RSTW Hold Time
SRCK "H" Pulse Width
SRCK "L" Pulse Width
RE Enable Setup Time
RE Enable Hold Time
RE Disable Setup Time
RE Disable Hold Time
OE Enable Setup Time
OE Enable Hold Time
OE Disable Setup Time
OE Disable Hold Time
RE "H" Puls Width
RE "L" Puls Width
OE "H" Puls Width
OE "L" Puls Width
RSTR Setup Time
RSTR Hold Time
SWCK Cycle Time
SRCK Cycle Time
Trandition Time (Rise and Fall)
MSM54V12222A-30
MIN
MAX
—
6
6
12
12
5
6
0
5
0
5
0
t WDSS
t WDSH
t IENS
t IENH
t IDSS
t IDSH
t WWEH
t WWEL
t WIEH
5
0
5
10
10
10
10
0
10
12
12
0
5
0
5
0
5
0
t WIEL
t RSTWS
t RSTWH
t WSRH
t WSRL
t RENS
t RENH
t RDSS
t RDSH
t OENS
t OENH
t ODSS
t ODSH
t WREH
5
t WREL
t WOEH
t WOEL
t RSTRS
t RSTRH
t SWC
t SRC
tT
30
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
10
10
10
—
0
—
10
30
30
—
—
—
30
3
9
30
—
—
—
—
MSM54V12222A-40
MIN
MAX
—
35
6
6
—
35
17
17
—
—
5
6
0
5
0
5
0
5
0
5
10
—
—
—
—
—
—
—
—
—
10
10
10
0
10
17
17
0
5
0
5
0
5
—
—
—
—
—
—
—
—
—
—
—
—
—
0
5
10
—
—
—
10
—
10
10
0
—
—
—
—
10
40
40
3
—
—
—
—
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OKI Semiconductor
MSM54V12222A
NOTE
1. Input signal reference levels for the parameter measurement are VIH=3.0V
and VIL=0V.
The transition time tT is defined to be a transition time that signal transfers between VIH=3.0V
and VIL=0V.
2. AC measurements assume tT=3ns.
3. Read address must have more than 600 address delay than write address in every cycle
when asynchronous read/write is performed.
4. Read must have more than 600 address delay than write in order to read the data written in a
current series of write cycle which has been started last write reset cycle : this is called "new
data read".
When read has less than 70 address delay than write, the read data are the data written in a
previous series of write cycle which had been written before last write reset cycle: this is called
"old data read".
5. When the read address delay is between more than 71 and less than 599, read data will be
undetermined. However, normal write is achieved in this address condition.
6. Outputs are measured with a load equivalent to 1 TTL load and 30pF.
Output reference levels are VOH=2.0V and VOL=0.8V.
10
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MSM54V12222A
OKI Semiconductor
WRITE CYCLE TIMING (Write Reset)
n cycle
0 cycle
2 cycle
1 cycle
—V IH
—V IL
SWCK
t WSWH
t WSWL
t RSTWH
t RSTWS
tT
t SWC
—V IH
—V IL
RSTW
t DH
tDS
Din
n-1
n
0
1
2
WE
—V IH
—V IL
—V IH
—V IL
IE
—V IH
—V IL
WRITE CYCLE TIMING (Write Enable)
n cycle
disable cycle
disable cycle
n+1 cycle
—V IH
—V IL
SWCK
t WDSH
t WENH
t WDSS
t WENS
—V IH
WE
t WWEL
Din
n-1
—V IL
t WWEH
n
n+1
—V IH
—V IL
—V IH
IE
—V IL
—V IH
—V IL
RSTW
11
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%&'.(/0
OKI Semiconductor
MSM54V12222A
WRITE CYCLE TIMING (Input Enable)
n cycle
n+1 cycle
n+2 cycle
n+3 cycle
—V IH
—V IL
SWCK
t IDSH
t IENH
t IENS
t IDSS
—V IH
—V IL
IE
t WIEH
t WIEL
n-1
Din
n
n+3
—V IH
—V IL
—V IH
—V IL
WE
—V IH
—V IL
RSTW
READ CYCLE TIMING (Read Reset)
n cycle
0 cycle
2 cycle
1 cycle
—VIH
SRCK
—VIL
t WSRH
t RSTRH
tT
t WSRL
t RSTRS
t SRC
—VIH
—VIL
RSTR
t DDCK
t AC
Dout
n-1
n
0
1
RE
2
—VOH
—VOL
—VIH
—VIL
OE
—V IH
—V IL
12
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MSM54V12222A
OKI Semiconductor
READ CYCLE TIMING (Read Enable)
n cycle
disable cycle
disable cycle
n+1 cycle
—V IH
—V IL
SRCK
t RDSS
t RDSH
t RENH
t RENS
—V IH
—V IL
RE
t WREL
Dout
t WREH
n-1
n
n+1
—V OH
—V OL
—V IH
—V IL
OE
—V IH
—V IL
RSTR
READ CYCLE TIMING (Output Enable)
n cycle
n+1 cycle
n+2 cycle
n+3 cycle
—V IH
—V IL
SRCK
t ODSS
t ODSH
t OENH
t OENS
—V IH
OE
t WOEN
Dout
n-1
n
—V IL
t DECK
t WOEH
Hi-Z
n+3
—V OH
—V OL
—V IH
RE
—V IL
—V IH
—V IL
RSTR
13
OKI Semiconductor
MSM54V12222A
NOTICE
1. The information contained herein is just a technical information for readers to know preliminary OKI
256KX12 bits FRAM idea.
2. The information herein does not guarantee configuration, features, characteristic, performance and
packages of the final products.
3. NO RESPONSIBILITY IS ASSUMED BY US FOR ANY CONSEQUENCE RESULTING FROM THE
INFORMATION HEREIN.
4. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 1994 OKI ELECTRIC INDUSTRY CO.,LTD
14