DATA SHEET MOS INTEGRATED CIRCUIT µPD485506 LINE BUFFER 5K-WORD BY 16-BIT/10K-WORD BY 8-BIT Description The µPD485506 is a high speed FIFO (First In First Out) line buffer. Word organization can be changed either 5,048 words by 16 bits or 10,096 words by 8 bits. Its CMOS static circuitry provides high speed access and low power consumption. The µPD485506 can be used for one line delay and time axis conversion in high speed facsimile machines and digital copiers. Moreover, the µPD485506 can execute read and write operations independently on an asynchronous basis. Thus the µPD485506 is suitable as a buffer for data transfer between units with different transfer rates and as a buffer for the synchronization of multiple input signals. There are four versions, E, K, P, X and L. This data sheet can be applied to the version X and L. These versions operate with different specifications. Each version is identified with its lot number (refer to 7. Example of Stamping). Features • 5,048 words by 16 bits (Word mode) /10,096 words by 8 bits (Byte mode) • Asynchronous read/write operations available • Variable length delay bits; 21 to 5,048 bits or 10,096 bits (Cycle time: 25 ns) 15 to 5,048 bits or 10,096 bits (Cycle time: 35 ns) • Power supply voltage VCC = 5.0 V ±0.5 V • Suitable for sampling two lines of A3 size paper (16 dots/mm) • All input/output TTL compatible • 3-state output • Full static operation; data hold time = infinity Ordering Information Part Number R/W Cycle Time Package µPD485506G5-25-7JF 25 ns 44-pin plastic TSOP (II) (10.16 mm (400)) µPD485506G5-35-7JF 35 ns The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M10060EJ7V0DSJ1 (7th edition) Date Published December 2000 N CP(K) Printed in Japan The mark shows major revised points. © 1994 µPD485506 Pin Configuration (Marking side) 44-pin plastic TSOP (II) (10.16 mm (400)) [µPD485506G5-7JF] DOUT0 1 44 DIN0 DOUT1 2 43 DIN1 DOUT2 3 42 DIN2 DOUT3 4 41 DIN3 DOUT4 5 40 DIN4 DOUT5 6 39 DIN5 DOUT6 7 38 DIN6 DOUT7 8 37 DIN7 OE 9 36 WE RE 10 35 MD GND 11 34 GND RSTR 12 33 RSTW RCK 13 32 WCK VCC 14 31 VCC DOUT8 15 30 DIN8 DOUT9 16 29 DIN9 DOUT10 17 28 DIN10 DOUT11 18 27 DIN11 DOUT12 19 26 DIN12 DOUT13 20 25 DIN13 DOUT14 21 24 DIN14 DOUT15 22 23 DIN15 D IN0 to D IN15 : Data Inputs D OUT0 to D OUT15 : Data Outputs Remark 2 WCK : Write Clock Input RCK : Read Clock Input WE : Write Enable Input RE : Read Enable Input OE : Output Enable Input RSTW : Reset Write Input RSTR : Reset Read Input MD : Mode Set Input V CC : +5.0 V Power Supply GND : Ground Refer to Package Drawing for the 1-pin index mark. Data Sheet M10060EJ7V0DS00 µPD485506 Block Diagram VCC GND RSTW WCK Write Address Pointer RSTR RCK Read Address Pointer WE RE DIN1 DOUT1 DIN4 DIN5 40,384 bits (5,048 words by 8 bits) Output Buffer DIN3 Memory Cell Array Input Buffer DIN2 Output Controller DOUT0 Input Controller DIN0 DOUT2 DOUT3 DOUT4 DOUT5 DIN6 DOUT6 DIN7 DOUT7 OE DIN10 DIN11 DIN12 DIN13 Memory Cell Array 40,384 bits (5,048 words by 8 bits) Output Controller DOUT9 Output Buffer DIN9 Input Buffer DOUT8 Input Controller DIN8 DOUT10 DOUT11 DOUT12 DOUT13 DIN14 DOUT14 DIN15 DOUT15 Mode Controller MD Data Sheet M10060EJ7V0DS00 3 µPD485506 1. Input/Output Pin Function Pin Pin Name I/O DIN0 | DIN15 Data Input In 1 – 8, DOUT0 | Data Output Out 15 – 22 DOUT15 Read data output pins. The access time is regulated from the rising edge of RCK at the beginning of a cycle and defined by tAC. 33 RSTW Reset Write Input In Reset input pin for the initialization of the write address pointer. The state of RSTW is strobed by the rising edge of WCK at the beginning of a cycle and the setup and hold times (tRS, tRH) are defined. 12 RSTR Reset Read Input In Reset input pin for the initialization of the read address pointer. The state of RSTR is strobed by the rising edge of RCK at the beginning of a cycle and the setup and hold times (tRS, tRH) are defined. 36 WE Write Enable Input In Write operation control signal input pin. When WE is in the disable mode (“H” level), the internal write operation is inhibited and the write address pointer stops at the current position. 10 RE Read Enable Input In Read operation control signal input pin. When RE is in the disable mode (“H” level), the internal read operation is inhibited and the read address pointer stops at the current position. The data outputs remain valid for that address. 9 OE Output Enable Input In Output operation control signal input pin. When OE is in the disable mode (“H” level), the data out is inhibited and the output changes to high impedance. The internal read operation is executed at that time and the read address pointer incremented in synchronization with the read clock. 32 WCK Write Clock Input In Write clock input pin. When WE is enabled (“L” level), the write operation is executed in synchronization with the write clock. The write address pointer is incremented simultaneously. 13 RCK Read Clock Input In Read clock input pin. When RE is enabled (“L” level), the read operation is executed in synchronization with the read clock. The read address pointer is incremented simultaneously. 35 MD Mode Set Input In Mode set input pin. The level of MD gives the operation mode. When MD is in “L” level, 5,048 words by 16 bits configuration with DIN0 - DIN15, DOUT0 - DOUT15 is enabled. When MD is in “H” level, 10,096 words by 8 bits configuration with DIN0 - DIN7, DOUT0 - DOUT7 is enabled. Pin Number 44 – 37, 30 – 23 4 Symbol Function Write data input pins. The data inputs are strobed by the rising edge of WCK at the end of a cycle and the setup and hold times (tDS, tDH) are defined at this point. Data Sheet M10060EJ7V0DS00 µPD485506 2. Operation Mode µ PD485506 is a synchronous memory. All signals are strobed at the rising edge of the clock (RCK, WCK). For this reason, setup time and hold time are specified for the rising edge of the clock (RCK, WCK). 2.1 Mode Set Cycle (5,048 words by 16 bits or 10,096 words by 8 bits organization) µ PD485506 has a capability of selecting from two operation modes by judging the MD level when RSTW or RSTR is enabled in the reset cycle. MD Level Bit Configuration “L” 5,048 words by 16 bits “H” Caution Data Inputs/Outputs 10,096 words by 8 bits Control Signal DIN0 - DIN15 WCK, WE, RSTW DOUT0 - DOUT15 RCK, RE, RSTR DIN0 - DIN7 WCK, WE, RSTW DOUT0 - DOUT7 RCK, RE, RSTR Don’t change the MD level during a reset cycle. (See Figure 4.6, 7, 8, 9 Mode Set Cycle Timing Chart) 5,048 Words by 16 Bits FIFO WCK WE RSTW 5,048 Words by 16 Bits DIN0 - DIN15 RCK RE DOUT0 - DOUT15 RSTR OE 10,096 Words by 8 Bits FIFO WCK DIN0 - DIN7 WE RSTW 10,096 Words by 8 Bits RCK RE RSTR DOUT0 - DOUT7 OE Remark Fix DIN8 - DIN15 to “L” or “H” level in the 10,096 words by 8 bits mode. Data Sheet M10060EJ7V0DS00 5 µPD485506 2.2 Write Cycle When the WE input is enabled (“L” level), a write cycle is executed in synchronization with the WCK clock input. The data inputs are strobed by the rising edge of the clock at the end of a cycle so that read data after a oneline (5,048 bits or 10,096 bits) delay and write data can be processed with the same clock. Refer to Write Cycle Timing Chart. When WE is disabled (“H” level) in a write cycle, the write operatoin is not performed during the cycle which the WCK rising edge is in the WE = “H” level (tWEW ). The WCK does not increment the write address pointer at this time. Unless inhibited by WE, the internal write address will automatically wrap around from 5,047 to 0 and begin incrementing again. 2.3 Read Cycle When the RE input is enabled (“L” level), a read cycle is executed in synchronization with the RCK clock input. When the OE input is also enabled (“L” level) at that time, data is output after tAC . Refer to Read Cycle Timing Chart. When RE is disabled (“H” level) in a read cycle, the read operation is not performed during the cycle which the RCK rising edge is in the RE = “H” level (t REW). The RCK does not increment the read address pointer at this time. 2.4 Write Reset Cycle/Read Reset Cycle After power up, the µ PD485506 requires the initialization of internal circuits because the read and write address pointers are not defined at that time. It is necessary to satisfy setup requirements and hold times as measured from the rising edge of WCK and RCK, and then input the RSTW and RSTR signals to initialize the circuit. Write and read reset cycles can be executed at any time and the address pointer returns zero. Refer to Write Reset Cycle Timing Chart, Read Reset Cycle Timing Chart. Remark Write and read reset cycles can be executed at any time and do not depend on the state of RE, WE or OE. 6 Data Sheet M10060EJ7V0DS00 µPD485506 Operation-related Restriction Following restriction exists to read data written in a write cycle. Read the written data after an elapse of 1/2 write cycle + t WAR since the write cycle ends (see Figure 2.1). If t WAR is not satisfied, the output data may undefined. Figure 2.1 Delay Bits Restriction Timing Chart 0 1 2 3 WCK 1/2 write cycle tWAR 0 1 2 RCK High impedance DIN 0 1 2 3 tAC High impedance DOUT 0 1 2 3 Remark This timing chart describes only the delay bits restriction, and does not defines the WE, RE, RSTW, RSTR signals. Data Sheet M10060EJ7V0DS00 7 µPD485506 3. Electrical Specifications All voltages are referenced to GND. Absolute Maximum Ratings Parameter Symbol Condition Rating –0.5Note Voltage on any pin relative to GND VT Supply voltage VCC Output current Unit to VCC + 0.5 V –0.5 to +7.0 V IO 20 mA Operating ambient temperature TA 0 to 70 ˚C Storage temperature Tstg –55 to +125 ˚C Note –3.0 V MIN. (Pulse width = 10 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition MIN. TYP. MAX. Unit 5.0 5.5 V Supply voltage VCC 4.5 High level input voltage VIH 2.4 VCC + 0.5 V Low level input voltage VIL –0.3Note +0.8 V Operating ambient temperature TA 0 70 ˚C MAX. Unit 140 mA Note –3.0 V MIN. (Pulse width = 10 ns) DC Characteristics (Recommended Operating Conditions unless otherwise noted) Parameter Symbol Test Condition MIN. TYP. Operating current ICC Input leakage current II VI = 0 to VCC, Other Input 0 V –10 +10 µA Output leakage current IO VO = 0 to VCC, DOUT: High impedance –10 +10 µA High level output voltage VOH IOH = –1 mA 2.4 Low level output voltage VOL IOL = 2 mA V 0.4 V MAX. Unit Capacitance (TA = 25 ˚C, f = 1 MHz) Parameter 8 Symbol Test Condition MIN. TYP. Input capacitance CI 10 pF Output capacitance CO 10 pF Data Sheet M10060EJ7V0DS00 µPD485506 AC Characteristics (Recommended Operating Conditions unless otherwise noted)Notes 1, 2, 3 Parameter Symbol µPD485506-25 µPD485506-35 MIN. MIN. MAX. Unit Notes MAX. Write clock cycle time tWCK 25 35 ns Write clock pulse width tWCW 11 12 ns Write clock precharge time tWCP 11 12 ns Read clock cycle time tRCK 25 35 ns Read clock pulse width tRCW 11 12 ns Read clock precharge time tRCP 11 12 ns Access time tAC Write data-read delay time tWAR 470 470 ns Output hold time tOH 5 5 ns Output low-impedance time tLZ 5 18 5 25 ns 4 Output high-impedance time tHZ 5 18 5 25 ns 4 Input data setup time tDS 7 10 ns Input data hold time tDH 3 3 ns MD Set setup time tMS 20 20 ns MD Set hold time tMH 10 10 ns MD Set time tMD 0 0 ns 5 Output low-impedance time (Mode change) tLZM 5 18 5 25 ns 4 Output high-impedance time (Mode change) tHZM 5 18 5 25 ns 4 RSTW/RSTR Setup time tRS 7 10 ns 6 RSTW/RSTR Hold time tRH 3 3 ns 6 RSTW/RSTR Deselected time (1) tRN1 3 3 ns 7 RSTW/RSTR Deselected time (2) tRN2 7 10 ns 7 WE Setup time tWES 7 10 ns 8 WE Hold time tWEH 3 3 ns 8 WE Deselected time (1) tWEN1 3 3 ns 9 WE Deselected time (2) tWEN2 7 10 ns 9 RE Setup time tRES 7 10 ns 10 RE Hold time tREH 3 3 ns 10 RE Deselected time (1) tREN1 3 3 ns 11 RE Deselected time (2) tREN2 7 10 ns 11 OE Setup time tOES 7 10 ns 10 OE Hold time tOEH 3 3 ns 10 OE Deselected time (1) tOEN1 3 3 ns 11 OE Deselected time (2) tOEN2 7 10 ns 11 WE Disable time tWEW 0 0 ms RE Disable time tREW 0 0 ms OE Disable time tOEW 0 0 ms Write reset time tRSTW 0 0 ms Read reset time tRSTR 0 0 ms Transition time tT 3 18 Data Sheet M10060EJ7V0DS00 35 25 3 35 ns ns 9 µPD485506 Notes 1. AC measurements assume tT = 5 ns. 2. AC Characteristics test condition Input Timing Specification 3.0 V 1.5 V Test points 0V tT = 5 ns tT = 5 ns Output Timing Specification 2.0 V High impedance High impedance Test points 0.8 V Output Loads for Timing VCC VCC 1.8 kΩ 1.8 kΩ DOUT DOUT 1.1 kΩ 30 pF 1.1 kΩ (tAC,tOH) 5 pF (tLZ,tHZ) 3. Input timing reference levels = 1.5 V. Output timing reference levels; VOH = 2.0 V, VOL = 0.8 V. 4. tLZ, tHZ, tLZM and tHZM are measured at ±200 mV from the steady state voltage. Under any conditions, tLZ ≥ tHZ and tLZM ≥ tHZM. 5. Mode set signal (MD) must be input synchronously with write reset signal (tRSTW period) or read reset signal (tRSTR period). Under this condition, tRSTW = tMD (tRSTR = tMD). 6. If either tRS or tRH is less than the specified value, reset operations are not guaranteed. 7. If either tRN1 or tRN2 is less than the specified value, reset operations may extend to cycles preceding or following the period of reset operations. 8. If either tWES or tWEH is less than the specified value, write disable operations are not guaranteed. 9. If either tWEN1 or tWEN2 is less than the specified value, internal write disable operations may extend to cycles preceding or following the period of write disable operations. 10. If either tRES or tREH, tOES or tOEH is less than the specified value, read disable operations are not guaranteed. 11. If either tREN1 or tREN2, tOEN1 or tOEN2 is less than the specified value, internal read disable operations may extend to cycles preceding or following the period of read disable operations. 10 Data Sheet M10060EJ7V0DS00 µPD485506 Write Cycle Timing Chart Cycle n Cycle n+1 Cycle n+2 Disable Cycle Cycle n+3 tWCK tWCP WCK (Input) tWCW tWEN1 tWES tWEH tWEN2 WE (Input) tWEW tDS DIN (Input) tDH tDS (n) (n+1) tDH (n+2) (n+3) Remark RSTW = “H” level Read Cycle Timing Chart (RE Control) Cycle n+1 Cycle n Cycle n+2 Disable Cycle Cycle n+3 tRCK tRCP RCK (Input) tRCW tREN1 tREH tRES tREN2 tAC tAC tREW RE (Input) tOH tOH tOH DOUT (Output) (n) (n+3) (n+2) (n+1) Remark OE = “L” level, RSTR = “H” level Read Cycle Timing Chart (OE Control) Cycle n Cycle n+1 Cycle n+2 Disable Cycle Cycle m tRCK tRCP RCK (Input) tRCW tOEN1 tOES tOEH tOEN2 tOH tAC OE (Input) tOEW tAC tHZ tLZ DOUT (Output) High impedance (n) (n+1) (n+2) tLZ High impedance (m) Remark RE = “L” level, RSTR = “H” level Data Sheet M10060EJ7V0DS00 11 µPD485506 Write Reset Cycle Timing Chart (WE = Active) Cycle n Reset Cycle Cycle 0 Cycle 1 WCK (Input) tRN1 tRSTW Note tRS tRH tRN2 RSTW (Input) WE (Input) “L” Level tDS DIN (Input) Note (n–1) tDH tDS (n) tDH (0) (1) In write reset cycle, reset operation is executed even without a reset cycle (tRSTW). WCK can be input any number of times in a reset cycle. Write Reset Cycle Timing Chart (WE = Inactive) Cycle n Disable Cycle Cycle 0 Reset Cycle WCK (Input) tRN1 tRS tWEN1 tWES tRSTW Note tRH tRN2 tWEH tWEN2 RSTW (Input) WE (Input) tWEW tDS DIN (Input) Note (n–1) tDH (n) (0) In write reset cycle, reset operation is executed even without a reset cycle (tRSTW). WCK can be input any number of times in a reset cycle. 12 tDS Data Sheet M10060EJ7V0DS00 µPD485506 Read Reset Cycle Timing Chart (RE = Active) Cycle n Reset Cycle Cycle 0 Cycle 1 RCK (Input) tRN1 tRSTR Note tRS tRH tRN2 RSTR (Input) RE (Input) “L” Level tAC DOUT (Output) tAC tAC (n – 1) (n) tAC (0) (0) tOH Note (1) tOH tOH In read reset cycle, reset operation is executed even without a reset cycle (tRSTR). RCK can be input any number of times in a reset cycle. Remark OE = “L” level Read Reset Cycle Timing Chart (RE = Inactive) Cycle n Disable Cycle Cycle 0 Reset Cycle RCK (Input) tRSTR Note tRN1 tRS tREN1 tRES tRH tRN2 tREH tREN2 RSTR (Input) RE (Input) tREW tAC DOUT (Output) (n–1) tAC tAC (n) Indefinite Data tOH Note (0) tOH In read reset cycle, reset operation is executed even without a reset cycle (tRSTR). RCK can be input any number of times in a reset cycle. Remark OE = “L” level Data Sheet M10060EJ7V0DS00 13 µPD485506 4. Application 4.1 1 H Delay Line µPD485506 easily allows a 1 H (5,048 bits/10,096 bits) delay line (see Figure 4.1). Figure 4.1 1 H Delay Line Circuit 40 MHz Clock Reset Data Input WCK RCK DIN DOUT WE RE Data Output 8/16 8/16 RSTW RSTR Figure 4.2 1 H Delay Line Timing Chart Write Read WCK/RCK (Input) Cycle 0 2H (5,048/10,096 Cycles) 1H (5,048/10,096 Cycles) tWCK tRCK Cycle 1 Cycle 5,047Note (10,095) Cycle 2 Cycle 0’ Cycle 0 Cycle 1’ Cycle 1 Cycle 2’ Cycle 2 Cycle 3’ Cycle 3 tWCW tWCP tRCW tRCP tRS tRH RSTW/ RSTR (Input) DIN (Input) tDS tDS tDH tDH (0) (1) (2) (5,046) (10,094) (5,047) (10,095) tAC DOUT (Output) Note 5,048 cycles by 16 bits/10,096 cycles by 8 bits Data Sheet M10060EJ7V0DS00 (1’) (2’) (3’) tOH (0) Remark RE, WE, OE = “L” level 14 (0’) (1) (2) (3) µPD485506 4.2 n Bit Delay It is possible to make delay read from the write data with the µ PD485506. (1) Perform a reset operation in the cycle proportionate to the delay length (see Figure 4.3). (2) Shift the input timing of write reset (RSTW) and read reset (RSTR) depending on the delay length (see Figure 4.4). (3) Shift the address by disabling RE for the period proportionate to the delay length (see Figure 4.5). n bit: Delay bits from write cycle to read cycle correspond to a same address cell. Restrictions Delay bits n can be set from minimum bits to maximum bits depending on the operating cycle time. Refer to 2. Operation Mode Operation-related Restriction. MAX. Cycle Time MIN. MD = “L” Level MD = “H” Level 25 ns 21 bits 5,048 bits 10,096 bits 35 ns 15 bits 5,048 bits 10,096 bits Figure 4.3 n-Bit Delay Line Timing Chart (1) Write Read WCK/RCK (Input) Cycle 0 2H (n Cycles) 1H (n Cycles) tWCK tRCK Cycle 1 Cycle 2 Cycle (n–1) Cycle 0’ Cycle 0 DIN (Input) Cycle 2’ Cycle 2 Cycle 3’ Cycle 3 tWCW tWCP tRCW tRCP tRS tRS tRH RSTW/ RSTR (Input) Cycle 1’ Cycle 1 tRH tDS tDS tWAR tDH (0) (1) (2) tDH (n–2) (n–1) (0’) tAC DOUT (Output) (1’) (2’) (3’) tOH (0) (1) (2) (3) Remark RE, WE, OE = “L” level Data Sheet M10060EJ7V0DS00 15 µPD485506 Figure 4.4 n-Bit Delay Line Timing Chart (2) tWCK tRCK Write Read WCK/RCK (Input) Cycle 0 Cycle 1 Cycle 2 Cycle n Cycle 0 Cycle n–1 Cycle n+1 Cycle n+2 Cycle 1 Cycle 2 Cycle n+3 Cycle 3 tWCW tWCP tRCW tRCP tRS tWAR tRH tRS RSTW (Input) tRH RSTR (Input) tDS tDS tDH tDH DIN (Input) (0) (1) (2) (n–2) (n–1) n Cycles (n) tAC (n+1) (n+2) (n+3) tOH DOUT (Output) (0) (1) (2) (3) Remark RE, WE, OE = “L” level Figure 4.5 n-Bit Delay Line Timing Chart (3) tWCK tRCK Write Read WCK/RCK (Input) Cycle 0 Cycle 1 Cycle 2 Cycle n–1 tRS tREH tREN2 tDS tDS tDH (0) tDH (1) n Cycles DOUT (Output) (2) (n–2) (n–1) tAC High impedance (n) Data Sheet M10060EJ7V0DS00 (n+1) (n+2) (n+3) tOH (0) Remark WE, OE = “L” level 16 Cycle n+3 Cycle 3 tWAR RSTW/ RSTR (Input) DIN (Input) Cycle n+1 Cycle n+2 Cycle 1 Cycle 2 tWCW tWCP tRCW tRCP tRH RE (Input) Cycle n Cycle 0 (1) (2) (3) µPD485506 Figure 4.6 Mode Set Cycle Timing Chart (Write) (1) Cycle n Cycle 0 Reset Cycle tMS tMD tMH tRS tRSTW tRH Cycle 1 MD (Input) RSTW (Input) tRN1 tRN2 WCK (Input) tDS DIN0 - DIN7 (Input) tDH tDS (n–1) tDS DIN8 - DIN15 (Input) (n) tDH tDS (n–1) tDH tDS tDH (0) (1) tDH (n) Remark WE = “L” level Figure 4.7 Mode Set Cycle Timing Chart (Write) (2) Cycle n Cycle 0 Reset Cycle tMS tMD tMH tRS tRSTW tRH Cycle 1 MD (Input) RSTW (Input) tRN1 tRN2 WCK (Input) tDS DIN0 - DIN7 (Input) tDH (n–1) tDS tDH tDS (n) tDH (0) tDS DIN8 - DIN15 (Input) (1) tDH (0) (1) Remark WE = “L” level Data Sheet M10060EJ7V0DS00 17 µPD485506 Figure 4.8 Mode Set Cycle Timing Chart (Read) (1) Cycle n Cycle 0 Reset Cycle tMS tMD Cycle 1 tMH MD (Input) RSTR (Input) tRN1 RCK (Input) tRS tRSTR tAC tAC DOUT0 - DOUT7 (Output) (n–1) tAC tOH (n) tOH tOH (0) tAC (1) (0) tHZM tOH DOUT8 - DOUT15 (Output) tAC tOH tOH tRN2 tRH tOH (n–1) High impedance (n) Remark RE, OE = “L” level Figure 4.9 Mode Set Cycle Timing Chart (Read) (2) Cycle n Cycle 0 Reset Cycle tMS tMD tRS tRSTR Cycle 1 tMH MD (Input) RSTR (Input) tRN1 RCK (Input) tAC tAC (n–1) (n) tOH (0) (1) tAC tOH (0) Remark RE, OE = “L” level 18 tOH (0) tAC tAC High impedance tAC tOH tLZM DOUT8 - DOUT15 (Output) tRN2 tAC tOH tOH DOUT0 - DOUT7 (Output) tRH Data Sheet M10060EJ7V0DS00 tOH tOH (0) (1) µPD485506 4.3 Double-speed Conversion Figure 4.10 shows an example timing chart of double-speed and twice reading operation (fR = 2f W, 5,048 by 2 cycles or 10,096 by 2 cycles Note ) for a write operation (fW = 5,048 cycles or 10,096 cycles). Caution The read operation collide with the write operation on the same line, last n bits output data (5,048 –n to 5,048/10,096 –n to 10,096) in the first read operation will be undefined (see Figure 4.10 Double-speed Conversion Timing Chart). Undefined bits mentioned above depend on the cycle time. Note Read Cycle Time Undefined Bits 25 ns 21 bits 35 ns 15 bits 5,048 cycles by 16 bits/10,096 cycles by 8 bits Data Sheet M10060EJ7V0DS00 19 20 Figure 4.10 Double-speed Conversion Timing Chart 1H (5,048/10,096 CyclesNote) 0 1 2H (5,048/10,096 Cycles) 5,046Note 5,047 (10,094) (10,095) 2 0’ 1’ 5,046’ 5,047’ (10,094’) (10,095’) 2’ 0” WCK (Input) RSTW (Input) DIN (Input) 0 1 Note 2 5,046 5,047 (10,094) (10,095) 0’ 1’ 2’ 5,046’ 5,047’ 0” (10,094’) (10,095’) Data Sheet M10060EJ7V0DS00 1H (5,048/10,096 CyclesNote) First read cycle 1H (5,048/10,096 Cycles) Second read cycle 2H (5,048/10,096 Cycles) First read cycle RCK (Input) RSTR (Input) tAC DOUT (Output) 0 1 2 Note 5,046 5,047 0 1 2 (10,094) (10,095) n bits output data will be undefined. Note 5,046 5,047 0’ 1’ 2’ (10,094) (10,095) 5,046’ 5,047’ 0’ 1’ (10,094’) (10,095’) n bits output data will be undefined. 5,048 cycles by 16 bits/10,096 cycles by 8 bits µPD485506 Remark RE, WE = “L” level µPD485506 5. Package Drawing 44-PIN PLASTIC TSOP(II) (10.16 mm (400)) 44 23 detail of lead end F P E 1 22 A H G I S C D N M M J L S B K NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 18.63 MAX. B 0.93 MAX. C 0.8 (T.P.) D 0.32 +0.08 −0.07 E 0.1±0.05 F 1.2 MAX. G 0.97 11.76±0.2 10.16±0.1 H I J 0.8±0.2 K 0.145+0.025 −0.015 L M 0.5±0.1 0.13 N 0.10 P 3°+7° −3° S44G5-80-7JF5-1 Data Sheet M10060EJ7V0DS00 21 µPD485506 6. Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µ PD485506. Type of Surface Mount Device µ PD485506G5-7JF: 44-pin plastic TSOP (II) (10.16 mm (400)) 7. Example of Stamping Letter E in the fifth character position in a lot number signifies version E, letter K, version K, letter P, version P, letter X, version X, and letter L, version L. JAPAN D485506 Lot number 22 Data Sheet M10060EJ7V0DS00 µPD485506 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M10060EJ7V0DS00 23 µPD485506 [MEMO] • The information in this document is current as of December, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4