DATA SHEET MOS INTEGRATED CIRCUIT µPD485505 LINE BUFFER 5K-WORD BY 8-BIT Description The µPD485505 is a 5,048 words by 8 bits high speed FIFO (First In First Out) line buffer. Its CMOS static circuitry provides high speed access and low power consumption. The µPD485505 can be used for one line delay and time axis conversion in high speed facsimile machines and digital copiers. Moreover, the µPD485505 can execute read and write operations independently on an asynchronous basis. Thus the µPD485505 is suitable as a buffer for data transfer between units with different transfer rates and as a buffer for the synchronization of multiple input signals. There are three versions, E, K, P, and L. This data sheet can be applied to the version P and L. These versions operate with different specifications. Each version is identified with its lot number (refer to 7. Example of Stamping). Features • 5,048 words by 8 bits • Asynchronous read/write operations available • Variable length delay bits; 21 to 5,048 bits (Cycle time: 25 ns) 15 to 5,048 bits (Cycle time: 35 ns) • Power supply voltage VCC = 5.0 V ± 0.5 V • Suitable for sampling one line of A3 size paper (16 dots/mm) • All input/output TTL compatible • 3-state output • Full static operation; data hold time = infinity Ordering Information Part Number µPD485505G-25 µPD485505G-35 R/W Cycle Time 25 ns 35 ns Package 24-pin plastic SOP (11.43 mm (450)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M10059EJ7V0DSJ1 (7th edition) Date Published December 2000 N CP(K) Printed in Japan The mark shows major revised points. © 1994,1996 µPD485505 Pin Configuration (Marking side) 24-pin plastic SOP (11.43 mm (450)) [µPD485505G] DOUT0 1 24 DIN0 DOUT1 2 23 DIN1 DOUT2 3 22 DIN2 DOUT3 4 21 DIN3 RE 5 20 WE RSTR 6 19 RSTW GND 7 18 VCC RCK 8 17 WCK DOUT4 9 16 DIN4 DOUT5 10 15 DIN5 DOUT6 11 14 DIN6 DOUT7 12 13 DIN7 D IN0 - D IN7 : Data Inputs D OUT0 - D OUT7 : Data Outputs WCK : Write Clock Input RCK : Read Clock Input WE : Write Enable Input RE : Read Enable Input RSTW : Reset Write Input RSTR : Reset Read Input V CC : +5.0 V Power Supply GND : Ground Remark Refer to 5. Package Drawing for the 1-pin index mark. 2 Data Sheet M10059EJ7V0DS00 µPD485505 Block Diagram VCC GND WCK RSTW Write Address Pointer RE DIN1 DOUT1 DIN2 DOUT2 DIN3 DIN4 Memory Cell Array 40,384 bits (5,048 words by 8 bits) Output Buffer DOUT0 Input Buffer DIN0 DOUT3 DOUT4 DIN5 DOUT5 DIN6 DOUT6 DIN7 DOUT7 WE RSTR Read Address Pointer Data Sheet M10059EJ7V0DS00 RCK 3 µPD485505 1. Input/Output Pin Function Pin Pin Number 24 - 21 16 - 13 DIN0 | DIN7 Pin Name I/O Data Input In Function Write data input pins. The data inputs are strobed by the rising edge of WCK at the end of a cycle and the setup and hold times (tDS, tDH) are defined at this point. Data Output Out 9 - 12 DOUT0 | DOUT7 Read data output pins. The access time is regulated from the rising edge of RCK at the beginning of a cycle and defined by tAC. 19 RSTW Reset Write Input In Reset input pin for the initialization of the write address pointer. The state of RSTW is strobed by the rising edge of WCK at the beginning of a cycle and the setup and hold times (tRS, tRH) are defined. 6 RSTR Reset Read Input In Reset input pin for the initialization of the read address pointer. The state of RSTR is strobed by the rising edge of RCK at the beginning of a cycle and the setup and hold times (tRS, tRH) are defined. 20 WE Write Enable Input In Write operation control signal input pin. When WE is in the disable mode (“H” level), the internal write operation is inhibited and the write address pointer stops at the current position. 5 RE Read Enable Input In Read operation control signal input pin. When RE is in the disable mode (“H” level), the internal read operation is inhibited and the read address pointer stops at the current position. The output changes to high impedance. 17 WCK Write Clock Input In Write clock input pin. When WE is enabled (“L” level), the write operation is executed in synchronization with the write clock. The write address pointer is incremented simultaneously. 8 RCK Read Clock Input In Read clock input pin. When RE is enabled (“L” level), the read operation is executed in synchronization with the read clock. The read address pointer is incremented simultaneously. 1-4 4 Symbol Data Sheet M10059EJ7V0DS00 µPD485505 2. Operation Mode µ PD485505 is a synchronous memory. All signals are strobed at the rising edge of the clock (RCK, WCK). For this reason, setup time and hold time are specified for the rising edge of the clock (RCK, WCK). 2.1 Write Cycle When the WE input is enabled (“L” level), a write cycle is executed in synchronization with the WCK clock input. The data inputs are strobed by the rising edge of the clock at the end of a cycle so that read data after a oneline (5,048 bits) delay and write data can be processed with the same clock. Refer to Write Cycle Timing Chart. When WE is disabled (“H” level) in a write cycle, the write operation is not performed during the cycle which the WCK rising edge is in the WE = “H” level (tWEW ). The WCK does not increment the write address pointer at this time. Unless inhibited by WE, the internal write address will automatically wrap around from 5,047 to 0 and begin incrementing again. 2.2 Read Cycle When the RE input is enabled (“L” level), a read cycle is executed in synchronization with the RCK clock input and data is output after t AC . Refer to Read Cycle Timing Chart. When RE is disabled (“H” level) in a read cycle, the read operation is not performed during the cycle which the RCK rising edge is in the RE = “H” level (t REW). The RCK does not increment the read address pointer at this time. 2.3 Write Reset Cycle/Read Reset Cycle After power up, the µ PD485505 requires the initialization of internal circuits because the read and write address pointers are not defined at that time. It is necessary to satisfy setup requirements and hold times as measured from the rising edge of WCK and RCK, and then input the RSTW and RSTR signals to initialize the circuit. Write and read reset cycles can be executed at any time and the address pointer returns zero. Refer to Write Reset Cycle Timing Chart, Read Reset Cycle Timing Chart. Remark Write and read reset cycles can be executed at any time and do not depend on the state of RE or WE. Data Sheet M10059EJ7V0DS00 5 µPD485505 Operation-related Restriction Following restriction exists to read data written in a write cycle. Read the written data after an elapse of 1/2 write cycle + t WAR since the write cycle ends (see Figure 2.1). If t WAR is not satisfied, the output data may undefined. Figure 2.1 Delay Bits Restriction Timing Chart 0 1 2 3 WCK 1/2 write cycle tWAR 0 1 2 RCK DIN High impedance 0 1 2 3 tAC High impedance DOUT 0 1 2 3 Remark This timing chart describes only the delay bits restriction, and does not defines the WE, RE, RSTW, RSTR signals. 6 Data Sheet M10059EJ7V0DS00 µPD485505 3. Electrical Specifications All voltages are referenced to GND. Absolute Maximum Ratings Parameter Symbol Condition Rating –0.5Note Voltage on any pin relative to GND VT Supply voltage VCC Output current Unit to VCC + 0.5 V –0.5 to +7.0 V IO 20 mA Operating ambient temperature TA 0 to 70 ˚C Storage temperature Tstg –55 to +125 ˚C Note –3.0 V MIN. (Pulse width = 10 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition MIN. TYP. MAX. Unit 5.0 5.5 V Supply voltage VCC 4.5 High level input voltage VIH 2.4 VCC + 0.5 V Low level input voltage VIL –0.3Note +0.8 V Operating ambient temperature TA 0 70 ˚C MAX. Unit 80 mA Note –3.0 V MIN. (Pulse width = 10 ns) DC Characteristics (Recommended Operating Conditions unless otherwise noted) Parameter Symbol Test Condition MIN. TYP. Operating current ICC Input leakage current II VI = 0 to VCC, Other Input 0 V –10 +10 µA Output leakage current IO VO = 0 to VCC, –10 +10 µA DOUT: High impedance High level output voltage VOH IOH = –1 mA Low level output voltage VOL IOL = 2 mA 2.4 V 0.4 V MAX. Unit Capacitance (TA = 25 ˚C, f = 1 MHz) Parameter Symbol Test Condition MIN. TYP. Input capacitance CI 10 pF Output capacitance CO 10 pF Data Sheet M10059EJ7V0DS00 7 µPD485505 AC Characteristics (Recommended Operating Conditions unless otherwise noted)Notes 1, 2, 3 Parameter 8 Symbol µPD485505-25 µPD485505-35 MIN. MIN. MAX. Unit Notes MAX. Write clock cycle time tWCK 25 35 ns Write clock pulse width tWCW 11 12 ns Write clock precharge time tWCP 11 12 ns Read clock cycle time tRCK 25 35 ns Read clock pulse width tRCW 11 12 ns Read clock precharge time tRCP 11 12 ns Access time tAC Write data-read delay time tWAR 470 470 ns Output hold time tOH 5 5 ns Output low-impedance time tLZ 5 18 5 25 ns 4 Output high-impedance time tHZ 5 18 5 25 ns 4 Input data setup time tDS 7 10 ns Input data hold time tDH 3 3 ns RSTW/RSTR Setup time tRS 7 10 ns 5 RSTW/RSTR Hold time tRH 3 3 ns 5 RSTW/RSTR Deselected time (1) tRN1 3 3 ns 6 RSTW/RSTR Deselected time (2) tRN2 7 10 ns 6 WE Setup time tWES 7 10 ns 7 WE Hold time tWEH 3 3 ns 7 WE Deselected time (1) tWEN1 3 3 ns 8 WE Deselected time (2) tWEN2 7 10 ns 8 RE Setup time tRES 7 10 ns 9 RE Hold time tREH 3 3 ns 9 RE Deselected time (1) tREN1 3 3 ns 10 RE Deselected time (2) tREN2 7 10 ns 10 WE Disable time tWEW 0 0 ms RE Disable time tREW 0 0 ms Write reset time tRSTW 0 0 ms Read reset time tRSTR 0 0 ms Transition time tT 3 18 Data Sheet M10059EJ7V0DS00 35 25 3 35 ns ns µPD485505 Notes 1. AC measurements assume tT = 5 ns. 2. AC Characteristics test condition Input Timing Specification 3.0 V 1.5 V Test points 0V tT = 5 ns tT = 5 ns Output Timing Specification High impedance 2.0 V High impedance Test points 0.8 V Output Loads for Timing VCC VCC 1.8 kΩ 1.8 kΩ DOUT DOUT 1.1 kΩ 30 pF (tAC, tOH) 1.1 kΩ 5 pF (tLZ, tHZ) 3. Input timing reference levels = 1.5 V. Output timing reference levels; VOH = 2.0 V, VOL = 0.8 V. 4. tLZ and tHZ are measured at ±200 mV from the steady state voltage. Under any conditions, tLZ ≥ tHZ. 5. If either tRS or tRH is less than the specified value, reset operations are not guaranteed. 6. If either tRN1 or tRN2 is less than the specified value, reset operations may extend to cycles preceding or following the period of reset operations. 7. If either tWES or tWEH is less than the specified value, write disable operations are not guaranteed. 8. If either tWEN1 or tWEN2 is less than the specified value, internal write disable operations may extend to cycles preceding or following the period of write disable operations. 9. If either tRES or tREH is less than the specified value, read disable operations are not guaranteed. 10. If either tREN1 or tREN2 is less than the specified value, internal read disable operations may extend to cycles preceding or following the period of read disable operations. Data Sheet M10059EJ7V0DS00 9 µPD485505 Write Cycle Timing Chart Cycle n Cycle n+1 Cycle n+2 Disable Cycle Cycle n+3 tWCK tWCP WCK (Input) tWCW tWEN1 tWES tWEH tWEN2 WE (Input) tWEW tDS DIN (Input) tDH tDS (n) (n+1) tDH (n+2) (n+3) Remark RSTW = “H” level Read Cycle Timing Chart Cycle n Cycle n+1 Cycle n+2 Disable Cycle Cycle n+3 tRCK tRCP RCK (Input) tRCW tREN1 tRES tREH tREN2 tOH tAC RE (Input) tREW tAC tHZ tLZ DOUT (Output) High impedance (n) (n+1) (n+2) Remark RSTR = “H” level 10 Data Sheet M10059EJ7V0DS00 tLZ High impedance (n+3) µPD485505 Write Reset Cycle Timing Chart (WE = Active) Cycle n Reset Cycle Cycle 0 Cycle 1 WCK (Input) tRN1 tRSTW Note tRS tRH tRN2 RSTW (Input) WE (Input) “L” Level tDH tDS DIN (Input) Note tDS (n) (n–1) tDH (0) (1) In write reset cycle, reset operation is executed even without a reset cycle (tRSTW). WCK can be input any number of times in a reset cycle. Write Reset Cycle Timing Chart (WE = Inactive) Cycle n Disable Cycle Cycle 0 Reset Cycle WCK (Input) tRN1 tRS tWEN1 tWES tRSTW Note tRH tRN2 tWEH tWEN2 RSTW (Input) WE (Input) tWEW tDS DIN (Input) Note (n–1) tDH (n) tDS (0) In write reset cycle, reset operation is executed even without a reset cycle (tRSTW). WCK can be input any number of times in a reset cycle. Data Sheet M10059EJ7V0DS00 11 µPD485505 Read Reset Cycle Timing Chart (RE = Active) Cycle n Reset Cycle Cycle 0 Cycle 1 RCK (Input) tRN1 tRSTR Note tRS tRH tRN2 RSTR (Input) RE (Input) “L” Level DOUT (Output) tAC tAC tAC (n–1) (n) tAC (0) (1) (0) Note tOH tOH tOH In read reset cycle, reset operation is executed even without a reset cycle (tRSTR). RCK can be input any number of times in a reset cycle. Read Reset Cycle Timing Chart (RE = Inactive) Cycle n Disable Cycle Cycle 0 Reset Cycle RCK (Input) tRSTR Note tRN1 tRS tREN1 tRES tRH tRN2 tREH tREN2 RSTR (Input) RE (Input) tREW tAC DOUT (Output) (n–1) tAC tHZ tLZ High impedance (n) tOH Note In read reset cycle, reset operation is executed even without a reset cycle (tRSTR). RCK can be input any number of times in a reset cycle. 12 Data Sheet M10059EJ7V0DS00 (0) tOH µPD485505 4. Application 4.1 1 H Delay Line µPD485505 easily allows a 1 H (5,048 bits) delay line (see Figure 4.1). Figure 4.1 1 H Delay Line Circuit 40 MHz Clock Data Input Reset WCK RCK DIN DOUT Data Output 8 8 WE RE RSTR RSTW Figure 4.2 1 H Delay Line Timing Chart 1H (5,048 Cycles) tWCK tRCK Write Read WCK/RCK (Input) Cycle 0 Cycle 1 Cycle 2 2H (5,048 Cycles) Cycle 5,047 Cycle 0’ Cycle 0 Cycle 1’ Cycle 1 Cycle 2’ Cycle 2 Cycle 3’ Cycle 3 tWCW tWCP tRCW tRCP tRS tRH RSTW / RSTR (Input) DIN (Input) tDS tDS tDH tDH (0) (1) (2) (5,046) (5,047) tAC DOUT (Output) (0’) (1’) (2’) (3’) tOH (0) (1) (2) (3) Remark RE, WE = “L” level Data Sheet M10059EJ7V0DS00 13 µPD485505 4.2 n Bit Delay It is possible to make delay read from the write data with the µ PD485505. (1) Perform a reset operation in the cycle proportionate to the delay length. (Figure 4.3) (2) Shift the input timing of write reset (RSTW) and read reset (RSTR) depending on the delay length. (Figure 4.4) (3) Shift the address by disabling RE for the period proportionate to the delay length. (Figure 4.5) n bit: Delay bits from write cycle to read cycle correspond to a same address cell. Restrictions Delay bits n can be set from minimum bits to maximum bits depending on the operating cycle time. Refer to 2. Operation Mode Operation-related Restriction. Cycle time MIN. MAX. 25 ns 21 bits 5,048 bits 35 ns 15 bits 5,048 bits Figure 4.3 n-Bit Delay Line Timing Chart (1) Write Read WCK/RCK (Input) Cycle 0 2H (n Cycles) 1H (n Cycles) tWCK tRCK Cycle 1 Cycle 2 Cycle n–1 Cycle 0’ Cycle 0 DIN (Input) Cycle 3’ Cycle 3 tRS tRS tRH tDS tDS tWAR tDH tDH (0) (1) (2) (n–2) (n–1) (0’) tAC DOUT (Output) Data Sheet M10059EJ7V0DS00 (1’) (2’) (3’) tOH (0) Remark RE, WE = “L” level 14 Cycle 2’ Cycle 2 tWCW tWCP tRCW tRCP tRH RSTW / RSTR (Input) Cycle 1’ Cycle 1 (1) (2) (3) µPD485505 Figure 4.4 n-Bit Delay Line Timing Chart (2) tWCK tRCK Write Read WCK/RCK (Input) Cycle 0 Cycle 1 Cycle 2 Cycle n Cycle 0 Cycle n–1 Cycle n+1 Cycle 1 Cycle n+2 Cycle 2 Cycle n+3 Cycle 3 tWCW tWCP tRCW tRCP tRS tWAR tRH tRS RSTW (Input) tRH RSTR (Input) tDS tDS tDH tDH DIN (Input) (0) (1) (2) (n–2) (n–1) n Cycles (n) tAC (n+1) (n+2) (n+3) tOH DOUT (Output) (0) (1) (2) (3) Remark RE, WE = “L” level Figure 4.5 n-Bit Delay Line Timing Chart (3) tWCK tRCK Write Read WCK/RCK (Input) Cycle 0 Cycle 1 Cycle 2 Cycle n Cycle 0 Cycle n–1 Cycle n+1 Cycle 1 Cycle n+2 Cycle 2 Cycle n+3 Cycle 3 tWCW tWCP tRCW tRCP tRS tWAR tRH RSTW/ RSTR (Input) RE (Input) tREH tREN2 tDS tDS tDH DIN (Input) (0) tDH (1) (2) (n–2) (n–1) n Cycles DOUT (Output) High impedance tAC (n) (n+1) (n+2) (n+3) tOH (0) (1) (2) (3) Remark WE = “L” level Data Sheet M10059EJ7V0DS00 15 µPD485505 4.3 Double-speed Conversion Figure 4.6 shows an example timing chart of double-speed and twice reading operation (fR = 2fW , 5,048 by 2 cycle) for a write operation (f W = 5,048 cycle). Caution The read operation collide with the write operation on the same line, last n bits output data (5,048–n to 5,048) in the first read operation will be undefined (see Figure 4.6 Double-speed Conversion Timing Chart). Undefined bits mentioned above depend on the cycle time. Read cycle time Undefined bits 25 ns 21 bits 35 ns 15 bits Figure 4.6 Double-speed Conversion Timing Chart 1H (5,048 Cycle) 0 1 2H (5,048 Cycle) 2 5046 5047 0' 1' 2' 5046' 5047' 0" WCK (Input) RSTW (Input) DIN (Input) 0 1 2 5046 5047 1H (5,048 Cycle) First read cycle 0' 1' 2' 5046' 1H (5,048 Cycle) Second read cycle 5047' 0" 5046' 5047' 0' 1' 2H (5,048 Cycle) First read cycle RCK (Input) RSTR (Input) tAC DOUT (Output) 0 1 2 5046 5047 0 1 2 n bits output data will be undefined. Remark RE, WE = “L” level 16 Data Sheet M10059EJ7V0DS00 5046 5047 0' 1' 2' n bits output data will be undefined. µPD485505 5. Package Drawing 24-PIN PLASTIC SOP (11.43 mm (450)) 24 13 detail of lead end P 1 12 A F H G I J S B C D M L N S K M E NOTE Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 15.5±0.2 B 1.27 MAX. C 1.27 (T.P.) D 0.42±0.08 E 0.1±0.1 F 2.1±0.2 G 2.0 H 12.2±0.3 I 8.4±0.2 J 1.9±0.2 K 0.17 +0.08 −0.07 L 0.9±0.2 M 0.12 N 0.10 P 5°±5° P24GM-50-450A-4 Data Sheet M10059EJ7V0DS00 17 µPD485505 6. Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µ PD485505. Type of Surface Mount Device µ PD485505G: 24-pin plastic SOP (11.43 mm (450)) 7. Example of Stamping Letter E in the fifth character position in a lot number signifies version E, letter K, version K, letter P, version P, and letter L, version L. JAPAN D485505 Lot number 18 Data Sheet M10059EJ7V0DS00 µPD485505 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M10059EJ7V0DS00 19 µPD485505 [MEMO] • The information in this document is current as of December, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. 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