MICRON MT9T001

PRELIMINARY‡
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
1/2-INCH 3-MEGAPIXEL
CMOS ACTIVE-PIXEL
DIGITAL IMAGE SENSOR
PART NUMBER: MT9T001P12STC
Features
Table 1:
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•
•
•
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DigitalClarity™ Image Sensor Technology
High frame rate
Global Reset Release
Horizontal and vertical binning
Column and row skip modes
Superior low-light performance
Low dark current
Simple two-wire serial interface
Programmable Controls: Gain, frame rate, frame
size, exposure
• Pin-for-Pin Compatible with Micron’s 1.3-Megapixel
MT9M001 and 2-Megapixel MT9D001
PARAMETER
Optical Format
Active Imager Size
Active Pixels
Pixel Size
Color Filter Array
Shutter Type
Maximum Data Rate/
Master Clock
QXGA
Frame (2,048 x 1,536)
Rate
UXGA
(1,600 x 1,200)
SXGA
(1,280 x 1,024)
XGA
(1,024 x 768)
VGA (640 x 480)
ADC Resolution
Responsivity
Dynamic Range
SNRMAX
Applications
• Digital still cameras
• Digital video cameras
• Converged DSCs/camcorders
Description
The Micron® Imaging MT9T001 is a QXGA-format
1/2-inch CMOS active-pixel digital image sensor with
an active imaging pixel array of 2,048H x 1,536V. It
incorporates sophisticated camera functions on-chip
such as windowing, column and row skip mode, and
snapshot mode. It is programmable through a simple
two-wire serial interface.
The 3-megapixel CMOS image sensor features DigitalClarity—Micron’s breakthrough low-noise CMOS
imaging technology that achieves CCD image quality
(based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS.
The sensor can be operated in its default mode or
programmed by the user for frame size, exposure, gain
setting, and other parameters. The default mode outputs a QXGA image at 12 frames per second (fps). An
on-chip analog-to-digital converter (ADC) provides 10
bits per pixel. FRAME_VALID and LINE_VALID signals
are output on dedicated pins, along with a pixel clock
that is synchronous with valid data.
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Key Performance Parameters
TYPICAL VALUE
1/2-inch (4:3)
6.55mm(H) x 4.92mm(V)
8.19 (Diagonal)
2,048H x 1,536V
3.2um x 3.2um
RGB Bayer Pattern
Global Reset Release, Electronic
Rolling Shutter (ERS)
48 MPS/48 MHz
Programmable up to 12 fps
Programmable up to 20 fps
Programmable up to 27 fps
Programmable up to 43 fps
Programmable up to 93 fps
10-bit, on-chip
>1.0 V/lux-sec (550nm)
61dB
43dB
Supply Voltage
3.0V−0 3.6V (3.3V nominal)
Power Consumption
240mW (nominal);
250uW (standby)
0°C to +60°C
48-pin PLCC
Operating Temperature
Packaging
Our MT9T001 produces extraordinarily clear, sharp
digital pictures, and its ability to capture both continuous video and single frames makes it the perfect choice
for a wide range of consumer and industrial applications, including digital still cameras, digital video cameras, and PC cameras.
1
©2003 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Pixel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Pixel Array Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Output Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Output Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Frame Timing Formulas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Feature Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Window Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Window Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Electronic Panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Blanking Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Frame Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
High Frame Rate Readout Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Pixel Integration Time Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Snapshot Mode and Flash Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Setting up for Snapshot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Triggering A Snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Strobe Pulse Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Global Shutter Release Snapshot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Programmed Exposure Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Bulb Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Skip and Bin Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Smaller Format Resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Line_Valid Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Gain Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Black Level Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Manual Black Level Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Black Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Standby Control and Chip Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Serial Bus Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Bus Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Data Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
No-Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Two-Wire Serial Interface Sample Write and Read Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
16-Bit Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
16-Bit Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Propagation Delay for FRAME_VALID and LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Two-Wire Serial Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
09005aef80c64010
MT9T001_3100_DSTOC.fm - Rev. C 9/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
09005aef80c64010
MT9T001_3100_DSTOC.fm - Rev. C 9/04 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
List of Figures
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Figure 2:
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Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
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Figure 12:
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Figure 26:
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Figure 28:
Figure 29:
Figure 30:
Figure 31:
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Typical Configuration (Connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pinout-48-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Spatial Illustration of Image Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Timing Example of Pixel Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Row Timing and FRAME_VALID/LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Windowing Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Windowing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Column Skip 2x; Row Skip 2X Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Column Skip 3x; Row Skip 3X Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Column Skip 4x; Row Skip 4X Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Column Skip 8x; Row Skip 8X Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Bin 2-to-1: 2,048H x 1,536V (QXGA) to 1,024H x 768V (XGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Bin 3-to-1: 2,048H x 1,536V (QXGA) to 640H x 480V (VGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Different LINE_VALID Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Timing Diagram Showing a Write to Reg0x09 with the Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . .31
Propagation Delays for FRAME_VALID and LINE_VALID Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Propagation Delays for PIXCLK and Data Out Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Serial Host Interface Start Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Serial Host Interface Stop Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Serial Host Interface Data Timing for Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Serial Host Interface Data Timing for Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Acknowledge Signal Timing After an 8-Bit Write to the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Acknowledge Signal Timing After an 8-Bit Read from the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Die Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Image Center Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
48-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
09005aef80c64010
MT9T001_3100_DSLOF.fm - Rev. C 9/04 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Key Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Frame Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Register List and Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Reserved Register List and Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Standard Resolutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Wide Screen (16:9) Resolutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Auto-Focus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
STROBE Pulse Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Bin and Skip Mode Resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Skip and Bin Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Gain Increment Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
09005aef80c64010
MT9T001_3100_DSLOT.fm - Rev. C 9/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Figure 1: Block Diagram
Two-Wire
Serial Interface
Control Register
Active-Pixel
Sensor (APS)
Array
Timing
and
Control
Analog Processing
Clock
Sync
Signals
10-bit
Data
ADC
Figure 2: Typical Configuration (Connection)
3.3V Analog
3.3V Digital
1.5KΩ
+
1.5KΩ
.1µF
2.2µF
Two-wire {
serial bus
6
5
4
3
2
1
48
47
46
45
44
43
1KΩ
NC
DGND
VDD
NC
NC
VAAPIX
AGND
AGND
SCLK
SDATA
NC
DGND
+
7
8
9
10
11
12
13
14
15
16
17
18
TRIGGER
GSHT_CTL
.01µF
MT9T001
NC
FRAME_VALID
LINE_VALID
STROBE
DGND
VDD
D9
D8
D7
D6
D5
PIXCLK
42
41
40
39
38
37
36
35
34
33
32
31
FRAME_VALID
LINE_VALID
STROBE
D9
D8
D7
D6
D5
PIXCLK
19
20
21
22
23
24
25
26
27
28
29
30
.1µF
STANDBY
TRIGGER
NC
RESET#
NC
GSHT_CTL
OE#
NC
AGND
VAA
AGND
AGND
NC
VAA
AGND
VDD
DGND
D0
D1
D2
D3
D4
CLKIN
NC
10µF
CLKIN
D4
D3
D2
D1
D0
NOTE:
Resistor value 1.5KΩ is recommended, but may be greater for slower two-wire speed.
09005aef80c64010
MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
NC
DGND
VDD
NC
NC
VAAPIX
AGND
AGND
SCLK
SDATA
NC
DGND
Figure 3: Pinout−48-Pin PLCC
6
5
4
3
2
1
48
47
46
45
44
43
NC
11
38
DGND
GSHT_CTL
12
37
VDD
OE#
13
36
DOUT<9>
NC
14
35
DOUT<8>
AGND
15
34
DOUT<7>
VAA
16
33
DOUT<6>
AGND
17
32
DOUT<5>
18
31
PIXCLK
AGND
19
20
21
22
23
24
25
26
27
28
29
30
NC
STROBE
CLKIN
LINE_VALID
39
DOUT<4>
40
10
DOUT<3>
NC
RESET#
DOUT<2>
FRAME_VALID
DOUT<1>
41
9
DOUT<0>
8
DGND
TRIGGER
VDD
NC
AGND
42
VAA
7
NC
STANDBY
.
Table 2:
Pin Descriptions
PIN
NUMBERS
SYMBOL
TYPE
7
STANDBY
Input
8
10
TRIGGER
RESET#
Input
Input
13
OE#
Input
29
46
12
45
CLKIN
SCLK
GSHT_CTL
SDATA
Input
Input
Input
I/O
24, 25, 26,
27, 28, 32,
33, 34, 35, 36
31
DOUT<0-9>
Output
Data Out: Pixel data output bit 0, DOUT<9> (MSB), DOUT<0> (LSB).
PIXCLK
Output
39
STROBE
Output
40
LINE_VALID
Output
41
FRAME_VALID
Output
Pixel Clock: Pixel data outputs are valid during falling edge of this clock.
Frequency = (master clock).
Strobe: Output is pulsed HIGH to indicate sensor reset operation of pixel array
has completed.
Line Valid: Output is pulsed HIGH during line of selectable valid pixel data (see
Reg0x20 for options).
Frame Valid: Output is pulsed HIGH during frame of valid pixel data.
09005aef80c64010
MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
DESCRIPTION
Standby: Activates (HIGH) standby mode, disables analog bias circuitry for
power saving mode.
Trigger: Activates (HIGH) snapshot sequence.
Reset: Activates (LOW) asynchronous reset of sensor. All registers assume
factory defaults.
Output Enable: OE# when HIGH, places outputs DOUT<0-9>, FRAME_VALID,
LINE_VALID, PIXCLK, and STROBE into a tri-state configuration.
Clock In: Master clock into sensor (48 MHz maximum).
Serial Clock: Clock for serial interface.
Global shutter control.
Serial Data: Serial data bus, requires 1.5KΩ resistor to 3.3V for pull-up.
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Table 2:
PIN
NUMBERS
1
4, 22, 37
5, 23, 38, 43
16, 20
15, 17, 18,
21, 47, 48
2, 3, 6, 9,
11,14,19, 30
42, 44
Pin Descriptions (continued)
SYMBOL
TYPE
VAAPIX
VDD
DGND
VAA
AGND
Supply
Supply
Supply
Supply
Supply
NC
–
09005aef80c64010
MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
DESCRIPTION
Analog Pixel Power: Provide power supply for pixel array, 3.3V ±0.3V.
Digital Power: Provide power supply for digital block, 3.3V ±0.3V.
Digital Ground: Provide isolated ground for digital block.
Analog Power: Provide power supply for analog block, 3.3V ±0.3V.
Analog Ground: Provide isolated ground for analog block and pixel array.
No Connect: These pins must be left unconnected.
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Pixel Data Format
Pixel Array Structure
Figure 5: Pixel Color Pattern Detail
(Top Right Corner)
The MT9T001 pixel array is configured as 2,112 columns by 1,568 rows, as shown in Figure 4. Columns
from 0 through 27 and from 2,085 through 2,111, and
also rows from 0 through 15 and from 1,561 through
1,567 are optically black. These optical black columns
and rows can be used to monitor the black level. The
black row data is used internally for the automatic
black level adjustment. However, the black rows and
columns can also be read out by setting Reg0x20 (11)
and Reg0x1E (7), respectively. There are 2,057 columns
by 1,545 rows of optically active pixels, which provides
a four-pixel boundary around the QXGA (2,048 x 1,536)
image to avoid boundary effects during color interpolation and correction.
column readout direction
..
.
Pixel
(28, 16)
row
readout
direction
The MT9T001 uses a Bayer color pattern, as shown
in Figure 5. The even-numbered rows contain green
and red color pixels, and odd-numbered rows contain
blue and green color pixels. The even-numbered columns contain green and blue color pixels; odd-numbered columns contain red and green color pixels.
27 black columns
4
28 black columns
R
G
R
G
B
G
B
G
B
G
B
G
R
G
R
G
R
G
B
G
B
G
B
G
B
G
R
G
R
G
R
G
B
G
B
G
B
G
B
Figure 6: Spatial Illustration of Image
Readout
5
(2111, 1567)
G
The MT9T001 image data is read out in a progressive scan. Valid image data is surrounded by horizontal
blanking and vertical blanking, as shown in Figure 6.
The amount of horizontal blanking and vertical blanking is programmable through Reg0x05 and Reg0x06,
respectively. LINE_VALID is HIGH during the shaded
region of the figure. FRAME_VALID timing is described
in “Output Data Timing” on page 10.
(0, 0)
5
R
Output Data Format
4
QXGA (2,048 x 1,536)
+ 4 pixel boundary for
color correction
+ additional active column
+ additional active row
= 2,057 x 1,545 active pixels
...
G
..
.
Figure 4: Pixel Array Description
16 black rows
black pixels
7 black rows
P0,0 P0,1 P0,2.....................................P0,n-1 P0,n
P1,0 P1,1 P1,2.....................................P1,n-1 P1,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
VALID IMAGE
HORIZONTAL
BLANKING
Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n 00 00 00 .................. 00 00 00
Pm,0 Pm,1.....................................Pm,n-1 Pm,n
00 00 00 .................. 00 00 00
09005aef80c64010
MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
9
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
VERTICAL BLANKING
VERTICAL/HORIZONTAL
BLANKING
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Output Data Timing
The PIXCLK can be used as a clock to latch the data.
DOUT data is valid on the falling edge of PIXCLK in
default mode. The PIXCLK is HIGH while master clock
is HIGH and then LOW while master clock is LOW. It is
continuously enabled, even during the blanking
period. The parameters in P, A, and Q shown in
Figure 8 are defined in Table 3.
The data output of the MT9T001 is synchronized
with the PIXCLK output. When LINE_VALID is HIGH,
one 10-bit pixel datum is output every PIXCLK period.
Figure 7: Timing Example of Pixel Data
....
LINE_VALID
....
PIXCLK
Blanking
P0
(9:0)
DOUT9-DOUT0
P1
(9:0)
P2
(9:0)
P3
(9:0)
Blanking
....
Valid Image Data
P4
(9:0)
....
Pn-1
(9:0)
Pn
(9:0)
Figure 8: Row Timing and FRAME_VALID/LINE_VALID Signals
...
FRAME_VALID
...
LINE_VALID
...
Number of master clocks P1+P2
09005aef80c64010
MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
A
Q
A
10
Q
A
P3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Frame Timing Formulas
Table 3:
Frame Timing
PARAMETER
NAME
EQUATION (PIXEL CLOCKS = MASTER CLOCK)
R
Active Rows
A
Active Columns
P1
Frame Start Blanking 1
P2
Frame Start Blanking 2
P3
Frame End Blanking 3
((Reg0x03 + 1)/((Reg0x22[2-0] + 1)))
(rounded up to next even number)
((Reg0x04 + 1)/((Reg0x23[2-0] + 1)))
(rounded up to next even number)
331 if Reg0x22[5-4] = 0, normal
673 if Reg0x22[5-4] = 1, Bin 2x
999 if Reg0x22[5-4] = 2, Bin 3x
38 if Reg0x23[5-4] = 0, normal
22if Reg0x23[5-4] = 1, Bin 2x
14 if Reg0x23[5-4] = 2, Bin 3x
Reg0x05 (minimum Reg0x05 value = 21)
Q
Horizontal Blanking
P1 + P2 + P3
P4
Shutter Overhead
Reg0x0C + 316 x (Reg0x23[5-4] +1)
tROW
RowTime
The greater of: (A + Q) or (P1+ P4)
V
Vertical Blanking
(Reg0x06 + 1) x tROW
tFV
Frame Valid Time
R x tROW
tFRAME
Total Frame Time
The greater of: ((65536 x Reg0x08 + Reg0x09) x tROW)
or (tFV + V)
09005aef80c64010
MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
11
DEFAULT TIMING
1,536 pixel clocks
= 32.0µs
2,048 pixel clocks
= 42.67µs
331pixel clocks
= 6.89µs
38 pixel clocks
= 0.79µs
142 pixel clocks
= 2.96µs
511 pixel clocks
= 10.65µs
316 pixel clocks
= 6.58µs
2,559 pixel clocks
= 53.31µs
66,534 pixel clocks
= 1.39ms
3,930,624 pixel clocks
= 81.89ms
3,997,158 pixel clocks
= 83.27ms
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Table 4:
Register List and Default Values
REGISTER # (HEX)
DESCRIPTION
DATA FORMAT
(BINARY)
DEFAULT VALUE (HEX)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x1E
0x20
0x21
0x22
0x23
0x2B
0x2C
0x2D
0x2E
0x35
0x49
0x4B
0x5D
0x5F
0x60
0x61
0x62
0x63
0x64
0xF8
0xFF
Chip Version
Row Start
Column Start
Row Size (Window Height)
Col Size (Window Width)
Horizontal Blanking
Vertical Blanking
Output Control
Shutter Width Upper
Shutter Width
Pixel Clock Control
Restart
Shutter Delay
Reset
Read Mode 1
Read Mode 2
Read Mode 3
Row Address Mode
Column Address Mode
Green1 Gain
Blue Gain
Red Gain
Green2 Gain
Global Gain
Black Level
Row Black Default Offset
BLC Delta Thresholds
Cal Threshold
Green1 Offset
Green2 Offset
Black Level Calibration
Red Offset
Blue Offset
Chip Enable/Synchronize
Chip Version
0001 0110 0000 0001
0000 00dd dddd ddd0
0000 0ddd dddd ddd0
0000 00dd dddd ddd1
0000 0ddd dddd ddd1
0000 00dd dddd dddd
0000 00dd dddd dddd
0d00 0000 d0dd 00dd
0000 0000 0000 dddd
dddd dddd dddd dddd
dddd dddd dddd dddd
0000 0000 0000 000d
0000 00dd dddd dddd
0000 0000 0000 000d
dddd dddd dd00 0000
ddd0 ddd0 0000 00dd
0000 0000 0000 00dd
0ddd 0ddd 0ddd 0ddd
0000 0ddd 00dd 0ddd
0ddd dddd 0d0d dddd
0ddd dddd 0d0d dddd
0ddd dddd 0d0d dddd
0ddd dddd 0d0d dddd
dddd dddd dddd dddd
0000 0ddd dddd dddd
0000 0ddd dddd dddd
0ddd dddd 0ddd dddd
dddd dddd dddd dddd
0000 000d dddd dddd
0000 000d dddd dddd
dddd d000 0000 00dd
0000 0ddd dddd dddd
0000 0ddd dddd dddd
0000 0000 0000 00dd
0001 0110 0000 0001
0x1611
0x0014
0x0020
0x05FF
0x07FF
0x008E
0x0019
0x0002
0x0000
0x0619
0x0000
0x0000
0x0000
0x0000
0xC040
0x0000
0x0000
0x0000
0x0000
0x0008
0x0008
0x0008
0x0008
0x0008
0x00A8
0x0028
0x2D13
0x231D
0x0020
0x0020
0x0000
0x0020
0x0020
0x0001
0x1611
NOTE:
1 = always 1
0 = always 0
d = programmable
? = read only
09005aef80c64010
MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Table 5:
Reserved Register List and Default Values
REGISTER # (HEX)
DESCRIPTION
DEFAULT VALUE (HEX)
0x27
0x29
0x30
0x32
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x4A
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x5B
0x5C
0x5E
0x65
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x70
0x71
0x72
0x73
0x74
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x0001
0x0401
0x0000
0x0008
0x0010
0x0005
0x0003
0x0002
0x0005
0x0003
0x0003
0x0003
0x0003
0x0010
0x0010
0x0010
0x0010
0x0010
0x0030
0x0020
0x0010
0x0028
0x8004
0x0002
0x8004
0x0002
0x0010
0x0010
0x0020
0x0007
0x071C
0x5364
0x0000
0x3FFF
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x00A3
0xA204
0xA006
0x260A
0x280C
09005aef80c64010
MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Table 5:
Reserved Register List and Default Values (continued)
REGISTER # (HEX)
DESCRIPTION
DEFAULT VALUE (HEX)
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x80
0x81
0x82
0x83
0x84
0x86
0x87
0x89
0x8A
0x8B
0x8C
0x90
0x91
0x92
0xF1
0xFA
0xFB
0xFC
0xFD
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x520D
0x7054
0x0000
0x9C57
0x9E02
0x9E04
0x9E06
0xA006
0x5308
0x3208
0x7C52
0x004E
0x4E00
0x4C02
0x480C
0x4A0E
0x2E0C
0x0000
0x4C02
0x0000
0x4F0A
0x3A0A
0x061F
0x0000
0x0001
0x0000
0x0000
0x0000
0x0000
0x0000
NOTE:
Even reading some of these registers will cause this part to go into an unknown state.
09005aef80c64010
MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Register Description
Table 6:
REGISTER
Chip ID
0x00
Row Start
0x01
Register Descriptions
BIT
DESCRIPTION
15:0
This register is read-only and gives the chip identification number: 0x1611.
10:0
First row to be read out—default = 0x0014 (20), register value must be an even number.
Column Start
0x02
11:0
First column to be read out—default = 0x0020 (32), register value must be an even number.
Note: If column bin is enabled, the value must be a multiple of Reg0x23 [5:4] + 1.
Row Size
0x03
10:0
Window height (number of rows - 1)—default = 0x5FF (1535), register value must be an odd
number. Minimum value for 0x03 = 0x0001.
Column Size
0x04
10:0
Window width (number of columns - 1)—default = 0x7FF (2047), register value must be an odd
number. Minimum value for 0x04 = 0x0001.
Horizontal Blank
10:0
0x05
Horizontal Blank—default = 0x008E (142 pixels). Minimum value = 0x0015 (21).
Vertical Blank
10:0
0x06
Vertical Blank—default = 0x0019 (25 rows). Minimum value = 0x0003 (3).
Output Control
This register controls various features of the output format for the sensor.
0
0x07
Synchronize changes.
0 = normal operation, update changes to registers that affect image brightness (integration
time, shutter delay, gain, horizontal and vertical blank, window size, row/column skip, or row
mirror) at the next frame boundary.
1 = do not update any changes to these settings until this bit is returned to “0.”
1
Chip Enable.
1 = normal operation.
0 = sensor readout is stopped and analog control signals are put in a state which draws minimal
power.
6
Override pixel data.
0 = normal operation.
1 = output programmed test data (see Reg0x32). First valid columns will output contents of test
data register; second columns will output inverted data. Third columns will output noninverted data, fourth inverted, etc.
Shutter Width Upper
15:0 The most significant bits of the shutter width, which are combined with Shutter Width
0x08
(Reg0x09). The total shutter width is therefore: (((Shutter_Width_Upper) x 65536) +
Shutter_Width). This should allow a shutter width from about 50us to about 50s at default row
time.
Shutter Width
15:0 Number of rows of integration, the exposure time; the time between when the rolling shutter
0x09
resets a row and that row is read out, in rows.
Default = 0x0619 (1561). Minimum value = 0x0001 (1).
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PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Table 6:
Register Descriptions (continued)
REGISTER
BIT
Pixel Clock Control
15
0x0A
Frame Restart
0x0B
DESCRIPTION
Invert Pixel Clock—default = 0x00 (0)
When set, line_valid, frame_valid, and data10_out will be set up to the rising edge of PIXCLK.
When clear, they are set up to the falling edge. This is accomplished by inverting the PIXCLK
output.
10:8
Shift Pixel Clock—default = 0x00 (0)
Two's compliment value representing how far to shift the PIXCLK output pin relative to DOUT,
in CLKIN cycles. Positive values shift PIXCLK later in time relative to DOUT (and thus relative to
the internal array/datapath clock. No effect unless PIXCLK is divided by Divide Pixel Clock.
6:0
Divide Pixel Clock —default = 0x00 (0)
Produces a PIXCLK that is divided by the value times two. The value must be a power of 2. This
will slow down the internal clock in the array control and datapath blocks, including pixel
readout. It will not affect the two-wire serial interface clock. A value of 0 corresponds to a
PIXCLK with the same frequency as CLK_IN. A value of 1 means f_PIXCLK = (f_CLK_IN / 2); 2
means f_PIXCLK = (f_CLK_IN / 4); 64 means f_PIXCLK = (f_CLK_IN / 128); etc.
0
Setting bit 0 to “1” of Reg0x0B will cause the sensor to abandon the readout of the current
frame and restart from the first row. This register automatically resets itself to 0x0000 after the
frame restart. The first frame after this event is considered to be a "bad frame" (see description
for Reg0x20, bit 0).
Shutter Delay
10:0
0x0C
Shutter delay—default = 0x0000 (0). This is the number of pixel clocks that the timing and
control logic waits before asserting the reset for a given row.
Reset
0x0D
0
Setting this bit will put the sensor into reset mode, which will set the sensor to its default
power-up state. Clearing this bit will resume normal operation.
Read Mode 1
0x1E
8
Snapshot Mode—default is 0 (continuous mode).
1 = enable Snapshot trigger signal can come from outside signal (trigger pin 8 on the sensor) or
from serial interface register restart, i.e. programming a “1” to bit 0 of Reg0x0B.
9
Strobe Enable—default is 0 (no strobe signal).
1 = enable strobe (signal output from the sensor during the time all rows are integrating). See
strobe width for more information.
10
Strobe Width—default is 0 (strobe signal width at minimum length, one row of integration
time, prior to Line_Valid going high).
1 = extend strobe width (strobe signal width extends to entire time all rows are integrating;
shutter width must be >= row size + vertical blanking).
11
Strobe Override—default is 0 (strobe signal created by digital logic).
1 = override strobe signal (strobe signal is set high when this bit is set, low when this bit is set
low. It is assumed that strobe enable is set to “0” if strobe override is being used).
0
No bad frames—1 = output all frames (including bad frames).
0 = default, only output good frames. A bad frame is defined as the first frame following a
change to: window size or position, horizontal blanking, row or column skip, or mirroring.
1 = "Continuous" LINE_VALID (continue producing Line_Valid during vertical blanking).
0 = Normal Line_Valid (default, no Line_Valid during vertical blank).
1 = LINE_VALID = "Continuous" LINE_VALID XOR FRAME_VALID.
0 = LINE_VALID determined by bit 9 (default).
Read Mode 2
0x20
9
10
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PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Table 6:
Register Descriptions (continued)
REGISTER
BIT
Read Mode 3
0x21
0
Global Reset—default = 0x0000—when set, snapshot mode will make use of the global reset
— that is, the entire array will be released from reset simultaneously. Ineffective unless
Snapshot (Reg0x1E[8]) is set.
1
Use GSHT_CTL—default = 0x0000.
When set, the leading edge of the GSHT_CTL pad signal will be used to start the shutter
sequence in snapshot mode, and the trailing edge will start the read sequence. When clear, the
leading edge of the TRIGGER pad signal will be used to initiate the shutter sequence, the
trailing edge of GSHT_CTL will start the exposure, and the trailing edge of the TRIGGER pad
signal will be used to start the strobe and readout. Ineffective unless Snapshot (Reg0x1E[8])
and Global Reset are set.
Row Address Mode
2:0
0x22
DESCRIPTION
Row Skip—the number of row-pairs to skip for every row read. For example, “0” means read
every row pair. “1” is skip 2x; 2 is skip 3x, etc. If Row Bin is non-zero, this should be set to the
interval between the first rows in each bin. For full binning, Row Skip equals Row Bin.
5:4
Row Bin—the number of rows to be read per row output minus one. For normal read out, this
should be “0.” For Bin 2x, it should be “1”; for Bin 3x, it should be “2.”
Column Address Mode
2:0
0x23
Column Skip—the number of column-pairs to skip for every pair read. Zero means read every
column. “1” means skip one pair for every pair read (Skip 2x); 2 means skip 2 pairs for every
pair read (Skip 3x) etc.
5:4
Column Bin—the number of columns to be addressed per column read out minus one. Zero will
produce standard 1:1 read out. A value of “1” will produce Bin 2x; “2” would be Bin 3x.
Note: Column start address value must be a multiple of Reg0x23 [5:4] + 1.
Green1 Gain
6:0
0x2B
Green1 analog gain—default = 0x08 (8) = 1x gain.
Blue Gain
0x2C
Red Gain
0x2D
Green2 Gain
0x2E
Global Gain
0x35
Black Level
0x49
14:8
Green1 digital gain—default = 0x00 (0) = 1x gain.
6:0
Blue analog gain—default = 0x08 (8) = 1x gain.
14:8
Blue digital gain—default = 0x00 (0) = 1x gain.
6:0
Red analog gain—default = 0x08 (8) = 1x gain.
14:8
Red digital gain—default = 0x00 (0) = 1x gain.
6:0
Green2 analog gain—default = 0x08 (8) = 1x gain.
14:8
Green2 digital gain—default = 0x00 (0) = 1x gain.
6:0
Global analog gain—default = 0x08 (8) = 1x gain.
14:8
Global digital gain—default = 0x00 (0) = 1x gain. This register can be used to set all four gains
at once. When read, it will return the value stored in Reg0x2B.
11:2
Desired black level in image.
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PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Table 6:
REGISTER
Register Descriptions (continued)
BIT
DESCRIPTION
Black Level Calibration Coarse Thresholds
6:0
0x5D
Low Coarse Threshold—default = 0x13. This value should be less than Low Target Threshold.
See High Coarse Threshold below.
14:8 High Coarse Threshold—default = 0x2D. If the average black value for a color is higher than
this value or lower than Low Coarse Threshold, the coarse mode will be activated (if enabled).
Once the black level is between the High Coarse Threshold and the Low Coarse Threshold, the
fine method will be used. This value should be set no lower than High Target Threshold.
Black Level Calibration Target Thresholds
6:0
0x5F
Thres_lo: Lower threshold for black level in units of ADC LSBs—default = 29.
14:8
Thres_hi: Upper threshold for black level in units of ADC LSBs—default = 35. When the black
value for a color is within these thresholds, it will be considered to be on target.
Green1 Offset
8:0
0x60
Cal Green1—Two's compliment representation of analog offset correction value for Green1.
Green2 Offset
8:0
0x61
Cal Green2—Two's compliment representation of analog offset correction value for Green2.
Black Level Calibration
0
0x62
Manual override of black level correction.
1 = override automatic black level correction with programmed values.
0 = normal operation (default).
1
Force/disable black level calibration.
0 = Enable Offset Correction (default).
1 = disable Offset Correction Voltage (Offset Correction Voltage = 0.0V).
12
Recalculate Black Level—1 = start a new running digitally filtered average for the black level
(this is internally reset to “0” immediately), and do a rapid sweep to find the new starting
point.
0 = normal operation (default).
13
Lock Red/Blue Calibration—when set, only one calibration value will be used for both red and
blue channels. Default is 0, set to “0” at all times.
Note: Gain for Red and Blue channels must be equal for setting to be effective.
14
Lock Green Calibration—when set, only one calibration value will be used for both Green1 and
Green2 channels. Default is 0, set to “0” at all times.
Note: Gain for Green1 and Green2 channels must be equal for setting to be effective.
Red Offset
8:0
0x63
Cal Red.
Two's compliment representation of analog offset correction value for Red.
Blue Offset
8:0
0x64
Cal Blue.
Two's compliment representation of analog offset correction value for Blue.
Chip Enable and Two-Wire Serial Interface Write Synchronize
0
0xF8
Mirrors the functionality of Reg0x07 bit 1,(Chip Enable).
1 = normal operation.
0 = stop sensor read out. When this is returned to “1,” sensor read out restarts at the starting
row in a new frame.
1
Mirrors the functionality of Reg0x07 bit 0 (Synchronize changes).
0 = normal operation, update changes to registers that affect image brightness (integration
time, integration delay, gain, horizontal and vertical blank, window size, row/column skip, or
row/column mirror) at the next frame boundary.
1 = do not update any changes to these settings until this bit is returned to ”0.”
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PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Feature Description
Window Control
value to be programmed in Reg0x03 is the desired
number of rows -1. The value to be programmed in
Reg0x04 is the desired number of columns -1.
The minimum value for Reg0x03 is 0x0001; for
Reg0x04, 0x0001. Thus, the smallest window size is two
columns by two rows (2H x 2V). Note that the value of
Reg0x03 and Reg0x04 must be an odd number (there
can only be even number of columns). It is also important to note that the user can program the window size
to be any format desired. Table 7 shows examples of
register settings to achieve various resolutions and
frame rates.
Reg0x01, Reg0x02, Reg0x03, and Reg0x04 These registers control the size of the window.
Window Size
The default programmed window size is 2,048 columns by 1,536 rows (2,048H x 1,536V). The control
logic allows the flexibility to change the window size by
programming Reg0x03 and Reg0x04. Reg0x03 controls
the window height (number of rows) and Reg0x04 controls the window width (number of columns). The
Table 7:
Standard Resolutions
RESOLUTION
2,048 x 1,536 QXGA
1,600 x 1,200 UXGA
1,280 x 1,024 SXGA
1,024 x 768 XGA
800 x 600 SVGA
640 x 480 VGA
Table 8:
FRAME RATE
COLUMN_SIZE
(REG0X04)
ROW_SIZE
(REG0X03)
SHUTTER WIDTH
(REG0X09)
12 fps
20 fps
27 fps
43 fps
65 fps
93 fps
2,047
1,599
1,279
1,023
799
639
1,535
1,199
1,023
767
599
479
<1,552
<1,216
<1,040
<784
<616
<496
Wide Screen (16:9) Resolutions
RESOLUTION
1,920 x 1,080 HDTV
1,280 x 720 HDTV
FRAME RATE
COLUMN_SIZE
(REG0X04)
ROW_SIZE
(REG0X03)
SHUTTER WIDTH
(REG0X09)
18 fps
39 fps
1,919
1,279
1,079
719
<1,096
<736
NOTE:
For Table 7 and Table 8 above, the settings for Reg0x05 (horizontal blanking) and Reg0x06 (vertical blanking) are 21 and
15 respectively, while all of the registers are set to default.
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PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Electronic Panning
In addition to changing the window size, the user
has the flexibility to change the location of the readout
window. Reg0x01 controls the first row to be read out
and Reg0x02 controls the first column to be read out.
The default values are 0x0014 (decimal 20) for Reg0x01
and 0x0020 (decimal 32) for Reg0x02. Note that the first
column to be read out must be an even number.
Reg0x01 and Reg0x02, together with Reg0x03 and
Reg0x04, allow the user to choose any segment of the
imager array to be read out. This is especially beneficial when the user needs to zoom in on a small portion
of the image and perform analysis on the image content.
Figure 9 shows some examples of the electronic
panning/zoom-in and windowing capabilities of the
sensor.
Reg0x06 controls the vertical blanking time in a row.
The value is specified in terms of the number of rows.
Default value of 0x0019 for Reg0x06 results in a vertical
blanking time of 26-row time.
Frame Time
Reg0x03, Reg0x04, Reg0x05, and Reg0x06 Total frame
time in terms of pixel clocks can be obtained using the
formula given in Table 3 on page 11. The user can
change the number of columns and rows read out,
horizontal blanking and vertical blanking times to
obtain different frame rates.
High Frame Rate Readout Modes
Reg0x01, Reg0x02, Reg0x03, Reg0x04, Reg0x05, and
Reg0x06 In addition to having the flexibility to read
out smaller standard formats, the sensor gives the user
the option of reading out nonstandard formats. This is
particularly useful if the user needs to zoom in on a
particular segment of the image to perform highspeed mathematical calculations (e.g., high-speed
viewfinder or auto-focus applications).
In applications such as the auto-focus mode, the
user may need more horizontal resolution than vertical. Thus, the user can window down to the mid-section of the imager array by programming Reg0x01 and
Reg0x03 to change the row start address and the window height. Figure 10 is an example of how the user
may want to window down to 2,048H x 512V from the
default of 2,048H x 1,536V. See also Table 9 for other
auto-focus mode resolutions.
Blanking Control
Reg0x05 and Reg0x06 These registers control the
blanking time in a row (called column fill-in or horizontal blanking) and between frames (vertical blanking). Horizontal blanking is specified in terms of pixel
clocks. Vertical blanking is specified in terms of row
readout times. The actual imager timing can be calculated using the equations given in Table 3 on page 11.
Reg0x05 controls the horizontal blanking time in a
row. The value is specified in terms of pixel clocks.
Default value of 0x008E for Reg0x05 results in a horizontal blanking time of 511 pixel clocks. Note that the
minimum value for Reg0x05 is 21. Thus, the minimum
horizontal blanking time is 390 pixel clocks.
Figure 9: Windowing Capabilities
(32, 20)
(1200, 180)
A
B
(1327, 307)
(568, 356)
C
(1079, 867)
(80, 912)
D
(1007, 479)
(2048, 1536)
Window A
Window B
Window C
Window D
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Window Size
2,048 x 1,536
128 x 128
512 x 512
400 x 96
Reg0x01
0x0014
0x00B4
0x0164
0x0390
20
Reg0x02
0x0020
0x04B0
0x0238
0x0050
Reg0x03
0x05FF
0x007F
0x01FF
0x018F
Reg0x04
0x07FF
0x007F
0x01FF
0x005F
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PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Table 9:
Auto-Focus Modes
RESOLUTION
FRAME
RATE
COLUMN_
SIZE
(REG0X04)
2,048 x 512
2,048 x 256
2,048 x 128
30 fps
60 fps
120 fps
2,047
2,047
2,047
ROW_
SIZE
(REG
0X03)
1,535
1,535
1,023
HORIZONTAL VERTICAL_
_BLANK
BLANK
(REG0X05)
(REG0X06)
22
22
34
1
0
14
ROW
(REG
0X22)
ROW_
SKIP
(REG
0X22)
COLUMN_
BIN
(REG0X23)
COLUMN_
SKIP
(REG0X23)
2
2
1
2
5
7
0
0
0
0
0
0
Figure 10: Windowing
2,048
Row Start = 20
(Reg0x01 = 0x0014)
Row Start = 356
(Reg0x01 = 0x0164)
512
1,536
While the user can adjust the integration time to the
desired value according to the aforementioned formula, not all integration times may be desired under
certain lighting conditions. If the light source has a
flicker component, then the integration time needs to
be set properly to avoid banding in the image.
Under 60Hz flicker, the integration time must be a
multiple of 1/120 of a second to avoid flicker. Under
50Hz flicker, the integration time must be a multiple of
1/100 of a second to avoid flicker.
The user can change Reg0x05 and Reg0x06 to obtain
the desired frame rate. Also, the user may want to perform row skip modes to obtain larger field of view if
high-frequency vertical resolution is not critical.
Pixel Integration Time Control
Reg0x09 and Reg0x0C The integration time of the
pixel is the amount of time the pixels are set to collect
charge generated from light. The user can change the
integration time of the sensor by programming
Reg0x09. The value of Reg0x09 sets the number of row
time for integration. The sensor also supports sub-row
integration time for fine control of pixel integration
time.
The formula for calculating the pixel integration
time is (reference Table 3 on page 11 for P1 description):
tINT
= (65536 x Reg0x08 + Reg0x09) x
P1+132
tROW
Snapshot Mode and Flash Control
Reg0x1E, STROBE pin and TRIGGER pin
Setting up for Snapshot Mode
Snapshot mode must be enabled before use by setting bit 8 = “1” of Reg0x1E. There are two important
signals used for snapshot mode: TRIGGER and
STROBE. The TRIGGER signal initiates the start of a
single frame capture and STROBE is an output pulse
that may be used to turn on a flash and/or activate a
mechanical shutter.
-Reg0x0C-
Typically, the value of Reg0x09 is limited to the
number of rows per frame (which includes vertical
blanking rows), such that the frame rate is not affected
by the integration time. However, if Reg0x09 is
increased beyond the total number of rows per frame,
then additional blanking rows are added as needed.
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Triggering A Snapshot
The TRIGGER signal required for starting a frame
capture may be generated in the following two ways:
a. External TRIGGER Pulse
Pin 8 is a digital input that may be used to supply an external trigger signal input. The snap-
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3-MEGAPIXEL DIGITAL IMAGE SENSOR
1. Set up snapshot mode as normal (including any
STROBE preferences).
2. Set Reg0x21 (Read Mode 3) to 0x0003.
3. Assert (transition LOW to HIGH) the GSHT_CTL
pin to reset the array. This pin must remain HIGH
for 18820 PIXCLKs.
4. Negate (transition HIGH to LOW) the GSHT_CTL
pin to begin the exposure. The exposure starts
1000 PIXCLKs after the falling edge of GSHT_CTL.
NOTE: Unlike normal snapshot mode, Reg0x0B
(Restart) may not be used to initiate the exposure
in global shutter modes.
5. Row readout will begin automatically. The
mechanical shutter should be closed before row
read out begins. The trailing edge of STROBE (if
enabled) will occur ((65536 x Reg0x08 + Reg0x09) x
tROW + 2000) PIXCLKs after the falling edge of
GSHT_CTL. Readout of the active window will
start the lesser of 16 x tROW or (Reg0x06 + 1) x
tROW later.
shot operation begins after the TRIGGER pulse
transitions from a HIGH to LOW state.
b. TRIGGER from Register Setting
A second method for triggering a snapshot is
by setting bit 0 = 1 of Reg0x0B (Restart). This
register automatically returns bit 0 to “0” after
the TRIGGER is initiated. This bit does not
need to be reset by the user after use.
Strobe Pulse Output
The STROBE pulse must be enabled before use by
setting Reg0x1E [bit 9] = 1. The STROBE signal has two
options for pulse length and may be selected using
Reg0x1E [bit 10] as shown in Table 10.
Table 10: STROBE Pulse Output
REG
0X1E
BIT 10
0
1
STROBE PULSE WIDTH
1 row time (default)
((655326 x Reg0x08 + Reg0x09 - R) -16) x tROW - V
Bulb Mode
To use bulb mode:
1. Set up snapshot mode as normal (including any
STROBE preferences).
2. Set Reg0x21 (Read Mode 3) to 0x0001.
3. Assert (transition LOW to HIGH) the GSHT_CTL
pin.
4. Assert (transition LOW to HIGH) the TRIGGER pin
to reset the array. This pin must remain HIGH for
at least 18,820 PIXCLKs.
5. Negate (transition HIGH to LOW) the GSHT_CTL
pin to begin the exposure. The exposure starts
1,000 PIXCLKs after the falling edge of GSHT_CTL.
NOTE: Unlike normal snapshot mode, Reg0x0B
(Restart) may not be used to initiate the exposure
in global shutter modes.
6. Negate (transition HIGH to LOW) the TRIGGER
pin to begin row read out. The mechanical shutter
should be closed before row read out begins. The
trailing edge of STROBE (if enabled) will occur
((65536 x Reg0x08 + Reg0x09) x tROW ) PIXCLKs
after the falling edge of TRIGGER. Read out of the
active window will start the lesser of 16 x tROW or
(Reg0x06 + 1) x tROW later. In this mode, the shutter width (Reg0x08, Reg0x09) would normally be
set to a low number, allowing row readout to start
immediately after the trailing edge of TRIGGER.
After the TRIGGER pulse has signaled a snapshot
operation, each row of the imager array is reset in
sequence to clear out any accumulated signal. Once
each row of the imager is reset, the STROBE pulse is
output from the imager with a length dependent upon
the characteristics described above. After the STROBE
pulse goes low, the imager waits 16 additional rows
and then each row from the pixel array is read out.
Note that no STROBE will be generated unless the
shutter width is greater than the output image height
plus vertical blanking.
Global Shutter Release Snapshot Mode
Reg0x1E and Reg0x21
In addition to the standard snapshot mode, the
MT9T001 has a global shutter release mode which may
be combined with a mechanical shutter to achieve
simultaneous exposure of all rows in the image.
Two global shutter modes are available: programmed exposure and bulb mode. In programmed
exposure mode, the exposure time is dictated by
{Reg0x08, Reg0x09} (Shutter Width). In bulb mode, the
TRIGGER and GSHT_CTL pins are used to achieve an
arbitrary exposure time.
Programmed Exposure Mode
To use programmed exposure mode:
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Skip and Bin Modes
by the averaging of two or three adjacent rows and columns (adjacent same-color pixels). Both 2x and 3x
binning modes are supported. Rows and columns can
be binned independently.
Row and column skip modes use subsampling to
reduce the output resolution without reducing fieldof-view. The MT9T001 also has row and column binning modes, which can reduce the impact of aliasing
introduced by the use of skip modes. This is achieved
Table 11: Bin and Skip Mode Resolution
RESOLUTION
COLUMN_
FRAME
SIZE
RATE (REG0X04)
ROW_
SIZE
(REG
0X03)
HORIZONTAL_ VERTICAL_
BLANK
BLANK
(REG0X05)
(REG0X06)
34 fps
2,047
1,535
22
40
1,024 x 768
XGA
50 fps
1,599
1,199
22
30
800 x 600
SVGA
48 fps
1,919
1,439
21
31
640 x 480
VGA
NOTE:
Column start address value must be a multiple of Reg0x23 [5-4] + 1.
ROW_
BIN
(REG
0X22)
ROW_
SKIP
(REG
0X22)
1
1
1
1
1
1
1
1
2
2
2
2
COLUMN_ COLUMN_
BIN
SKIP
(REG0X23) (REG0X23)
ning modes to achieve greater reductions, but binning
must be done. The different skip modes supported are
between 2x and 8x in both column and row directions.
The different binning modes supported are 2x and 3x.
See Table 12 for register bits controlling the different
bin and skip modes.
To use binning mode, set Reg0x22[5–4] (row bin) or
Reg0x23[5–4] (column bin) to the desired reduction
minus 1, as would be done for skip mode. Additionally,
Reg0x22[2–0] (column skip) must be set no less than
Reg0x22[5–4], and Reg0x23[2–0] (row skip) must be set
no less than Reg0x23[5–4]. Row and column skip
modes may be set higher than the corresponding bin-
Table 12: Skip and Bin Modes
REGISTER BIT
Reg0x23
Bit[2-0]
Bit[5-4]
Reg0x22
Bit[2-0]
Bit[5-4]
SKIP/BIN MODES
READOUTS
No column skip
Column skip 2x
Column skip 3x
Column skip 4x
Column skip 8x
col0, col1, col2, col3, col4, col5, etc.
col0, col1, col4, col5, col8, col9, etc.
col0, col1, col16, col7, col12, col13 etc.
col0, col1, col8, col9, col16, col17, etc.
col0, col1, col16, col17, col32, col33, etc.
Column Bin 2x
Column Bin 3x
Binning of 2 adjacent same-color pixels in a 4x4 window
Binning of 3 pixel of each color plane in a 6x6 window
No row skip
Row skip 2x
Row skip 3x
Row skip 4x
Row skip 8x
row0, row1, row2, row3, row4, row5, etc.
row0, row1, row4, row5, row8, row9, etc.
row0, row1, row6, row7, row12, row13, etc.
row0, row1, row8, row9, row16, row17, etc.
row0, row1, row16, row17, row32, row33, etc.
Row bin 2x
Row bin 3x
Binning of 2 pixel of each color plane in a 4x4 window
Binning of 3 pixel of each color plane in a 6x6 window
NOTE:
Column and row skip modes 1x through 8x are available on the MT9T001. Also, the read outs shown assume column start
and row start addresses are both “0”.
09005aef80c64010
MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Figure 11: Column Skip 2x; Row Skip 2X Enabled
Pixel
(Reg0x01, Reg0x02)
...
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
..
.
Figure 12: Column Skip 3x; Row Skip 3X Enabled
Pixel
(Reg0x01, Reg0x02)
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
09005aef80c64010
MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Figure 13: Column Skip 4x; Row Skip 4X Enabled
...
G
R
G
B
R
G
G
B
G
R
G
B
R
G
G
B
G
R
G
B
R
G
G
B
R
G
R
G
B
R
G
G
B
G
R
G
B
R
G
G
B
G
R
G
B
G
B
R
G
R
G
G
B
G
B
G
R
G
B
R
G
G
B
G
R
G
B
R
G
G
B
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
Pixel
(Reg0x01, Reg0x02)
..
.
Figure 14: Column Skip 8x; Row Skip 8X Enabled
Pixel
(Reg0x01, Reg0x02)
...
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
..
.
09005aef80c64010
MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Figure 15: Bin 2-to-1: 2,048H x 1,536V (QXGA) to 1,024H x 768V (XGA)
Gr
R
Gr
R
B
Gb
B
Gb
Grs
Rs
Gr
R
Gr
R
Bs
Gbs
B
Gb
B
Gb
NOTE:
Grs = binning of 4 Gr[s] in a 4 x 4 window; Gbs = binning of 4 Gb[s] in a 4 x 4 window.
Rs = binning of 4 R[s] in a 4 x 4 window; B[s] = binning of 4 B[s] in a 4 x 4 window.
Figure 16: Bin 3-to-1: 2,048H x 1,536V (QXGA) to 640H x 480V (VGA)
Gr
R
Gr
R
Gr
R
B
Gb
B
Gb
B
Gb
Gr
R
Gr
R
Gr
B
Gb
B
Gb
B
R
Gb
Gr
R
Gr
R
Gr
R
B
Gb
B
Gb
B
Gb
Grs
Rs
Bs
Gbs
NOTE:
Grs = binning of 9 Gr[s] in a 6 x 6 window; Gbs = binning of 9 Gb[s] in a 6 x 6 window.
Rs = binning of 9 R[s] in a 6 x 6 window; Bs = binning of B[s] in a 6 x 6 window.
Smaller Format Resolution
To maintain the same field of view while reducing
the read out resolution, the user would need to perform row and column skip. For example, if the desired
read out resolution needs to be XGA (1,024H x 7,68V)
instead of QXGA (2,048H x 1,536V). To maintain the
same field of view, the user can select column skip 2x
and row skip 2x modes. This effectively reduces the
horizontal and vertical resolution by 2x for a factor of
4x reduction in overall number of pixels that are read
out. To perform this read out mode, the user would
need to set the following:
Reg0x01, Reg0x02, Reg0x03, Reg0x04, Reg0x05,
Reg0x06, Reg0x22, and Reg0x23 With the aforementioned flexible windowing capability of the sensor, the
user is able to read out different resolution formats
from default of QXGA to UXGA, SXGA, XGA, SVGA,
VGA, CIF, QVGA, QCIF, etc. Below are some examples
of programmable register settings to obtain the estimated frame rates for the desired formats.
The user can change the values of Reg0x05 and
Reg0x06 to obtain different frame rates. Note that the
field of view of the image will be reduced since the programmed settings effectively reduce the read out window to the specified settings without skipping any
rows or columns.
If the user only changes the register settings mentioned above without changing the row and column
start address, the read out window would start from
that coordinate. To read out the center of the image or
any portion that is desired, the user would need to program Reg0x01 and Reg0x02, thus performing electronic panning.
09005aef80c64010
MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
Reg0x03 = 0x05FF
Reg0x04 = 0x07FF
Reg0x23 Bit[2:0]=1
Reg0x22 Bit[2:0] = 1
1,536V rows
2,048H columns
Column skip 2x—> 1,024H
columns read out
Row skip 2x —> 768
rows read out
Note that if the user sets Reg0x03 = 0x02FF (768V
rows), Reg0x04 = 0x03FF (1,024H columns), and then
enable column skip 2x and row skip 2x, the effective
readout resolution will be 512H x 384V.
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Line_Valid Formats
Reg0x20 is used to control many aspects of the readout of the sensor. By setting Bit 9 and 10 of Reg0x20 the
LINE_VALID signal can get three different output formats. The formats are shown in Figure 17 when read-
ing out four rows and two vertical blanking rows. In the
last format the LINE_VALID signal is the XOR between
the continuously LINE_VALID signal and the
FRAME_VALID signal.
Figure 17: Different LINE_VALID Formats
Default
FRAME_VALID
LINE_VALID
Continuously
FRAME_VALID
LINE_VALID
XOR
FRAME_VALID
LINE_VALID
09005aef80c64010
MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Signal Path
After the gain stage, the differential signal goes
through the analog offset correction circuitry. The user
can decide if a positive or negative offset or no offset
needs to be added to the differential signal. The signal
is then sampled onto the sample and hold circuitry of
the ADC before being digitized.
The MT9T001 sensor analog signal path consists of
the pixel array, the column sample and hold (S/H) circuitry, the programmable gain stage, the analog offset
correction and the analog-to-digital converter (ADC).
The reset and signal voltages from the pixel are
sampled onto the column sample and hold circuitry
on a row-wise basis. After signal sampling is complete,
the differential signal (reset - signal) is transferred to
the programmable gain stage.
Figure 18: Signal Path
Analog Gain
(color-wise)
Pixel Voltage
X
Digital Offset
(color-wise)
+
Analog Offset
(color-wise)
10-bit ADC
Black Level
Calibration
Gain Settings
+
X
DOUT[9:0]
Digital Gain
(color-wise)
stage gain is set by Bit(5-0). The gain is individually
controllable for each color in the Bayer pattern as follows:
Reg0x2B, Reg0x2C, Reg0x2D, Reg0x2E, and Reg0x35
The analog programmable gain stage consists of
two stages of gain circuitry that operate in a pipelined
manner. The first stage of gain has programmable gain
of 1 or 2 while the second stage of gain has programmable gain of 1 to 4 with steps of 0.125 for a maximum
analog gain of 8. The gain settings can be independently adjusted for the colors of Green1, Blue, Red,
and Green2 and are programmed through Reg0x2B,
Reg0x2C, Reg0x2D, and Reg0x2E, respectively. The
gain may also be adjusted globally through Reg0x35.
The first stage of gain is set by Bit(6), while the second
Analog Gain < = 8:
Gain = (Bit[6] + 1) x (Bit[5:0] x 0.125)
Digital Gain = 1 + Bit[14:8]/8
Total Gain = Analog Gain x Digital Gain
Since Bit[6] of the gain registers are multiplicative
factors for the gain settings, there are alternative ways
of achieving certain gains. Some settings offer superior
noise performance to others, despite the same overall
gain, as shown in Table 13.
Table 13: Gain Increment Settings
NOMINAL GAIN
INCREMENTS
RECOMMENDED SETTINGS
1 to 4.000
4.25 to 8.00
9.0 to 128.0
0.125
0.25
1.0
0x0008 to 0x0020
0x0051 to 0x0060
0x0160 to 0x7860
09005aef80c64010
MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Black Level Calibration
Black Level
Reg0x5D, and Reg0x5F The digitized black level of the
MT9T001 sensor will potentially vary with temperature
or gain setting changes. The MT9T001 sensor allows
the user the flexibility of automatic black level calibration or manual black level control.
Reg0x49 Digital offset will be applied such that the
average black level of a frame in a resulting image
equals the value of this register. This adjustment happens after black level calibration.
Reset
Manual Black Level Calibration
This register is used to reset the sensor registers to
their default, power-up state. To reset the MT9T001,
first write a “1” into bit 0 of this register to put the
MT9T001 in reset mode, then write a “0” into bit 0 to
resume operation.
Another way to reset the sensor is through the
RESET# pin (pin 10) - by pulling the RESET# signal to
0V.
The reset operation is an asynchronous reset and
the sensor will remain in reset as long as RESET# signal
= 0V. In both methods of reset, the sensor register settings will return to their default states.
Reg0x60, Reg0x61, Reg0x62, Reg0x63, and Reg0x64
The programmable analog offset stage corrects for
analog offset that might be present in the analog signal. The user would need to program Reg0x62 appropriately to enable the analog offset correction. The
analog offset settings can be independently adjusted
for the colors of Green1, Green2, Red and Blue and are
programmed through Reg0x60, Reg0x61, Reg0x63 and
Reg0x64 respectively. Note that Bit[8] of Reg0x60,
Reg0x61, Reg0x63 and Reg0x64 (these registers have
two’s complement representation) determines the
sign of the analog offset. Bit[8] = 1 makes the analog
correction negative instead of positive.
The lower 8 bits (Bit[7:0]) determine the absolute
value of the analog offset to be corrected and Bit[8]
determines the sign of the correction. When Bit[8] is
“1”, the sign of the correction is negative and vice
versa. The analog value of the correction relative to the
analog gain stage can be determined from the following formula:
Standby Control and Chip Enable
There are two steps required to put the sensor in
standby mode:
1. Through the two-wire serial interface program
Reg0x07 Bit[1] = 0. This stops the sensor readout and powers down analog circuitry of the
sensor. The sensor will stay in standby mode
until the user reprograms Reg0x07 Bit[1] = 1.
2. Set STANDBY (pin 7) to HIGH.
Analog offset = Bit[8:0] x 1 LSB
Note that the 1 LSB value in the formula is an estimate amount. It will deviate from 1 LSB with process
variation.
09005aef80c64010
MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Serial Bus Description
bit after each 8-bit transfer. The register address is
auto-incremented after every 16 bits is transferred.
The data transfer is stopped when the master sends a
no-acknowledge bit.
Registers are written to and read from the MT9T001
through the two-wire serial interface bus. The
MT9T001 is a serial interface slave and is controlled by
the serial clock (SCLK), which is driven by the serial
interface master. Data is transferred into and out of
the MT9T001 through the serial data (SDATA) line. The
SDATA line is pulled up to 3.3V off-chip by a 1.5KΩ
resistor. Either the slave or master device can pull the
SDATA line down—the serial interface protocol determines which device is allowed to pull the SDATA line
down at any given time.
Bus Idle State
The bus is idle when both the data and clock lines
are HIGH. Control of the bus is initiated with a start
bit, and the bus is released with a stop bit. Only the
master can generate the start and stop bits.
Start Bit
Protocol
The start bit is defined as a HIGH-to-LOW transition
of the data line while the clock line is HIGH.
The two-wire serial defines several different transmission codes, as follows:
• a start bit
• the slave device 8-bit address
• a(n) (no) acknowledge bit
• an 8-bit message
• a stop bit
Stop Bit
The stop bit is defined as a LOW-to-HIGH transition
of the data line while the clock line is HIGH.
Slave Address
The eight-bit address of a two-wire serial interface
device consists of seven bits of address and 1 bit of
direction. A “0” (0xBA) in the LSB (least significant bit)
of the address indicates write mode, and a “1” (0xBB)
indicates read mode.
Sequence
A typical read or write sequence begins by the master sending a start bit. After the start bit, the master
sends the slave device's 8-bit address. The last bit of
the address determines if the request will be a read or a
write, where a “0” indicates a write and a “1” indicates
a read. The slave device acknowledges its address by
sending an acknowledge bit back to the master.
If the request was a write, the master then transfers
the 8-bit register address to which a write should take
place. The slave sends an acknowledge bit to indicate
that the register address has been received. The master
then transfers the data eight bits at a time, with the
slave sending an acknowledge bit after each eight bits.
The MT9T001 uses 16-bit data for its internal registers,
thus requiring two 8-bit transfers to write to one register. After 16 bits are transferred, the register address is
automatically incremented, so that the next 16 bits are
written to the next register address. The master stops
writing by sending a start or stop bit.
A typical read sequence is executed as follows. First
the master sends the write-mode slave address and 8bit register address, just as in the write request. The
master then sends a start bit and the read-mode slave
address. The master then clocks out the register data
eight bits at a time. The master sends an acknowledge
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Data Bit Transfer
One data bit is transferred during each clock pulse.
The serial interface clock pulse is provided by the master. The data must be stable during the HIGH period of
the two-wire serial interface clock—it can only change
when the serial clock is LOW. Data is transferred eight
bits at a time, followed by an acknowledge bit.
Acknowledge Bit
The master generates the acknowledge clock pulse.
The transmitter (which is the master when writing, or
the slave when reading) releases the data line, and the
receiver indicates an acknowledge bit by pulling the
data line LOW during the acknowledge clock pulse.
No-Acknowledge Bit
The no-acknowledge bit is generated when the data
line is not pulled down by the receiver during the
acknowledge clock pulse. A no-acknowledge bit is
used to terminate a read sequence.
30
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©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Two-Wire Serial Interface Sample Write and Read Sequences
16-Bit Write Sequence
image sensor will give an acknowledge bit. All 16 bits
must be written before the register will be updated.
After 16 bits are transferred, the register address is
automatically incremented so that the next 16 bits are
written to the next register. The master stops writing
by sending a start or stop bit.
A typical write sequence for writing 16 bits to a register is shown in Figure 19. A start bit given by the master, followed by the write address, starts the sequence.
The image sensor will then give an acknowledge bit
and expects the register address to come first, followed
by the 16-bit data. After each eight-bit transfer, the
Figure 19: Timing Diagram Showing a Write to Reg0x09 with the Value 0x0284
SCLK
SDATA
Reg0x09
0xBA ADDR
START
0000 0010
ACK
ACK
16-Bit Read Sequence
1000 0100
ACK
STOP
ACK
bits at a time. The master sends an acknowledge bit
after each eight-bit transfer. The register address
should be incremented after every 16 bits is transferred. The data transfer is stopped when the master
sends a no-acknowledge bit.
A typical read sequence is shown in Figure 20. First
the master has to write the register address, as in a
write sequence. Then a start bit and the read address
specifies that a read is about to happen from the register. The master then clocks out the register data eight
Figure 20: Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284
SCLK
SDATA
0xBA ADDR
START
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MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
Reg0x09
ACK
0xBB ADDR
ACK START
ACK
31
1000 0100
0000 0010
ACK
STOP
NACK
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©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Electrical Specifications
Table 14: DC Electrical Characteristics
(VPWR = 3.3 ±0.3V; TA = 25°C)
SYMBOL
DEFINITION
VIH
VIL
IIN
Input High Voltage
Input Low Voltage
Input Leakage Current
VOH
VOL
IOZ
IPWRA
IPWRD
Output High Voltage
Output Low Voltage
Tri-state Output Leakage Current
Analog Quiescent Supply Current
Digital Quiescent Supply Current
IPWRA
Standby
IPWRD
Standby
IPWRD
Standby
ClkOn
Analog Standby Supply Current
Digital Standby Supply Current
Digital Standby Supply Current
with Clock On
CONDITION
MIN
TYP
VPWR - 0.3
-0.3
-15
No Pull-up Resistor;
VIN = VPWR or VGND
MAX
UNITS
VPWR + 0.3
0.8
15
V
V
µA
0.2
15
TBD
V
V
µA
mA
mA
VPWR - 0.2
0.0
Default settings
CLKIN = 48 MHz;
default setting,
CLOAD = 10pF
STDBY = VDD
STDBY = VDD,
CLKIN = 0 MHz
STDBY = VDD,
CLKIN = 48 MHz
TBD
50
22
TBD
TBD
TBD
µA
TBD
TBD
TBD
µA
TBD
TBD
TBD
µA
MIN
Table 15: AC Electrical Characteristics
(VPWR = 3.3 ±0.3V; TA = 25°C; CLKIN at 48 MHz)
SYMBOL
TYP
MAX
UNITS
tR
Input Clock Frequency Clock
Duty Cycle
Input Clock Rise Time
1
45
TBD
TBD
48
55
TBD
MHz
%
ns
tF
Input Clock Fall Time
TBD
TBD
t
CLKIN to PIXCLK propagation delay, LOW-toHIGH
CLKIN to PIXCLK propagation delay, HIGH-toLOW
CLKIN to DOUT<9-0> propagation delay,
LOW-to-HIGH
CLKIN to DOUT<9-0> propagation delay,
HIGH-to-LOW
Data Hold Time
CLOAD = 10pF
4
5
6
ns
CLOAD = 10pF
6
7
8
ns
FCLK_IN
PLHP
tPHLP
t
PLHD
tPHLD
tOH
t
PLHF,L
tPHLF,L
DEFINITION
CONDITION
CLOAD = 10pF
TBD
CLOAD = 10pF
TBD
TBD
CLKIN to FRAME_VALID and LINE_VALID
propagation, LOW-to-HIGH
CLKIN to FRAME_VALID and LINE_VALID
propagation, HIGH-to-LOW
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MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
ns
32
TBD
TBD
TBD
ns
TBD
TBD
TBD
ns
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©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Propagation Delay for FRAME_VALID
and LINE_VALID Signals
pixel's data and returns LOW on the same master clock
rising edge as the end of the output of the last valid
pixel's data.
The typical output delay, relative to the master
clock edge, is TBD. Note that the data outputs change
on the rising edge of the master clock.
The FRAME_VALID and LINE_VALID signals
change on the same falling master clock edge as the
data output. The LINE_VALID goes HIGH on the same
rising master clock edge as the output of the first valid
Figure 21: Propagation Delays for FRAME_VALID and LINE_VALID Signals
tPLHF,L
tPHLF,L
CLKIN
CLKIN
FRAME_VALID
LINIE_VALID
FRAME_VALID
LINE_VALID
Figure 22: Propagation Delays for PIXCLK and Data Out Signals
tR
tF
CLKIN
tPLHP
tPHLP
PIXCLK
tOH
tPLHD, tPHLD
DOUT (9:0)
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MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
DOUT (9:0)
DOUT (9:0)
33
DOUT (9:0)
DOUT (9:0)
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©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Two-Wire Serial Bus Timing
Figure 25: Serial Host Interface Data
Timing for Write
The two-wire serial bus operation requires certain
minimum master clock cycles between transitions.
These are specified in the following diagrams in master clock cycles.
4
SCLK
Figure 23: Serial Host Interface Start
Condition Timing
5
4
SDATA
4
SCLK
NOTE:
SDATA is driven by an off-chip transmitter.
SDATA
Figure 26: Serial Host Interface Data
Timing for Read
Figure 24: Serial Host Interface Stop
Condition Timing
5
5
4
SCLK
SCLK
SDATA
SDATA
NOTE:
SDATA is pulled LOW by the sensor, or allowed to be
pulled HIGH by a pull-up resistor off-chip.
NOTE:
All timing are in units of master clock cycle.
Figure 27: Acknowledge Signal Timing After an 8-Bit Write to the Sensor
3
6
SCLK
Sensor pulls down
SDATA pin
SDATA
Figure 28: Acknowledge Signal Timing After an 8-Bit Read from the Sensor
6
7
SCLK
SDATA
Sensor tri-states SDATA pin
(turns off pull down)
NOTE:
After a read, the master receiver must pull down SDATA to acknowledge receipt of data bits. When read sequence is complete, the master must generate a no acknowledge by leaving SDATA to float HIGH. On the following cycle, a start or stop
bit may be used.
09005aef80c64010
MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
34
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Figure 29: Die Placement
14.22mm
Sensor
Chip
Package center
48 PLCC
Package
Pixel
Array
14.22mm
Pin 1
Pin 48
Die
center
Pixel
(0,0)
Package Center = Die Center
Figure 30: Image Center Offset
Pixel Array
Pixel
(0, 0)
Pad 1
0.078mm
0.934mm
Optical
Center
7.721mm
Dark
Pixels
Die Center
7.802mm
NOTE:
Diagrams are not to scale.
09005aef80c64010
MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
35
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Figure 31: 48-Pin PLCC
0.55 ±0.05
2.225 ±0.150
0.425 ±0.100
1.950 ±0.125
1.250 ±0.075
SEATING PLANE
SUBSTRATE: PLASTIC LAMINATE
MOLD COMPOUND: EPOXY NOVOLAC
LID MATERIAL: BOROSILICATE GLASS
11.176
12.50
CTR
1.90 1.016
TYP
47X 0.90
48
1
48X 0.50
6.56 ±0.10
7.11 ±0.10
6.06 ±0.10
CL
11.176
12.50
CTR
1.016
TYP
5.588 ±0.100
14.22 ±0.20
(0.10)
CL
5.588 ±0.100
6.56 ±0.10
7.11 ±0.10
14.22 ±0.20
LEAD FINISH:
GOLD PLATING, 0.50 MICRONS MINIMUM THICKNESS
Data Sheet Designation
Preliminary: This data sheet contains initial characterization limits that are subject to change upon full
characterization of production devices.
®
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E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
09005aef80c64010
MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PRELIMINARY
MT9T001
3-MEGAPIXEL DIGITAL IMAGE SENSOR
Revision History
Rev C, Preliminary ...........................................................................................................................................................9/04
• Added Applications
• Updated Image Center Offset, Figure 30
Rev B, Preliminary ...........................................................................................................................................................3/04
• Updated Figure 29
• Added Table 1
• Updated Tables 2, 4, 5, and 6
Rev A, Version 1.0, Preliminary.....................................................................................................................................12/03
• Initial Release of document
09005aef80c64010
MT9T001_3100_DS_2.fm - Rev. C 9/04 EN
37
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.