MTV230M
(Rev 1.0)
MYSON
TECHNOLOGY
8051 Embedded LCD Monitor Controller
with Flash OSD
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8051 core, 12MHz operating frequency with double CPU clock option, 3.3V power supply.
1024-byte RAM, 64K-byte program Flash-ROM.
Maximum 4 channels of 5V open-drain PWM DAC.
Maximum 32 bi-directional I/O pins.
SYNC processor for composite separation/insertion, H/V polarity/frequency check and polarity adjustment.
Built-in low power reset circuit.
Compliant with VESA DDC2B/2Bi/2B+ standard.
Dual slave IIC addresses.
Single master IIC interface for internal device communication.
Maximum 4-channel 6-bit ADC.
Watchdog timer with programmable interval.
OSD controller features:
. Full-screen display consists of 15 (rows) by 30 (columns) characters.
. Programmable OSD menu positioning for display screen center.
. 512 Flash-ROM fonts, with 12x18 dot matrix, including 480 standard fonts and 32 multi-color fonts.
. Character (per row) and window intensity control.
. Character bordering, shadowing and blinking effect.
. Character height control (18 to 71 lines), double height and/or width control.
. 4 programmable windows with multi-level operation and programmable shadowing width/height/color.
In System Programming function (ISP).
42-pin SDIP or 44-pin PLCC/QFP package.
GENERAL DESCRIPTIONS
The MTV230M micro-controller is an 8051 CPU core embedded device specially tailored to LCD Monitor
applications. It includes an 8051 CPU core, 1024-byte SRAM, OSD controller, 4 built-in PWM DACs, VESA
DDC interface, 4-channel A/D converter, a 64K-byte internal program Flash-ROM and a 9K-word internal
OSD character Flash-ROM.
BLOCK DIAGRAM
P1.0-7
P3.0-2
P3.4-5
P4.0-7
P5.0-7
RST
X1
X2
8051
CORE
P0.0-7
P0.0-7
P2.0-3
P2.0-3
RD
WR
ALE
INT1
RD
WR
ALE
INT1
XFR
AD0-3
ADC
OSD
CONTROL
OSDHS
OSDVS
XIN
ROUT
GOUT
BOUT
FBKG
INT
H/VSYNC
CONTROL
HSYNC
VSYNC
HBLANK
VBLANK
PWM DAC
DA0-3
DDC & IIC
INTERFACE
ISCL
ISDA
HSCL
HSDA
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
Revision 1.0
-1-
2000/11/15
MTV230M
MYSON
TECHNOLOGY
(Rev 1.0)
PIN CONNECTION
P5.7/DA3
INT/P6.2
FBKG
BOUT
XIN
GOUT
ROUT
OSDHS
OSDVS
P4.7/VBLANK
P4.6/HBLANK
40
41
42
43
44
1
2
3
4
5
6
X1
X2
P4.5
P4.4
P4.3
P4.2
P4.1/VSYNC
P4.0/HSYNC
P3.0/Rxd/HSCL
P3.1/Txd/HSDA
P3.2/INT0
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
MTV230M
44 Pin
PLCC
P5.6/DA2
P5.5/DA1
P5.4/DA0
P5.3/AD3
P5.2/AD2
P5.1/AD1
P5.0/AD0
P1.7
P1.6
P1.5
P1.4
28
27
26
25
24
23
22
21
20
19
18
P1.3
P1.2
P1.1
P1.0
P6.1/ISDA
P6.0/ISCL
P3.5/T1
P3.4/T0
VSS
RST
VDD
Revision 1.0
-2-
ROUT
XIN
OSDHS
OSDVS
P4.7/VBLANK
P4.6/HBLANK
X1
X2
P4.5
P4.4
P4.3
P4.2
P4.1/VSYNC
P4.0/HSYNC
P3.0/Rxd/HSCL
P3.1/Txd/HSDA
P3.2/INT0
VDD
RST
VSS
P3.4/T0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
MTV230M
42 Pin
SDIP
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
GOUT
BOUT
FBKG
INT/P6.2
P5.7/DA3
P5.6/DA2
P5.5/DA1
P5.4/DA0
P5.1/AD1
P5.0/AD0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
P6.1/ISDA
P6.0/ISCL
P3.5/T1
2000/11/15
MTV230M
MYSON
TECHNOLOGY
(Rev 1.0)
PIN CONFIGURATION
A “CMOS pin” can be used as Input or Output mode. To use these pins as output mode, S/W needs to set
the corresponding output enable control bit “Pxxoe” to 1. Otherwise, the “Pxxoe” should clear to 0. In Output
mode, these pins can sink and drive at least 4mA current.
A “5V open drain pin” means it can sink at least 4mA current but no drive current to VDD. It can be used as
input or output function and needs an external pull up resistor.
A “8051 standard pin” is a pseudo open drain pin. It can sink at least 4mA current when output low level, and
drive at least 4mA current for 160nS when output transit from low to high, then keep drive 100uA to maintain
the pin at a high level. It can be used as input or output function. It needs an external pull up resistor when
driving heavy load device.
4mA
10uA
120uA
8051 Standard Pin
2 OSC
period
delay
Pin
4mA
Output
Data
Input
Data
No Current
Input
Data
Pin
5V Open Drain Pin
4mA
Output
Data
No Current
4mA
Output
Data
Input
Data
Pin
Pin
No Current
4mA
Input
Data
CMOS Pin (Input Mode)
Pxx oe = 0
CMOS Pin (Output Mode)
Pxx oe = 1
Revision 1.0
-3-
2000/11/15
MYSON
TECHNOLOGY
MTV230M
(Rev 1.0)
PIN DESCRIPTION
Name
RST
VDD
VSS
X2
X1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P3.0/Rxd/HSCL
P3.1/Txd/HSDA
P3.2/INT0
P3.4/T0
P3.5/T1
P4.7/VBLANK
P4.6/HBLANK
P4.5/HCLAMP
P4.4
P4.3
P4.2
P4.1/VSYNC
P4.0/HSYNC
P5.7/DA3
P5.6/DA2
P5.5/DA1
P5.4/DA0
P5.3/AD3
P5.2/AD2
P5.1/AD1
P5.0/AD0
P6.0/ISCL
P6.1/ISDA
INT/P6.2
FBKG
BOUT
GOUT
ROUT
XIN
OSDHS
OSDVS
Revision 1.0
Type
I
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
I
I
I
#44/42
19
18
20
8
7
25
26
27
28
29
30
31
32
15
16
17
21
22
5
6
9
10
11
12
13
14
40/38
39/37
38/36
37/35
36/35/34
33
23
24
41/39
42/40
43/41
44/42
1
2
3
4
Description
Active high reset
Positive Power Supply
Ground
Oscillator output
Oscillator input
General purpose I/O (8051 standard)
General purpose I/O (8051 standard)
General purpose I/O (8051 standard)
General purpose I/O (8051 standard)
General purpose I/O (8051 standard)
General purpose I/O (8051 standard)
General purpose I/O (8051 standard)
General purpose I/O (8051 standard)
General purpose I/O / Rxd / Slave IIC clock (5V open drain)
General purpose I/O / Txd / Slave IIC data (5V open drain)
General purpose I/O / INT0 (8051 standard)
General purpose I/O / T0 (8051 standard)
General purpose I/O / T1 (8051 standard)
General purpose I/O / Vertical blank output (CMOS)
General purpose I/O / Horizontal blank output (CMOS)
General purpose I/O / Hclamp output (CMOS)
General purpose I/O (CMOS)
General purpose I/O (CMOS)
General purpose I/O (CMOS)
General purpose I/O / Vsync input (5V open drain)
General purpose I/O / Hsync or Xsync input (5V open drain)
General purpose I/O / PWM DAC output (5V open drain)
General purpose I/O / PWM DAC output (5V open drain)
General purpose I/O / PWM DAC output (5V open drain)
General purpose I/O / PWM DAC output (5V open drain)
General purpose I/O / ADC Input (CMOS)
General purpose I/O / ADC Input (CMOS)
General purpose I/O / ADC Input (CMOS)
General purpose I/O / ADC Input (CMOS)
General purpose output / Master IIC clock (5V open drain)
General purpose output / Master IIC data (5V open drain)
OSD intensity output / General purpose output (CMOS)
OSD fast blanking output (CMOS)
OSD blue color video signal output (CMOS)
OSD green color video signal output (CMOS)
OSD red color video signal output (CMOS)
OSD pixel clock input (CMOS)
OSD vertical SYNC input (CMOS)
OSD horizontal SYNC input (CMOS)
-4-
2000/11/15
MTV230M
MYSON
TECHNOLOGY
(Rev 1.0)
FUNCTIONAL DESCRIPTIONS
1. 8051 CPU Core
The CPU core of MTV230M is compatible with the industry standard 8051, which includes 256 bytes RAM,
Special Function Registers (SFR), two timers, five interrupt sources and serial interface. The CPU core
fetches its program code from the 64K bytes Flash in MTV230M. It uses Port0 and Port2 to access the
“external special function register” (XFR) and external auxiliary RAM (AUXRAM).
The CPU core can run at double rate when FclkE is set. Once the bit is set, the CPU runs as if a 24MHz X’tal
is applied on MTV230M, but the peripherals (IIC, DDC, H/V processor ) still run at the original frequency.
Note: All registers listed in this document reside in 8051’s external RAM area (XFR). For internal RAM
memory map, please refer to 8051 spec.
2. Memory Allocation
2.1 Internal Special Function Registers (SFR)
The SFR is a group of registers that are the same as standard 8051.
2.2 Internal RAM
There are total 256 bytes internal RAM in MTV230M, same as standard 8052.
2.3 External Special Function Registers (XFR)
The XFR is a group of registers allocated in the 8051 external RAM area F00h - FFFh. These registers are
used for OSD control or other special function. Program can use "MOVX" instruction to access these
registers.
2.4 Auxiliary RAM (AUXRAM)
There are total 768 bytes auxiliary RAM allocated in the 8051 external RAM area 800h - AFFh. Program can
use "MOVX" instruction to access the AUXRAM.
FFh
80h
7Fh
Internal RAM
SFR
Accessible by
indirect
addressing only
(Using
MOV A,@Ri
instruction)
Accessible by
direct addressing
FFFh
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction)
F00h
AFFh
Internal RAM
Accessible by
direct and indirect
addressing
AUXRAM
Accessible by
indirect external
RAM addressing
(Using MOVX
instruction
00h
Revision 1.0
XFR
800h
-5-
2000/11/15
MTV230M
MYSON
TECHNOLOGY
(Rev 1.0)
3. Chip Configuration
The Chip Configuration registers define the chip pins function, as well as the connection, configuration and
frequency of the functional block.
Reg name
PADMOD
PADMOD
PADMOD
PADMOD
OPTION
addr
F2Bh (w)
F2Ch (w)
F2Dh (w)
F2Eh (w)
F2Fh (w)
bit7
HIICE
DA3E
P47oe
P57oe
PWMF
bit6
bit5
Bit4
bit3
IIICE
HVE
HclpE
DA2E
DA1E
DA0E
AD3E
P46oe
P45oe
P44oe
P43oe
P56oe
P55oe
P54oe
P53oe
DIV253 SlvAbs1 SlvAbs0 ENSCL
bit2
AD2E
P42oe
P52oe
Msel
bit1
FclkE
AD1E
P41oe
P51oe
MIICF1
bit0
P62E
AD0E
P40oe
P50oe
MIICF0
PADMOD (w) : Pad mode control registers. (All are "0" in Chip Reset)
HIICE = 1
→ pin “P3.0/Rxd/HSCL” is HSCL;
pin “P3.1/Txd/HSDA” is HSDA.
=0
→ pin “P3.0/Rxd/HSCL” is P3.0/Rxd;
pin “P3.1/Txd/HSDA” is P3.1/Txd.
IIICE = 1
→ pin “P6.1/ISDA” is ISDA;
pin “P6.0/ISCL” is ISCL.
=0
→ pin “P6.1/ISDA” is P6.1;
pin “P6.0/ISCL” is P6.0.
HVE
=1
→ pin “P4.7/VBLANK” is VBLANK;
pin “P4.6/HBLANK” is HBLANK.
=0
→ pin “P4.7/VBLANK” is P4.7;
pin “P4.6/HBLANK” is P4.6.
HclpE = 1
→ pin “P4.5/HCLAMP” is HCLAMP.
=0
→ pin “P4.5/HCLAMP” is P4.5.
FclkE = 1
→ CPU is running at double rate.
=0
→ CPU is running at normal rate.
P62E = 1
→ pin “INT/P6.2” is P6.2.
=0
→ pin “INT/P6.2” is INT.
DA3E = 1
→ pin “P5.7/DA3” is DA3.
=0
→ pin “P5.7/DA3” is P5.7.
DA2E = 1
→ pin “P5.6/DA2” is DA2.
=0
→ pin “P5.6/DA2” is P5.6.
DA1E = 1
→ pin “P5.5/DA1” is DA1.
=0
→ pin “P5.5/DA1” is P5.5.
DA0E = 1
→ pin “P5.4/DA0” is DA0.
=0
→ pin “P5.4/DA0” is P5.4.
AD3E = 1
→ pin “P5.3/AD3” is AD3.
=0
→ pin “P5.3/AD3” is P5.3.
AD2E = 1
→ pin “P5.2/AD2” is AD2.
=0
→ pin “P5.2/AD2” is P5.2.
AD1E = 1
→ pin “P5.1/AD1” is AD1.
=0
→ pin “P5.1/AD1” is P5.1.
AD0E = 1
→ pin “P5.0/AD0” is AD0.
=0
→ pin “P5.0/AD0” is P5.0.
P47oe = 1
→ P4.7 is output pin.
=0
→ P4.7 is input pin.
P46oe = 1
→ P4.6 is output pin.
=0
→ P4.6 is input pin.
P45oe = 1
→ P4.5 is output pin.
=0
→ P4.5 is input pin.
P44oe = 1
→ P4.4 is output pin.
=0
→ P4.4 is input pin.
P43oe = 1
→ P4.3 is output pin.
=0
→ P4.3 is input pin.
P42oe = 1
→ P4.2 is output pin.
Revision 1.0
-6-
2000/11/15
MYSON
TECHNOLOGY
=0
P41oe = 1
=0
P40oe = 1
=0
P57oe = 1
=0
P56oe = 1
=0
P55oe = 1
=0
P54oe = 1
=0
P53oe = 1
=0
P52oe = 1
=0
P51oe = 1
=0
P50oe = 1
=0
MTV230M
(Rev 1.0)
→ P4.2 is input pin.
→ P4.1 is output pin.
→ P4.1 is input pin.
→ P4.0 is output pin.
→ P4.0 is input pin.
→ P5.7 is output pin.
→ P5.7 is input pin.
→ P5.6 is output pin.
→ P5.6 is input pin.
→ P5.5 is output pin.
→ P5.5 is input pin.
→ P5.4 is output pin.
→ P5.4 is input pin.
→ P5.3 is output pin.
→ P5.3 is input pin.
→ P5.2 is output pin.
→ P5.2 is input pin.
→ P5.1 is output pin.
→ P5.1 is input pin.
→ P5.0 is output pin.
→ P5.0 is input pin.
OPTION (w) : Chip option configuration (All are "0" in Chip Reset).
PWMF = 1
→ Selects 94KHz PWM frequency.
=0
→ Selects 47KHz PWM frequency.
DIV253 = 1
→ PWM pulse width is 253 step resolution.
=0
→ PWM pulse width is 256 step resolution.
SlvAbs1,SlvAbs0 : Slave IIC block A's slave address length.
= 1,0 → 5-bits slave address.
= 0,1 → 6-bits slave address.
= 0,0 → 7-bits slave address.
ENSCL = 1
→ Enables slave IIC block to hold HSCL pin low while MTV230M is not able to
catch-up the speed of external master.
Msel
=1
→ Master IIC block connects to HSCL/HSDA pins.
=0
→ Master IIC block connecst to ISCL/ISDA pins.
MIICF1,MIICF0 = 1,1 → Selects 400KHz Master IIC frequency.
= 1,0 → Selects 200KHz Master IIC frequency.
= 0,1 → Selects 50KHz Master IIC frequency.
= 0,0 → Selects 100KHz Master IIC frequency.
4. I/O Ports
4.1 Port1
Port1 is a group of pseudo open drain pins. It can be use as general purpose I/O. The behavior Port is the
same as standard 8051.
4.2 P3.0-2, P3.4-5
If these pins are not set as IIC pins, Port3 can be used as general purpose I/O, interrupt, UART and Timer
pins. The behavior of Port3 is the same as standard 8051.
4.3 Port4, Port5 and Port6
Port4 and Port5 are used as general purpose I/O. S/W needs to set the corresponding P4(n)oe and P5(n)oe
Revision 1.0
-7-
2000/11/15
MTV230M
MYSON
TECHNOLOGY
(Rev 1.0)
to define whether these pins are input or output. Port6 is purely output.
Reg name
PORT4
PORT4
PORT4
PORT4
PORT4
PORT4
PORT4
PORT4
PORT5
PORT5
PORT5
PORT5
PORT5
PORT5
PORT5
PORT5
PORT6
PORT6
PORT6
addr
F30h(r/w)
F31h(r/w)
F32h(r/w)
F33h(r/w)
F34h(r/w)
F35h(r/w)
F36h(r/w)
F37h(r/w)
F38h(r/w)
F39h(r/w)
F3Ah(r/w)
F3Bh(r/w)
F3Ch(r/w)
F3Dh(r/w)
F3Eh(r/w)
F3Fh(r/w)
F28h(w)
F29h(w)
F2Ah(w)
bit7
bit6
PORT4 (r/w) :
Port 4 data input/output value.
PORT5 (r/w) :
Port 5 data input/output value.
PORT6 (w) :
Port 6 data output value.
bit5
bit4
bit3
bit2
bit1
bit0
P40
P41
P42
P43
P44
P45
P46
P47
P50
P51
P52
P53
P54
P55
P56
P57
P60
P61
P62
5. PWM DAC
Each PWM DAC output pulse width of the converter is controlled by an 8-bit register in XFR. The frequency
of PWM clock is 47KHz or 94KHz, selected by PWMF. And the total duty cycle step of these DAC outputs is
253 or 256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high
output. If DIV253=0, the output will pulse low at least once even if content of the DAC register is FFH. Writing
00H to DAC register generates stable low output.
Reg name
DA0
DA1
DA2
DA3
addr
F20h (r/w)
F21h (r/w)
F22h (r/w)
F23h (r/w)
bit7
bit6
bit5
Pulse
Pulse
Pulse
Pulse
bit4
bit3
bit2
width of PWM DAC 0
width of PWM DAC 1
width of PWM DAC 2
width of PWM DAC 3
bit1
bit0
DA0-3 (r/w) : The output pulse width control for DA0-3.
* All of PWM DAC converters are centered with value 80h after power on.
Revision 1.0
-8-
2000/11/15
MTV230M
MYSON
TECHNOLOGY
(Rev 1.0)
6. H/V SYNC Processing
The H/V SYNC processing block performs the functions of composite signal separation/insertion, SYNC
inputs presence check, frequency counting, polarity detection and H/V output polarity control. The present
and frequency function block treat any pulse shorter than one OSC period as noise.
Present
Check
Vpre
Polarity Check &
Freq. Count
Vfreq
Vpol
Digital Filter
Vbpl
VSYNC
XOR
CVSYNC
Present
Check
Digital Filter
Polarity Check &
Sync Seperator
Hpol
Present Check &
Freq. Count
Hpre
Hfreq
XOR
VBLANK
CVpre
Hbpl
Composite
Pulse Insert
XOR
XOR
HBLANK
HSYNC
H/V SYNC Processor Block Diagram
6.1 Composite SYNC Separation/Insertion
The MTV230M continuously monitors the input HSYNC, if the vertical SYNC pulse can be extracted from the
input, a CVpre flag is set and users can select the extracted "CVSYNC" for the source of polarity check,
frequency count, and VBLANK output. The CVSYNC will have 8us delay compared to the original signal.
The MTV230M can also insert pulse to HBLANK output during composite active time of VSYNC. The width
of the insert pulse is 1/8 HSYNC period and the insertion frequency can adapt to original HSYNC. The insert
pulse of HBLANK can be disabled or enabled by setting “NoHins” control bit.
6.2 H/V Frequency Counter
MTV230M can discriminate HSYNC/VSYNC frequency and saves the information in XFRs. The 14 bits
Hcounter counts the time of 64xHSYNC period, then loads the result into the HCNTH/HCNTL latch. The
output value will be [(128000000/H-Freq) - 1], updated once per VSYNC/CVSYNC period when
VSYNC/CVSYNC is present or continuously updated when VSYNC/CVSYNC is non-present. The 12 bits
Vcounter counts the time between two VSYNC pulses, then loads the result into the VCNTH/VCNTL latch.
The output value will be (62500/V-Freq), updated every VSYNC/CVSYNC period. An extra overflow bit
indicates the condition of H/V counter overflow. The VFchg/HFchg interrupt is set when VCNT/HCNT value
changes or overflowes. Table 6.2.1 and table 6.2.2 show the HCNT/VCNT value under the operations of
12MHz.
Revision 1.0
-9-
2000/11/15
MYSON
TECHNOLOGY
MTV230M
(Rev 1.0)
6.2.1 H-Freq Table
H-Freq(KHZ)
1
2
3
4
5
6
7
8
9
10
11
12
31.5
37.5
43.3
46.9
53.7
60.0
68.7
75.0
80.0
85.9
93.8
106.3
Output Value (14 bits)
12MHz OSC (hex / dec)
0FDEh / 4062
0D54h / 3412
0B8Bh / 2955
0AA8h / 2728
094Fh / 2383
0854h / 2132
0746h / 1862
06AAh / 1706
063Fh / 1599
05D1h / 1489
0554h / 1364
04B3h / 1203
6.2.2 V-Freq Table
V-Freq(Hz)
1
2
3
4
5
6
56
60
70
72
75
85
Output value (12bits)
12MHz OSC (hex / dec)
45Ch / 1116
411h / 1041
37Ch / 892
364h / 868
341h / 833
2DFh / 735
6.3 H/V Present Check
The Hpresent function checks the input HSYNC pulse, Hpre flag is set when HSYNC is over 10KHz or
cleared when HSYNC is under 10Hz. The Vpresent function checks the input VSYNC pulse, the Vpre flag is
set when VSYNC is over 40Hz or cleared when VSYNC is under 10Hz. The HPRchg interrupt is set when
the Hpre value changes. The VPRchg interrupt is set when the Vpre/CVpre value changes. However, the
CVpre flag interrupt may be disabled when S/W disables the composite function.
6.4 H/V Polarity Detect
The polarity functions detect the input HSYNC/VSYNC high and low pulse duty cycle. If the high pulse
duration is longer than that of the low pulse, the negative polarity is asserted; otherwise, positive polarity is
asserted. The HPLchg interrupt is set when the Hpol value changes. The VPLchg interrupt is set when the
Vpol value changes.
6.5 Output HBLANK/VBLANK Control and Polarity Adjust
The HBLANK is the mux output of HSYNC and composite Hpulse. The VBLANK is the mux output of
VSYNC and CVSYNC. The mux selection and output polarity are S/W controllable.
6.6 VSYNC Interrupt
The MTV230M checks the VSYNC input pulse and generates an interrupt at its leading edge. The VSYNC
flag is set each time when MTV230M detects a VSYNC pulse. The flag is cleared by S/W writing a "0".
Revision 1.0
- 10 -
2000/11/15
MYSON
TECHNOLOGY
MTV230M
(Rev 1.0)
6.7 H/V SYNC Processor Register
Reg name
HVSTUS
HCNTH
HCNTL
VCNTH
VCNTL
HVCTR0
HVCTR3
INTFLG
INTEN
addr
bit7
bit6
bit5
bit4
bit3
bit2
F40h (r)
CVpre
Hpol
Vpol
Hpre
Vpre
F41h (r)
Hovf
HF13
HF12
HF11
HF10
F42h (r)
HF7
HF6
HF5
HF4
HF3
HF2
F43h (r)
Vovf
VF11
VF10
F44h (r)
VF7
VF6
VF5
VF4
VF3
VF2
F40h (w)
C1
C0
NoHins
F43h (w)
CLPEG CLPPO CLPW2 CLPW1 CLPW0
F48h (r/w) HPRchg VPRchg HPLchg VPLchg HFchg
VFchg
F49h (w) EHPR
EVPR
EHPL
EVPL
EHF
EVF
bit1
Hoff
HF9
HF1
VF9
VF1
HBpl
bit0
Voff
HF8
HF0
VF8
VF0
VBpl
Vsync
EVsync
HVSTUS (r) : The status of polarity, present and static level for HSYNC and VSYNC.
CVpre = 1
→ The extracted CVSYNC is present.
=0
→ The extracted CVSYNC is not present.
Hpol
=1
→ HSYNC input is positive polarity.
=0
→ HSYNC input is negative polarity.
Vpol
=1
→ VSYNC (CVSYNC) is positive polarity.
=0
→ VSYNC (CVSYNC) is negative polarity.
Hpre = 1
→ HSYNC input is present.
=0
→ HSYNC input is not present.
Vpre
=1
→ VSYNC input is present.
=0
→ VSYNC input is not present.
Hoff* = 1
→ The off level HSYNC input is high.
=0
→ The off level HSYNC input is low.
Voff* = 1
→ The off level VSYNC input is high.
=0
→ The off level VSYNC input is low.
*Hoff and Voff are valid when Hpre=0 or Vpre=0.
HCNTH (r) :
High bits of H-Freq counter.
Hovf
=1
→ H-Freq counter is overflowed, this bit is cleared by H/W when condition removed.
HF13 - HF8 : 6 high bits of H-Freq counter.
HCNTL (r) :
Low byte of H-Freq counter.
VCNTH (r) :
High bits V-Freq of counter.
Vovf
=1
→ V-Freq counter is overflowed, this bit is cleared by H/W when condition removed.
VF11 - 8 :
4 high bits of V-Freq counter.
VCNTL (r) :
Low byteV-Freq counter.
HVCTR0 (w) : H/V SYNC processor control register 0.
C1, C0 = 1,1 → Selects CVSYNC as the polarity, freq and VBLANK source.
= 1,0 → Selects VSYNC as the polarity, freq and VBLANK source.
= 0,0 → Disables composite function.
= 0,1 → H/W auto switches to CVSYNC when CVpre=1 and VSpre=0.
NoHins = 1
→ HBLANK has no insert pulse in composite mode.
=0
→ HBLANK has insert pulse in composite mode.
HBpl = 1
→ Negative polarity HBLANK output.
=0
→ Positive polarity HBLANK output.
VBpl = 1
→ Negative polarity VBLANK output.
Revision 1.0
- 11 -
2000/11/15
MYSON
TECHNOLOGY
=0
MTV230M
(Rev 1.0)
→ Positive polarity VBLANK output.
HVCTR3 (w) : HSYNC clamp pulse control register.
CLPEG = 1
→ Clamp pulse follows HSYNC leading edge.
=0
→ Clamp pulse follows HSYNC trailing edge.
CLPPO = 1
→ Positive polarity clamp pulse output.
=0
→ Negative polarity clamp pulse output.
CLPW2 : CLPW0 : Pulse width of clamp pulse is
[(CLPW2:CLPW0) + 1] x 0.167 µs for 12MHz X’tal selection.
INTFLG (w) :
Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt
enable bit is set, INT1 source of the 8051 core will be driven by a zero level. Software MUST
clear this register while serve the interrupt routine.
HPRchg= 1
→ No action.
=0
→ Clears HSYNC presence change flag.
VPRchg= 1
→ No action.
=0
→ Clears VSYNC presence change flag.
HPLchg= 1
→ No action.
=0
→ Clears HSYNC polarity change flag.
VPLchg = 1
→ No action.
=0
→ Clears VSYNC polarity change flag.
HFchg = 1
→ No action.
=0
→ Clears HSYNC frequency change flag.
VFchg = 1
→ No action.
=0
→ Clears VSYNC frequency change flag.
Vsync = 1
→ No action.
=0
→ Clears VSYNC interrupt flag.
INTFLG (r) :
Interrupt flag.
HPRchg= 1
→ Indicates a HSYNC presence change.
VPRchg= 1
→ Indicates a VSYNC presence change.
HPLchg= 1
→ Indicates a HSYNC polarity change.
VPLchg = 1
→ Indicates a VSYNC polarity change.
HFchg = 1
→ Indicates a HSYNC frequency change or counter overflow.
VFchg = 1
→ Indicates a VSYNC frequency change or counter overflow.
Vsync = 1
→ Indicates a VSYNC interrupt.
INTEN (w) :
Interrupt enable.
EHPR = 1
→ Enables HSYNC presence change interrupt.
EVPR = 1
→ Enables VSYNC presence change interrupt.
EHPL = 1
→ Enables HSYNC polarity change interrupt.
EVPL = 1
→ Enables VSYNC polarity change interrupt.
EHF
=1
→ Enables HSYNC frequency change / counter overflow interrupt.
EVF
=1
→ Enables VSYNC frequency change / counter overflow interrupt.
EVsync = 1
→ Enables VSYNC interrupt.
7. DDC & IIC Interface
7.1 DDC2B Mode
To perform DDC2 function, S/W can configure the Slave A IIC block to act as EEPROM behavior. The slave
address of the Slave A block can be chosen by S/W as 5-bits, 6-bits or 7-bits. For example, if S/W chooses
5-bits slave address as 10100b, the slave IIC block A will respond to slave address 10100xxb and save the 2
Revision 1.0
- 12 -
2000/11/15
MYSON
TECHNOLOGY
MTV230M
(Rev 1.0)
LSB "xx" in XFR. This feature enables MTV230M to meet PC99 requirement.
7.2 Slave Mode IIC Function Block
The slave mode IIC block is connected to HSDA and HSCL pins. This block can receive/transmit data using
IIC protocol. There are 2 slave addresses MTV230M can respond to. S/W may write the
SLVAADR/SLVBADR register to determine the slave addresses. The SlaveA address can be configured to
5-bits, 6-bits or 7-bits by S/W setting the SlvAbs1 and SlvAbs0 control bits.
In receive mode, the block first detects IIC slave address matching the condition then issues a
SlvAMI/SlvBMI interrupt. If the matched address is slave A, MTV230M will save the 2 LSB bits of the
matched address to SlvAlsb1 and SlvAlsb0 register. The data from HSDA is shifted into shift register then
written to RCABUF/RCBBUF register when a data byte is received. The first byte loaded is word address
(slave address is dropped). This block also generates a RCAI/RCBI (receives buffer full interrupt) every time
the RCABUF/RCBBUF is loaded. If S/W is not able to read out the RCABUF/RCBBUF in time, the next byte
in shift register will not be written to RCABUF/RCBBUF and the slave block returns NACK to the master.
This feature guarantees the data integrity of communication. The WadrA/WadrB flag can tell S/W that if the
data in RCABUF/RCBBUF is a word address.
In transmit mode, the block first detects IIC slave address match condition then issues a SlvAMI/SlvBMI
interrupt. In the mean time, the SlvAlsb1/SlvAlsb0 is also updated if the matched address is slave A, and the
data pre-stored in the TXABUF/TXBBUF is loaded into shift register, result in TXABUF/TXBBUF empty and
generates a TXAI/TXBI (transmit buffer empty interrupt). S/W should write the TXABUF/TXBBUF a new byte
for next transfer before shift register empties. A failure of this process will cause data corrupt. The TXAI/TXBI
occurs every time when shift register reads out the data from TXABUF/TXBBUF.
The SlvAMI/SlvBMI is cleared by writing "0" to corresponding bit in INTFLG register. The RCAI/RCBI is
cleared by reading RCABUF/RCBBUF. The TXAI/TXBI is cleared by writing TXABUF/TXBBUF. If the control
bit ENSCL is set, the block will hold HSCL low until the RCAI/RCBI/TXAI/TXBI is cleared.
*Please see the attachments about "Slave IIC Block Timing".
7.3 Master Mode IIC Function Block
The master mode IIC block can be connected to the ISDA /ISCL pins or the HSDA/HSCL pins, selected by
Msel control bit. Its speed can be selected to 50KHz-400KHz by S/W setting the MIICF1/MIICF0 control bit.
The software program can access the external IIC device through this interface. A summary of master IIC
access is illustrated as follows.
7.3.1. To write IIC Device
1. Write MBUF the Slave Address.
2. Set S bit to Start.
3. After the MTV230M transmit this byte, a MbufI interrupt will be triggered.
4. Program can write MBUF to transfer next byte or set P bit to stop.
* Please see the attachments about "Master IIC Transmit Timing".
7.3.2. To read IIC Device
1. Write MBUF the Slave Address.
2. Set S bit to Start.
3. After the MTV230M transmit this byte, a MbufI interrupt will be triggered.
4. Set or reset the MAckO flag according to the IIC protocol.
5. Read out MBUF the useless byte to continue the data transfer.
6. After the MTV230M receives a new byte, the MbufI interrupt is triggered again.
7. Read MBUF also trigger the next receive operation, but set P bit before read can terminate the operation.
* Please see the attachments about "Master IIC Receive Timing".
Revision 1.0
- 13 -
2000/11/15
MTV230M
MYSON
TECHNOLOGY
Reg name
addr
IICCTR
F00h (r/w)
IICSTUS
F01h (r)
IICSTUS
F02h (r)
INTFLG
F03h (r)
INTFLG
F03h (w)
INTEN
F04h (w)
MBUF
F05h (r/w)
RCABUF
F06h (r)
TXABUF
F06h (w)
SLVAADR F07h (w)
RCBBUF
F08h (r)
TXBBUF
F08h (w)
SLVBADR F09h (w)
bit7
bit6
WadrB
MAckIn
TXBI
WadrA
ETXBI
ENSlvA
ENSlvB
bit5
(Rev 1.0)
bit4
SlvRWB SAckIn
bit3
bit2
MAckO
SLVS
RCBI
SlvBMI
TXAI
RCAI
SlvAMI
SlvBMI
SlvAMI
ERCBI ESlvBMI ETXAI ERCAI ESlvAMI
Master IIC receive/transmit data buffer
Slave A IIC receive buffer
Slave A IIC transmit buffer
Slave A IIC address
Slave B IIC receive buffer
Slave B IIC transmit buffer
Slave B IIC address
bit1
bit0
P
S
SlvAlsb1 SlvAlsb0
MbufI
MbufI
EMbufI
IICCTR (r/w) : IIC interface control register.
MAckO = 1
→ In master receive mode, NACK is returned by MTV230M.
=0
→ In master receive mode, ACK is returned by MTV230M.
S, P
= ↑, 0 → Start condition when Master IIC is not during transfer.
= X, ↑ → Stop condition when Master IIC is not during transfer.
= 1, X → Will resume transfer after a read/write MBUF operation.
IICSTUS (r) : IIC interface status register.
WadrB = 1
→ The data in RCBBUF is word address.
WadrA = 1
→ The data in RCABUF is word address.
SlvRWB = 1
→ Current transfer is slave transmit.
=0
→ Current transfer is slave receive.
SAckIn = 1
→ The external IIC host respond NACK.
SLVS = 1
→ The slave block has detected a START, cleared when STOP detected.
SlvAlsb1,SlvAlsb0 : The 2 LSB which host send to Slave A block.
MAckIn = 1
→ Master IIC bus error, no ACK received from the slave IIC device.
=0
→ ACK received from the slave IIC device.
INTFLG (w) :
Interrupt flag. A interrupt event will set its individual flag, and, if the corresponding interrupt
enable bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear
this register while serve the interrupt routine.
SlvBMI = 1
→ No action.
=0
→ Clears SlvBMI flag.
SlvAMI = 1
→ No action.
=0
→ Clears SlvAMI flag.
MbufI = 1
→ No action.
=0
→ Clears Master IIC bus interrupt flag (MbufI).
INTFLG (r) :
TXBI
RCBI
Interrupt flag.
=1
→ Indicates the TXBBUF needs a new data byte, cleared by writing TXBBUF.
=1
→ Indicates the RCBBUF has received a new data byte, cleared by reading
RCBBUF.
SlvBMI = 1
→ Indicates the slave IIC address B matches condition.
TXAI = 1
→ Indicates the TXABUF needs a new data byte, cleared by writing TXABUF.
RCAI = 1
→ Indicates the RCABUF has received a new data byte, cleared by reading
RCABUF.
SlvAMI = 1
→ Indicates the slave IIC address A match condition.
Revision 1.0
- 14 -
2000/11/15
MYSON
TECHNOLOGY
MbufI
=1
MTV230M
(Rev 1.0)
→ Indicates a byte is sent/received to/from the master IIC bus.
INTEN (w) :
Interrupt enable.
ETXBI = 1
→ Enables TXBBUF interrupt.
ERCBI = 1
→ Enables RCBBUF interrupt.
ESlvBMI = 1
→ Enables slave address B match interrupt.
ETXAI = 1
→ Enables TXABUF interrupt.
ERCAI = 1
→ Enables RCABUF interrupt.
ESlvAMI = 1
→ Enables slave address A match interrupt.
EMbufI = 1
→ Enables Master IIC bus interrupt.
Mbuf (w) :
Master IIC data shift register, after START and before STOP condition, writing this register
will resume transmission of MTV230M to the IIC bus.
Mbuf (r) :
Master IIC data shift register, after START and before STOP condition, reading this register
will resume receiving of MTV230M from the IIC bus.
RCABUF (r) :
Slave IIC block A receives data buffer.
TXABUF (w) : Slave IIC block A transmits data buffer.
SLVAADR (w) : Slave IIC block A's enable and address.
ENslvA = 1
→ Enables slave IIC block A.
=0
→ Disables slave IIC block A.
bit6-0 :
Slave IIC address A to which the slave block should respond.
RCBBUF (r) :
Slave IIC block B receives data buffer.
TXBBUF (w) : Slave IIC block B transmits data buffer.
SLVBADR (w) : Enable and address of Slave IIC block B.
ENslvB = 1
→ Enables slave IIC block B.
=0
→ Disables slave IIC block B.
bit6-0 :
Slave IIC address B to which the slave block should respond.
8. Low Power Reset (LVR) & Watchdog Timer
When the voltage level of power supply is below 2.7V for a specific period of time, the LVR will generate a
chip reset signal. After the power supply is above 2.7V, LVR maintain in reset state for 144 Xtal cycle to
guarantee the chip exit reset condition with a stable X'tal oscillation.
The Watchdog Timer automatically generates a device reset when it is overflowed. The interval of overflow is
0.25 sec x N, where N is a number from 1 to 8, and can be programmed via register WDT(2:0). The timer
function is disabled after power on reset, users can activate this function by setting WEN, and clear the timer
by set WCLR.
9. A/D converter
The MTV230M is equipped with four 6-bit A/D converters. S/W can select the current convert channel by
setting the SADC1/SADC0 bit. The refresh rate for the ADC is OSC freq./12288. The ADC compares the
input pin voltage with internal VDD*N/64 voltage (where N = 0 - 63). The ADC output value is N when pin
voltage is greater than VDD*N/64 and smaller than VDD*(N+1)/64.
Revision 1.0
- 15 -
2000/11/15
MTV230M
MYSON
TECHNOLOGY
Reg name
ADC
ADC
WDT
addr
bit7
F10h (w) ENADC
F10h (r)
F18h (w)
WEN
bit6
bit5
(Rev 1.0)
bit4
WCLR
bit3
bit2
bit1
SADC3 SADC2 SADC1
ADC convert Result
WDT2
WDT1
bit0
SADC0
WDT0
WDT (w) :
Watchdog Timer control register.
WEN
=1
→ Enables Watchdog Timer.
WCLR
=1
→ Clears Watchdog Timer.
WDT2: WDT0 = 0
→ Overflow interval = 8 x 0.25 sec.
=1
→ Overflow interval = 1 x 0.25 sec.
=2
→ Overflow interval = 2 x 0.25 sec.
=3
→ Overflow interval = 3 x 0.25 sec.
=4
→ Overflow interval = 4 x 0.25 sec.
=5
→ Overflow interval = 5 x 0.25 sec.
=6
→ Overflow interval = 6 x 0.25 sec.
=7
→ Overflow interval = 7 x 0.25 sec.
ADC (w) :
ADC control.
ENADC
=1
SADC0
=1
SADC1
=1
SADC2
=1
SADC3
=1
ADC (r) :
→ Enables ADC.
→ Selects ADC0 pin input.
→ Selects ADC1 pin input.
→ Selects ADC2 pin input.
→ Selects ADC3 pin input.
ADC converts result.
10. In System Programming function (ISP)
The two Flash memories (OSD Flash and Code Flash) can be programmed by a specific WRITER in parallel
mode, or by IIC Host in serial mode while the system is working. The feature of ISP is outlined as below:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Single 3.3V power supply for Program/Erase/Verify.
Block Erase: 512 Byte for Program Code or 256 words for OSD fonts, both are 10mS time.
Whole Flash erase (Blank): 10mS
Byte/Word programming Cycle time: 60uS per byte, 120uS per word
Read access time: 40ns
Only one two-pin IIC bus (shared with DDC2) is needed for ISP in user/factory mode.
IIC Bus clock rates up to 140KHz.
Whole 64K-byte/9K-word Flash programming within 6/2 Sec.
CRC check provides 100% coverage for all single/double bit errors.
After power on/Reset, The MTV230M is running the original Program Code. Once the S/W detects an ISP
request (by key or IIC), S/W can accept the request following the steps below:
1.
2.
3.
4.
5.
Clear watchdog to prevent reset during ISP period.
Disable all interrupt to prevent CPU wake-up.
Write IIC address of ISP slave to ISPSLV for communication.
Write 93h to ISP enable register (ISPEN) to enable ISP.
Enter 8051 idle mode.
When ISP is enabled, the MTV230M will disable Watchdog reset and switch the Flash interface to ISP host
in 15-22.5uS. So S/W MUST enter idle mode immediately after enabling ISP. In the 8051 idle mode, PWM
DACs and I/O pins keep running at its former status. There are 4 types of IIC bus transfer protocols in ISP
Revision 1.0
- 16 -
2000/11/15
MYSON
TECHNOLOGY
MTV230M
(Rev 1.0)
mode.
Command Write
S-tttttt10k-cccccxxBk-AAAAAAAAk-P
Command Read
S-tttttt11k-cccccXXBK-AAAAAAAAK-aaaaaaaaK-RRRRRRRRK-rrrrrrrrK-P
Data Write
S-tttttt00k-aaaaaaaak-ddddddddk-ddddddddk- ... –ddddddddk-ddddddddk-P
Data Read
S-tttttt00k-aaaaaaaak-(P)S-tttttt01k-ddddddddK-ddddddddK- ... –ddddddddK-ddddddddK-P
where
S = start or re-start
P = stop
K = ack by host (0 or 1)
k = ack by slave
tttttt = ISP slave address
ccccc = command
B = OSD/Code select (1=OSD)
x = don’t care
X = not defined
AAAAAAAA = Code_address[15:8]
aaaaaaaa = Code_address[7:0]
AAAAAAA = OSD_address[13:7]
aaaaaaa = OSD_address[6:0]
RRRRRRRR = CRC_register[15:8]
rrrrrrrr = CRC_register[7:0]
dddddddd-dddddddd = Code_data
dddd-dddddddd = OSD_data
ccccc = 10100 → Program
ccccc = 00110 → Page Erase 512 bytes or 256 words (Erase)
ccccc = 01101 → Erase entire Flash (Blank)
ccccc = 11010 → Clear CRC_register (Clr_CRC)
ccccc = 01001 → Reset MTV230M (Reset_CPU)
10.1 ISP Command Write
The 2nd byte of “Command Write” can define the operating mode of MTV230M in its “Data write” stage,
clear CRC register, or reset MTV230M. The bit 0 of 2nd byte selects the target Flash to be operated (1=OSD,
0=Code). The 3rd byte of Command Write defines the page address (A15-8 of Code Flash, A13-7 of OSD
Flash). A Command Write may consist of 1,2 or 3 bytes.
10.2 ISP Command Read
The 2nd byte echoes the current command in ISP slave. The 3rd and 4th byte reflect the current Flash address.
The 5th and 6th byte report the CRC result. A Command Read may consist of 2,3,4,5 or 6 bytes.
10.3 ISP Data Write
The 2nd byte defines the low address of Flash (A7-0 for Code, A6-0 for OSD). After receiving the 3rd byte, the
MTV230M will execute a Program/Erase/Blank command depending on the preceding “Command Write”. If
Code area is selected, the low address of Code Flash will increase every time when ISP slave acknowledges
the data byte. If OSD Flash is selected, the low address of OSD Flash will increase when every 2 data bytes
are received. The Blank/Erase command needs one data byte (content is “don’t care”). The executing time is
10mS. During the 10mS period, the ISP slave does not accept any command/data and returns non-ack to
any IIC bus activity. The Program command may have 1-256 data bytes for Code Flash, and have 1-128
word(256 bytes) for OSD Flash. The program cycle time is 60us. If the ISP slave is not able to complete the
program cycle in time, it will return non-ack to the following data byte. In the meantime, the low address does
not increase and the CRC does not count the non-acked data byte. A Data Write may consist of 1,2 or more
bytes.
Data Write (Blank/Erase)
S-tttttt00k-aaaaaaaak-ddddddddk-P ... S-ttttttxxk|----Min. 10mS----|
Data Write (Program)
Revision 1.0
- 17 -
2000/11/15
MTV230M
MYSON
TECHNOLOGY
(Rev 1.0)
S-tttttt00k-aaaaaaaak-ddddddddk-ddddddddk- ...
|Min. 60uS|
10.4 ISP Data Read
The 1st and 2nd byte are the same as “Data write” to define the low address of Flash. Between 2nd and 3rd
bytes, the ISP host may issue Stop-Start or only Re-Start. From the 4th byte, the ISP slave sends data
byte/word of Flash to ISP Host. The low address automatically increases every time when data byte/word is
transferred.
10.5 Cyclic Redundancy Check (CRC)
To shorten the verify time, the ISP slave provides a simple way to check whether data error occurs during
the program data transfer. After the ISP Host sends a lot of data byte to ISP slave, Host can use Command
Read to check CRC register’s result instead of reading every byte in Flash. The CRC register counts every
data byte which ISP slave acknowledges during “Data Write” period. However, the low address byte and the
data byte of Erase/Blank are not counted. The Clear CRC command will write all “1” to the 16-bit CRC
register. The OSD Flash and Code share the same CRC counter. For CRC generation, the 16-bit CRC
register is seeded with all “1” pattern (by device reset or Clear CRC command). The data byte shifted into
the CRC register is Msb first. The real implementation is described as follows:
CRCin = CRC[15]^DATAin;
CRC[15:0] = {CRC[14]^CRCin, CRC[13:2], CRC[1]^CRCin, CRC[0], CRCin};
Where ^ = XOR
example:
data_byte
F6H
28H
C3H
CRC_register_remainder
FFFFH
FF36H
34F2H
7031H
10.6 Reset Device
After the Flash programming is completed and verified OK, the ISP Host can use “Command Write” with
Reset_CPU command to wake up MTV230M.
Reg name
ISPSLV
ISPEN
addr
F0bh (w)
F0ch (w)
bit7
bit6
bit5
bit4
bit3
bit2
ISP Slave address
Write 93h to enable ISP Mode
bit1
bit0
11. On-Screen Display (OSD)
11.1 Horizontal Display control
The horizontal display control is used to generate control timing for horizontal display. The horizontal display
size is based on the information of pixel clock input cycle, double width control bit (DWE), and double
character width bit (CWS). The horizontal display center could be figured out according to the information of
horizontal starting position register (HORD) and OSDHS input. A horizontal display line includes 360 dots for
30 display characters and the remaining dots for blank region. The horizontal display starting position from
the leading edge of OSDHS is calculated using the following equation:
Horizontal delay time = (HORD * 6 +49) * P
, where P = one pixel display time
11.2 Vertical Display control
The vertical display control can generate different vertical display sizes for most display standards in current
monitors. The vertical display size is calculated with the information of double character height bit (CHS),
character vertical height control register (CH6-CH0). The algorithms of repeating character line display are
Revision 1.0
- 18 -
2000/11/15
MTV230M
MYSON
TECHNOLOGY
(Rev 1.0)
shown in the table below. The programmable vertical size ranges are 270 lines to maximum 2130 lines.
The vertical display center for full screen display could be figured out according to the information of vertical
starting position register (VERTD) and OSDVS input. The vertical display starting position from the leading
edge of OSDVS is calculated using the following equation:
Vertical delay time = (VERTD * 4 +1) * H
, where H = one horizontal line display time
Repeat Line Weight of Character
CH6 – CH0
Repeat Line Weight
CH6, CH5 = 11
+18*3
CH6, CH5 = 10
+18*2
CH6, CH5 = 0x
+18
CH4 = 1
+16
CH3 = 1
+8
CH2 = 1
+4
CH1 = 1
+2
CH0 = 1
+1
Repeat Line Number of character
Repeat Line
Repeat Line #
Weight
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17
+1
v
+2
v
v
+4
v
v
v
v
+8
v
v
v
v
v
v
v
v
+16
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
+17
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
+18
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Note: “v” means the nth line in the character would be repeated once, while “-“ means the nth line in the
character would not be repeated.
11.3 Display RAM
The display RAM contains character address, attribute and row control registers. The display registers have
450 locations which are allocated between (row 0, column 0) to (row14, column 29). Each display register
has its corresponding character address on ADDRESS bytes, and its corresponding color, blink bit,
background color on ATTRIBUTE bytes. The row control register is allocated at column 30 from row 0 to row
14 of address bytes. It is used to set character size to each respective row. If double width character is
chosen, only even column characters could be displayed on screen and the odd column characters will be
hidden.
There are 4 registers to program display RAM: OSDRA, OSDCA, OSDDT0 and OSDDT1. OSDRA is the row
address; OSDCA is the column address; OSDDT0 and OSDDT1 are the programming data byte. The 2 MSB
(bit 7 - bit 6) of OSDRA register are used to distinguish ADDRESS byte when they are set to “0, 0” and
ATTRIBUTE byte when they are set to “0, 1”. OSDDT0 and OSDDT1 are used to differentiate the MSB (bit 8)
of display characters address. The MSB (bit 8) of display characters address will be equal to ”0“ while data
byte is filled into OSDDT0, or “1” while data byte is filled into OSDDT1; and OSDDT0 or OSDDT1 are the 8
LSB (bit 7 - bit 0) of display characters address.
The programming row (OSDRA) and column (OSDCA) address of display RAM will be incremented
automatically when MCU continues to update OSDDT0 or OSDDT1. It is used to save the program ROM
size of MCU while massive data update or full screen data change.
Since bit 8 is fixed on OSDDT0 (OSDDT1) while programming ADDRESS byte, the continued OSDDT0
(OSDDT1) will be the same bank of lower 256 fonts (upper 256 fonts) until program another data byte
OSDDT1 (OSDDT0) register.
Revision 1.0
- 19 -
2000/11/15
MTV230M
MYSON
TECHNOLOGY
(Rev 1.0)
To program ADDRESS bytes and ATTRIBUTE bytes of the display RAM:
Step 1. Write data into OSDRA to determine the programming row address of the display RAM. And define
whether it is the row address of ADDRESS byte (bit7-bit6 = “0, 0”) or ATTRIBUTE byte (bit7-bit6 =
“0, 1”).
Step 2. Write data into OSDCA to determine the programming column address of the display RAM.
Step 3. Write to OSDDT0 or OSDDT1 the address or attribute of the character to be displayed on the
screen.
Step 4. Post increment operation is executed in the OSDCA (i.e. OSDCA ← OSDCA + 1) to make it point
to the next display RAM location. Overflow of the OSDCA, i.e. overflow from 31, makes itself return
to 0 and makes post increment operation executed in the OSDRA (i.e. OSDRA ← OSDRA + 1).
Overflow of the OSDRA, i.e. overflow from 15, makes itself return to 0.
It is the step 3 which triggers the load of OSDDT0 or OSDDT1 into the current OSDRA, OSDCA address of
the display RAM and the post increment operation. Furthermore, the undefined locations in the display RAM
should be filled with dummy data while post increment operation is executed.
So there are three transmission formats shown as below:
Format (a) R - C - D −> R - C - D −> R - C - D … ..
Format (b) R - C - D −> C - D −> C - D −> C - D … ..
Format (c) R - C - D −> D −> D −> D −> D −> D … ..
Where R= OSDRA (row address), C= OSDCA (column address), D= OSDDT0 or OSDDT1 (display data)
Format (a) is suitable for updating small amount of data which will be allocated with different row address
and column address. Format (b) is recommended for updating data that has same row address but different
column address. Massive data updating or full screen data change should use format (c) to increase
transmission efficiency. The row and column address will be incremented automatically when the format (c)
is applied. Furthermore, the undefined locations in display or user fonts RAM should be filled with dummy
data.
The Configuration of Transmission Formats
Address
OSDRA (row address)
ADDRESS
OSDCA (column address)
Bytes of
OSDDT0 (data, b8=0)
Display Reg.
OSDDT1 (data, b8=1)
OSDRA (row address)
ATTRIBUTE
OSDCA (column address)
Bytes of
OSDDT0 (data, b8=0)
Display Reg.
OSDDT1 (data, b8=1)
Row #
(OSDRA)
0 1
b7
0
D7
D7
0
D7
D7
b6
0
D6
D6
1
D6
D6
b5
D5
D5
D5
D5
b4
C4
D4
D4
C4
D4
D4
b3
R3
C3
D3
D3
R3
C3
D3
D3
ADDRESS Bytes of the Display RAM
Column # (OSDCA)
28 29
b2
R2
C2
D2
D2
R2
C2
D2
D2
b1
R1
C1
D1
D1
R1
C1
D1
D1
30
0
1
Character ADDRESS
of the Display RAM
13
14
Revision 1.0
- 20 -
ROW
CTRL REG
b0
R0
C0
D0
D0
R0
C0
D0
D0
31
R
E
S
E
R
V
E
D
2000/11/15
MTV230M
MYSON
TECHNOLOGY
Row #
(OSDRA)
0 1
(Rev 1.0)
ATTRIBUTE Bytes of the Display RAM
Column # (OSDCA)
28 29
30
31
0
1
Character ATTRIBUTE
of the Display RAM
RESERVED
13
14
ADDRESS bytes:
Display characters address (OSDRA 0 ~ 14, OSDCA 0 ~ 29),
B8
B7
B6
B5
B4
B3
B2
CRADDR
MSB
B1
B0
LSB
CRADDR : Defines Flash-ROM OSD character address from address 0 to 511.
(a) 0 ~ 479 => 480 standard fonts.
(b) 480 ~ 511 => 32 multi-color fonts.
Row control registers (OSDRA 0 ~ 14, OSDCA 30),
B7
B6
B5
B4
B3
B2
RINT
B1
CHS
B0
CWS
RINT : The displayed character/symbol foreground color intensity control to the respective row. Setting this
bit to “0” means low intensity in this row. 15-character foreground color is achievable by this bit.
CHS : Defines double height character to the respective row.
CWS : Defines double width character to the respective row. If double width character is chosen, only even
column characters could be displayed on screen and the odd column characters will be hidden.
ATTRIBUTE bytes:
Display character attribute (OSDRA 0 ~ 14, OSDCA 0 ~ 29),
B7
B6
B5
B4
B3
B2
BGR
BGG
BGB
BLINK
R
B1
G
B0
B
BGR, BGG, BGB : These three bits define the background color for its relative address character. If these
three bits are set to (0, 0, 0), no background will be shown (transparent). Therefore, a
total of 7 background colors can be selected.
BLINK = 1
→ Enables blink effect for its relative address character. And the blinking is alternate per 32
vertical frames.
=0
→ Disables blink effect for its relative address character.
R, G, B : These three bits are used to specify their relative address character colors.
11.4 Character Flash-ROM
MTV230M character flash-ROM contains 512 characters and symbols including 496 standard fonts and 16
multi-color fonts. The 496 standard fonts are located from character address 0 to 495. And the multi-color
fonts are located from character address 496 to 511. Each character and symbol consists of 12x18 dots
matrix. The MTV230M font edit tools can be used to design the 512 characters and symbols by software.
11.5 Multi-color Font
The color fonts comprise three different R, G, B fonts. When the code of color font is accessed, the separate
Revision 1.0
- 21 -
2000/11/15
MTV230M
MYSON
TECHNOLOGY
(Rev 1.0)
R/G/B dot pattern is output to corresponding R/G/B output. See figure below for the sample displayed color
font.
Note: No black color can defined in color font, black window or background underline the color font can make
the dots become black in color.
B
G
R
Magenta
Green
Blue
Cyan
Example of Multi-color Font
The Multi-color Font Color Selection
R
G
Background Color
0
0
Blue
0
0
Green
0
1
Cyan
0
1
Red
1
0
Magenta
1
0
Yellow
1
1
White
1
1
B
0
1
0
1
0
1
0
1
11.6 Luminance & Border Generator
There are 3 shift registers included in the design which can shift out of luminance and border dots to color
encoder. The bordering and shadowing feature is configured in this block. For bordering effect, the character
will be enveloped with blackedge on four sides. For shadowing effect, the character is enveloped with
blackedge for right and bottom sides only.
11.7 Window Control
The window size and position controls are specified in W1ROW, W1COL, W2ROW, W2COL, W3ROW,
W3COL, W4ROW and W4COL registers. And window 1 has the highest priority, and window 4 has the least,
when two windows are overlapping.
The window shadow width and height controls are specified in WINSW and WINSH registers. And each
shadow has the same priority with its corresponding window.
Revision 1.0
- 22 -
2000/11/15
MYSON
TECHNOLOGY
MTV230M
(Rev 1.0)
11.8 OSD Processor registers
Reg name
OSDRA
OSDCA
OSDDT0
OSDDT1
W1ROW
W1COL
W1COL
W2ROW
W2COL
W2COL
W3ROW
W3COL
W3COL
W4ROW
W4COL
W4COL
VERTD
HORD
CH
RSPACE
OSDCON
OSDCON
CHSC
FSSTP
WINSW
WINSH
WINSC
WINSC
XDEL
addr
bit7
FA0h (w)
A1
FA1h (w)
FA2h (w)
D7
FA3h (w)
D7
FC0h (w)
FC1h (w)
FC2h (w)
FC3h (w)
FC4h (w)
FC5h (w)
FC6h (w)
FC7h (w)
FC8h (w)
FC9h (w)
FCAh (w)
FCBh (w)
FCCh (w)
FCDh (w)
FCEh (w)
FD0h (w)
FD1h (r/w) OSDEN
FD2h (r/w)
FD3h (w)
FD4h (w)
FSW
FD5h (w) WW41
FD6h (w) WH41
FD7h (w)
FD8h (w)
FD9h (w)
-
bit6
bit5
bit4
bit3
bit2
bit1
A0
R3
R2
R1
C4
C3
C2
C1
D6
D5
D4
D3
D2
D1
D6
D5
D4
D3
D2
D1
Row start address
Row end address
Column start address
WEN
WINT
Column end address
R
G
Row start address
Row end address
Column start address
WEN
WINT
Column end address
R
G
Row start address
Row end address
Column start address
WEN
WINT
Column end address
R
G
Row start address
Row end address
Column start address
WEN
WINT
Column end address
R
G
Vertical delay
Horizontal delay
Character height
Row to row spacing
BSEN Shadow FBEN
Blend WENclr RAMclr
DWE
HSP
VSP
CSR
CSG
FSR
FSG
WW40 WW31 WW30 WW21 WW20 WW11
WH40
WH31
WH30
WH21
WH20
WH11
R1
G1
B1
R2
G2
R3
G3
B3
R4
G4
D2
D1
bit0
R0
C0
D0
D0
WSHD
B
WSHD
B
WSHD
B
WSHD
B
FBKGC
CSB
FSB
WW10
WH10
B2
B4
D0
OSDRA (w) :
R3-R0 : This is the row address of the display RAM that next 9-bit data should be written into.
A1-A0 = (0, 0) → Next 9-bit data will be written into ADDRESS byte.
= (0, 1) → Next 9-bit data will be written into ATTRIBUTE byte.
OSDCA (w) : This is the column address of the display RAM that next 9-bit data should be written into.
OSDDT0 (w) : The MSB (bit 8) = 0, 8 LSB (bit 7 ~ bit 0) = OSDDT0. The 9-bit data will be written into current
(OSDRA, OSDCA) address of the display RAM. It will also trigger the post increment
operation of OSDRA and OSDCA.
OSDDT1 (w) : The MSB (bit 8) = 1, 8 LSB (bit 7 ~ bit 0) = OSDDT1. The 9-bit data will be written into current
(OSDRA, OSDCA) address of the display RAM. It will also trigger the post increment
operation of OSDRA and OSDCA.
W1ROW, W1COL (w) : Window 1 control registers.
Row (column) start (end) address : These registers are used to specify the window 1 size. It should
be noted that when the start address is greater than end address,
the corresponding window display will be disabled.
WEN : Enables the relative background window 1 display.
Revision 1.0
- 23 -
2000/11/15
MYSON
TECHNOLOGY
MTV230M
(Rev 1.0)
WINT :
Specifies the color intensity of the background window 1. Setting this bit to “0” means low
intensity.
WSHD : Enables shadowing on the window 1.
R, G, B : Specifies the color of the relative background window 1.
W2ROW, W2COL (w) : Window 2 control registers.
Row (column) start (end) address : These registers are used to specify the window 2 size.
WEN : Enables the relative background window 2 display.
WINT : Specifies the color intensity of the background window 2. Setting this bit to “0” means low
intensity.
WSHD : Enables shadowing on the window 2.
R, G, B : Specifies the color of the relative background window 2.
W3ROW, W3COL (w) : Window 3 control registers.
Row (column) start (end) address : These registers are used to specify the window 3 size.
WEN : Enables the relative background window 3 display.
WINT : Specifies the color intensity of the background window 3. Setting this bit to “0” means low
intensity.
WSHD : Enables shadowing on the window 3.
R, G, B : Specifies the color of the relative background window 3.
W4ROW, W4COL (w) : Window 4 control registers.
Row (column) start (end) address : These registers are used to specify the window 4 size.
WEN : Enables the relative background window 4 display.
WINT : Specifies the color intensity of the background window 4. Setting this bit to “0” means low
intensity.
WSHD : Enables shadowing on the window 4.
R, G, B : Specifies the color of the relative background window 4.
VERTD (w) :
Specifies the starting position for vertical display. The total steps are 256, and the increment
of each step is 4 horizontal display lines. The starting position is calculated as (VERTD*4 + 1)
horizontal display lines. The initial value is 4 after power up.
HORD (w) :
Specifies the starting position for horizontal display. The total steps are 256, and the
increment of each step is 6 dots. The starting position is calculated as (HORD*6 + 49)
horizontal display dots. The initial value is 15 after power up.
CH (w) :
Defines the character vertical height, the height is programmable from 18 to 71 lines. The
character vertical height is at least 18 lines if the content of CH6-CH0 is less than 18. For
example, when the content is “2”, the character vertical height is regarded as equal to 20
lines. And if the content of CH4-CH0 is greater than or equal to 18, it will be regarded as
equal to 17. See table list in section 11.1 for detail description of this operation.
RSPACE (w) : Defines the row to row spacing in unit of horizontal line. Extra RSPACE horizontal lines will be
appended below each display row, and the maximum space is 31 lines. The initial value is 0
after power up.
OSDCON (r/w) : OSD control registers.
OSDEN = 1
→ Activates the OSD operation.
=0
→ Disables the OSD operation.
BSEN = 1
→ Enables the character bordering or shadowing effect.
=0
→ Disables bordering and shadowing effect.
Shadow = 1
→ Selects the character shadowing effect if BSEN bit is set to “1”.
=0
→ Selects the character bordering effect if BSEN bit is set to “1”.
FBEN = 1
→ Enables the fade-in/fade-out or blending-in/blending-out effect when OSD is
Revision 1.0
- 24 -
2000/11/15
MTV230M
MYSON
TECHNOLOGY
turned on from off state or vice versa.
→ Disables the fade-in/fade-out and blending-in/blending-out effect.
→ Selects the blending-in/blending-out effect if FBEN bit is set to “1”.
→ Selects the fade-in/fade-out effect if FBEN bit is set to “1”.
→ Clears all WEN bits of window control registers.
→ Normal.
→ Clears all ADDRESS bytes, BGR, BGG, BGB and BLINK bits of display RAM.
→ Normal.
→ Pin FBKG outputs is high only during the displaying of characters.
→ Pin FBKG outputs is high during the displaying of characters or windows.
→ Enables double width. The OSD menu will change to half resolution for double
character width. And the number of pixels of each line should be even.
→ Normal.
→ Accepts positive polarity OSDHS input.
→ Accepts negative polarity OSDHS input.
→ Accepts positive polarity OSDVS input.
→ Accepts negative polarity OSDVS input.
=0
Blend = 1
=0
WENclr = 1
=0
RAMclr = 1
=0
FBKGC = 1
=0
DWE = 1
HSP
VSP
(Rev 1.0)
=0
=1
=0
=1
=0
CHSC (w) : Character shadow color select registers.
CSR, CSG, CSB : Defines the color of bordering or shadowing color on characters.
FSSTP (w) : Full screen self-test pattern registers.
FSW
=1
→ Enables full screen self-test pattern and force pin FBKG outputs high to disable
video RGB.
=0
→ Disables full screen self-test pattern.
FSR, FSG, FSB : Defines the color of full screen self-test pattern.
WINSW (w) : Window shadowing width control registers.
WW41, WW40 : Determines the shadow width of window 4 when WSHD bit of window 4 is enabled.
Please refer to the table below for more details.
(WW41, WW40)
Shadow Width (unit in Pixel)
(0, 0)
2
(0, 1)
4
(1, 0)
6
(1, 1)
8
WW31, WW30 : Determines the shadow width of window 3 when WSHD bit of window 3 is enabled.
WW21, WW20 : Determines the shadow width of window 2 when WSHD bit of window 2 is enabled.
WW11, WW10 : Determines the shadow width of window 1 when WSHD bit of window 1 is enabled.
WINSH (w) : Window shadowing height control registers.
WH41, WH40 : Determines the shadow height of window 4 when WSHD bit of window 4 is enabled.
Please refer to the table below for more details.
(WH41, WH40)
Shadow Height (unit in Line)
WH31, WH30 :
WH21, WH20 :
WH11, WH10 :
Revision 1.0
(0, 0)
2
(0, 1)
4
(1, 0)
6
(1, 1)
8
Determines the shadow height of window 3 when WSHD bit of window 3 is enabled.
Determines the shadow height of window 2 when WSHD bit of window 2 is enabled.
Determines the shadow height of window 1 when WSHD bit of window 1 is enabled.
- 25 -
2000/11/15
MTV230M
MYSON
TECHNOLOGY
(Rev 1.0)
M Pixels
N Horizontal lines
Note:
M and N are defined
by the registers of
WINSW and WINSH.
N Horizontal lines
Bordering
Shadowing
M Pixels
Character Bordering and Shadowing and Shadowing on Window
WINSC (w) : Window shadowing color control registers.
R1, G1, B1 : Define the shadowing color of window 1.
R2, G2, B2 : Define the shadowing color of window 2.
R3, G3, B3 : Define the shadowing color of window 3.
R4, G4, B4 : Define the shadowing color of window 4.
XDEL (w) : Rout, Gout, Bout, FBKG and INT outputs delay reference to pin XIN input falling edge control
registers.
XIN
Internal CLK
OSD output
tPD
tPD
OSDHS
tSETUP
tHOLD
Revision 1.0
- 26 -
2000/11/15
MTV230M
MYSON
TECHNOLOGY
(Rev 1.0)
Memory Map of XFR
Reg name
IICCTR
IICSTUS
IICSTUS
INTFLG
INTFLG
INTEN
MBUF
RCABUF
TXABUF
SLVAADR
RCBBUF
TXBBUF
SLVBADR
ISPSLV
ISPEN
ADC
ADC
WDT
DA0
DA1
DA2
DA3
PORT6
PORT6
PORT6
PADMOD
PADMOD
PADMOD
PADMOD
OPTION
PORT4
PORT4
PORT4
PORT4
PORT4
PORT4
PORT4
PORT4
PORT5
PORT5
PORT5
PORT5
PORT5
PORT5
PORT5
PORT5
HVSTUS
HCNTH
HCNTL
Revision 1.0
addr
F00h (r/w)
F01h (r)
F02h (r)
F03h (r)
F03h (w)
F04h (w)
F05h (r/w)
F06h (r)
F06h (w)
F07h (w)
F08h (r)
F08h (w)
F09h (w)
F0bh (w)
F0ch (w)
F10h (w)
F10h (r)
F18h (w)
F20h (r/w)
F21h (r/w)
F22h (r/w)
F23h (r/w)
F28h(w)
F29h(w)
F2Ah(w)
F2Bh (w)
F2Ch (w)
F2Dh (w)
F2Eh (w)
F2Fh (w)
F30h(r/w)
F31h(r/w)
F32h(r/w)
F33h(r/w)
F34h(r/w)
F35h(r/w)
F36h(r/w)
F37h(r/w)
F38h(r/w)
F39h(r/w)
F3Ah(r/w)
F3Bh(r/w)
F3Ch(r/w)
F3Dh(r/w)
F3Eh(r/w)
F3Fh(r/w)
F40h (r)
F41h (r)
F42h (r)
bit7
bit6
WadrB
MAckIn
TXBI
WadrA
ETXBI
ENSlvA
ENSlvB
ENADC
WEN
bit5
bit4
SlvRWB SAckIn
bit3
bit2
MAckO
SLVS
bit1
bit0
P
S
SlvAlsb1 SlvAlsb0
RCBI
SlvBMI
TXAI
RCAI
SlvAMI
SlvBMI
SlvAMI
ERCBI ESlvBMI ETXAI ERCAI ESlvAMI
Master IIC receive/transmit data buffer
Slave A IIC receive buffer
Slave A IIC transmit buffer
Slave A IIC address
Slave B IIC receive buffer
Slave B IIC transmit buffer
Slave B IIC address
ISP Slave address
Write 93h to enable ISP Mode
SADC3 SADC2 SADC1
ADC convert Result
WCLR
WDT2
WDT1
Pulse width of PWM DAC 0
Pulse width of PWM DAC 1
Pulse width of PWM DAC 2
Pulse width of PWM DAC 3
HIICE
DA3E
P47oe
P57oe
PWMF
IIICE
HVE
HclpE
DA2E
DA1E
DA0E
AD3E
P46oe
P45oe
P44oe
P43oe
P56oe
P55oe
P54oe
P53oe
DIV253 SlvAbs1 SlvAbs0 ENSCL
CVpre
Hovf
HF7
Hpol
Vpol
HF13
HF12
HF5
HF4
- 27 -
HF6
Hpre
HF11
HF3
AD2E
P42oe
P52oe
Msel
FclkE
AD1E
P41oe
P51oe
MIICF1
Vpre
HF10
HF2
Hoff
HF9
HF1
MbufI
MbufI
EMbufI
SADC0
WDT0
P60
P61
P62
P62E
AD0E
P40oe
P50oe
MIICF0
P40
P41
P42
P43
P44
P45
P46
P47
P50
P51
P52
P53
P54
P55
P56
P57
Voff
HF8
HF0
2000/11/15
MYSON
TECHNOLOGY
VCNTH
VCNTL
HVCTR0
HVCTR3
INTFLG
INTEN
OSDRA
OSDCA
OSDDT0
OSDDT1
W1ROW
W1COL
W1COL
W2ROW
W2COL
W2COL
W3ROW
W3COL
W3COL
W4ROW
W4COL
W4COL
VERTD
HORD
CH
RSPACE
OSDCON
OSDCON
CHSC
FSSTP
WINSW
WINSH
WINSC
WINSC
XDEL
MTV230M
(Rev 1.0)
F43h (r)
Vovf
VF11
VF10
VF9
F44h (r)
VF7
VF6
VF5
VF4
VF3
VF2
VF1
F40h (w)
C1
C0
NoHins
HBpl
F43h (w)
CLPEG CLPPO CLPW2 CLPW1 CLPW0
F48h (r/w) HPRchg VPRchg HPLchg VPLchg HFchg
VFchg
F49h (w) EHPR
EVPR
EHPL
EVPL
EHF
EVF
FA0h (w)
A1
A0
R3
R2
R1
FA1h (w)
C4
C3
C2
C1
FA2h (w)
D7
D6
D5
D4
D3
D2
D1
FA3h (w)
D7
D6
D5
D4
D3
D2
D1
FC0h (w)
Row start address
Row end address
FC1h (w)
Column start address
WEN
WINT
FC2h (w)
Column end address
R
G
FC3h (w)
Row start address
Row end address
FC4h (w)
Column start address
WEN
WINT
FC5h (w)
Column end address
R
G
FC6h (w)
Row start address
Row end address
FC7h (w)
Column start address
WEN
WINT
FC8h (w)
Column end address
R
G
FC9h (w)
Row start address
Row end address
FCAh (w)
Column start address
WEN
WINT
FCBh (w)
Column end address
R
G
FCCh (w)
Vertical delay
FCDh (w)
Horizontal delay
FCEh (w)
Character height
FD0h (w)
Row to row spacing
FD1h (r/w) OSDEN BSEN Shadow FBEN
Blend WENclr RAMclr
FD2h (r/w)
DWE
HSP
VSP
FD3h (w)
CSR
CSG
FD4h (w)
FSW
FSR
FSG
FD5h (w) WW41 WW40 WW31 WW30 WW21 WW20 WW11
FD6h (w) WH41
WH40
WH31
WH30
WH21
WH20
WH11
FD7h (w)
R1
G1
B1
R2
G2
FD8h (w)
R3
G3
B3
R4
G4
FD9h (w)
D2
D1
VF8
VF0
VBpl
Vsync
EVsync
R0
C0
D0
D0
WSHD
B
WSHD
B
WSHD
B
WSHD
B
FBKGC
CSB
FSB
WW10
WH10
B2
B4
D0
Test Mode Condition
In normal application, users should avoid the MTV230M entering its test mode, outlined as follow:
Test Mode A: RESET=1 & P5.7=1 & P5.6=0 & P5.5=1 & P5.4=0
Test Mode B: RESET's falling edge & P5.7=0 & P5.6=1 & P5.5=1 & P5.4=0
Writer Mode: RESET=1 & P5.5=0 & P5.4=1 & “special serial data on OSDVS”
Revision 1.0
- 28 -
2000/11/15
MTV230M
MYSON
TECHNOLOGY
(Rev 1.0)
ELECTRICAL PARAMETERS
1. Absolute Maximum Ratings
at: Ta= 0 to 70 oC, VSS=0V
Name
Maximum Supply Voltage
Maximum Input Voltage (except Open Drain Pin))
Maximum Input Voltage (Open Drain pin)
Maximum Operating Temperature
Symbol
VDD
Vin
Vin
Topg
Range
-0.3 to +4.0
-0.3 to VDD+0.3
6
0 to +70
Unit
V
V
V
oC
Tstg
-25 to +125
oC
Maximum Storage Temperature
2. Allowable Operating Conditions
at: Ta= 0 to 70 oC, VSS=0V
Name
Supply Voltage
Input "H" Voltage
Input "L" Voltage
Operating Freq.
Symbol
VDD
Vih
Vil
Fopg
Min.
3.0
0.7 x VDD
-0.3
-
Max.
3.6
VDD +0.3
0.25 x VDD
15
Unit
V
V
V
MHz
3. DC Characteristics
at: Ta=0 to 70 oC, VDD=5.0V, VSS=0V
Name
Symbol
Output "H" Voltage, open drain pin
Voh1
Output "H" Voltage, 8051 I/O port pin
Voh2
Output "H" Voltage, CMOS
Voh3
Output "L" Voltage
Vol
Power Supply Current
Idd
RST Pull-Down Resistor
Pin Capacitance
Rrst
Cio
Condition
Ioh=0uA
Ioh=-50uA
Ioh=-5mA
Iol=8mA
Active
Idle
Power-Down
VDD=3.3V
Min.
2.7
2.7
2.7
Condition
Min.
Typ.
18
1.3
50
100
Max.
0.4
4
4.0
80
250
15
Unit
V
V
V
V
mA
mA
uA
Kohm
pF
4. AC Characteristics
at: Ta=0 to 70 oC, VDD=5.0V, VSS=0V
Name
Symbol
Crystal Frequency
fXtal
PWM DAC Frequency
fDA
HS input pulse Width
tHIPW
VS input pulse Width
tVIPW
H+V to Vblank output delay
tVVBD
VS pulse width in H+V signal
tVCPW
SDA to SCL setup time
tDCSU
SDA to SCL hold time
tDCH
SCL high time
tSCLH
Revision 1.0
fXtal=12MHz
fXtal=12MHz
fXtal=12MHz
fXtal=12MHz
FXtal=12MHz
- 29 -
Typ.
12
46.875
0.3
3
94.86
8
8
20
200
100
500
Max.
Unit
MHz
KHz
uS
uS
uS
uS
ns
ns
ns
2000/11/15
MTV230M
MYSON
TECHNOLOGY
SCL low time
START condition setup time
START condition hold time
STOP condition setup time
STOP condition hold time
(Rev 1.0)
tSCLL
tSU:STA
tHD:STA
tSU:STO
tHD:STO
t
500
500
500
500
500
ns
ns
ns
ns
ns
SCKH
t
t
HD:STO
SCKL
t
SU:STA
t HD:STA
t DCSU
t DCH
tSU:STO
Data interface timing (I C)
2
PACKAGE DIMENSION
1. 42 pin SDIP Unit: mm
Symbol
A
A1
B1
D
E1
F
eB
θ
Dimension in mm
Min
3.937
1.78
0.914
36.78
13.945
15.19
15.24
0°
15.494mm +/0.254
13.868mm +/0.102
Nom
4.064
1.842
1.270
36.83
13.970
15.240
16.510
7.5°
Max
4.2
1.88
1.118
36.88
13.995
15.29
17.78
15°
0.254m
m
+/-0.102
5o~7
0
6o +/o
16.256mm +/- 3
0.508
Revision 1.0
- 30 -
2000/11/15
MTV230M
MYSON
TECHNOLOGY
(Rev 1.0)
2. 44 pin PLCC Unit:
PIN #1 HOLE
0.045*450
0.180 MAX.
0.020 MIN.
0.013~0.021 TYP.
0.690 +/-0.005
0.610 +/-0.02
0.653 +/-0.003
0.500
70TYP.
0.010
0.050 TYP.
0.026~0.032 TYP.
0.070
0.070
0.653 +/-0.003
0.690 +/-0.005
Ordering Information
Standard Configurations:
Prefix
MTV
Part Type
230M
Package Type
S: SDIP
V: PLCC
ROM Size (K)
Package Type
V
F
ROM Size (K)
64
64
64
Part Numbers:
Prefix
MTV
MTV
Revision 1.0
Part Type
230M
230M
- 31 -
2000/11/15