NB100LVEP17 2.5V / 3.3V Quad Differential Driver/Receiver Description The NB100LVEP17 is a 4-bit differential line receiver. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Inputs of unused gates can be left open and will not affect the operation of the rest of the device. Features • • • • • • • • • http://onsemi.com MARKING DIAGRAMS* N100 VP17 ALYWG G TSSOP−20 DT SUFFIX CASE 948E Maximum Input Clock Frequency > 2.5 GHz Typical Maximum Input Data Rate > 2.5 Gb/s Typical 250 ps Typical Propagation Delay Low Profile QFN Package PECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −2.375 V to −3.8 V Q Output Will Default LOW with Inputs Open or at VEE VBB Output Pb−Free Packages are Available 24 1 24 1 24 PIN QFN MN SUFFIX CASE 485L A L Y W G N100 VP17 ALYWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 7 1 Publication Order Number: NB100LVEP17/D NB100LVEP17 D0 R1 Q0 R2 D0 R1 D1 R1 Q0 Q1 R2 D1 R1 D2 R1 Q1 Q2 R2 D2 R1 Q2 D3 R1 Q3 VCC VEE R2 D3 R1 Q3 VBB Figure 1. Logic Diagram Table 1. PIN DESCRIPTION ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Pin TSSOP QFN Name I/O Default State 1,20 13,18,21, 22,23 VCC − − Positive Supply Voltage. All VCC Pins Must be Externally Connected to Power Supply to Guarantee Proper Operation. 11 10 VEE − − Negative Supply Voltage. All VEE Pins Must be Externally Connected to Power Supply to Guarantee Proper Operation. 10 9 VBB − − ECL Reference Voltage Output. 2,4,6,8 1,3,5,7 D[0:3] ECL Input Low Noninverted Differential Inputs [0:3]. Internal 75 k to VEE. 3,5,7,9 2,4,6,8 D[0:3] ECL Input High Inverted Differential Inputs [0:3]. Internal 75 k to VEE and 37 k to VCC. 19,17,15,13 12,15,17,2 0 Q[0:3] ECL Output − Noninverted Differential Outputs [0:3]. Typically Terminated with 50 to VTT = VCC − 2 V. 18,16,14,12 11,14,16,1 9 Q[0:3] ECL Output − Inverted Differential Outputs [0:3]. Typically Terminated with 50 to VTT = VCC − 2 V. N/A 24 NC − − No Connect. The NC Pin is Electrically Connected to the Die and “MUST BE” Left Open. N/A − EP − Description Exposed Pad. (Note 1) 1. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally conductive expose pad on the package bottom (see case drawing) must be attached to a heat−sinking conduit. http://onsemi.com 2 NB100LVEP17 NC VCC VCC VCC Q0 24 VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 20 18 17 15 14 13 19 16 Q3 VEE 12 11 NB100LVEP17 1 2 3 4 5 6 7 8 9 VCC D0 D0 D1 D1 D2 D2 D3 D3 VBB 10 23 22 21 20 19 D0 1 18 VCC D0 2 17 Q1 D1 3 16 Q1 D1 4 15 Q2 D2 5 14 Q2 D2 6 13 VCC NB100LVEP17 7 8 D3 D3 9 10 VBB VEE 11 12 Q3 Q3 Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor (R1) 75 k Internal Input Pullup Resistor (R2) 37 k Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) TSSOP−20 QFN−24 Flammability Rating Exposed Pad (EP) Figure 3. QFN−24 Lead Pinout (Top View) Figure 2. TSSOP−20 Lead Pinout (Top View) ESD Protection Q0 Oxygen Index: 28 to 34 Transistor Count > 2 kV > 150 V > 2 kV Pb Pkg Pb−Free Pkg Level 1 Level 1 Level 1 Level 1 UL 94 V−0 @ 0.125 in 274 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 3 NB100LVEP17 Table 3. MAXIMUM RATINGS Symbol Rating Unit VCC Positive Mode Power Supply Parameter VEE = 0 V Condition 1 Condition 2 6 V VEE Negative Mode Power Supply VCC = 0 V −6 V VI Positive Mode Input Voltage Negative Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source $0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C JA Thermal Resistance (Junction−to−Ambient) JEDEC 51−3 (1S − Single Layer Test Board) 0 lfpm 500 lfpm 20 TSSOP 20 TSSOP 140 50 °C/W °C/W JA Thermal Resistance (Junction−to−Ambient) JEDEC 51−6 (2S2P Multilayer Test Board) with Filled Thermal Vias 0 lfpm 500 lfpm 24 QFN 24 QFN 37 32 °C/W °C/W JC Thermal Resistance (Junction−to−Case) Standard Board 20 TSSOP 24 QFN 23 to 41 11 °C/W °C/W Tsol Wave Solder 265 265 °C VI v VCC VI w VEE Pb Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 4. DC CHARACTERISTICS, PECL VCC = 2.5 V; VEE = 0 V (Note 2) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 30 40 50 30 40 50 30 40 55 mA 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV 775 775 775 IEE Negative Power Supply Current VOH Output HIGH Voltage (Note 3) VOL Output LOW Voltage (Note 3) 555 900 555 900 555 900 mV VIH Input HIGH Voltage (Single−Ended) (Note 4) 1335 1620 1335 1620 1275 1620 mV VIL Input LOW Voltage (Single−Ended) (Note 4) 555 875 555 875 555 875 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 5) 1.2 2.5 1.2 2.5 1.2 2.5 V IIH Input HIGH Current (@ VIH) 150 A IIL Input LOW Current (@ VIL) 150 D D 0.5 −150 150 0.5 −150 0.5 −150 A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary −0.125 V to +1.3 V. 3. All loading with 50 to VEE = VCC − 2.0 V. 4. Do not use VBB at VCC < 3.0 V. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 NB100LVEP17 Table 5. DC CHARACTERISTICS, PECL VCC = 3.3 V; VEE = 0 V (Note 6) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 30 40 50 30 40 50 30 40 55 mA IEE Negative Power Supply Current VOH Output HIGH Voltage (Note 7) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 7) 1355 1575 1700 1355 1575 1700 1355 1575 1700 mV VIH Input HIGH Voltage (Single−Ended) 2135 2420 2135 2420 2135 2420 mV VIL Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV VBB ECL Output Reference Voltage (Note 8) 1775 1975 1775 1975 1775 1975 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 9) 3.3 1.2 3.3 1.2 3.3 V IIH Input HIGH Current (@ VIH) 150 A IIL Input LOW Current (@ VIL) 1875 1.2 1875 150 D D 0.5 −150 1875 150 0.5 −150 0.5 −150 A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.5 V to −0.3 V. 7. All loading with 50 to VCC − 2.0 V. 8. Single ended input operation is limited VCC ≥ 3.0 V in PECL mode. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 6. DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −2.375 V to −3.8 V (Note 10) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit IEE Negative Power Supply Current 30 40 50 30 40 50 30 40 55 mA VOH Output HIGH Voltage (Note 11) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 11) −1945 −1725 −1600 −1945 −1725 −1600 −1945 −1725 −1600 mV VIH Input HIGH Voltage (Single−Ended) −1165 −880 −1165 −880 −1165 −880 mV VIL Input LOW Voltage (Single−Ended) −1945 −1600 −1945 −1600 −1945 −1600 mV VBB ECL Output Reference Voltage (Note 12) −1525 −1325 −1525 −1325 −1525 −1325 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 13) 0.0 V IIH Input HIGH Current (@ VIH) 150 A IIL Input LOW Current (@ VIL) −1425 VEE + 1.2 0.0 VEE + 1.2 150 D D 0.5 −150 −1425 0.0 VEE + 1.2 150 0.5 −150 −1425 0.5 −150 A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Input and output parameters vary 1:1 with VCC. 11. All loading with 50 to VCC − 2.0 V. 12. Single ended input operation is limited VEE ≤ −3.0V in NECL mode. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 5 NB100LVEP17 Table 7. AC CHARACTERISTICS VCC = 0 V; VEE = −2.375 V to −3.8 V or VCC = 2.375 V to 3.8 V; VEE = 0 V (Note 14) −40°C Symbol 25°C Min Typ fin < 1 GHz fin = 2 GHz fin = 2.5 GHz 600 400 300 700 500 400 D to Q, Q 200 250 325 5 5 25 Characteristic VOUTPP Output Voltage Amplitude (See Figures 4, 5) tPLH, tPHL Propagation Delay to Output Differential tSkew Pulse Skew (Note 15) Within Device Skew (Note 17) Device−to−Device Skew (Note 17) tJITTER RMS Random Clock Jitter (Note 18) Peak−to Peak Data Dependent Jitter (Note 19) VINPP Input Voltage Swing (Differential Configuration) (Note 20) tr tf Output Rise/Fall Times @ 50 MHz (20% − 80%) Q, Q 85°C Min Typ 600 325 250 700 500 400 200 250 325 25 25 100 5 5 25 0.5 5 5 1 15 15 150 800 1200 125 175 225 fin = 2.5 GHz fin = 1.5 Gb/s fin = 2.5 Gb/s Max Max Min Typ Max 550 300 200 700 500 400 225 300 350 25 25 100 5 5 25 25 25 100 ps 0.5 5 5 1 15 15 0.5 5 5 1 15 15 ps 150 800 1200 150 800 1200 mV 140 190 240 150 200 250 Unit mV ps ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC − 2.0 V. Input edge rates 150 ps (20% − 80%). 15. Pulse Skew = |tPLH − tPHL| 16. Worst case difference between Q0 and Q1 outputs. 17. Skew is measured between outputs under identical transitions. 18. Additive RMS jitter with 50% Duty Cycle Clock Signal at 2.5 GHz. 19. Peak−to−Peak jitter with input NRZ data at PRBS 231−1 at 2.5 Gb/s with all inputs active. 20. Input voltage swing is a single−ended measurement operating in differential mode, with minimum propagation change of 50 ps. http://onsemi.com 6 NB100LVEP17 10 9.0 750 8.0 Q AMP (mV) 7.0 650 6.0 550 5.0 4.0 450 3.0 2.0 350 250 RMS JITTER (ps) OUTPUT VOLTAGE AMPLITUDE (mV) 850 RMS JITTER (ps) 0.5 1.0 1.5 2.0 2.5 1.0 0 INPUT FREQUENCY (GHz) 10 850 9.0 750 8.0 Q AMP (mV) 7.0 650 6.0 550 5.0 4.0 450 3.0 2.0 350 250 RMS JITTER (ps) OUTPUT VOLTAGE AMPLITUDE (mV) Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at VCC = 2.5 V, Ambient Temperature RMS JITTER (ps) 0.5 1.0 1.5 2.0 2.5 1.0 0 INPUT FREQUENCY (GHz) Figure 5. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at VCC = 3.3 V, Ambient Temperature D VINPP = VIH(D) − VIL(D) D Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 6. AC Reference Measurement http://onsemi.com 7 NB100LVEP17 Q Zo = 50 D Receiver Device Driver Device Q D Zo = 50 50 50 VTT VTT = VCC − 2.0 V Figure 7. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device Package Shipping† NB100LVEP17DT TSSOP−20* 75 Units / Rail NB100LVEP17DTG TSSOP−20* 75 Units / Rail NB100LVEP17DTR2 TSSOP−20* 2500 Tape & Reel NB100LVEP17DTR2G TSSOP−20* 2500 Tape & Reel QFN−24 92 Units / Rail NB100LVEP17MNG QFN−24 (Pb−Free) 92 Units / Rail NB100LVEP17MNR2 QFN−24 3000 Tape & Reel QFN−24 (Pb−Free) 3000 Tape & Reel NB100LVEP17MN NB100LVEP17MNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *This package is inherently Pb−Free. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 8 NB100LVEP17 PACKAGE DIMENSIONS TSSOP−20 CASE 948E−02 ISSUE C 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V K K1 S ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ J J1 11 B −U− PIN 1 IDENT SECTION N−N 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING DIM A B C D F G H J J1 K K1 L M PLANE SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 9 MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ NB100LVEP17 PACKAGE DIMENSIONS QFN 24 MN SUFFIX 24 PIN QFN, 4x4 CASE 485L−01 ISSUE O D A PIN 1 IDENTIFICATION NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. B E DIM A A1 A2 A3 b D D2 E E2 e L 2X 0.15 C 0.15 C 2X A2 0.10 C A 0.08 C A3 A1 SEATING PLANE REF D2 C e L 7 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.60 0.80 0.20 REF 0.23 0.28 4.00 BSC 2.70 2.90 4.00 BSC 2.70 2.90 0.50 BSC 0.35 0.45 12 6 13 E2 24X b 1 0.10 C A B 18 24 19 e 0.05 C ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 10 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB100LVEP17/D