NB4N121K 3.3V Differential In 1:21 Differential Fanout Clock Driver with HCSL level Output http://onsemi.com Description The NB4N121K is a Clock differential input fanout distribution 1 to 21 HCSL level differential outputs, optimized for ultra low propagation delay variation. The NB4N121K is designed with HCSL clock distribution for FBDIMM applications in mind. Inputs can accept differential LVPECL, CML, or LVDS levels. Single-ended LVPECL, CML, LVCMOS or LVTTL levels are accepted with the proper VREFAC supply (see Figures 5, 10, 11, 12, and 13). Clock input pins incorporate an internal 50 W on die termination resistors. Output drive current at IREF (Pin 1) for 1X load is selected by connecting to GND. To drive a 2X load, connect IREF to VCC. See Figure 9. The NB4N121K specifically guarantees low output–to–output skews. Optimal design, layout, and processing minimize skew within a device and from device to device. System designers can take advantage of the NB4N121K's performance to distribute low skew clocks across the backplane or the motherboard. QFN-52 MN SUFFIX CASE 485M 1 52 MARKING DIAGRAM* 52 1 NB4N 121K AWLYYWWG A WL YY WW G Features •Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and = Assembly Site = Wafer Lot = Year = Work Week = Pb-Free Package 400 MHz •340 ps Typical Rise and Fall Times •800 ps Typical Propagation Delay •Dtpd 100 ps Maximum Propagation Delay Variation Per Each Differential Pair •<1 ps RMS Additive Clock jitter •Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V •Differential HCSL Output Level (700 mV Peak-to-Peak) •Pb-Free Packages are Available* *For additional marking information, refer to Application Note AND8002/D. Q0 Q0 VTCLK Q1 Q1 CLK CLK Q19 Q19 VTCLK Q20 VCC GND *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. RREF IREF Q20 Figure 1. Pin Configuration (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. © Semiconductor Components Industries, LLC, 2007 June, 2007 - Rev. 0 1 Publication Order Number: NB4N121K/D VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 52 51 50 49 48 47 46 45 44 43 42 41 40 NB4N121K Exposed Pad (EP) IREF 1 39 VCC GND 2 38 Q6 VTCLK 3 37 Q6 CLK 4 36 Q7 CLK 5 35 Q7 VTCLK 6 34 Q8 VCC 7 33 Q8 Q20 8 32 Q9 Q20 9 31 Q9 Q19 10 30 Q10 Q19 11 29 Q10 Q18 12 28 Q11 Q18 13 27 Q11 18 19 20 21 22 23 24 25 Q15 Q15 Q14 Q14 Q13 Q13 Q12 Q12 26 17 Q16 VCC 16 15 Q17 Q16 14 Q17 NB4N121K Figure 2. Pinout Configuration (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 IREF Output 2 GND - Supply Ground. GND pin must be externally connected to power supply to guarantee proper operation. 3, 6 VTCLK, VTCLK - Internal 50 W Termination Resistor connection Pins. In the differential configuration when the input termination pins are connected to the com‐ mon termination voltage, and if no signal is applied then the device may be susceptible to self-oscillation. 4 CLK LVPECL Input CLOCK Input (TRUE) 5 CLK LVPECL Input CLOCK Input (INVERT) 7, 26, 39, 52 VCC - 8, 10, 12, 14, 16, 18, 20, 22, 24, 27, 29, 31, 33, 35, 37, 40, 42, 44, 46, 48, 50 Q[20-0] HCSL Output Output (INVERT) 9, 11, 13, 15, 17, 19, 21, 23, 25, 28, 30, 32, 34, 36, 38, 41, 43, 45, 47, 49, 51 Q[20-0] HCSL Output Output (TRUE) Exposed Pad EP GND Output current programming pin to select load drive. For 1X configuration, connect IREF to GND, or for 2X configuration, connect IREF to VCC (See Figure 9). Positive Supply pins. VCC pins must be externally connected to a power supply to guarantee proper operation. Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a sufficient heat-sinking conduit for proper thermal operation. (Note 1) 1. The exposed pad must be connected to the circuit board ground. http://onsemi.com 2 NB4N121K Table 2. ATTRIBUTES Characteristic Value Input Default State Resistors None ESD Protection Human Body Model Moisture Sensitivity (Note 2) >2 kV QFN-52 Flammability Rating Oxygen Index: 28 to 34 Level 3 UL 94 V-0 @ 0.125 in Transistor Count 622 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS (Note 3) Symbol Parameter Condition 1 Rating Unit GND = 0 V 6 V GND = 0 V GND - 0.3 v VI v VCC V 1.2 V 50 100 mA mA VCC Positive Power Supply VI Positive Input VINPP Differential Input Voltage IOUT Output Current Continuous Surge TA Operating Temperature Range QFN-52 Tstg Storage Temperature Range qJA Thermal Resistance (Junction-to-Ambient) (Note 3) 0 lfpm 500 lfpm qJC Thermal Resistance (Junction-to-Case) 2S2P (Note 4) Tsol Wave Solder Condition 2 |CLK - CLKb| Pb-Free -40 to +70 °C -65 to +150 °C QFN-52 QFN-52 25 19.6 °C/W °C/W QFN-52 21 °C/W 265 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard 51-6, multilayer board - 2S2P (2 signal, 2 power). 4. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB4N121K Table 4. DC CHARACTERISTICS (VCC = 3.0 V to 3.6 V, TA = -40°C to +70°C Note 5) Symbol Characteristic IGND GND Supply Current (All Outputs Loaded) ICC Power Supply Current (All Outputs Loaded) IIH Input HIGH Current CLKx, CLKx IIL Input LOW Current CLKx, CLKx Min Typ Max Unit 70 98 120 mA 1X 2X 420 780 2.0 -150 mA 150 mA mA -2.0 DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (Figures 5 and 7) Vth Input Threshold Reference Voltage Range (Note 6) VIH VIL 1050 VCC - 150 mV Single-Ended Input HIGH Voltage Vth + 150 VCC mV Single-Ended Input LOW Voltage GND Vth - 150 mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 6 and 8) VIHD Differential Input HIGH Voltage 1200 VCC mV VILD Differential Input LOW Voltage GND VCC - 75 mV VID Differential Input Voltage (VIHD - VILD) 75 2400 mV VCMR Input Common Mode Range 1163 VCC - 75 HCSL OUTPUTS (Figure 4) VOH Output HIGH Voltage 600 740 900 mV VOL Output LOW Voltage -150 0 150 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input parameters vary 1:1 with VCC. Measurements taken with outputs in either 1X (all outputs loaded 50 W to GND) or 2X (all outputs loaded 25 W to GND) configuration, see Figure 9. For 1X configuration, connect IREF to GND, or for 2X configuration, connect IREF to VCC. 6. Vth is applied to the complementary input when operating in single ended mode. http://onsemi.com 4 NB4N121K Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; -40°C to +70°C (Note 7) Symbol Characteristic Typ Max Unit 725 725 725 900 900 900 mV 800 950 ps Propagation Delay Variations Variation Per Each Diff Pair CLK/CLK to Qx/Qx (Note 8) (See Figure 3) 100 ps tSKEW Duty Cycle Skew (Note 9) Within-Device Skew, 1X Mode Only (Note 10) Within-Device Skew, 2X Mode (Note 10) Device-to-Device Skew (Note 10) 20 50 80 150 ps ps ps ps tJITTER RMS Random Clock Jitter (Note 11) 1 ps VINPP Input Voltage Swing/Sensitivity (Differential Configuration) 150 1200 mV Vcross Absolute Crossing Magnitude Voltage 250 550 mV DVcross Variation in Magnitude of Vcross 150 mV tr, tf Absolute Magnitude in Output Risetime and Falltime (From 175 mV to 525 mV) Qx, Qx 700 ps Dtr, Dtf Variation in Magnitude of Risetime and Falltime (Single-Ended) (See Figure 4) Qx, Qx VOUTPP Output Voltage Amplitude (@ VINPPmin) tPLH, tPHL Propagation Delay to (See Figure 3) DtPLH, DtPHL Min fin = 133 MHz fin = 166 MHz fin = 200 MHz CLK/CLK to Qx/Qx 550 fin =133 MHz fin = 166 MHz fin = 200 MHz 175 340 1X 2X ps 125 150 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. Measurements taken with outputs in either 1X (all outputs loaded 50 W to GND) or 2X (all outputs loaded 25 W to GND) configuration, see Figure 9. For 1X configuration, connect IREF to GND, or for 2X configuration, connect IREF to VCC. Typical gain is 20 dB. 8. Measured from the input pair crosspoint to each single output pair crosspoint across temp and voltage ranges. 9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw- and Tpw+. 10. Skew is measured between outputs under identical transition @ 133 MHz. 11. Additive RMS jitter with 50% duty cycle clock signal using phase noise integrated from 12 KHz to 33 MHz CLK VINPP = VIH(CLK) - VIL(CLK) = VIH(CLK) - VIL(CLK) CLK tPLH tPHL Q VOUTPP = VOH(Q) - VOL(Q) = VOH(Q) - VOL(Q) Q DtPLH DtPHL Figure 3. AC Reference Measurement http://onsemi.com 5 NB4N121K 525 mV DVCROSS VCROSS 175 mV tr tf Figure 4. HCSL Output Parameter Characteristics CLK CLK CLK CLK Vth Vth Figure 5. Differential Input Driven Single-Ended (Vth = VREFAC) VCC Vthmax Figure 6. Differential Inputs Driven Differentially VCC VCMmax VIHmax Vth Vthmin GND VIH Vth VIL VIHDmax VILDmax VID = VIHD - VILD VIHDtyp VILmax VCMR VILDtyp VIHmin VCMmin VILmin GND Figure 7. Vth Diagram VIHDmin VILDmin Figure 8. VCMR Diagram http://onsemi.com 6 NB4N121K RS1C Qx 1X Load Z0 = 50 W Receiver HCSL Driver RS2C Z0 = 50 W Qx RL1B 50 RL2B 50 CL1D 2 pF CL2D 2 pF RREFA 2X Load Option A. For 1X configuration, connect IREF pin to GND or for 2X configuration, connect IREF pin to VCC. To adjust load drive for 1X configuration, use RREF from 0 W to 1 kW, to adjust 2X load, use 20 kW to 50 kW. B. RL1, RL2: 50 W for 1X Load 25 W for 2X Load C. RS1, RS2: 0 W for Test and Evaluation. Select to Minimizing Ringing. D. CL1, CL2, CL3, CL4: Receiver Input Simulation Load Capacitance Only Receiver 2 CL3D 2 pF CL4D 2 pF Figure 9. Typical Termination Configuration for Output Driver and Device Evaluation CLx for Test Only (Representing Receiver Input Loading); Not Added to Application VCC = 3.3 V VCC = 3.3 V Z0 = 50 W LVPECL Driver VCC = 3.3 V Z0 = 50 W NB4N121K D 50 W* VTD LVDS Driver VTD Z0 = 50 W 50 W* D NB4N121K D 50 W* VTD VTD Z0 = 50 W VTD = VTD = VCC - 2.0 V GND VCC = 3.3 V 50 W* D VTD = VTD GND GND GND *RTIN, Internal Input Termination Resistor *RTIN, Internal Input Termination Resistor Figure 10. LVPECL Interface Figure 11. LVDS Interface http://onsemi.com 7 NB4N121K VCC VCC Z0 = 50 W VCC CML Driver VCC Z0 = 50 W NB4N121K D 50 W* VTD 50 W* D NB4N121K D 50 W* VTD LVCMOS/‐ LVTTL Driver VTD Z0 = 50 W VCC VTD 50 W* D 1.5 kW** VTD = VTD = VCC GND GND GND GND GND VTD = OPEN D = GND *RTIN, Internal Input Termination Resistor *RTIN, Internal Input Termination Resistor **or VREFAC Figure 12. Standard 50 W Load CML Interface Figure 13. LVCMOS/LVTTL Interface VCC VDR INTQb INTQ Q Qb Figure 14. HCSL Output Structure http://onsemi.com 8 NB4N121K ORDERING INFORMATION Package Shipping† QFN-52 260 Units / Tray NB4N121KMNG QFN-52 (Pb-Free) 260 Units / Tray NB4N121KMNR2 QFN-52 2000 / Tape & Reel QFN-52 (Pb-Free) 2000 / Tape & Reel Device NB4N121KMN NB4N121KMNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 9 NB4N121K PACKAGE DIMENSIONS 52 PIN QFN 8x8 CASE 485M-01 ISSUE A D A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. B E DIM A A1 A2 A3 b D D2 E E2 e K L 2X 0.15 C 2X 0.15 C A2 0.10 C A 0.08 C A3 A1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.60 0.80 0.20 REF 0.18 0.30 8.00 BSC 6.50 6.80 8.00 BSC 6.50 6.80 0.50 BSC 0.20 --0.30 0.50 REF SEATING PLANE C D2 14 26 27 13 52 X L E2 39 1 52 X K 52 40 e 52 X b NOTE 3 0.10 C A B 0.05 C ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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