ETC NC7WZ241P8X

Revised March 2001
NC7WZ241
TinyLogic UHS Dual Buffer with 3-STATE Outputs
General Description
Features
The NC7WZ241 is a Dual Non-Inverting Buffer with
3-STATE outputs. The output enable circuitry is organized
as active LOW for one buffer and active HIGH for the other
buffer, thus facilitating transceiver operation.
■ Space saving US8 surface mount package
The Ultra High Speed device is fabricated with advanced
CMOS technology to achieve superior switching performance with high output drive while maintaining low static
power dissipation over a broad VCC operating range. The
device is specified to operate over the 1.65V to 5.5V VCC
operating range. The inputs and outputs are high impedance when VCC is 0V. Inputs tolerate voltages up to 5.5V
independent of VCC operating range. Outputs tolerate voltages above VCC when in the 3-STATE condition.
■ Broad VCC Operating Range; 1.65V to 5.5V
■ Ultra High Speed; tPD 2.6 ns Typ into 50 pF at 5V VCC
■ High Output Drive; ±24 mA at 3V VCC
■ Matches the performance of LCX when operated at
3.3V VCC
■ Power down high impedance inputs/outputs
■ Overvoltage tolerant inputs facilitate 5V to 3V
translation
■ Outputs are overvoltage tolerant in 3-STATE mode
■ Patented noise/EMI reduction circuitry implemented
Ordering Code:
Order
Package
Package
Number
Number
Top Mark
MAB08A
WZ41
NC7WZ241P8X
Package Description
Supplied As
8-Lead US8, 0.7mm x 3.1mm x 2.0mm
Logic Symbol
3k Units on Tape and Reel
Connection Diagram
(Top View)
Pin Descriptions
Function Table
Pin Names
Description
Inputs
Output
OE, OE
Enable Inputs for 3-STATE Outputs
OE or OE
An
Y1
An
Inputs
L
L
L
Z
Yn
3-STATE Outputs
L
H
H
Z
H
L
Z
L
H
H
Z
H
Y2
H = HIGH Logic Level
L = LOW Logic Level
Z = 3-STATE
TinyLogic is a trademark of Fairchild Semiconductor Corporation.
© 2001 Fairchild Semiconductor Corporation
DS500399
www.fairchildsemi.com
NC7WZ241 TinyLogic UHS Dual Buffer with 3-STATE Outputs
March 2001
NC7WZ241
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 3)
Supply Voltage (VCC )
−0.5V to +7.0V
DC Input Voltage (VIN) (Note 2)
−0.5V to +7.0V
Supply Voltage Operating (VCC)
DC Output Voltage (VOUT)
−0.5V to +7.0V
Supply Voltage Data Retention (VCC)
DC Input Diode Current (IIK)
1.65V to 5.5V
1.5V to 5.5V
Input Voltage (VIN)
@VIN < 0V
−50 mA
DC Output Diode Current (IOK)
@VOUT < 0V
−50 mA
±50 mA
DC Output Source/Sink Current (IOUT)
+150 °C
Junction Lead Temperature (TL)
+260 °C
(Soldering, 10 seconds)
0V to VCC
0V to 5.5V
−40°C to +85°C
Input Rise and Fall Time (tr, tf)
−65°C to +150 °C
Storage Temperature Range (TSTG)
Junction Temperature under Bias (TJ)
Active State
3-State
Operating Temperature (TA)
±100 mA
DC VCC/GND Current (ICC/IGND)
0V to 5.5V
Output Voltage (VOUT)
VCC = 1.8V, 0.15V, 2.5V ± 0.2V
0 ns/V to 20 ns/V
VCC = 3.8V ± 0.3V
0 ns/V to 10 ns/V
VCC = 5.0V ± 0.5V
0 ns/V to 5 ns/V
Thermal Resistance (θJA)
Power Dissipation (PD) @+85°C
250°C/W
SC70-6
SC70-6
250 mW
Note 1: Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. The datasheet specifications should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside datasheet specifications.
Note 2: The input and output negative voltage ratings may be exceeded is
the input and output diode current ratings are observed.
Note 3: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
VIH
Parameter
HIGH Level Input Voltage
.
VIL
LOW Level Input Voltage
VOH
HIGH Level Output Voltage
TA = +25°C
VCC
(V)
Min
Typ
1.65-1.95 0.75 VCC
2.3-5.5
LOW Level Output Voltage
IIN
Input Leakage Current
IOZ
3-STATE Output Leakage
IOFF
Power Off Leakage Current
ICC
Quiescent Supply Current
Min
Max
0.75 VCC
1.65-1.95
0.25 VCC
0.25 VCC
0.3 VCC
0.3 VCC
Unit
Conditions
V
0.7 VCC
0.7 VCC
2.3-5.5
VOL
TA = −40°C to +85°C
Max
V
1.65
1.55
1.65
1.55
2.3
2.2
2.3
2.2
3.0
2.9
3.0
2.9
4.5
4.4
4.5
4.4
1.65
1.29
1.52
1.29
IOH = −4 mA
2.3
1.9
2.15
1.9
VIN = VIH IOH = −8 mA
3.0
2.4
2.80
2.4
3.0
2.3
3.68
2.3
4.5
3.8
4.20
1.65
V
V
VIN = VIH IOH = −100 µA
or VIL
or VIL
IOH = −32 mA
3.8
0.0
0.10
IOH = −16 mA
IOH = −24 mA
0.10
2.3
0.0
0.10
0.10
3.0
0.0
0.10
0.10
V
VIN = VIH IOL = 100 µA
or VIL
4.5
0.0
0.10
0.10
1.65
0.08
0.24
0.24
IOL = 4 mA
2.3
0.10
0.3
0.3
VIN = VIH IOL = 8 mA
3.0
0.15
0.4
0.4
3.0
0.22
0.55
0.55
4.5
0.22
V
or VIL
IOL = 16 mA
IOL = 24 mA
IOL = 32 mA
0.55
0.55
0-5.5
±0.1
±1
µA
VIN = 5.5V, GND
1.65-5.5
±0.5
±5
µA
VIN = VIH or VIL
0.0
1
10
µA
VIN or VOUT = 5.5V
1.65-5.5
1
10
µA
VIN = 5.5V, GND
0 ≤ VOUT ≤ 5.5V
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2
NC7WZ241
Noise Characteristics
Symbol
TA = +25°C
VCC
Parameter
Units
Conditions
VOLP (Note 4)
Quiet Output Maximum Dynamic VOL
5.0
1.0
V
CL = 50 pF
VOLV (Note 4)
Quiet Output Minimum Dynamic VOL
5.0
1.0
V
CL = 50 pF
VOHV (Note 4)
Quiet Output Minimum Dynamic VOH
5.0
4.0
V
CL = 50 pF
VIHD (Note 4)
Minimum HIGH Level Dynamic Input Voltage
5.0
3.5
V
CL = 50 pF
VILD (Note 4)
Maximum LOW Level Dynamic Input Voltage
5.0
1.5
V
CL = 50 pF
(V)
Typ
Max
Note 4: Parameter guaranteed by design.
AC Electrical Characteristics
Symbol
Parameter
TA = +25°C
VCC
(V)
Min
TA = −40°C to +85°C
Typ
Max
Min
Max
tPLH
Propagation Delay
1.8 ± 0.15
2.0
12.0
2.0
13.0
tPHL
An to Yn
2.5 ± 0.2
1.0
7.5
1.0
8.0
3.3 ± 0.3
0.8
5.2
0.8
5.5
4.8
5.0 ± 0.5
0.5
4.5
0.5
tPLH
Propagation Delay
3.3 ± 0.3
1.2
5.7
1.2
6.0
tPHL
An to Yn
5.0 ± 0.5
0.8
5.0
0.8
5.3
tOSLH
Output to Output Skew
3.3 ± 0.3
1.0
1.0
tOSHL
(Note 5)
5.0 ± 0.5
0.8
0.8
Units
Conditions
CL = 15 pF
ns
RD = 1 MΩ
S1 = OPEN
CL = 50 pF
ns
RD = 500Ω
S1 = OPEN
CL = 50 pF
ns
RD = 500Ω
S1 = OPEN
tPZL
Output Enable Time
tPZH
1.8 ± 0.15
3.0
14.0
3.0
15.0
2.5 ± 0.2
1.8
8.5
1.8
9.0
3.3 ± 0.3
1.2
6.2
1.2
6.5
5.0 ± 0.5
0.8
5.5
0.8
5.8
1.8 ± 0.15
2.5
12.0
2.5
13.0
2.5 ± 0.2
1.5
8.0
1.5
8.5
3.3 ± 0.3
0.8
5.7
0.8
6.0
5.0 ± 0.5
0.3
4.7
0.3
5.0
Figure
Number
Figures
1, 3
Figures
1, 3
Figures
1, 3
CL = 50 pF
RD, RU = 500Ω
ns
S1 = GND for tPZH
S1 = VI for tPZL
Figures
1, 3
VI = 2 × VCC
tPLZ
Output Disable Time
tPHZ
CL = 50 pF
RD, RU = 500Ω
ns
S1 = GND for tPHZ
S1 = VI for tPLZ
Figures
1, 3
VI = 2 × VCC
CIN
Input Capacitance
COUT
Output Capacitance
CPD
0
2.5
5.0
4
Power Dissipation
3.3
10
Capacitance (Note 6)
5.0
12
pF
pF
OE = GND
OE = VCC
Figure 2
Note 5: Parameter guaranteed by design. tOSLH = | tPLHmax − tPLHmin | ; tOSHL = | tPHLmax − tPHLmin |.
Note 6: CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at no output
loading and operating at 50% duty cycle. (See Figure 2.) CPD is related to ICCD dynamic operating current by the expression:
ICCD = (CPD) (V CC) (fIN) + (ICC static).
3
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NC7WZ241
AC Loading and Waveforms
CL includes load and stray capacitance
Input PRR = 1.0 MHz, tw = 500 ns
FIGURE 1. AC Test Circuit
Input = AC Waveform; tr = tf = 1.8 ns;
PRR = 10 MHz; Duty Cycle = 50%
FIGURE 2. ICCD Test Circuit
FIGURE 3. AC Waveforms
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TAPE FORMAT
Package
Designator
Tape
Number
Cavity
Section
Cavities
Status
Status
125 (typ)
Empty
Sealed
3000
Filled
Sealed
75 (typ)
Empty
Sealed
Leader (Start End)
K8X
Carrier
Trailer (Hub End)
Cover Tape
TAPE DIMENSIONS inches (millimeters)
REEL DIMENSIONS inches (millimeters)
Tape
Size
8 mm
A
B
C
D
N
W1
W2
W3
7.0
0.059
0.512
0.795
2.165
0.331 + 0.059/−0.000
0.567
W1 + 0.078/−0.039
(177.8)
(1.50)
(13.00)
(20.20)
(55.00)
(8.40 + 1.50/−0.00)
(14.40)
(W1 + 2.00/−1.00)
5
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NC7WZ241
Tape and Reel Specification
NC7WZ241 TinyLogic UHS Dual Buffer with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead US8, 0.7mm x 3.1mm x 2.0mm
Package Number MAB08A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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