NCN6000 Product Preview Compact Smart Card Interface IC The NCN6000 is an integrated circuit dedicated to the smart card interface applications. The device handles any type of smart card through a simple and flexible microcontroller interface. On top of that, thanks to the built–in chip select pin, several couplers can be connected in parallel. The device is particularly suited for low cost, low power applications, with high extended battery life coming from extremely low quiescent current. http://onsemi.com MARKING DIAGRAM 20 Features • 100% Compatible with ISO 7816–3 and EMV Standard • Wide Battery Supply Voltage Range: 2.7 < Vbat < 6.0 V • Programmable Vcc Supply to Cope with either 3.0 V or 5.0 V Card TSSOP–20 TBD CASE 948E 20 1 TBD 1 Operation • Built–in DC/DC Converter Generates the Vcc Supply with a Single • • • • • • • External Low Cost Inductor only, providing a High Efficiency Power Conversion Full Control of the Power Up/Down Sequence Yields High Signal Integrity on both the Card I/O and the Signal Lines Programmable Card Clock Generator Built–in Chip Select Logic allows Parallel Coupling Operation ESD Protection on Card Pins (4.0 kV, Human Body Model) Fault Monitoring includes Vbatlow and Vcclow, providing Logic Feedback to External CPU Card Detection Programmable to Handle Positive or Negative Going Input Built–in Programmable CRD_CLK Stop Function Handle both High or Low State Typical Application • E–Commerce Interface • ATM Smart Card • Pay TV System A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week PIN CONNECTIONS A0 1 20 Vbat A1 2 19 Lout_H PGM 3 18 Lout_L PWR_ON 4 17 PWR_GND STATUS 5 16 GROUND CS 6 15 CRD_VCC RESET 7 14 CRD_IO I/O 8 13 CRD_CLK INT 9 12 CRD_RST CLOCK_IN 10 11 CRD_DET (Top View) ORDERING INFORMATION Device NCN6000 Package Shipping TSSOP–20 TBD This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2000 November, 2000 – Rev. 0 1 Publication Order Number: NCN6000/D NCN6000 +5 V PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 2 3 4 5 6 7 8 9 IRQ 10 MCU 20 A0 Vbat A1 Lout_H PGM Lout_L PWR_ON PWR_GND STATUS GROUND CS CRD_VCC RESET 10 µF C1 U? 1 CRD_IO I/O CRD_CLK INT CRD_RST XTAL CLOCK_IN CRD_DET GND NCN6000 GND 19 L1 18 22 µF 17 16 GND 15 C2 10 µF C3 100 nF 14 13 GND 17 18 12 8 11 4 3 2 1 GND GND 5 7 Swb C8 C4 CLK RST VCC GND I/O VPP J1 SMARTCARD Figure 1. Typical Application http://onsemi.com 2 GND GND Swa ISO7816 VCC NCN6000 +Vbat + - Vbat_OK 20 Vbat 2.0 V 50 k INT 9 500 k Vbat GND 11 Q R GND +Vbat CARD DETECTION POLARITY PROGRAMMABLE 50 k CS CRD_DET 50 µs Delay S STATUS INT 6 CLK STOP PGM 3 A1 2 A0 1 Fout DC/DC CONVERTER DATA SELECT DECODER 1:16 3V/5V 1/1 1/2 1/4 1/8 CLOCK DIVIDER 15 CRD_VCC Power Down Active Pwr_Down Set_VCC CLOCK_IN 10 VCC CLOCK 19 Lout_H GND FAULT 18 Lout_L ON/OFF 17 PWR_GND STATUS INT DC/DC STATUS ENABLE VCC CARD STATUS PWR_ON 4 16 GROUND LOGIC & CARD PINS SEQUENCER SEQ 3 50 k SEQ 2 SEQ 1 Vbat STATUS GND Vbat Vbat_OK CLOCK CLK_STOP 5 VCC CLOCK 13 CRD_CLK SEQ 2 2 A GND Vbat 1 20 k Vbat_OK I/O 20 k SEQ 1 8 I/O DATA DATA 14 CRD_IO I/O 1 RESET 7 2 Vbat 3 SEQ 3 PWR_ON Figure 2. Block Diagram http://onsemi.com 3 RESET 12 CRD_RST CARD PRESENT NO CARD DC/DC OK DC/DC OVERLOADED STATUS Program Chip Normal Chip Operation PGM RESET A1 A0 I/O CS STATUS PGM RESET A1 1 – L L L I/O L L 3 V CLOCK_IN 1/1 H 3 V CLOCK_IN 1/2 3 V CLOCK_IN 1/4 2 – L L L L 3 – L L L H L 4 – L L L H H 5 – L L H L L 3 V CLOCK_IN 1/8 5 V CLOCK_IN 1/1 6 – L L H L H 5 V CLOCK_IN 1/2 7 – L L H H L 5 V CLOCK_IN 1/4 8 – L L H H H 9 – L H L L L 5 V CLOCK_IN 1/8 ENABLE CRD_CLK 10 – L H L L H 11 – L H L H L STOP CRD_CLKLow STOP CRD_CLKHigh 12 – L H L H H Reserved 13 – L H H L L CRD_DET = NormallyOpen 14 – L H H L H CRD_DET = Normally Close 15 – L H H H L CRD_DET = Normally Close 16 – L H H H H 17 H/L H Z L L Z CRD_DET = Normally Close Read STATUS = 1 > Card Present/ = 0 > No Card 18 H/L H Z L H Z 19 H H Z H L Z 20 H H Z H H Z Read STATUS = 1 DC/DCOK/ = 0 > DC/DC Overloaded Read Vbat status–> Low = Battery Low Voltage Read CRD_VCC status–> Low = CRD_VCCLow Voltage Figure 3. Programming and Normal Operation Basic Timing NCN6000 4 http://onsemi.com A0 NCN6000 table in Figure 3. During the programming mode, the PGM pin can be released to High since the mode is internally latched by the Negative going transition presents on the Chip Select pin. The programming can be achieved with the card powered ON or OFF. The identification of the interrupt is carried out by polling the STATUS pin, the Vbat voltage and the DC/DC results being provided on the same pin as depicted by the INTERRUPT ACKNOWLEDGE CARD IDENTIFICATION POLLING 50 µs CARD EXTRACTED 50 µs CRD_DET INT CS PGM High A0 Low A1 Low STATUS S1 CLEAR INTERRUPT S2 CARD PRESENT: STATUS = 1 S3 CLEAR INTERRUPT S4 CARD PRESENT: STATUS = 0 Figure 4. Interrupt Servicing and Card Polling otherwise a Low is presented pin 5. The 50 µs digital filter is activated during both Insertion and Extraction of the card. The MPU shall clear the INT line when the card has been extracted, making the interrupt function available for other purposes. However, neither the NCN6000 operation nor the smart card I/O line or commands are affected by the state of the INT pin. On the other hand, clearing the INT and reading the STATUS register can be performed by a single read by the MPU: states S1 and S2 can be combined in a single instruction, the same for S3 and S4. When a card is either inserted or extracted, the CRD_DET pin signal is debounced internally prior to pull the INT pin to Low. The built–in logic circuit automatically accommodates positive or negative input signal slope, on both insertion and extraction state, depending upon the polarity defined during the initialization sequence. The default condition is Normally Open switch, negative going card detection. The external CPU shall acknowledge the request by forcing CS = L which, in turn, releases the INT pin to High upon positive going of Chip Select (see Table 5). Polling the STATUS pin as depicted in Table 3 identifies the active card. If a card is present, the STATUS returns High, http://onsemi.com 5 NCN6000 ABBREVIATIONS Lout_H DC/DC External Inductor Lout_L DC/DC External Inductor Cout Output Capacitor VCC Card Power Supply Input Icc Current at CRD_VCC Pin Class A 5.0 V Smart Card Class B 3.0 V Smart Card CS Chip Select (from MPU) Z High Impedance Logic State (according to ISO7816) CRD_VCC Interface IC Card Power Supply Output CRD_CLK Interface IC Card Clock Output CRD_RST Interface IC Card Reset Output CRD_IO Interface IC Card I/O Signal Line CRD_DET Interface IC Card Detection ATR Answer to Reset PGM Select Programming or Normal Operation INT Interrupt (to MPU) PIN FUNCTIONS AND DESCRIPTION Pin Name Type Description 1 A0 INPUT This pin is combined with A1, PGM, RESET and I/O to program the chip mode of operation and to read the data provided by STATUS. (See Figures 3 and 4 and Tables 2 and 3) 2 A1 INPUT This pin is combined with A0, PGM, RESET and I/O to program the chip mode of operation and to read the data provided by STATUS. (See Figures 3 and 4 and Tables 2 and 3) 3 PGM INPUT This pin is combined with A0, A1, RESET and I/O to program the chip mode of operation and to read the data provided by STATUS. (See Figures 3 and 4 and Tables 2 and 3) 4 PWR_ON INPUT Pull Down This pin validates the operation of the internal DC/DC converter: CS = L + PWR_ON = Negative going: DC/DC is OFF CS = L + PWR_ON = Positive going: DC/DC is ON Note: The PWR_ON bit must be combined with a Low state CS signal to activate the function. 5 STATUS OUTPUT This pin provides logic state related to the card and NCN6000 status. According to the A0, A1 and PGM logic state, this pin carries either the Card present status or the Vbat or the DC/DC operation state. When PGM = L, STATUS is not affected. 6 CS INPUT Pull Up This pin provides the NCN6000 chip select function. The PWR_ON, RESET, I/O, A0, A1 and PGM signals are disabled when CS = H. When PGM = L and CS = L, the device jumps to the programming mode (See Figure 3 and Tables 1, 2 and 3). The Chip Select pin must be a unique physical address when more than one card are controlled by a single MPU. The data presented by the MPU are latched upon positive going edge of the Chip Select pin. 7 RESET INPUT Pull Down This pin provides two modes of operation depending upon the logic state of PGM pin 3: PGM = 1: The signal present on this pin is translated to pin 14 (card reset signal) when CS = L and PWR_ON = H. It is latched when CS = H. PGM = 0: The signal present on this pin is used as a logic input to program the internal functions (See Figure 4 and Tables 1 and 2). http://onsemi.com 6 NCN6000 PIN FUNCTIONS AND DESCRIPTION (continued) Pin Name Type Description 8 I/O Input/Output Pull Up This pin is connected to an external microcontroller interface. A bidirectional level translator adapts the serial I/O signal between the smart card and the microcontroller. The level translator is enabled when CS = L. The signal present on this pin is latched when CS = H. This pin is also used in programming mode (See Tables 1, 2 and 3, Figures 3 and 4). 9 INT OUTPUT Pull Down This pin is activated LOW when a card has been inserted and detected by the interface or when the NCN6000 reports Vbat or CRD_VCC status (See Table 5). The signal is reset to a logic 1 on the rising edge of either CS or PWR_ON. The Collector open mode makes possible the wired AND/OR external logic. When two or more interfaces share the INT function with a single microcontroller, the software must poll the STATUS pin to identify the origin of the interrupt (See Figure 4). 10 CLOCK_IN CLOCK INPUT High Impedance This pin can be connected to either the microcontroller master clock, or to any clock signal, to drive the external smart cards. The signal is fed to internal clock selector circuit and translated to the CRD_CLK pin at either the same frequency, or divided by 2 or 4 or 8, depending upon the programming mode (See Table 2). 11 CRD_DET INPUT The signal coming from the external card connector is used to detect the presence of the card. A built–in pull up low current source makes this pin active LOW or HIGH, assuming one side of the external switch is connected to ground. At Vbat start up, the default condition is Normally Open switch, negative going insertion detection. The Normally Closed switch, positive going insertion detection, can be defined by programming the NCN6000 accordingly. In this case, the polarity must be set up during the first cycles of the system initialization, otherwise an already inserted card will not be detected by the chip. 12 CRD_RST OUTPUT This pin is connected to the RESET pin of the card connector. A level translator adapts the RESET signal from the microcontroller to the external card. The output current is internally limited to 15 mA. The CRD_RST is validated when PWR_ON = H and PGM = H and hard wired to Ground when the card is deactivated. 13 CRD_CLK OUTPUT This pin is connected to the CLK pin of the card connector. The CRD_CLK signal comes from the clock selector circuit output. Combining A0, A1, PGM and I/O, as depicted in Table 3 and Figure 3, programs the clock selection. This signal can be forced into a standby mode with CRD_CLK either High or Low, depending upon the mode defined by the programming sequence (See Tables 1 and 2 and Figure 3). 14 CRD_IO I/O 15 CRD_VCC POWER This pin provides the power to the external card. It is the logic level “1” for CRD_IO, CRD_RST and CRD_CLK signals. The energy stored by the DC/DC external inductor Lout must be smoothed by a 10 µF capacitor, associated with a 100 nF ceramic in parallel, connected across CRD_VCC and GND. In the event of a CRD_VCC UVLOW voltage, the NCN6000 detects the situation and feedback the information in the STATUS bit. The device does not take any further action, particularly the DC/DC converter is neither stopped nor reprogrammed by the NCN6000. It is up to the external MPU to handle the situation. However, when the CRD_VCC is overloaded, the NCN6000 shut off the DC/DC converter, pulls the INT pin Low and reports the fault in the STATUS register. 16 GROUND SIGNAL The logic and low level analog signals shall be connected to this ground pin. This pin must be externally connected to the PWR_GND pin 17. The designer must make sure no high current transients are shared with the low signal currents flowing into this pin. 17 PWR_GND POWER This pin is the Power Ground associated with the built–in DC/DC converter and must be connected to the system ground together with GROUND pin 11. Using good quality ground plane is recommended to avoid spikes on the logic signal lines. 18 Lout_L POWER The High Side of the external inductor is connected between this pin and Lout_H to provide the DC/DC function. The built–in MOS devices provide the switching function together with the CRD_VCC voltage rectification. This pin handles the connection to the serial I/O pin of the card connector. A bidirectional level translator adapts the serial I/O signal between the card and the microcontroller. The CRD_IO pin current is internally limited to 15 mA. A built–in register holds the previous state presents on the I/O input pin. http://onsemi.com 7 NCN6000 PIN FUNCTIONS AND DESCRIPTION (continued) Pin Name Type Description 19 Lout_H POWER The High Side of the external inductor is connected between this pin and Lout_L to provide the DC/DC function. The current flowing into this inductor is performed by a sense resistor internally connected from Vbat/pin 20 and pin 19. Typically, Lout = 22 µH, with ESR < = 1.0 Ω, for a nominal 55 mA output load. 20 Vbat POWER This pin is connected to the supply voltage and monitored by the NCN6000. The operation is inhibited when Vbat is below the minimum 2.70 V value, followed by a PWR_DOWN sequence and a Low STATUS state. MAXIMUM RATINGS Rating Symbol Value Unit Battery Supply Voltage Vbat 7.0 V Battery Supply Current Ibat 200 mA Power Supply Voltage Vcc 6.0 V Power Supply Current Icc 100 mA Digital Input Pins Vin –0.5 V < Vin < Vbat +0.5 V, but < 7.0 V V Digital Input Pins Iin 5.0 mA Digital Output Pins Vout –0.5 V < Vin < Vbat +0.5 V, but < 7.0 V V Digital Output Pins Iout 10 mA Card Interface Pins Vcard –0.5 V < Vcard < Vcc +0.5 V V Card Interface Pins Icard 25 mA Inductor Current ILout 200 mA ESD Capability (See Note 2.) Standard Pins Card Interface Pins and CRD_DET VESD kV 2.0 4.0 TSSOP–20 Package Power Dissipation @ Tamb = +85°C Thermal Resistance Junction to Air (Rthja) PDS Rθja TBD TBD mW °C/W Operating Ambient Temperature Range TA –25 to +85 °C Operating Junction Temperature Range TJ –25 to +125 °C TJmax +150 °C Tsg –65 to +150 °C Maximum Junction Temperature (Note 3.) Storage Temperature Range 1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = +25°C. 2. Human Body Model, R = 1500 Ω, C = 100 pF. 3. Absolute Maximum Rating beyond which damage to the device may occur. http://onsemi.com 8 NCN6000 POWER SUPPLY SECTION (–25°C to +85°C ambient temperature, unless otherwise noted.) Symbol Pin Min Typ Max Unit Power Supply Vbat 20 2.7 – 6.0 V Standby Supply Current Conditions: PWR_ON = L, STATUS = H, CLOCK_IN = H, CS = H. All other logic inputs and outputs are open: Vbat = 3.0 V Vbat = 5.0 V Ibatsb 20 – – DC Operating Current @ Vbat = 6.0 V, Vcc = 5.0 V PWR_ON = H, CLOCK_IN = 0, CS = H, all CRD pins unloaded Ibatop 20 – – TBD mA VbatLH VbatLL VbatHY 20 2.2 2.1 – 2.35 2.25 100 2.7 2.6 – V V mV Vcc 15 Rating Vbat Undervoltage DetectionHigh Vbat Undervoltage DetectionLow Vbat Undervoltage DetectionHysteresis Output Card Supply Voltage @ Icc = 55 mA @ 2.70 V < Vbat < 6.0 V CRD_VCC = 3.0 V CRD_VCC = 5.0 V @ VbatLL < Vbat < 2.70 V CRD_VCC = 5.0 V µA 5.0 15 V VC3H VC5H 2.75 4.75 – – 3.25 5.25 VC5H 4.50 – – Output Card Supply Peak Current @ Vcc = 5.0 V Iccp 15 55 – – mA Output Current Limit Time Out tdoff 15 – 4.0 – ms Output Over Current Limit Iccov 15 – – 85 mA Output Dynamic Peak Current @ Vcc = 3.0 V or 5.0 V, Cout = 10 µF + 100 nF Ceramic, Pulse Width 400 ns (See Notes 4. and 5.) Iccd 15 100 – – mA Battery Start–Up Current @ Vcc = 3.0 V 0°C < TA < +85°C –25°C < TA < 0°C @ Vcc = 5.0 V 0°C < TA < +85°C –25°C < TA < 0°C Iccst 20 TBD – – mA Output Card Supply Voltage Ripple @ Lout = 22 µH, Cout 1 = 10 µF, Cout 2 = 100 nF Iout = 55 mA Vcc = 5.0 V (See Note 4.) Vcc = 3.0V Vccrip 15 – – Output Card Supply Turn On Time @ Lout = 22 µF, Cout1 = 10 µF, Cout2 = 100 nF, Vbat = 2.7 V, Vcc = 5.0 V VccTON 15 – – 2.0 ms Output Card Supply Shut Off Time @ Cout1 = 10 µF, Cout2 = 100 nF, Vbat = 2.7 V, Vcc = 5.0 V, VccOFF < 0.4V VccTOFF 15 – – 250 µs Fsw 18 – 600 – kHz Power Switch Drain/Source Resistor RONS 18 – – TBD Ω Output Rectifier ON Resistor ROND 15 – – TBD Ω DC/DC Converter Operating Frequency mV 50 50 4. Ceramic, SMD type capacitors are mandatory to achieve the CRD_VCC specifications. When electrolytic capacitor is used, the external filter must include a 100 nF, max 50 mΩ ESR capacitor in parallel, to reduce both the high frequency noise and ripple to a minimum. A good way is to use 3 x 3.3 µF/ceramic capacitors in parallel. 5. According to ISO7816–3, paragraph 4.3.2. http://onsemi.com 9 NCN6000 DIGITAL PARAMETERS SECTION @ 2.70 V < Vbat < 6.0 V, NORMAL OPERATING MODE (–25°C to +85°C ambient temperature, unless otherwise noted.) Rating Input Asynchronous Clock Duty Cycle = 50% Clock Rise Time Clock Fall Time I/O Data Transfer Switching Time, Both Directions (I/O and CRD_IO), @ Cout = 30 pF I/O Rise Time* (See Note 6.) I/O Fall Time Symbol Pin Min Typ FCLKIN 10 – – 8, 14 – Max Unit 40 5.0 5.0 MHz ns ns µs – TRIO TFIO 1.0 1.0 Input/Output Data Transfer Time, Both Directions @ 50% Vcc, L to H and H to L TTIO 8, 14 – – 150 ns Minimum PWR_ON Low Level Logic State Time to Power Down the DC/DC Converter TWON 4 2.0 – – µs Vcc Power Up/Down Sequence Interval TDSEQ – 0.5 2.0 µs RSTA 5 30 50 70 kΩ Chip Select CS Pull Up Resistance RCSPU 6 30 50 70 kΩ Interrupt INT Pull Up Resistance RINTPU 9 30 50 70 kΩ Positive Going Input High Voltage Threshold (A0, A1, PGM, PWR_ON, CS, RESET, CLOCK_IN, CRD_DET) VIH 1, 2, 3, 4, 6, 7, 10, 11 0.70 * Vbat – Vbat + 0.3 V Negative Going Input High Voltage Threshold (A0, A1, PGM, PWR_ON, CS, RESET, CLOCK_IN, CRD_DET) VIL 1, 2, 3, 4, 6, 7, 10, 11 –0.3 – 0.30 * Vbat V Output High Voltage STATUS, INT @ IOH = –10 µA VOH 5, 9 Vbat – 1.0 V – – V Output High Voltage STATUS, INT @ IOH = 200 µA VOL 5, 9 – – 0.40 V STATUS Pull Up Resistance 6. Since a 20 kΩ pull up resistor is provided by the NCN6000, the external MPU can use an Open Drain connection. DIGITAL PARAMETERS SECTION @ 2.70 V < Vbat < 6.0 V, CHIP PROGRAMMING MODE (–25°C to +85°C ambient temperature, unless otherwise noted.) Rating Symbol Pin Min Typ Max A0, A1, PGM, PWR_ON, RESET and I/O Data Set Up Time TSMOD 1, 2, 3, 4, 7, 8 2.0 – – A0, A1, PGM, PWR_ON, RESET and I/O Data Set Up Time THMOD 1, 2, 3, 4, 7, 8 2.0 Chip Select CS Low State Pulse Width TWCS 6 2.0 Unit µs – – µs http://onsemi.com 10 – – µs NCN6000 SMART CARD SECTION (–25°C to +85°C ambient temperature, unless otherwise noted.) Rating Symbol CRD_RST @ Vcc = +5.0 V Output RESET VOH @ Irst = –20 µA Output RESET VOL @ Irst = 200 µA Output RESET Rise Time @ Cout = 30 pF Output RESET Fall Time @ Cout = 30 pF VOH VOL tR tF CRD_RST @ Vcc = +3.0 V Output RESET VOH @ Irst = –20 µA Output RESET VOL @ Irst = 200 µA Output RESET Rise Time @ Cout = 30 pF Output RESET Fall Time @ Cout = 30 pF VOH VOL tR tF Pin Min Max Unit Vcc –0.9 –0.3 Vcc 0.4 100 100 V V ns ns Vcc –0.9 –0.3 Vcc 0.4 100 100 V V ns ns 5.0 55 18 18 TBD Vcc +0.3 +0.5 MHz % ns ns ns V V 5.0 60 18 18 TBD Vcc +0.3 0.7 MHz % ns ns ns V V 1.0 1.0 TBD Vcc 0.4 kHz µs µs ns V V 1.0 1.0 TBD kHz µs µs ns Vcc 0.4 V V 26 kΩ 150 150 µs µs 12 CRD_CLK @ Vcc = +3.0 V or Vcc = 5.0 V – 13 CRD_VCC = +5.0 V Output Frequency (See Note 7.) Output Duty Cycle @ DC Fin = 50% 1% Output CRD_CLK Rise Time @ Cout = 30 pF Output CRD_CLK Fall Time @ Cout = 30 pF Output CRD_CLK Delay Output VOH @ Iclk = –20 µA Output VOL @ Iclk = 100 µA FCRDCLK FCRDDC tR tF tD VOH VOL CRD_VCC = +3.0 V Output Frequency (See Note 7.) Output Duty Cycle @ DC Fin = 50% 1% Output CRD_CLK Rise Time @ Cout = 30 pF Output CRD_CLK Fall Time @ Cout = 30 pF Output CRD_CLK Delay Output VOH @ Iclk = –20 µA @ Cout = 30 pF Output VOL @ Iclk = 100 µA @ Cout = 30 pF FCRDCLK FCRDDC tR tF tD VOH VOL CRD_I/O @ CRD_VCC = +5.0 V CRD_I/O Data Transfer Frequency CRD_I/O Rise Time @ Cout = 30 pF CRD_I/O Fall Time @ Cout = 30 pF CRD_I/O Delay Time Output VOH @ Icrd = –20 µA Output VOL @ Iclk = 1.0 mA, VIL = 0 V FIO TRIO TFIO TDIO VOH VOL CRD_I/O @ CRD_VCC = +3.0 V CRD_I/O Data Transfer Frequency CRD_I/O Rise Time @ Cout = 30 pF CRD_I/O Fall Time @ Cout = 30 pF CRD_I/O Delay Time Output VOH @ I = –20 µA Output VOL @ I = 1.0 mA, VIL = 0 V FIO TRIO TFIO TDIO VOH VOL Typ – 45 3.15 –0.3 40 1.85 –0.3 14 315 Vcc –0.9 –0.3 315 CRD_IO Pull Up Resistor @ PWR_ON = H RCRDPU Card Detection Debouncing Delay: Card Insertion Card Extraction TCRDIN TCRDOFF Vcc –0.9 –0.3 14 14 11 20 – 50 50 Card Insertion or Extraction Positive Going Input High Voltage VIHDET 11 0.70 * Vbat – Vbat + 0.3 V Card Insertion or Extraction Negative Going Input Low Voltage VILDET 11 –0.3 – 0.30 * Vbat V Card Detection Bias Pull Up Current @ Vbat = 5.0 V IDET 11 – 15 TBD µA Output Peak Max Current Under Card Static Operation Mode @ Vcc = 3.0 V or Vcc = 5.0 V Icrd 12, 13, 14 5.0 – 15 mA 7. The CRD_CLK clock can operate up to 20 MHz, but the rise and fall time are not guaranteed to be fully within the ISO7816 specification over the temperature range. Typically, tr and tf are 12 ns @ CRD_CLK = 10 MHz. http://onsemi.com 11 NCN6000 Programming and Status Functions The NCN6000 features a programming interface and a status interface. Figure 3 illustrates the programming mode. Table 1. Programming and Status Functions Pinout Logic Pins Name CRD_VCC Prg. 3.0 V/5.0 V CLOCK_IN Divide Ratio CRD_DET CLOCK STOP AND START Poll Card Status DC/DC Status Vbat Status CRD_VCC Status 5 STATUS Not Affected Not Affected Not Affected Not Affected READ READ READ READ 6 CS Latch On Rising Edge Latch On Rising Edge Latch On Rising Edge Latch On Rising Edge 0 0 0 0 3 PGM 0 0 0 0 1 1 1 1 1 A0 0/1 0/1 0/1 0/1 0 1 0 1 2 A1 0/1 0/1 1 0 0 0 1 1 7 RESET 0 0 1 1 Z Z Z Z 8 I/O (in) 0/1 0/1 0/1 0/1 Z Z Z Z Card VCC, Card CLOCK and Card Detection Polarity Programming I/O logic states for the possible options. The default power reset condition is state 1: asynchronous clock, ratio 1/1, CRD_CLK active, CRD_DET = Normally Open. All states are latched for each output variable in programming mode at the positive going slope of Chip Select [CS] signal. It is the system designer’s responsibility to set up the options needed to match the chip with the peripherals. In particular, when using Normally Close switch, the CRD_DET polarity must be defined during the first cycles of the initialization. The CRD_VCC and CLOCK_IN programming options allows matching the system frequency with the card clock frequency, and to select 3.0 V or 5.0 V CRD_VCC supply. The CRD_DET programming option allows the usage of either Normally Open or Normally Close detection switch. The Table 2 given hereafter highlights the A0, A1, PGM and http://onsemi.com 12 NCN6000 Table 2. Card VCC, Card Clock and Card Detection Polarity Truth Table STATE# PGM RESET A1 A0 I/O CRD_VCC CRD_CLK CRD_DET STATUS H12 1 L L L L L 3.0 V CLOCK_IN 1/1 – 2 L L L L H 3.0 V CLOCK_IN 1/2 – H12 3 L L L H L 3.0 V CLOCK_IN 1/4 – H12 4 L L L H H 3.0 V CLOCK_IN 1/8 – H12 H12 5 L L H L L 5.0 V CLOCK_IN 1/1 – 6 L L H L H 5.0 V CLOCK_IN 1/2 – H12 7 L L H H L 5.0 V CLOCK_IN 1/4 – H12 8 L L H H H 5.0 V CLOCK_IN 1/8 – H12 9 L H L L L – START – H12 10 L H L L H – STOP Low – H12 H12 11 L H L H L – STOP High – 12 L H L H H – Reserve – H12 13 L H H L L – – Normally Open11 H12 14 L H H L H – – Normally Close11 H12 15 L H H H L – – Normally Close11 H12 16 L H H H H – – Normally Close11 H12 17 H Z L L Z – – – Card Present – – DC/DC Status – – Vbat UvLow – – CRD_VCC UvLow 18 H 19 Z H 20 L Z H H Z H H Z L – Z H – Z – 8. The programmed conditions are latched upon Chip Select (CS pin 6) positive going transient. 9. Card clock integrity is guaranteed no spikes whatever be the frequency switching. 10. The STATUS register is not affected when the NCN6000 operates in any of the programming functions. 11. The CRD_VCC and CRD_CLK are not affected when the NCN6000 operates outside their respective decoded logic address. 12. At turn on, the NCN6000 is initialized with CRD_VCC = 3.0 V, CLOCK_IN Ratio = 1/1, CRD_CLK = START, CRD_DET = Normally Open. 13. The High Level present to status 1 to 16 included has been implemented to reduce current consumption but has no other meanings. DC/DC Converter and Card Detector Status Vbat undervoltage and CRD_VCC undervoltage situations. When PGM = H, the STATUS pin returns a High if a card is detected present, a Low being asserted if there is no card inserted. In any case, the external card is not automatically powered up. When the external MPU asserts PWR_ON = H, together with CS = L, the Vcc supply is provided to the card and the state of the DC/DC converter, the Vbat and the CRD_VCC can be polled through the STATUS pin. The NCN6000 status can be polled when CS = L. Please consult Figures 3 and 4 for a description of input and output signals. The status message is described in Table 3. Table 3. Card and DC/DC Status Output PGM A1 A0 STATUS Message HIGH L L LOW No Card HIGH L L HIGH Card Present HIGH L H LOW DC/DC Converter Overloaded HIGH L H HIGH DC/DC Converter OK HIGH H L LOW Vbat OK HIGH H L HIGH Vbat Undervoltage HIGH H H HIGH CRD_VCC OK HIGH H H LOW CRD_VCC Undervoltage Card Power Supply Timing At power up, the CRD_VCC power supply rise time depends upon the current capability of the DC/DC converter associated with the external inductor L1 and the reservoir capacitor connected across CRD_VCC and GROUND. On the other hand, at turn off, the CRD_VCC fall time depends upon the external reservoir capacitor and the peak current absorbed by the internal CMOS transistor built across CRD_VCC and GROUND. These behaviors are depicted in Figure 5. Since none of these parameters can have infinite values, the designer must take care of these limits if the tON or the tOFF provided by the data sheets does not meet his requirement. The STATUS pin provides a feedback related to the detection of the card, the state of the DC/DC converter, the http://onsemi.com 13 NCN6000 Figure 6. Turn ON & Turn OFF Typical Curve as a Function of the Reservoir Capacitor Figure 5. Card Power Supply Turn ON and OFF Timing Basic NCN6000 Operating Modes Flow Chart During the transaction operation, the external MPU takes care of whatever is necessary to he data on the single bidirectional I/O line. Leaving aside the DC–DC control and associated failures, the NCN6000 does not take any further responsibility in the data transaction. When the chip operates in the programming mode, the NCN6000 provide a flexible access to set up the CRD_VCC voltage, the CRD_CLK and the CRD_DET smart card signals. The NCN6000 brings all the functions necessary to handle data communication between a host computer and the smart card. The built–in Chip Select pin provides a simple way to share the same MPU bus with several card interface. On top of that, the logic control are derived from specific pins, avoiding the risk of mixing up the operation when the interface is controlled by a low end microcontroller. CRD_VCC = Over loaded Vbat = Under Voltage ISO STOP SEQUENCE CS = PGM = L CS = L PWR_ON = H CS = ACTIVE MODE CS = L PGM = H PWR_ON = L IDLE MODE CS = L PGM = H PWR_ON = L CS = ISO START SEQUENCE INT = L PWR_ON = L CS = STANDBY MODE CS = H PWR_ON = L PROGRAMMING MODE CS = L PGM = L Figure 7. Operating Modes Flow Chart http://onsemi.com 14 CS = PGM = H TRANSACTION MODE CS = L PGM = L PWR_ON = H CS = PGM = L CS = PGM = H CS = NCN6000 Standby Mode Programming Mode The Standby Mode allows the NCN6000 to detect a card insertion, keeping the power consumption at a minimum. The power supply CRD_VCC is not applied to the card, until the external MPU set PWR_ON = H with CS = L. The programming mode allows the configuration of the card power supply, card clock and Card Detection input logic polarity. These signals (CRD_VCC, CRD_CLK and CRD_DET) are described in the pin description paragraph associated with Tables 1 and 2 and Figures 3 and 8. Standby Mode Logic Conditions: CS PWR_ON A0 A1 PGM I/O RESET =H =H =Z =Z =Z =Z =Z Card Output: CRD_VCC CRD_CLK CRD_RST CRD_IO Programming Mode Logic Conditions: =0 =L =L = H/L depending upon the previous I/O pin logic state CS PWR_ON A0 A1 PGM I/O RESET When a card is inserted, the internal logic filters the signal present pin 11, then asserts the INT pin to Low. The external MPU shall run whatever is necessary to handle the card. The INT is cleared (return to High) when a positive going transition is asserted to either the CS or to the PWR_ON signal logically combined with Chip Select = Low. =L =L = 0/1 = 0/1 =L = 0/1 = 0/1 Card Output: CRD_VCC CRD_CLK CRD_RST CRD_IO =0 =L =L = H/L depending upon the previous I/O pin logic state The I/O and RESET pins are not connected to the smart card and become logic inputs to control the NCN6000 programming sequence. The programmed values are latched upon transition of CS from Low to High, PGM being Low during the transition. PROGRAMMING NORMAL MODE PGM I/O A0 A1 RESET CS 2 µs 1 µs 2 µs Figure 8. Minimum Programming Timings When a programming mode is validated by a negative going transient on Chip Select, the mode is latched and PGM can be released to High. This latch is automatically reset when CS returns to High. The logic input signals can be set simultaneously, or bit a time (using either a STAA or a BSET function), the key point being the minimum delay between the shorter bit and the Chip Select pulse. The programmed value is latched into the NCN6000 register on the CS positive going edge. Active Mode Logic Conditions: CS PWR_ON A0 A1 PGM I/O RESET STATUS =L =L =0 =0 =1 =Z =Z = 0/1 is Card Inserted? Card Output: CRD_VCC CRD_CLK CRD_RST CRD_IO =0 =L =L = H/L depending upon the previous I/O pin logic state Active Mode The Chip Select pulse [CS] will automatically clear the previously asserted INT signal. If a card is present, the MPU shall activate the DC/DC converter by asserting PWR_ON = H. The NCN6000 will automatically run a power up sequence when the In the active mode, the NCN6000 is selected by the external MPU and the STATUS pin can be polled to get the status of either the DC/DC converter or the presence of the card (inserted or not valid). The power is not connected to the card: CRD_VCC = 0 V. http://onsemi.com 15 NCN6000 CRD_VCC reaches the undervoltage level (either VC5H or VC3H, depending upon the CRD_VCC voltage supply programmed). The CRD_IO, CRD_RST and CRD_CLK pins are validated, according to the ISO7816–3 sequence. The interface is now in transaction mode and the system is ready for data exchange through the I/O and RESET lines. In addition, the CRD_CLK signal can be stopped, as depicted in Tables 1 and 2, to minimize the current consumption of the external smart card, leaving CRD_VCC active. Power Down Operation The power down mode can be initiated by either the external MPU (pulling PWR_ON = L) or by one of the internal error condition (CRD_VCC overload or Vbat Low). The communication session is terminated immediately, according to the ISO7816–3 sequence. On the other hand, the MPU can run the Standby mode by forced CS = H. When the card is extracted, the interface shall detect the operation and run the Power Shut Off of the card as described by the ISO/CEI 7816–3 sequence depicted here after: The time delay between each negative going signal is 500 ns typical. Transaction Mode During the transaction mode, the NCN6000 maintains power supply and clock signal to the card. All the signal levels related with the card are translated as necessary to cope with the MPU and the card. The DC/DC converter status and the Vbat state can be monitored on the STATUS by using the A0 and A1 logic inputs as depicted Tables 2 and 3. Transaction Mode Logic Conditions: Card Output: CS PWR_ON A0 A1 PGM I/O CRD_VCC = Vcc 3.0 or 5.0 V CRD_CLK = CLOCK CRD_RST = H/L CRD_IO = DATA TRANSFER RESET STATUS =L =1 =1 =0 =1 = DATA TRANSFER = H/L = 0/1 DC/DC status: Fail/Pass? Card Detection The card detector circuit gives a positive constant low current to bias the CRD_DET pin, yielding a logic High when the pin is left open. The internal logic associated with pin 11 provides an automatic selection of the slope card detection, depending upon the polarity set by the external MPU. At start up, the CRD_DET is preset to cope with Normally Open switch. When a Normally Close switch is used in the card socket, it is mandatory to program the NCN6000 chip during the initialization sequence, otherwise the system will not start if a card was previously inserted. Table 2 gives the programming code for such a function. The next lines provide a typical assembler source to handle this CRD_DET Normally Close polarity: To make sure the data is not polluted by power losses, it is recommended to check the state of CRD_VCC before launching a new data transaction. Idle Mode The idle mode is used when a card is powered up (CRD_VCC = Vcc), without communication on going. Idle Mode Logic Conditions: CS PWR_ON A0 A1 PGM I/O RESET STATUS =L =1 =L =L =1 =Z =H = 0/1 according to the internal register results Smart EQU LDX LDAA STAA Card Output: CRD_VCC = Vcc 3.0 or 5.0 V CRD_CLK = CLOCK CRD_RST = H CRD_IO = Z $20 #$1000 #$09 smart, X ; NCN6000 Physical CS Address ; Offset ; I/O = H, A0 = A1 = L, RESET = H ; Set CRD_DET = Normally Closed Switch The CRD_DET polarity can be updated at any time, during the Program Mode sequence (PGM = L), but, generally speaking, is useless since the switch does not change during the usage of the considered module. On the other hand, the card detection switch shall be connected across pin 11 and ground, for any polarity selected. http://onsemi.com 16 NCN6000 CARD EXTRACTION DETECTED CRD_VCC Voltage CRD_CLK CRD_RST CRD_IO Digital Filter Delay (50 µs min) Figure 9. Typical Power Down Sequence in the NCN6000 Interface extraction, the power down sequence is activated, regardless of the PWR_ON state, and the INT pin is asserted Low. It is up to the external MPU to clear this interrupt by forcing a chip select pulse as depicted in Figure 4. The 75 µs delay represents the digital filter built into the NCN6000 chip. Any pulse shorter than this delay does not generate an interrupt. The transition presents pin 11, whatever be the polarity, is filtered out by the internal digital filter circuit, avoiding false interrupt. In addition to the typical internal 50 µs timing, the MPU shall provide an additional delay to cope with the mechanical stabilization of the card interface (typically 3 ms), prior to valid the CRD_VCC supply. When a card is inserted, the detector circuit asserts INT = Low as depicted before. When the NCN6000 detects a card Digital Filter Delay INTERRUPT Chip Select Acknowledge or Clear Interrupt Figure 10. Card Insertion Detection and Interrupt Signals When the card is extracted, the CRD_DET signal generates an interrupt, assuming the positive pulse width is longer than the digital filter. The oscillogram here above depicts the behavior for a Normally Open switch. The Chip Select pulse is generated by the external microcontroller, the minimum pulse width being 2.0 µs to make sure the card is detected. The oscillogram here above depicts the behavior for a Normally Open switch. http://onsemi.com 17 NCN6000 CRD_DET Input Voltage (card extracted) Digital Filter Delay INTERRUPT Chip Select Acknowledge or Clear Interrupt Figure 11. Card Extraction Detection and Interrupt Signals CRD_DET Input Voltage (card inserted) INTERRUPT Chip Select Figure 12. Interrupt Acknowledgement During a Card Insertion Detection Sequence In the event of a power up request coming from the external MPU (PWR_ON = H, CS = L), the power manager starts the DC/DC converter. When the CRD_VCC voltage reaches the programmed value (3.0 V or 5.0 V), the circuit activates the card signals according to the following sequence: The interrupt signal, provided in pin 9, is cleared by a positive going Chip Select signal as depicted by the oscillogram here above. The CS pulse width is irrelevant, as long as it is larger than 2.0 µs. Power Management CRD_VCC→CRD_IO→CRD_CLK→CRD_RST The purpose of the power management is to activate the circuit functions needed to run a given mode of operation, yielding a minimum current consumption on the Vbat supply. In the Standby mode (PWR_ON = L), the power management provides energy to the card detection circuit only. All the card interface pins are forced to ground potential. The logic level of the data lines are asserted High or Low, depending upon the state forced by the external MPU, when the start up sequence is completed. Under no situation the NCN6000 shall launch a smart card ATR sequence. http://onsemi.com 18 NCN6000 At the end of the transaction, asserted by the MPU (PWR_ON = L, CS = L), or under a card extraction, the ISO7816–3 power down sequence takes place: When CS = L, the bidirectional I/O line (pin 8 and 15) is forced into the High impedance mode to avoid signal collision with any data coming from the external MPU. CRD_RST→CRD_CLK→CRD_IO→CRD_VCC CS PWR_ON CRD_VCC 250 µs 2 ms CRD _VCC Rise Time CRD_VCC No Change CRD_VCC Power Down Fall Time CRD_VCC No Change Figure 13. Card Power Supply Control DC/DC Converter Operation an automatic system to accommodate the mode of operation whatever be the Vbat and CRD_VCC voltages. Comparator U3/Figure 14 tracks the two voltages and set up the operating mode accordingly. The built–in DC/DC converter is based on a modified boost structure to cover the full battery and card operating voltage range. The built–in battery voltage monitor provides Vbat 20 Current Sense U1 Vbat – U3 Vbat/VCC Comparator + + R1 - Vbat 1R 19 Lout_H GND L2 22 µH GND PWR_ON Overload VCC_OK LOGIC CONTROL 3 V/ 5 V 18 MOS Drive Substrat Bias 15 Gate Drive Q1 Q2 CRD_VCC C? + GND GND Gate Drive Lout_L Vbat Vref Voltage Regulation – U2 + CAPACITOR: Electrolytic Tantalum Ceramic Q3 GND Vref_3/5 V GND Vout_3_5 GND Figure 14. Basic DC/DC Structure http://onsemi.com 19 17 PWR_GND NCN6000 typically 22 µH, stores the energy to drive the +5.0 V card supply from a 2.7 V to 6.0 V voltage range battery. The oscillogram Figure 15 depicts the DC/DC behavior under these two modes of operation. When the input voltage Vbat is lower than the programmed CRD_VCC, the system operates under the boost mode, providing the voltage regulation and current limit to the smart card. In this mode, the external inductor, POWER_ON Ibat IL CRD_VCC Step Down Mode CRD_VCC 5 V Step Up Mode Figure 15. DC/DC Operating Modes The standard electrolytic capacitors have the low cost advantage for a relative high micro farad value, but have poor tolerance, high leakage current and high ESR. The tantalum type brings much lower leakage current together with high capacity value per volume, but cost can be an issue and ESR is rarely better than 300 mΩ. The new ceramic type have a very low leakage together with ESR in the 50 mΩ range, but value above 10 µF are relatively rare. Moreover, depending upon the low cost ceramic material used to build these capacitors , the thermal coefficient can be very bad, as depicted in Figure 15. The X7R type are highly recommended when low voltage ripple is mandatory. Based on the experiments carried out during the NCN6000 characterization, the best comprise, at time of printing this document, is to use two 6.8 µF/10 V/ceramic/X7R capacitor in parallel to achieve the CRD_VCC filtering. The ESR will not extend 50 mΩ over the temperature range and the combination of standard parts provide an acceptable –20% to +20% tolerance, together with a low cost. Obviously, the capacitor must be SMD type to achieve the extremely low ESR and ESL necessary for this application. When the input voltage Vbat is higher than the programmed CRD_VCC, the system operates under a step down mode, yielding the voltage regulation and current limit identical to the boost mode. In this case, the built–in structure turns Off Q1 and inverts the Q2 substrate bias to control the current flowing to the load.These operations are fully automatic and transparent for the end user. The High and Low limits of the current flowing into the external inductor L1 are sensed by the operational amplifier U1 associated with the internal shunt R1. Since this shunt resistor is located on the hot side of the inductor, the device reads both the charge and discharge of the inductor, providing a clean operation of the converter. In order to optimize the DC/DC power conversion efficiency, it is recommended to use external inductor with R < = 2.0 Ω. The output capacitor C1 stores the energy coming from the converter and smooth the CRD_VCC voltage applied to the external card. At this point, cares must be observed, beside the micro farad value, to select the right type of capacitor. According to the capacitor’s manufacturers, the internal ESR can range from a low 10 mΩ to more than 1.0 Ω, thus yielding high losses during the DC/DC operation, depending upon the technology used to build the capacitor. Table 4. Ceramic/Electrolytic Capacitors Comparison Manufacturers Type/Series Format Max Value Tolerance Typ. Z @ 500 kHz MURATA CERAMIC/GRM225 0805 10 µF/6.3 V +80%/–20% 30 m VISHAY Tantalum/594C/593C 10 µF/16 V VISHAY Electrolytic/94SV 10 µF/10 V http://onsemi.com 20 450 m –20%/+20% 400 m NCN6000 Clock Divider The logic input pins A0, A1, PGM, I/O and RESET fulfill the programming functions when both PGM and CS are Low. The clock input stage (CLOCK_IN) can handle a 40 MHz frequency maximum, the divider being capable to provide a 1:8 ratio. Of course, the ratio must be defined by the engineer to cope with the Smart Card considered in a given application and, in any case, the output clock [CRD_CLK] shall be limited to 20 MHz maximum. In order to minimize the dI/dt and dV/dV developed in the CRD_CLK line, the peak current as been internally limited to 30 mA peak (typical @ CRD_VCC = 5.0 V), hence limited the rise and fall time to 10 ns typical. Consequently, the NCN6000 fulfills the ISO7816 specification up to 10 MHz maximum, but can be used up to 20 MHz when the final application operates in a limited ambient temperature range. The main purpose of the built–in clock generator is threefold: 1. Adapts the voltage level shifter to cope with the different voltages that might exist between the MPU and the Smart Card. 2. Provides a frequency division to adapt the Smart Card operating frequency from the external clock source. 3. Controls the clock state according to the smart card specification. In addition, the NCN6000 adjusts the signal coming from the microprocessor to get the Duty Cycle window as defined by the ISO7816–3 specification. CLOCK_IN CS 1 2 3 3 CRD_VCC RESET 1 2 3 3 PGM Clock & VCC Programming Block I/O Level Shifter & Control CRD_CLK A0 A1 +3.0 V +5.0 V Figure 16. Simplified Frequency Divider and Programming Functions CRD_CLK frequency division can be delayed by eight CLOCK_IN pulses and the microcontroller software must take this delay into account prior to launch a new data transaction. In order to avoid any duty cycle out of the frequency smart card ISO7816–3 specification, the divider is synchronized by the last flip flop, thus yielding a constant 50% duty cycle, whatever be the divider ratio. Consequently, the output http://onsemi.com 21 NCN6000 CLOCK CRD CLK PGM CS to make sure the next card transaction is not activated before the CRD_CLK signal has been updated. Generally speaking, such a delay can be derived from the maximum clock frequency provided to the interface, keeping in mind the maximum delay is eight incoming clock pulses. The example given by the oscillogram here above highlights the delay coming from the internal clock duty cycle resynchronization. In this case, the clock is internally divided by 2 prior to be applied to the CRD_CLK pin. Since the clock signal is asynchronous, it is up to the programmer CLOCK CRD CLK PGM CS Figure 17. Clock Programming Examples The clock can be reprogrammed without halting the rest of the circuit, whatever be the new clock divider ratio. CRD CLK CLOCK PGM RESET A0_ A1_ IO CS Figure 18. Command Stop Clock HIGH The CRD_CLK signal is halted in the High logic state, following the Chip Select positive going transition. Logic Input conditions: PGM = Low RESET = Low I/O = Low http://onsemi.com 22 A0 = Low A1 = Low CS = Low, pulsed NCN6000 CRD CLK CLOCK PGM RESET A0_ A1_ IO CS Figure 19. Command Stop Clock LOW previous halted state is irrelevant and the clock signal is synchronized with the internal clock divider to avoid non CRD_CLK 50% duty cycle. PGM = Low A0 = Low RESET = High A1 = Low I/O = Low CS = Low, pulsed The CRD_CLK signal is halted in the Low logic state, following the Chip Select positive going transition. Logic Input conditions: PGM = Low A0 = Low RESET = Low A1 = Low I/O = High CS = Low, pulsed The CRD_CLK signal is resumed in the normal operation, following the Chip Select positive going transition. The CRD CLK CLOCK PGM RESET A0_ A1_ IO CS Figure 20. Command Resume Clock Normal Operation http://onsemi.com 23 NCN6000 CRD_CLK C3 Rise 7.900 ns Cp = 30 pF CRD_CLK C3 Fall 8.255 ns Cp = 30 pF Figure 21. Card Clock Rise & Fall Time CRD_VCC voltage reaches the minimum value. During the CRD_VCC slope, all the card outputs are kept Low and no spikes can be write to the smart card. The oscillograms give the worst case operation when the stray capacitance is 15 pF. Since both tr and tf increase when the stray capacitance increases, the uncontrolled noise reduce as well. The oscillogram on the right hand side is a magnification of the curves given on the opposite side. Since the CRD_CLK signal can generate very fast transient (i.e. tr = 2.5 ns @ Cp = 10 pF), adapting the design to cope with the EMV noise specification might be necessary at final check out. Using an external RC network is a way to reduce the dv/dt, hence the EMI noise. In order to avoid uncontrolled command applied to the smart card, the NCN6000 internal logic circuit, together with the Vbat monitoring, clamps the card outputs until the CRD_VCC 5.0 V 5.0 V CRD_VCC CRD_RST CRD_RST CRD_CLK CRD_CLK Cp = 15 pF Cp = 15 pF CRD_IO CRD_IO Figure 22. Smart Card Signal Sequence at Power On http://onsemi.com 24 NCN6000 Bidirectional Level Shifter When the CS signal goes High, or if the MPU is running any of the programming functions, the built–in register holds the previous state presents on the input I/O pin. This mechanism is useful to force the CRD_IO card pin in either a High or a Low pre–defined logic state. It is the responsibility of the programmer to set up the I/O line according to the system’s activity. The NCN6000 carries out the voltage difference between the MPU and the Smart Card I/O signals. When the start sequence is completed, and if no failures have been detected, the device becomes essentially transparent for the data transferred on the I/O line. To fulfill the ISO7816–3 specification, both sides of the I/O line have built–in pulsed circuitry to accelerate the signal rise transient. The I/O line is connected on both side of the interface by a NMOS switch which provide the level shifter and, thanks to its relative high internal impedance, protects the Smart Card in the event of data collision. Such a situation could occurs if either the MPU of the smart card forces a signal in the opposite logic level direction. Input Schmitt Triggers All the Logic Input pins have built–in Schmitt trigger circuits to prevent the NCN6000 against uncontrolled operation. The typical dynamic characteristics of the related pins are depicted in Figure 10. The output signal is guaranteed to go High when the input voltage is above 0.70*Vbat, and will go Low when the input voltage is below 0.30*Vbat. CRD_VCC Vbat Output Q1 Q2 Vbat 20 k 20 k 200 ns 200 ns I/O ON CRD_IO Q3 OFF Q4 LOGIC GND Seq 1 0.70 *Vbat CARD ENABLE 0.30 *Vbat Input Vbat Figure 24. Typical Schmitt Trigger Characteristic Figure 23. Basic Internal I/O Level Shifter http://onsemi.com 25 NCN6000 Interrupt Function The NCN6000 flags the external microprocessor by pulling down the INT signal provided in pin 9. This signal is activated by one of the here below referenced operations. Table 5. Interrupt Functions Pin Related Clear Function STATUS Pin 5 Card Insertion and Extraction 11 Positive Going Chip Select, or logical combination of Chip Select Low and PWR_ON Positive Going High = Card Presents Low = No Card Inserted DC/DC Converter Overloaded 15 Positive Going Chip Select, or logical combination of Chip Select Low and PWR_ON Positive Going High = DC/DC Operates Normally Low = Output CRD_VCC Overloaded Security Features limited to 15 mA. The CRD_VCC pin has the same ESD protection, but can source up to 55 mA continuously, the absolute maximum current being 85 mA. In order to protect both the interface and the external smart card, the NCN6000 provides security features to prevent catastrophic failures as depicted here after. Pin Current Limitation: In the case of a short circuit to ground, the current forced by the device is limited to 15 mA for any pins, except CRD_CLK pin. No feedback is provided to the external MPU. DC/DC Operation: The internal circuit continuously senses the CRD_VCC voltage and, in the case of either over or undervoltage situation, update the STATUS register accordingly. This register can be read out by the MPU. Battery Voltage: Both the Over and Undervoltage are detected by the NCN6000, a POWER_DOWN sequence and the STATUS register being updated accordingly. The external MPU can read the STATUS pin to take whatever is appropriate to cope with the situation. Parallel Operation When two or more NCN6000 operate in parallel on a common digital bus, the Chip Select pin allows the selection of one chip from the bank of the paralleled devices. Of course, the external MPU shall provide one unique CS line for each of the NCN6000 considered interfaces. When a given interface is selected by CS = L, all the logic inputs becomes active, the chip can be programmed or/and the external card can be accessed. When CS = H, all the input logic pins are in the high impedance state, thus leaving the bus available for other purpose. On the other hand, when CS = H, the CRD_IO and CRD_RST hold the previous I/O and RESET logic state, the CRD_CLK being either active or stopped, according to the programmed state forced by the MPU. ESD Protection The NCN6000 includes silicon devices to protect the pins against the ESD spikes voltages. To cope with the different ESD voltages developed across these pins, the built–in structures have been designed to handle either 2.0 kV, when related to the microcontroller side, or 4.0 kV when connected with the external contacts. Practically, the CRD_RST, CRD_CLK, VRD_IO and CRD_DET pins can sustain 4.0 kV, the maximum short circuit current being Printed Circuit Board Layout Since the NCN6000 carries high speed currents together with high frequency clock, the printed circuit board must be carefully designed to avoid the risk of uncontrolled operation of the interface. A typical single–sided PCB layout is provided in Figure 25 highlighting the ground technique. http://onsemi.com 26 NCN6000 2335 mis (60 mm) SMARTCARD ISO CONTACTS MPU 2760 mis (70 mm ) U1 NCN6000 +Vbat C4 CLK Vsupply RST C8 I/O VPP GND GROUND Figure 25. Typical Single Sided Printed Circuit Board Layout The card socket uses a low cost ISO only version, all the parts being located on the Component side. Connector J3 makes reference to the microcontroller used by the final application. Of course, connector is not necessary and standard copper tracks might be used to connect the MPU to the NCN6000 interface chip. http://onsemi.com 27 +5 V C1 U2 C15 100 nF P02 21 GND 10 C4 22 pF 1 A1 2 PGM 3 PWR_ON 4 STATUS 5 CS 6 RESET 7 8 I/O RX 9 TX 10 U1 20 A0 Vbat A1 Lout_H PGM Lout_L PWR_ON STATUS CS 10 µF/10 V 19 18 GND L1 47 µF 17 PWR_GND 16 CRD_VCC I/O 14 CRD_IO 13 CRD_CLK 12 CRD_RST 11 CRD_DET INT CLOCK_IN GND 15 RESET 17 18 8 4 Swa Swb C8 C4 CLK 14 7 C11 100 nF U5 MC78L05CG +5 C12 100 nF GND U4 MAX202 2 +5 V Vin GND 3 1 B C14 100 µF 25 V + GND 1 2 6 7 POWER SUPPLY 1 2 8 9 J2 RS232 3 GND 3 15 16 4 GND TP5 1 RST 6 5 RESET 2 C13 100 nF SW4 GND 5 8 R3 10 R +5 3 DET TP3 1 2 + 3 13 C8 2.2 µF 10 V C10 100 nF VCC 1 IN RESET GND RST TP2 1 1 2 CLK J1 SMARTCARD VPP U3 M34164 GND C9 100 nF I/O ISO7816 4 1 R2 220 R I/O 11 10 9 12 IRQ1 5 IRQ0 CLOCK +5 TP4 1 NCN6000 Z86E136 R1 4.7 k VCC TP1 1 GROUND 7 Figure 26. 28 http://onsemi.com 11 P31 12 P32 13 P33 14 P34 A0 GND NCN6000 P01 19 P00 18 P30 17 P36 16 P37 15 P35 XTAL1 GND 23 22 20 Y1 8 MHz C3 22 pF C2 + 26 25 24 3.3 µF/10 V C7 +5 P23 P22 P21 P20 P03 GND 100 nF 27 3.3 µF/10 V C6 GND P24 28 3.3 µF/10 V C5 1 P25 2 P26 3 P27 4 P04 5 P05 6 P06 7 P07 8 V 9 CC XTAL2 29 Figure 27. http://onsemi.com 15 16 CRD_RST 12 CRD_DET 11 CRD_IO 14 CRD_CLK 13 CRD_VCC GROUND PWR_GND 17 GND 2 3 14 S2 2–>3 13 S1 1 2 3 3 1 4 3 5 1 2 1 2 J6 RS232 GND CLOCK_IN INT I/O RESET CS STATUS PWR_ON I/O 1 TP1 1 J4 GROUND 10 9 8 7 6 5 L2 22 µF 1 1 TP7 1 TP3 1 J1 SMARTCARD GND RST CLK TP5 VCC 1 GND J1 SMARTCARD 17 18 Swb 4 VCC GND 8 RST VPP CLK I/O C4 C8 3–>2 POWER SUPPLY GND Swa J3 GROUND 8 GND 2 12 3 9 2 7 1 10 + 2 GND C12 100 nF Lout_L 18 C10 C19 10 µF/ 25 V GND 15 PGM 10 µF/10 V TP7 TP3 GND RST CLK TP5 VCC 1 GND C12 GND C20 1 F 11 J5 +5 16 4 Lout_H C6 22 µF/10 V GND RESET GND 6 A1 19 GND 6.8 µF/10 V D1 U7 +5V MC78L05CG 2 1 +5 V Vin R5 1k C15 330 nF 2 3 Vbat 8 +5 SW1 5 A0 100 nF 6 GND 3 2 C8 + C4 C11 100 nF 20 I/O NCN6000 4 CLK R4 10 R C14 330 nF 1 7 C8 VPP 4 +5 V RST 3 1 U3 8 U6 MAX202 GND RESET 4 U5 74VHC1G32 I/O TP1 1 VCC GND 1 CRD_RST 12 CRD_DET 11 GND Swb + 8 MHz IN 2 CS_2 CLOCK CLOCK_IN INT 15 CRD_IO 14 CRD_CLK 13 CRD_VCC 16 10 µF/10 V C5 100 nF 18 C3 2.2 µF/ 10 V +5 1 11 TX 10 I/O RESET GROUND PWR_GND 17 L1 22 µF + 3 2 Y1 U4 MC34164 P37 P30 IRQ0 9 8 7 CS STATUS PWR_ON Lout_L 18 19 20 17 R3 220 R P33 P32 12 RX I/O RESET 6 5 STATUS CS_1 4 PWR_ON Lout_H A1 PGM Vbat 2 IRQ1 10 P31 GND R1 4.7 k 3 PGM NCN6000 A0 1 R2 4.7 k GND 9 15 16 17 18 19 P01 14 13 P00 P02 GND P20 P21 P22 P23 2 A1 1 C9 8 XTAL1 XTAL2 VCC P27 P26 P25 P24 20 A0 C11 C4 22 pF 7 6 5 4 3 2 1 U2 Z86E126 C7 22 µF/10 V C3 22 pF +5 +5 6.8 µF/10 V GND C2 100 nF C1 4.7 F/6 V + U2 1 TP9 DET 1 TP9 DET NCN6000 Swa 6 7 8 1 6 7 8 9 NCN6000 PACKAGE DIMENSIONS TSSOP–20 TBD CASE 948E–02 ISSUE A 20X 0.15 (0.006) T U 2X K REF 0.10 (0.004) S L/2 20 M T U S V S K K1 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ 11 J J1 B –U– L PIN 1 IDENT SECTION N–N 1 10 0.25 (0.010) N 0.15 (0.006) T U S M A –V– NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. N F DETAIL E –W– C D G H DETAIL E 0.100 (0.004) –T– SEATING PLANE http://onsemi.com 30 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 NCN6000 Notes http://onsemi.com 31 NCN6000 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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