RENESAS HA13173H

HA13173H
Multiple Voltage Regulator for Car Audio
REJ03F0226-0100
Rev.1.00
Jan 16, 2007
Description
The HA13173H is a multiple voltage regulator for car audio system. This IC has 5.0 V output for a microcontroller, 3.3
V output for a Digital Signal Processor, 8.0 V output for CD driver, 8.4 V output for audio control, 8.4 V output for
illuminations, and high side switch output for external output.
The HA13173H also has FREG that is possible to control external PNP transistor. It is adjustable output voltage by
changing an external resistor.
Functions
•
•
•
•
•
•
•
Standby current is 100 µA max.
The Vdd output for microcontroller has backup function, by independent power supply line.
Low saturation output (PNP output) used for audio output.
Output current limit circuit to avoid device destruction caused by shorted output, etc.
High surge input protector against VB and VBUP.
Built in a thermal shutdown circuit to prevent against the thermal destruction.
The package is PRSS0015DA-C (SP-15TGV).
Rev.1.00 Jan 16, 2007 page 1 of 23
HA13173H
Pin Description
Pin
No.
Protection
Pin Name
Specification
1
GND
Ground
Normal
—
2
3
FREG_B
FREG_F
External transistor bias operation
FREG feed back terminal
On/Off
On/Off
On/Off
On/Off
Off
Off
Off
Off
4
5
ILM OUT
CTL4
8.4 V output for ILM/500 mA max
FREG control terminal
On/Off
—
Off
—
Off
—
Off
—
6
7
CD OUT
DSP OUT
8.0 V output for CD/1.3 A max
3.3 V output for DSP/250 mA max
On/Off
On/Off
Off
Off
Off
Off
Off
Off
8
9
VB
CTL3
Battery
ILM control terminal
—
—
—
—
—
—
—
—
10
11
AUDIO OUT
CTL1
8.4 V output for AUDIO/500 mA max
DSP, CD, AUDIO control terminal
On/Off
—
Off
—
Off
—
Off
—
12
13
EXT OUT
CTL2
High side output/600 mA max
EXT control terminal
On/Off
—
Off
—
Off
—
Off
—
14
15
VDD OUT
VBUP
5.0 V output for microcontroller
Back up
On
—
On
—
On
—
Off
—
Rev.1.00 Jan 16, 2007 page 2 of 23
TSD ON
—
VB = 24 V
—
VB = 50 V
—
HA13173H
Equivalent Circuit
VB
5 kΩ
Pin 2 (FREG_B)
100 Ω
Pin 3 (FREG_F)
10 kΩ
VB
VB
Pin 4 (ILMOUT)
Pin 6 (CDOUT)
71 kΩ
67 kΩ
13 kΩ
13 kΩ
VB
VB
Pin 10 (AUDIOOUT)
Pin 7 (DSPOUT)
71 kΩ
20 kΩ
13 kΩ
13 kΩ
VB
10
kΩ
Pin 12 (EXTOUT)
94 kΩ
Pin 5 (CTL4)
Pin 9 (CTL43)
Pin 13 (CTL2)
90
kΩ
100
kΩ
30
kΩ
6 kΩ
VBUP
10
kΩ
Pin 14 (VDDOUT)
37 kΩ
15 kΩ
Rev.1.00 Jan 16, 2007 page 3 of 23
90
kΩ
90
kΩ
Pin 11 (CTL1)
75
kΩ
30
kΩ
30
kΩ
HA13173H
Timing Chart
Load dump
21 V
VB
0V
26 V
τ = CBUP × 300 Ω
VBUP
5.5 V
0V
5V
VDDOUT
L
CTL1
H
M
L
8.4 V
AUDIOOUT
0V
3.3 V
DSPOUT
0V
8.0 V
CDOUT
0V
H
CTL2
L
VB
EXTOUT
0V
H
CTL3
L
8.4 V
ILMOUT
0V
CTL4
Variable
FREG
(VOUT)
0V
Limiter
FREG_B
(IB)
0A
Rev.1.00 Jan 16, 2007 page 4 of 23
to maximum current, because impossible to sense
saturation of external Trs.
HA13173H
Block Diagram
+B
+
C1
100 µF
DBUP
VB
C2
0.1 µF
8
+
−
CTL1
Over voltage detect
3.5 V
11
+
−
1.5 V
CTL2
13
+
−
9
5
−
+
14
+
−
+
−
−
+
2.5 V
7
DEXT1
EXT OUT
+
DEXT2
−
+
VREF
+
−
6
DSP OUT
+
CDSP
10 µF
CD OUT
4
−
+
10
FREG_B
−
+
2
RFREG3
CFREG
10 µF
+
CVDD
10 µF
CCD
0.1 µF
VREF
+
−
CILM
0.1 µF
QFREG
VDD OUT
12
CEXT
10 µF
ILM OUT
+
CBUP
100 µF
VREF
2.5 V
CTL4
VBUP
TSD
BIAS
2.5 V
CTL3
15
+
RFREG1
3
FREG_F
RFREG2
Note: TAB (header of IC) connected to GND.
Rev.1.00 Jan 16, 2007 page 5 of 23
1
GND
TAB
GND
AUDIO OUT
+
CAUDIO
10 µF
HA13173H
External Parts Lineup
Parts
No.
Function
Range of
Recommended
Operation with Different Value from the
Range of Recommended Value
More than the Range
—
Less than the Range
Unstable
Lower ripple rejection
ratio
C1
Bypass capacitor
Upper 100 µF
C2
CBUP
To prevent oscillation
B backup capacitor
0.1 µF
0.1 to 1000 µF
Stability improve
Backup time becomes
long
Unstable
Unstable
CCD
CILM
CVDD
CDSP
CAUDIO
CFREG
CEXT
To prevent oscillation
0.1 to 1000 µF
Unconfirmed
Unstable
To prevent oscillation
0.1 to 470 µF
Unconfirmed
Unstable
IF ≥ 200 mA
IF ≥ 1 A
Be careful of the maximum rating
—
Be careful of the
maximum rating. The
ability to protect
terminal lower. And
there is some
possibility of
destruction.
DBUP
DEXT1
DEXT2
Protection against mistake in joining.
Terminal protection for short circuit to
+B when VCC terminal is open and
for short circuit to GND when GND
terminal is open.
We recommend Schottky barrier
diodes.
RFREG1
RFREG2
GFREG3
Output voltage = (1 +
RFREG1/RFREG2) × 1.26 V
Resistance for limiting base current of
PNP transistor
100 to 10 kΩ
Unstable
Loss of current
increases
Choose resistance by a required output current value and hFE of
PNP transistor
QFREG
Output PNP transistor for FREG
(We recommend Renesas 2SB857.)
hFE = 50 to 200
Choose resistance by a required output current
value and hFE of PNP transistor
Unstable
Lower output current
capability
Notes: 1. We recommend Polyester film capacitor. To improve stability, take notes of the below precautions.
(1) Use capacitor that is temperature independent.
(2) Use capacitor that is bias voltage independent.
(3) In order to bypass high frequency noise efficiently, mount the capacitor as close as possible to the VCC
and GND of IC to eliminate PCB pattern inductance.
2. For using of the lower limit of recommended value, take notes of the below precautions.
(1) Use capacitor that is temperature independent.
(2) Use capacitor that is bias voltage independent.
(3) To eliminate PCB pattern inductance mount the capacitor as close as possible to the output pin and
GND of IC.
3. To improve stability, take notes of the below precautions.
(1) Use capacitor that is temperature independent.
(2) Use capacitor that is bias voltage independent.
(3) ESR needs to be less than 10 Ω in all the temperature ranges to be used.
(4) To eliminate PCB pattern inductance mount the capacitor as close as possible to the output pin and
GND of IC.
Rev.1.00 Jan 16, 2007 page 6 of 23
HA13173H
Absolute Maximum Ratings
(Ta = 25°C)
Item
Operating power supply voltage 1
Symbol
Rating
19
Unit
V
Note
Vcc1
Operating power supply voltage 2
Peak voltage
Vcc2
Vcc(PEAK)
24
50
V
V
1
2
Power dissipation
Junction temperature
Pd
Tj
36
150
W
°C
3
Operating temperature
Storage temperature
Topr
Tstg
–40 to +85
–55 to +125
°C
°C
Notes: Recommended power supply voltage range 10 to 16 V.
1. Applied time is less than 60 s.
2. Surge pulse as input.
3. Ta = 25°C. : Permissible power dissipation when using a heat sink of infinite area. Refer to the derating
curves below.
Power dissipation Pd (W)
20
15
thin = 1.6 mm, 100 cm Aluminum heat sink
11.0 W
thin = 1.6 mm, 50 cm Aluminum heat sink
10
8.7 W
5
w/o heat sink
1.8 W
0
0
25
50
75
100
125
Ambient temperature Ta (°C)
Rev.1.00 Jan 16, 2007 page 7 of 23
150
175
HA13173H
Electrical Characteristics
Item
Standby current
Symbol
IST
Min
Typ
Max
Unit
—
65
100
µA
CTL1 L level (DSP, AUDIO, CD OFF)
VC1L
0.0
—
1.0
V
CTL1 M level (DSP, AUDIO ON, CD OFF)
VC1M
2.0
—
3.0
V
CTL1 H level (DSP, AUDIO, CD ON)
VC1H
4.0
—
6.0
V
CTL2 L level (EXT OFF)
VC2L
0.0
—
2.0
V
CTL2 H level (EXT ON)
VC2H
3.0
—
6.0
V
CTL3 L level (ILM OFF)
VC3L
0.0
—
2.0
V
Test Condition
CTL1, 2, 3, 4 = 0 V
CTL3 H level (ILM ON)
VC3H
3.0
—
6.0
V
CTL4 L level (FREG OFF)
VC4L
0.0
—
2.0
V
CTL4 H level (FREG ON)
VC4H
3.0
—
6.0
V
VDD
OUT
Output voltage
Vo1
4.75
5.00
5.25
V
Voltage regulation
∆Vo11
—
10
50
mV
Vcc = 10 to 16 V, Io1 = 160 mA
Load regulation
∆Vo12
—
50
100
mV
Io1 = 0 to 160 mA
Minimum I/O voltage
differential
∆Vo13
—
0.4
0.9
V
Io1 = 160 mA
Output current capacity
Io1
200
400
—
mA
Vo1 ≥ 4.75 V
f = 100 Hz, Io1 = 160 mA
CD
OUT
AUDIO
OUT
DSP
OUT
ILM
OUT
Io1 = 160 mA
Ripple rejection ratio
SVR1
45
55
—
dB
Output voltage
Vo2
7.6
8.0
8.4
V
Voltage regulation
∆Vo21
—
40
100
mV
Vcc = 10 to 16V, Io2 = 1.0 A
Load regulation
∆Vo22
—
70
150
mV
Io2 = 10m to 1.0 A
Minimum I/O voltage
differential
∆Vo23
—
1.0
1.5
V
Output current capacity
Io2
1.3
2.0
—
mA
Vo2 ≥ 7.6 V
Ripple rejection ratio
SVR2
40
50
—
dB
f = 100 Hz, Io2 = 1.0 A
Output voltage
Vo3
8.1
8.4
8.7
V
Voltage regulation
∆Vo31
—
30
90
mV
Vcc = 10 to 16 V, Io3 = 400 mA
Load regulation
∆Vo32
—
100
200
mV
Io3 = 10 to 400 mA
Minimum I/O voltage
differential
∆Vo33
—
0.4
0.9
V
Output current capacity
Io3
500
850
—
mA
Vo3 ≥ 8.1 V
f = 100 Hz, Io3 = 400 mA
Io2 = 1.0 A
Io2 = 1.0 A
Io3 = 400 mA
Io3 = 400 mA
Ripple rejection ratio
SVR3
45
50
—
dB
Output voltage
Vo4
3.1
3.3
3.5
V
Voltage regulation
∆Vo41
—
40
100
mV
Vcc = 10 to 16 V, Io4 = 200 mA
Load regulation
∆Vo42
—
50
100
mV
Io4 = 0 to 200 mA
Output current capacity
Io4
250
500
—
mA
Vo4 ≥ 3.1 V
Ripple rejection ratio
SVR4
45
55
—
dB
f = 100 Hz, Io4 = 200 mA
Output voltage
Vo5
8.0
8.4
8.8
V
Voltage regulation
∆Vo51
—
40
100
mV
Vcc = 10 to 16 V, Io5 = 400 mA
Load regulation
∆Vo52
—
70
150
mV
Io5 = 10 to 400 mA
Minimum I/O voltage
differential
∆Vo53
—
1.0
1.3
V
Io4 = 200 mA
Io5 = 400 mA
Io5 = 400 mA
Output current capacity
Io5
500
900
—
mA
Vo5 ≥ 8.0 V
Ripple rejection ratio
SVR5
40
50
—
dB
f = 100 Hz, Io5 = 400 mA
EXT
OUT
Minimum I/O voltage
differential
∆Vo61
—
0.6
1.0
V
Vcc = 10 to 16 V, Io6 = 480 mA
Output current capacity
Io6
600
900
—
mA
FREG
OUT
FREG_F Output voltage
VFF7
1.20
1.26
1.32
V
FREG_F Voltage regulation
∆VFF71
—
10
25
mV
Vcc = 10 to 16 V, Iload = 400 mA
FREG_F Load regulation
∆VFF72
—
10
25
mV
Iload = 10 to 400 mA
FREG_B Output current
capacity
IFB7
35
50
80
mA
VFF ≥ 1.20 V
FREG_F input bias current
IFF7
—
50
300
nA
Rev.1.00 Jan 16, 2007 page 8 of 23
Vo61 ≤ 1.0 V
Iload (external PNP) = 400 mA
HA13173H
Evaluation Circuit
HA13173H
ILM
GND FREG_B FREG_F OUT
1
2
3
4
CTL4
5
CD
OUT
6
RL2
RL5
QFREG
2SB857
FREG
CFREG1
10 µF
+
Io5
Io2
ILM
RL7
AUDIO
OUT CTL1
10
11
EXT
OUT
12
CAUDIO
+
10
µF
Io4
Io3
DSP
CTL2
13
VDD
OUT
14
CEXT
+
10
µF
RL3
RL4
CD
RFREG1
1.6 kΩ
RFREG2
1 kΩ
CTL3
9
CDSP
+
0.1
10
µF
µF
0.1
µF
IFF7
VB
8
CCD
CILM
IFB7
DSP
OUT
7
CVDD
+
10
µF
RL6
Io6
AUDIO
RL1
Io1
EXT
VDD
SW4
SW3
Iload
SW2
SW5 ON
C1
100 µF
CTL4
Rev.1.00 Jan 16, 2007 page 9 of 23
+
C2
0.1 µF
VB
CTL3
SW1
CTL1
VBUP
15
OFF R1
200 kΩ
CTL2
HA13173H
Main Characteristics
Standby Current vs. Tc
100
VB = 14.4 V,
90 CTL1,2,3,4 = 0 V
80
70
Ist (µA)
60
50
40
30
20
10
0
–50
0
50
100
150
200
Tc (°C)
CTL-Vth vs. Tc
4.0
3.5
3.0
Vo (V)
2.5
2.0
1.5
1.0
CTL1(M)
CTL1(H)
CTL2
CTL3
CTL4
0.5
0
–50
Rev.1.00 Jan 16, 2007 page 10 of 23
0
50
Tc (°C)
100
150
HA13173H
VDD Output Voltage vs. Tc
5.25
VB = 14.4 V,
5.20 Io = 160 mA
5.15
5.10
Vo (V)
5.05
5.00
4.95
4.90
4.85
4.80
4.75
–50
0
50
Tc (°C)
100
150
100
150
CD Output Voltage vs. Tc
8.4
VB = 14.4 V,
Io = 1.0 A
8.3
8.2
Vo (V)
8.1
8.0
7.9
7.8
7.7
7.6
–50
Rev.1.00 Jan 16, 2007 page 11 of 23
0
50
Tc (°C)
HA13173H
Audio Output Voltage vs. Tc
8.7
VB = 14.4 V,
Io = 400 mA
8.6
Vo (V)
8.5
8.4
8.3
8.2
8.1
–50
0
50
Tc (°C)
100
150
100
150
DSP Output Voltage vs. Tc
3.50
VB = 14.4 V,
Io = 200 mA
3.45
3.40
Vo (V)
3.35
3.30
3.25
3.20
3.15
3.10
–50
Rev.1.00 Jan 16, 2007 page 12 of 23
0
50
Tc (°C)
HA13173H
ILM Output Voltage vs. Tc
8.8
VB = 14.4 V,
Io = 400 mA
8.7
8.6
Vo (V)
8.5
8.4
8.3
8.2
8.1
8.0
–50
0
50
Tc (°C)
100
150
EXT Output Remainder Voltage vs. Tc
1.0
VB = 14.4 V,
Io = 480 mA
0.8
Vo (V)
0.6
0.4
0.2
0
–50
Rev.1.00 Jan 16, 2007 page 13 of 23
0
50
Tc (°C)
100
150
HA13173H
FREG_F Terminal Voltage vs. Tc
1.32
VB = 14.4 V
1.30
Vo (V)
1.28
1.26
1.24
1.22
1.20
–50
0
50
Tc (°C)
100
150
SVR vs. Tc
65
VB = 14.4 V,
vrip = 0 dBm,
frip = 100 Hz
60
SVR (dB)
55
50
45
VDD(0.16A)
CD(1A)
Audio(0.4A)
DSP(0.2A)
ILM(0.4A)
40
35
–50
Rev.1.00 Jan 16, 2007 page 14 of 23
0
50
Tc (°C)
100
150
HA13173H
SVR vs. f
70
VB = 14.4 V,
vrip = 0 dBm
60
SVR (dB)
50
40
30
20
VDD
CD
Audio
DSP
ILM
10
0
10
100
1000
f (Hz)
10000
100000
SVR vs. Io
70
VB = 14.4 V,
vrip = 0 dBm,
frip = 100 Hz
65
SVR (dB)
60
55
50
VDD
CD
Audio
DSP
ILM
45
40
0
500
1000
Io (mA)
Rev.1.00 Jan 16, 2007 page 15 of 23
1500
HA13173H
Vo-Io Characteristics VDD Output
6
VB = 14.4 V
5
Vo (V)
4
3
2
1
100°C
25°C
–40°C
0
0
200
400
600
Io (mA)
Vo-Io Characteristics CD Output
9
VB = 14.4 V
8
7
Vo (V)
6
5
4
3
2
100°C
25°C
–40°C
1
0
0
1
2
Io (A)
Rev.1.00 Jan 16, 2007 page 16 of 23
3
HA13173H
Vo-Io Characteristics Audio Output
9
VB = 14.4 V
8
7
Vo (V)
6
5
4
3
2
100°C
25°C
–40°C
1
0
0
500
1000
1500
Io (mA)
Vo-Io Characteristics DSP Output
4.0
VB = 14.4 V
3.5
3.0
Vo (V)
2.5
2.0
1.5
1.0
0.5
0
100°C
25°C
–40°C
0
200
400
Io (mA)
Rev.1.00 Jan 16, 2007 page 17 of 23
600
HA13173H
Vo-Io Characteristics ILM Output
9
8
7
Vo (V)
6
5
4
3
2
100°C
25°C
–40°C
1
VB = 14.4 V
0
0
200
400
600
800
Io (mA)
1000
1200
1400
Vo-Io Characteristics EXT Output
16
VB = 14.4 V
100°C
25°C
–40°C
14
12
Vo (V)
10
8
6
4
2
0
0
300
600
900
Io (mA)
Rev.1.00 Jan 16, 2007 page 18 of 23
1200
1500
HA13173H
VFB-IB Characteristics FREG Output
1.4
VB = 14.4 V
1.2
VFB (V)
1.0
0.8
0.6
0.4
0.2
0
100°C
25°C
–40°C
0
Rev.1.00 Jan 16, 2007 page 19 of 23
20
40
IB (mA)
60
80
HA13173H
Handling Cautions (SP-15TGV Package)
Mounting
1. For mounting the package on the heat sink, 4 to 8 kg⋅cm of screwing-torque is recommended; excessive torque will
cause device deformation, resulting in pellet-crack, connector-lead-wire-breaking, etc., and too less torque will
increase the heat resistance.
2. The use of screws needs the following cautions.
1) Use the standardized binding-head screws.
2) Ova counter-sunk screws, subjecting the IC to intense stress, must not be used.
3) To the use of tapping screws the cautions for binding torque strength must be applied.
4) Use a tapping screw diameter smaller than an IC mounting-hole.
Binding-head screw
Small-head screw
Recommended Screw
Flat-head screw
Oval counter-sunk screws
Unused Screws
3. In IC binding, metal-fittings striking on the plastic of the IC may cause characteristics-deterioration or packagecrack.
4. Poor flatness of heat sink sometimes prevents effective heat-sinking or subjects the IC surface to intense stress,
causing characteristics-deterioration or package-crack.
1) 0.1 mm max. of heat-sink flatness error for the contact area (14.3 mm × 19.66 mm) will be tolerated.
2) Contact-surface ruggedness should be finished in ∇∇ grade.
3) For aluminum, copper, or iron plates, check them for no burr and mold them for screw-holes.
4) Cutting chips between the IC header and the heat sink will cause heat-sinking deterioration.
5) The heat-sink hole diameter should not exceed 4.0 mm.
5. As silicone grease, the Shin-Etsu Chemical Industry G746 is recommended. Coarse or an excessive amount of
grease may cause intensive stress to the IC, when binding.
6. Do not Screw the IC on the heat sink after soldering the lead wires on the printed circuit board (PCB). If the IC is
screwed after the lead wires are soldered on the PCB then characteristics of the IC may deteriorate in the cause of
large strain concentrate to the lead wires because of dimension-difference of the PCB and the heat sink.
7. Do not solder of lead wires to the header of the IC on direct. If you solder direct then the IC life characteristics will
deteriorate remarkably with bad-influence on the die.
For the method and conditions of lead-wire forming, users are requested to contact the vendor.
Rev.1.00 Jan 16, 2007 page 20 of 23
HA13173H
8. Header of IC (TAB) have to connect to GND.
For mounting the header of IC on the heat sink with the screw, heat sink have to connect to GND. When header of
IC mount with heat sink with holding parishes conductive material, holding parts have to connect to GND. At this
time, the holding parts mount with heat sink with the screw, or it must connect to header of IC. If users have
question or request, please contact the vendor.
Example of Recommendation about the Method of Connecting Header of IC to GND
Bad example
There is a crevice or
the insulator is inserted.
NG
Header of IC and GND
are not connected.
NG
Header of IC is not
connected to GND.
NG
There is no heat sink.
9. Soldering should be done within the soldering heat test standard of the IC, specifying that the lead wires, up to 1 to
1.5 mm off the IC body, are kept in solder at 260°C for 10 seconds (2 or less times) and at 350°C for 3 seconds.
Therefore give careful consideration in order to do not exceed the condition. In a soldering iron is used, use a
soldering iron grounded and do not leak at the tip.
Characteristics
1. When there may be the mode which VB, VBUP or GND, and each output reverse with a normal potential state in
application, it recommends attaching a diode for IC protection. When outputting the terminal of IC to the direct set
exterior, a diode is required in order to protect IC from incorrect contact on a battery and a GND line. Especially
EXTOUT is required.
2. In the parts shown in external part lineup, the value of a capacitor is the minimum value required in order to secure
the oscillation stability of IC. Please use the capacitor independent of temperature and bias. Moreover, please use
the capacitor whose ESR is 10 Ω or less in the operating temperature range.
Rev.1.00 Jan 16, 2007 page 21 of 23
HA13173H
Protections
1. Overvoltage protection circuit
The overvoltage protection circuit (surge protector) turns off all outputs without Vdd, when VB voltage is more than
about 21 V.
And the overvoltage protection circuit (surge protector) turns off Vdd output with other all outputs, when VB
voltage is more than about 26 V.
The VB ≥ 18 V condition, the stand by current increases.
2. Overcurrent protection circuit
FREG_B (pin 2), ILM OUT (pin 4), CD OUT (pin 6), DSP OUT (pin 7), AUDIO OUT (pin 10), EXT OUT (pin 12),
VDD OUT (pin 14) output circuits are built-in overcurrent protection circuit, based on the respective output current.
3. Thermal protection circuit
A built-in thermal protection circuit (TSD: Thermal Shut Down) prevents thermal damage to the IC.
All outputs except VDD (pin 14) and FREG (pin 2, 3) are switched off when the circuit operates, revert to the
original state when the temperature drops to a certain level.
4. FREG operation
FREG function needs external PNP transistor, feedback resistor, stability capacitor. If the external transistor
become saturation level, the base current depend on IC specification, that is FREG_B (pin 2) maximum current
specification.
5. We recommend to mount a bypass diode in your application if there is a mode where potential difference between
each output and VB (pin 8), VBUP (pin 15) or GND (pin 1) is reversed from the normal state.
6. Header of IC (TAB) have to connect to GND.
For mounting the header of IC on the heat sink with the screw, heat sink have to connect to GND. When header of
IC mount with heat sink with holding parts (use conductive material), holding parts have to connect to GND.
At this time, the holding parts mount with heat sink with the screw, or it must connect to header of IC.
If users have question or request, please contact the vendor.
7. Soldering should be done within the soldering heat test standard of the IC, specifying that the lead wires, up to 1 to
1.5 mm off the IC body, are kept in solder at 260°C for 10 s and at 350°C for 3 s. Therefore give careful
consideration in order to do not exceed the condition. In a soldering iron is used, use a soldering iron grounded and
do not leak at the tip.
8. To keep stability regulation
The stability capacitor should be no temperature dependability and no bias voltage dependability.
ESR level should be bellow 10 W all temperature range.
Rev.1.00 Jan 16, 2007 page 22 of 23
HA13173H
Package Dimensions
JEITA Package Code
P-HSIP15-14.3x19.66-1.27
RENESAS Code
PRSS0015DA-C
Previous Code
SP-15TGV
MASS[Typ.]
3.0g
Unit : mm
20.5 MAX
19.66
19.0
3.3MiN
±0.3
2-C3.0
±0.2
3.5 TYP 3.8MAX
1.1MiN 1.28 TYP 1.50MAX
±0.2
17.9
7.8
13.8
11.3 ±0.3
3.0
±0.2
φ 3.6
1.11±0.25
0.6
±0.1
1.27
±0.25
2.54
*1
±0.25
0.25
*1
+0.10
-0.05
1.8 ±0.25
3.5
±0.5
6.04
*1
±0.5 *1
Note) 1. Dimension "*1" is the value after bending.
( Ni/Pd/Au plating )
Rev.1.00 Jan 16, 2007 page 23 of 23
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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