NCP1611 Enhanced, High-Efficiency Power Factor Controller The NCP1611 is designed to drive PFC boost stages based on an innovative Current Controlled Frequency Fold−back (CCFF) method. In this mode, the circuit classically operates in Critical conduction Mode (CrM) when the inductor current exceeds a programmable value. When the current is below this preset level, the NCP1611 linearly decays the frequency down to about 20 kHz when the current is null. CCFF maximizes the efficiency at both nominal and light load. In particular, the stand−by losses are reduced to a minimum. Like in FCCrM controllers, internal circuitry allows near−unity power factor even when the switching frequency is reduced. Housed in a SO−8 package, the circuit also incorporates the features necessary for robust and compact PFC stages, with few external components. http://onsemi.com MARKING DIAGRAM 8 8 1 1 • Near−Unity Power Factor • Critical Conduction Mode (CrM) • Current Controlled Frequency Fold−back (CCFF): Low Frequency Operation is Forced at Low Current Levels PIN CONNECTIONS • On−time Modulation to Maintain a Proper Current Shaping in CCFF • • • • • • • • • NCP1611x ALYW G NCP1611x = Specific Device Code x = A or B A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package Features Mode Skip Mode Near the Line Zero Crossing Fast Line / Load Transient Compensation (Dynamic Response Enhancer) Valley Turn on High Drive Capability: −500 mA / +800 mA VCC Range: from 9.5 V to 35 V Low Start−up Consumption A Version: Low VCC Start−up Level (10.5 V), B Version: High VCC Start−up level (17.0 V) Line Range Detection This is a Pb−Free Device SOIC−8 CASE 751 SUFFIX D Vcontrol 1 Feedback Vsense VCC FFcontrol DRV CS/ZCD GND (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 27 of this data sheet. Safety Features • • • • • • • • Non−latching, Over−Voltage Protection Brown−Out Detection Soft−Start for Smooth Start−up Operation (A version) Over Current Limitation Disable Protection if the Feedback Pin is Not Connected Thermal Shutdown Low Duty−Cycle Operation if the Bypass Diode is Shorted Open Ground Pin Fault Monitoring © Semiconductor Components Industries, LLC, 2011 December, 2011 − Rev. 1 Typical Applications • PC Power Supplies • All Off Line Appliances Requiring Power Factor Correction 1 Publication Order Number: NCP1611/D NCP1611 Vin IL L1 Vbulk Ac line R X1 . . D1 Rfb1 Feedback Dzcd R X2 Rbo1 EMI Filter 1 8 2 7 3 6 4 5 Vcc Rz Vbulk R zcd Q1 LOAD Rocp Cin Rbo2 Rfb2 Cz Cp R FF C bulk R sense Figure 1. MAXIMUM RATINGS TABLE Symbol Pin Rating Value Unit VCC 7 Power Supply Input −0.3, + 35 V Vi 2, 3, 4, 8 Input Voltage (Note 1) −0.3, +10 V VCONTROL 1 VCONTROL pin −0.3, VCONTROLMAX* V DRV 6 Driver Votage Driver Current −0.3, VDRV* −500, +800 V mA PD RqJA Power Dissipation and Thermal Characteristics Maximum Power Dissipation @ TA = 70°C Thermal Resistance Junction−to−Air 550 145 mW °C/W TJ Operating Junction Temperature Range −40 to+125 °C TJmax Maximum Junction Temperature 150 °C TSmax Storage Temperature Range −65 to 150 °C TLmax Lead Temperature (Soldering, 10s) 300 °C MSL Moisture Sensitivity Level 3 − ESD Capability, Human Body Model (Note 2) > 4000 V ESD Capability, Machine Model (Note 2) > 200 V ESD Capability, Charged Device Model (Note 2) 2000 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. *“VCONTROLMAX” is the VCONTROL pin clamp voltage. “VDRV” is the DRV clamp voltage (VDRVhigh) if VCC is higher than (VDRVhigh). “VDRV” is VCC unless otherwise noted. 1. When the applied voltage exceeds 5 V, these pins sink about VI * 5 V 4 kW that is about 1.25 mA if VI = 10 V. 2. This device(s) contains ESD protection and exceeds the following tests: Human Body Model 2000 V per JEDEC Standard JESD22−A114E Machine Model Method 200 V per JEDEC Standard JESD22−A115−A Charged Device Model Method per JEDEC Standard JESD22−C101E. 3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78. http://onsemi.com 2 NCP1611 TYPICAL ELECTRICAL CHARACTERISTICS TABLE (Conditions: VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified) Symbol Rating Min Typ Max Unit VCC(on) Start−Up Threshold, VCC increasing: A version B version 9.75 15.80 10.50 17.00 11.25 18.20 VCC(off) Minimum Operating Voltage, VCC falling 8.50 9.00 9.50 VCC(HYST) Hysteresis (VCC (on ) − VCC (off )) A version B version 0.75 6.00 1.50 8.00 − − ICC(start) Start−Up Current, VCC = 9.4 V − 20 50 mA ICC(op)1 Operating Consumption, no switching (Vsense pin being grounded) − 0.5 1.0 mA ICC(op)2 Operating Consumption, 50 kHz switching, no load on DRV pin − 2.0 3.0 mA START−UP AND SUPPLY CIRCUIT V V V CURRENT CONTROLLED FREQUENCY FOLD−BACK TDT1 Dead−Time, VFFcontrol = 2.60 V (Note 4) − − 0 ms TDT2 Dead−Time, VFFcontrol = 1.75 V 14 18 22 ms TDT3 Dead−Time, VFFcontrol = 1.00 V 32 38 44 ms IDT1 FFcontrol pin current, Vsense = 1.4 V and Vcontrol maximum 180 200 220 mA IDT2 FFcontrol pin current, Vsense = 2.8 V and Vcontrol maximum 110 135 160 mA VSKIP−H FFcontrol pin Skip Level, VFFcontrol rising − 0.75 0.85 V VSKIP−L FFcontrol pin Skip Level, VFFcontrol falling 0.55 0.65 − V VSKIP−HYST FFcontrol pin Skip Hysteresis 50 − − mV TR Output voltage rise−time @ CL = 1 nF, 10−90% of output signal − 30 − ns TF Output voltage fall−time @ CL = 1 nF, 10−90% of output signal − 20 − ns ROH Source resistance − 10 − W ROL Sink resistance − 7.0 − W ISOURCE Peak source current, VDRV = 0 V (guaranteed by design) − 500 − mA GATE DRIVE ISINK Peak sink current, VDRV = 12 V (guaranteed by design) − 800 − mA VDRVlow DRV pin level at VCC close to VCC (off ) with a 10 kW resistor to GND 8.0 − − V VDRVhigh DRV pin level at VCC = 35 V (RL = 33 kW, CL = 1 nF) 10 12 14 V VREF Feedback Voltage Reference: from 0°C to 125°C Over the temperature range 2.44 2.42 2.50 2.50 2.54 2.54 IEA Error Amplifier Current Capability − ±20 − mA GEA Error Amplifier Gain 110 220 290 mS VCONTROL −VCONTROLMAX −VCONTROLMIN Vcontrol Pin Voltage − @ VFB = 2 V − @ VFB = 3 V − − 4.5 0.5 − − VOUTL / VREF Ratio (VOUT Low Detect Threshold / VREF ) (guaranteed by design) 95.0 95.5 96.0 % HOUTL / VREF Ratio (VOUT Low Detect Hysteresis / VREF ) (guaranteed by design) − − 0.5 % IBOOST Vcontrol Pin Source Current when (VOUT Low Detect) is activated 180 220 250 mA 450 500 550 mV REGULATION BLOCK V V CURRENT SENSE AND ZERO CURRENT DETECTION BLOCKS VCS(th) Current Sense Voltage Reference 4. There is actually a minimum dead−time that is the delay between the core reset detection and the DRV turning on (TZD parameter of the “Current Sense and Zero Current Detection Blocks” section). http://onsemi.com 3 NCP1611 TYPICAL ELECTRICAL CHARACTERISTICS TABLE (Conditions: VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified) Symbol Rating Min Typ Max Unit CURRENT SENSE AND ZERO CURRENT DETECTION BLOCKS TLEB,OCP Over−Current Protection Leading Edge Blanking Time (guaranteed by design) 100 200 350 ns TLEB,OVS “Overstress” Leading Edge Blanking Time (guaranteed by design) 50 100 170 ns TOCP Over−Current Protection Delay from VCS/ZCD > VCS(th) to DRV low (dVCS/ZCD / dt = 10 V/ms) − 40 200 ns VZCD(th)H Zero Current Detection, VCS/ZCD rising 675 750 825 mV VZCD(th)L Zero Current Detection, VCS/ZCD falling 200 250 300 mV VZCD(hyst) Hysteresis of the Zero Current Detection Comparator 375 500 − mV RZCD/CS VZCD(th)H over VCS(th) Ratio 1.4 1.5 1.6 − VCL(pos) CS/ZCD Positive Clamp @ ICS/ZCD = 5 mA − 15.6 − V IZCD(bias) CS/ZCD Pin Bias Current, VCS/ZCD = 0.75 V 0.5 − 2.0 mA IZCD(bias) CS/ZCD Pin Bias Current, VCS/ZCD = 0.25 V 0.5 − 2.0 mA TZCD (VCS/ZCD < VZCD (th )L ) to (DRV high) − 60 200 ns TSYNC Minimum ZCD Pulse Width − 110 200 ns TWDG Watch Dog Timer 80 200 320 ms TWDG(OS) Watch Dog Timer in “OverStress” Situation 400 800 1200 ms TTMO Time−Out Timer 20 30 50 ms IZCD(gnd) Source Current for CS/ZCD pin impedance Testing − 250 − mA Duty Cycle, VFB = 3 V, Vcontrol Pin Open − − 0 % TON(LL) Maximum On Time, Vsense = 1.4 V and Vcontrol maximum (CrM) 22 25 29 ms TON(LL)2 On Time, Vsense = 1.4 V and Vcontrol = 2.5 V (CrM) 10.5 12.5 14.0 ms TON(HL) Maximum On Time, Vsense = 2.8 V and Vcontrol maximum (CrM) 7.3 8.5 9.6 ms TON(LL)(MIN) Minimum On Time, Vsense = 1.4 V (not tested, guaranteed by characterization) − − 200 ns TON(HL)(MIN) Minimum On Time, Vsense = 2.8 V (not tested, guaranteed by characterization) − − 100 ns STATIC OVP DMIN ON−TIME CONTROL FEED−BACK OVER AND UNDER−VOLTAGE PROTECTIONS (OVP AND UVP) RsoftOVP Ratio (Soft OVP Threshold, VFB rising) over VREF (VsoftOVP /VREF ) (guaranteed by design) 104 105 106 % RsoftOVP(HYST) Ratio (Soft OVP Hysteresis) over VREF (guaranteed by design) 1.5 2.0 2.5 % RfastOVP2 Ratio (Fast OVP Threshold, VFB rising) over VREF (VfastOVP /VREF ) (guaranteed by design) 106 107 108 % RUVP Ratio (UVP Threshold, VFB rising) over VREF (VUVP /VREF ) (guaranteed by design) 8 12 16 % RUVP(HYST) Ratio (UVP Hysteresis) over VREF (guaranteed by design) − − 1 % (IB)FB FB Pin Bias Current @ VFB = VOV P and VFB = VUVP 50 200 450 nA BROWN−OUT PROTECTION AND FEED−FORWARD VBOH Brown−Out Threshold, Vsense rising 0.96 1.00 1.04 V VBOL Brown−Out Threshold, Vsense falling 0.86 0.90 0.94 V VBO(HYST) Brown−Out Comparator Hysteresis 60 100 − mV TBO(blank) Brown−Out Blanking Time 35 50 65 ms 4. There is actually a minimum dead−time that is the delay between the core reset detection and the DRV turning on (TZD parameter of the “Current Sense and Zero Current Detection Blocks” section). http://onsemi.com 4 NCP1611 TYPICAL ELECTRICAL CHARACTERISTICS TABLE (Conditions: VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified) Symbol Rating Min Typ Max Unit BROWN−OUT PROTECTION AND FEED−FORWARD ICONTROL(BO) Vcontrol Pin Sink Current, Vsense < VBOL 40 50 60 mA VHL Comparator Threshold for Line Range Detection, Vsense rising 2.1 2.2 2.3 V VLL Comparator Threshold for Line Range Detection, Vsense falling 1.6 1.7 1.8 V VHL(hyst) Comparator Hysteresis for Line Range Detection 400 500 600 mV THL(blank) Blanking Time for Line Range Detection 15 25 35 ms IBO(bias) Brown−Out Pin Bias Current, Vsense = VBOH −250 − 250 nA TLIMIT Thermal Shutdown Threshold − 150 − °C HTEMP Thermal Shutdown Hysteresis − 50 − °C THERMAL SHUTDOWN 4. There is actually a minimum dead−time that is the delay between the core reset detection and the DRV turning on (TZD parameter of the “Current Sense and Zero Current Detection Blocks” section). http://onsemi.com 5 NCP1611 DETAILED PIN DESCRIPTION Pin Number 1 2 3 Name Function VCONTROL The error amplifier output is available on this pin. The network connected between this pin and ground adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve high Power Factor ratios. Pin1 is grounded when the circuit is off so that when it starts operation, the power increases slowly to provide a soft−start function. VSENSE A portion of the instantaneous input voltage is to be applied to pin 2 in order to detect brown−out conditions. If Vpin 2 is lower than 0.9 V for more than 50 ms, the circuit stops pulsing until the pin voltage rises again and exceeds 1.0 V. This pin also detects the line range. By default, the circuit operates the “low−line gain” mode. If Vpin 2 exceeds 2.2 V, the circuit detects a high−line condition and reduces the loop gain by 3. Conversely, if the pin voltage remains lower than 1.7 V for more than 25 ms, the low−line gain is set. Connecting the pin 2 to ground disables the part. FFCONTROL This pin sources a current representative to the line current. Connect a resistor between pin3 and ground to generate a voltage representative of the line current. When this voltage exceeds the internal 2.5 V reference (VREF ), the circuit operates in critical conduction mode. If the pin voltage is below 2.5 V, a dead−time is generated that approximately equates [83 ms x (1 − (Vpin3/VREF))]. By this means, the circuit forces a longer dead−time when the current is small and a shorter one as the current increases. The circuit skips cycles whenever Vpin 3 is below 0.65 V to prevent the PFC stage from operating near the line zero crossing where the power transfer is particularly inefficient. This does result in a slightly increased distortion of the current. If superior power factor is required, offset pin 3 by more than 0.75 V offset to inhibit the skip function. This pin monitors the MOSFET current to limit its maximum current. This pin is also connected to an internal comparator for Zero Current Detection (ZCD). This comparator is designed to monitor a signal from an auxiliary winding and to detect the core reset when this voltage drops to zero. The auxiliary winding voltage is to be applied through a diode to avoid altering the current sense information for the on−time (see application schematic). 4 CS / ZCD 5 Ground 6 Drive The high−current capability of the totem pole gate drive (−0.5/+0.8 A) makes it suitable to effectively drive high gate charge power MOSFETs. 7 VCC This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 10.5 V (A version, 17.0 V for the B version) and turns off when VCC goes below 9.0 V (typical values). After start−up, the operating range is 9.5 V up to 35 V. Feedback This pin receives a portion of the PFC output voltage for the regulation and the Dynamic Response Enhancer (DRE) that drastically speeds−up the loop response when the output voltage drops below 95.5% of the desired output level. Vpin8 is also the input signal for the (non−latching) Over−Voltage (OVP) and Under−Voltage (UVP) comparators. The UVP comparator prevents operation as long as Vpin8 is lower than 12% of the reference voltage (VREF). A soft OVP comparator gradually reduces the duty−ratio when Vpin8 exceeds 105% of VREF. If despite of this, the output voltage still increases, the driver is immediately disabled if the output voltage exceeds 107% of the desired level (fast OVP). A 250 nA sink current is built−in to trigger the UVP protection and disable the part if the feedback pin is accidentally open. 8 Connect this pin to the PFC stage ground. http://onsemi.com 6 NCP1611 Figure 2. Block Diagram http://onsemi.com 7 NCP1611 TYPICAL CHARACTERISTICS 12.0 17.6 17.4 11.5 VCC(on) (V) VCC(on) (V) 17.2 11.0 10.5 10.0 17.0 16.8 16.6 16.4 9.5 16.2 9.0 −50 −30 −10 10 30 50 70 90 110 16.0 −50 −30 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 3. Start−Up Threshold, VCC Increasing (VCC(on)) vs. Temperature (A Version) Figure 4. Start−Up Threshold, VCC Increasing (VCC(on)) vs. Temperature (B Version) 10.00 2.00 9.75 1.75 9.25 VCC(hysr) (V) VCC(off) (V) 9.50 9.00 8.75 1.50 1.25 1.00 8.50 0.75 8.25 8.00 −50 −30 −10 10 30 50 70 90 110 0.50 −50 −30 130 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 5. VCC Minimum Operating Voltage, VCC Falling (VCC(off)) vs. Temperature Figure 6. Hysteresis (VCC(on) − VCC(off)) vs. Temperature (A Version) 70 1.50 60 1.25 ICC(0p)1 (mA) 50 ICC(start) (mA) −10 40 30 20 1.00 0.75 0.50 0.25 10 0 −50 −30 −10 10 30 50 70 90 110 0 −50 −30 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 7. Start−Up Current @ VCC = 9.4 V vs. Temperature Figure 8. Operating Current, No Switching (VSENSE Grounded) vs. Temperature http://onsemi.com 8 NCP1611 TYPICAL CHARACTERISTICS 300 200 275 175 150 225 IDT2 (mA) IDT1 (mA) 250 200 175 125 100 150 75 125 −10 10 30 50 70 90 110 50 −50 −30 130 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) Figure 9. FFcontrol Pin Current, VSENSE = 1.4 V and VCONTROL Maximum vs. Temperature Figure 10. FFcontrol Pin Current, VSENSE = 2.8 V and VCONTROL Maximum vs. Temperature 22.5 40 20.5 39 18.5 38 16.5 37 36 14.5 12.5 −50 −30 −10 10 30 50 70 90 110 35 −50 −30 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 11. Dead−Time, VFFcontrol = 1.75 V vs. Temperature Figure 12. Dead−Time, VFFcontrol = 1.00 V vs. Temperature 0.85 0.85 0.75 0.75 VSKIP−L (V) VSKIP−H (V) −10 TJ, JUNCTION TEMPERATURE (°C) TDT3 (ms) TDT2 (ms) 100 −50 −30 0.65 0.55 0.65 0.55 0.45 −50 −30 −10 10 30 50 70 90 110 0.45 −50 −30 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 13. FFcontrol Pin Skip Level (VFFcontrol Rising) vs. Temperature Figure 14. FFcontrol Pin Skip Level (VFFcontrol Falling) vs. Temperature http://onsemi.com 9 NCP1611 TYPICAL CHARACTERISTICS 70 25 60 20 15 Trise (ns) ROH (W) 50 10 40 30 20 5 10 0 −50 −30 −10 10 30 50 70 90 110 0 −50 −30 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 15. DRV Source Resistance vs. Temperature Figure 16. DRV Voltage Rise−Time (CL = 1 nF, 10−90% of Output Signal) vs. Temperature 70 25 60 20 15 Tfall (ns) ROL (W) 50 10 40 30 20 5 10 0 −50 −30 −10 10 30 50 70 90 110 0 −50 −30 130 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 17. DRV Sink Resistance vs. Temperature Figure 18. DRV Voltage Fall−Time (CL = 1 nF, 10−90% of Output Signal) vs. Temperature 20 2.65 2.60 16 2.55 12 VREF (V) VDRVhigh (V) −10 8 2.50 2.45 4 2.40 0 −50 −30 −10 10 30 50 70 90 110 130 2.35 −50 −30 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 19. DRV Pin Level @ VCC = 35 V (RL = 33 kW, CL = 1 nF) vs. Temperature Figure 20. Feedback Reference Voltage vs. Temperature http://onsemi.com 10 NCP1611 TYPICAL CHARACTERISTICS 250 98 97 VOUTL / VREF (%) GEA (mS) 225 200 175 −10 10 30 50 70 90 110 93 −50 −30 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 21. Error Amplifier Transconductance Gain vs. Temperature Figure 22. Ratio (VOUT Low Detect Threshold / VREF) vs. Temperature 0.5 280 260 0.4 240 IBOOST (mA) HOUTL / VREF (%) 95 94 150 −50 −30 0.3 0.2 220 200 180 0.1 160 0 −50 −30 −10 10 30 50 70 90 110 140 −50 −30 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 23. Ratio (VOUT Low Detect Hysteresis / VREF) vs. Temperature Figure 24. VCONTROL Source Current when (VOUT Low Detect) is Activated for Dynamic Response Enhancer (DRE) vs. Temperature 520 280 515 260 510 240 TLEB−OCP (ns) VBCS(th) (mV) 96 505 500 495 220 200 180 490 160 485 140 480 −50 −30 −10 10 30 50 70 90 110 130 120 −50 −30 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 25. Current Sense Voltage Threshold vs. Temperature Figure 26. Over−Current Protection Leading Edge Blanking vs. Temperature http://onsemi.com 11 NCP1611 TYPICAL CHARACTERISTICS 140 100 130 80 110 TOCP (ns) TLEB−OVS (ns) 120 100 90 80 60 40 20 70 60 −50 −30 −10 10 30 50 70 90 0 −50 −30 110 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 27. “Overstress” Protection Leading Edge Blanking vs. Temperature Figure 28. Over−Current Protection Delay from VCS/ZCD > VCS(th) to DRV Low (dVCS/ZCD / dt = 10 V/ms) vs. Temperature 850 270 265 260 VZCD(th)L (mV) VZCD(th)H (mV) 800 750 700 255 250 245 240 235 −10 10 30 50 70 90 110 230 −50 −30 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 29. Zero Current Detection, VCS/ZCD Rising vs. Temperature Figure 30. Zero Current Detection, VCS/ZCD Falling vs. Temperature 560 1.8 540 1.7 520 RZCD/CS (−) VZCD(hyst) (mV) 650 −50 −30 500 480 460 1.6 1.5 1.4 1.3 440 420 −50 −30 −10 10 30 50 70 90 1.2 −50 −30 110 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 31. Hysteresis of the Zero Current Detection Comparator vs. Temperature Figure 32. VZCD(th) over VCS(th) Ratio vs. Temperature http://onsemi.com 12 NCP1611 TYPICAL CHARACTERISTICS 1.5 240 1.4 230 220 1.2 1.1 TWTG (ms) IZCD/(bias) (mA) 1.3 1.0 0.9 0.8 210 200 190 180 0.7 0.6 0.5 −50 −30 170 −10 10 30 50 70 90 110 160 −50 −30 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 33. CS/ZCD Pin Bias Current @ VCS/ZCD = 0.75 V vs. Temperature Figure 34. Watchdog Timer vs. Temperature 960 140 920 130 840 TSYNC (ns) TWTG(OS) (ms) 880 800 760 120 110 100 720 90 680 640 −50 −30 −10 10 30 50 70 90 110 80 −50 −30 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 35. Watchdog Timer in “Overstress” Situation vs. Temperature Figure 36. Minimum ZCD Pulse Width for ZCD Detection vs. Temperature 110 32 100 31 TTMO (ms) TZCD (ns) 90 80 70 60 30 29 50 40 −50 −30 −10 10 30 50 70 90 28 −50 −30 110 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 37. ((VCS/ZCD < VZCD(th)) to DRV High) Delay vs. Temperature Figure 38. Timeout Timer vs. Temperature http://onsemi.com 13 NCP1611 27.0 8.8 26.5 8.7 26.0 8.6 TON(HL) (ms) TON(LL) (ms) TYPICAL CHARACTERISTICS 25.5 25.0 8.4 8.3 24.5 24.0 −50 −30 −10 10 30 50 70 90 110 8.2 −50 −30 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 39. Maximum On Time @ VSENSE = 1.4 V vs. Temperature Figure 40. Maximum On Time @ VSENSE = 2.8 V vs. Temperature 100 100 90 90 80 80 TON(HL)(MIN) (ns) TON(LL)(MIN) (ns) 8.5 70 60 50 70 60 50 40 40 30 30 20 −50 −30 −10 10 30 50 70 90 110 20 −50 −30 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 41. Minimum On Time @ VSENSE = 1.4 V vs. Temperature Figure 42. Minimum On Time @ VSENSE = 2.8 V vs. Temperature 105.4 2.2 105.3 RsoftOVP(HYST) (%) RsoftOVP (%) 105.2 105.1 105.0 104.9 104.8 2.1 2.0 1.9 104.7 104.6 −50 −30 −10 10 30 50 70 90 110 130 1.8 −50 −30 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 43. Ratio (Soft OVP Threshold, VFB Rising) over VREF vs. Temperature Figure 44. Ratio (Soft OVP Hysteresis) over VREF vs. Temperature http://onsemi.com 14 NCP1611 TYPICAL CHARACTERISTICS 107.4 290 107.3 270 250 107.1 IB(FB) (nA) RfastOVP2 (%) 107.2 107.0 106.9 210 190 106.8 170 106.7 106.6 −50 −30 −10 10 30 50 70 90 150 −50 −30 110 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 45. Ratio (Fast OVP Threshold, VFB Rising) over VREF vs. Temperature Figure 46. Feedback Pin Bias Current @ VFB = VOVP vs. Temperature 290 15 270 14 250 13 RfUVP (%) IB(FB)2 (nA) 230 230 210 12 11 190 10 170 150 −50 −30 −10 10 30 50 70 90 110 9 −50 −30 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 47. Feedback Pin Bias Current @ VFB = VUVP vs. Temperature Figure 48. Ratio (UVP Threshold, VFB Rising) over VREF vs. Temperature 0.8 1.10 0.7 VBOH (V) RfUVP(HYST) (%) 1.05 0.6 0.5 1.00 0.4 0.95 0.3 0.2 −50 −30 −10 10 30 50 70 90 0.90 −50 −30 110 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 49. Ratio (UVP Hysteresis) over VREF vs. Temperature Figure 50. Brown−Out Threshold, VSENSE Rising vs. Temperature http://onsemi.com 15 NCP1611 1.00 110 0.95 105 VBO(HYST) (mV) VBOL (V) TYPICAL CHARACTERISTICS 0.90 0.85 95 −10 10 30 50 70 90 110 90 −50 −30 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 51. Brown−Out Threshold, VSENSE Falling vs. Temperature Figure 52. Brown−Out Comparator Hysteresis vs. Temperature 60 60 55 55 ICONTROL(BO) (mA) TBO(blank) (ms) 0.80 −50 −30 50 45 40 −50 −30 −10 10 30 50 70 90 110 50 45 40 −50 −30 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 53. Brown−Out Blanking Time vs. Temperature Figure 54. VCONTROL Pin Sink Current when a Brown−Out Situation is Detected vs. Temperature 2.4 1.9 2.3 1.8 2.2 VLL (V) VHL (V) 100 2.1 1.7 1.6 2.0 1.9 −50 −30 −10 10 30 50 70 90 1.5 −50 −30 110 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 55. Comparator Threshold for Line Range Detection, VSENSE Rising vs. Temperature Figure 56. Comparator Threshold for Line Range Detection, VSENSE Falling vs. Temperature http://onsemi.com 16 NCP1611 TYPICAL CHARACTERISTICS 30 8 7 6 5 IBO(bias) (nA) THL(blank) (ms) 28 26 24 4 3 2 1 0 −1 −2 22 20 −50 −30 −10 10 30 50 70 90 110 −3 −4 −50 −30 130 −10 10 30 50 70 90 110 130 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 57. Blanking Time for Line Range Detection vs. Temperature Figure 58. Brown−Out Pin Bias Current, (VSENSE = VBOH) vs. Temperature DETAILED OPERATING DESCRIPTION Introduction The NCP1611 is designed to optimize the efficiency of your PFC stage throughout the load range. In addition, it incorporates protection features for rugged operation. More generally, the NCP1611 is ideal in systems where cost−effectiveness, reliability, low stand−by power and high efficiency are key requirements: • Current Controlled Frequency Fold−back: the NCP1611 is designed to drive PFC boost stages in so−called Current Controlled Frequency Fold−back (CCFF). In this mode, the circuit classically operates in Critical conduction Mode (CrM) when the inductor current exceeds a programmable value. When the current is below this preset level, the NCP1611 linearly reduces the frequency down to about 20 kHz when the current is zero. CCFF maximizes the efficiency at both nominal and light load. In particular, stand−by losses are reduced to a minimum. Similarly to FCCrM controllers, an internal circuitry allows near−unity power factor even when the switching frequency is reduced. • Skip Mode: to further optimize the efficiency, the circuit skips cycles near the line zero crossing when the current is very low. This is to avoid circuit operation when the power transfer is particularly inefficient at the cost of current distortion. When superior power factor is required, this function can be inhibited by offsetting the “FFcontrol” pin by 0.75 V. • Low Start−up Current and large VCC range (B version): The start−up consumption of the circuit is minimized to allow the use of high−impedance start−up resistors to pre−charge the VCC capacitor. Also, the minimum value of the UVLO hysteresis is 6 V to avoid the need for large VCC capacitors and help shorten the start−up time • • without the need for too dissipative start−up elements. The A version is preferred in applications where the circuit is fed by an external power source (from an auxiliary power supply or from a downstream converter). Its maximum start−up level (11.25 V) is set low enough so that the circuit can be powered from a 12−V rail. After start−up, the high VCC maximum rating allows a large operating range from 9.5 V up to 35 V. Fast Line / Load Transient Compensation (Dynamic Response Enhancer): since PFC stages exhibit low loop bandwidth, abrupt changes in the load or input voltage (e.g. at start−up) may cause excessive over or under−shoot. This circuit limits possible deviations from the regulation level as follows: − The NCP1611 linearly decays the power delivery to zero when the output voltage exceeds 105% of its desired level (soft OVP). If this soft OVP is too smooth and the output continues to rise, the circuit immediately interrupts the power delivery when the output voltage is 107% above its desired level. − The NCP1611 dramatically speeds−up the regulation loop when the output voltage goes below 95.5% of its regulation level. This function is enabled only after the PFC stage has started−up to allow normal soft−start operation to occur. Safety Protections: the NCP1611 permanently monitors the input and output voltages, the MOSFET current and the die temperature to protect the system from possible over−stress making the PFC stage extremely robust and reliable. In addition to the OVP protection, these methods of protection are provided: http://onsemi.com 17 NCP1611 − Maximum Current Limit: the circuit senses the MOSFET current and turns off the power switch if the set current limit is exceeded. In addition, the circuit enters a low duty−cycle operation mode when the current reaches 150% of the current limit as a result of the inductor saturation or a short of the bypass diode. − Under−Voltage Protection: this circuit turns off when it detects that the output voltage is below 12% of the voltage reference (typically). This feature protects the PFC stage if the ac line is too low or if there is a failure in the feedback network (e.g., bad connection). − Brown−Out Detection: the circuit detects low ac line conditions and stops operation thus protecting the PFC stage from excessive stress. − Thermal Shutdown: an internal thermal circuitry disables the gate drive when the junction • temperature exceeds 150°C (typically). The circuit resumes operation once the temperature drops below approximately 100°C (50°C hysteresis). Output Stage Totem Pole: the NCP1611 incorporates a −0.5 A / +0.8 A gate driver to efficiently drive most TO220 or TO247 power MOSFETs. NCP1611 Operation Modes As mentioned, the NCP1611 PFC controller implements a Current Controlled Frequency Fold−back (CCFF) where: − The circuit operates in classical Critical conduction Mode (CrM) when the inductor current exceeds a programmable value. − When the current is below this preset level, the NCP1611 linearly reduces the operating frequency down to about 20 kHz when the current is zero. High Current No delay è CrM Low Current The next cycle is delayed Timer delay Lower Current Longer dead−time Timer delay Figure 59. CCFF Operation As illustrated in Figure 59, under high load conditions, the boost stage is operating in CrM but as the load is reduced, the controller enters controlled frequency discontinuous operation. Figure 60 details the operation. A voltage representative of the input current (“current information”) is generated. If this signal is higher than a 2.5 V internal reference (named “Dead−Time Ramp Threshold” in Figure 60), there is no dead−time and the circuit operates in CrM. If the current information is lower than the 2.5 V threshold, a dead−time is inserted that lasts for the time necessary for the internal ramp to reach 2.5 V from the current information floor. Hence, the lower the current information is, the longer the dead−time. When the current information is 0.75 V, the dead−time is 50 ms. To further reduce the losses, the MOSFET turns on is stretched until its drain−source voltage is at its valley. As illustrated in Figure 60, the ramp is synchronized to the drain−source ringing. If the ramp exceeds the 2.5 V threshold while the drain−source voltage is below Vin , the ramp is extended until it oscillates above Vin so that the drive will turn on at the next valley. http://onsemi.com 18 NCP1611 Top: CrM operation when the current information exceeds the preset level during the demagnetization phase Middle: the circuit re−starts at the next valley if the sum (ramp + current information) exceeds the preset level during the dead−time, while the drain−source voltage is high Bottom: the sum (ramp + current information) exceeds the preset level while during the dead−time, the drain−source voltage is low. The circuit skips the current valley and re−starts at the following one. Figure 60. Dead−Time Generation Current Information Generation multiplier gain (Km of Figure 61) is three times less in high−line conditions (that is when the “LLine” signal from the brown−out block is in low state) so that Ipin3 provides a voltage representative of the input current across resistor RFF placed between pin 3 and ground. Pin 3 voltage is the current information. The “FFcontrol” pin sources a current that is representative of the input current. In practice, Ipin3 is built by multiplying the internal control signal (VREGUL, i.e., the internal signal that controls the on−time) by the sense voltage (pin 4) that is proportional to the input voltage. The http://onsemi.com 19 NCP1611 BO pinpin VSENSE IREGUL IBO V to I converter IBO Vcontrol pin VCONTROL pin LLine Multiplier IREGUL V to I converter Km . IREGUL . IBO IREGUL= K .VREGUL + FFcontrol pin FFcontrol pin SUM SUM RAMP RAMP RFF skip2 SKIP 0.75 V / 0.651V V pfcOK pfcOK Figure 61. Generation of the Current Information Skip Mode mode capability is disabled whenever the PFC stage is not in nominal operation (as dictated by the “pfcOK” signal − see block diagram and “pfcOK Internal Signal” Section). The circuit does not abruptly interrupt the switching when Vpin3 goes below 0.65 V. Instead, the signal VTON that controls the on−time is gradually decreased by grounding the VREGUL signal applied to the VTON processing block (see Figure 9). Doing so, the on−time smoothly decays to zero in three to four switching periods typically. Figure 62 shows the practical implementation. As illustrated in Figure 61, the circuit also skips cycles near the line zero crossing where the current is very low. A comparator monitors the pin 3 voltage (“FFcontrol” voltage) and inhibits the drive when Vpin3 is lower than a 0.65 V internal reference. Switching resumes when Vpin3 exceeds 0.75 V (0.1 V hysteresis). This inhibits circuit operation when the power transfer is particularly inefficient at the expense of slightly increased current distortion. When superior power factor is needed, this function can be inhibited offsetting the “FFcontrol” pin by 0.75 V. The skip http://onsemi.com 20 NCP1611 Figure 62. CCFF Practical Implementation CCFF maximizes the efficiency at both nominal and light load. In particular, the stand−by losses are reduced to a minimum. Also, this method avoids that the system stalls between valleys. Instead, the circuit acts so that the PFC stage transitions from the n valley to (n + 1) valley or vice versa from the n valley to (n − 1) cleanly as illustrated by Figure 63. Figure 63. Clean Transition Without Hesitation Between Valleys NCP1611 On−time Modulation up when the MOSFET is on. The slope is (VIN/L) where L is the coil inductance. At the end of the on−time (t1), the inductor starts to demagnetize. The inductor current ramps down until it reaches zero. The duration of this phase is (t2). Let’s analyze the ac line current absorbed by the PFC boost stage. The initial inductor current at the beginning of each switching cycle is always zero. The coil current ramps http://onsemi.com 21 NCP1611 In some cases, the system enters then the dead−time (t3) that lasts until the next clock is generated. One can show that the ac line current is given by: ƪ t 1ǒt 1 ) t 2Ǔ I in + V in 2TL ƫ Where T = (t1 + t2 + t3) is the switching period and Vin is the ac line rectified voltage. In light of this equation, we immediately note that Iin is proportional to Vin if [t1 (t1 + t2) / T] is a constant. (eq. 1) Figure 64. PFC Boost Converter (left) and Inductor Current in DCM (right) parametric table shows that ton ,max is equal to 25 ms (TON(LL)) at low line and to 8.3 ms (TON(HL)) at high line (when pin2 happens to exceed 2.2 V with a pace higher than 40 Hz – see BO 25 ms blanking time). The input current is then proportional to the input voltage. Hence, the ac line current is properly shaped. One can note that this analysis is also valid in the CrM case. This condition is just a particular case of this functioning where (t3=0), which leads to (t1+t2=T) and (VTON=VREGUL). That is why the NCP1611 automatically adapts to the conditions and transitions from DCM and CrM (and vice versa) without power factor degradation and without discontinuity in the power delivery. Hence, we can re−write the above equation as follows: The NCP1611 operates in voltage mode. As portrayed by Figure 8, the MOSFET on−time t1 is controlled by the signal Vton generated by the regulation block and an internal ramp as follows: t1 + C ramp @ V ton I ch (eq. 2) The charge current is constant at a given input voltage (as mentioned, it is 3 times higher at high line compared to its value at low line). Cramp is an internal capacitor. The output of the regulation block (VCONTROL) is linearly transformed into a signal (VREGUL) varying between 0 and 1 V. (VREGUL) is the voltage that is injected into the PWM section to modulate the MOSFET duty−cycle. The NCP1611 includes some circuitry that processes (VREGUL ) to form the signal (Vton) that is used in the PWM section (see Figure 9). (Vton) is modulated in response to the dead−time sensed during the precedent current cycles, that is, for a proper shaping of the ac line current. This modulation leads to: V ton + T @ V REGUL t1 ) t2 I in + t1 ) t2 T I in + (eq. 3) + V REGUL where : k + constant + ƪ V REGUL 1 @ 2L ǒV Ǔ REGUL max 2@L V REGUL ǒVREGULǓ max V in @ T ON(HL) 2@L @ V REGUL ǒVREGULǓ max at high line. From these equations, we can deduce the expression of the average input power: Given the low regulation bandwidth of the PFC systems, (VCONTROL ) and then (VREGUL ) are slow varying signals. Hence, the (Vton • (t1 + t2) / T) term is substantially constant. Provided that in addition, (t1) is proportional to (Vton ), Equation 1 leads to: (Iin = k • Vin), where k is a constant. More exactly: I in + k @ V in @ at low line. or V ton @ V in @ T ON(LL) P in,avg + ǒVin,rmsǓ 2 @ V REGUL @ T ON(LL) 2 @ L @ ǒV REGULǓ max at low line P in,avg + ƫ @ t on,max ǒVin,rmsǓ 2 @ V REGUL @ T ON(HL) 2 @ L @ ǒV REGULǓ max at high line Where (VREGUL)max is the 1 V VREGUL maximum value. Where ton ,max is the maximum on−time obtained when VREGUL is at its (VREGUL )max maximum level. The http://onsemi.com 22 NCP1611 Hence, the maximum power that can be delivered by the PFC stage is: ǒPin,avgǓ max + ǒVin,rmsǓ 2 @ T ON(LL) 2@L at low line ǒPin,avgǓ max + ǒVin,rmsǓ 2 @ T ON(HL) 2@L at high line Figure 65. PWM circuit and timing diagram. Figure 66. VTON Processing Circuit. The integrator OA1 amplifies the error between VREGUL and IN1 so that on average, (VTON * (t1+t2)/T) equates VREGUL. Remark: Regulation Block and Output Voltage Control The “Vton processing circuit” is “informed” when a condition possibly leading to a long interruption of the drive activity (functions generating the STOP signal that disables the drive – see block diagram − except OCP, i.e., OVP, OverStress, SKIP, staticOVP and OFF). Otherwise, such situations would be viewed as a normal dead−time phase and Vton would inappropriately over−dimension Vton to compensate it. Instead, as illustrated in Figure 66, the Vton signal is grounded leading to a short soft−start when the circuit recovers. A trans−conductance error amplifier (OTA) with access to the inverting input and output is provided. It features a typical trans−conductance gain of 200 mS and a maximum capability of ±20 mA. The output voltage of the PFC stage is typically scaled down by a resistors divider and monitored by the inverting input (pin 8). Bias current is minimized (less than 500 nA) to allow the use of a high impedance feed−back network. However, it is high enough so that the pin remains in low state if the pin is not connected. http://onsemi.com 23 NCP1611 The output of the error amplifier is brought to pin 1 for external loop compensation. Typically a type 2 network is applied between pin1 and ground, to set the regulation bandwidth below about 20 Hz and to provide a decent phase boost. The swing of the error amplifier output is limited within an accurate range: − It is forced above a voltage drop (VF ) by some circuitry. − It is clamped not to exceed 4.0 V + the same VF voltage drop. Hence, Vpin1 features a 4 V voltage swing. Vpin1 is then offset down by (VF ) and scaled down by a resistors divider before it connects to the “VTON processing block” and the PWM section. Finally, the output of the regulation block is a signal (“VREGUL ” of the block diagram) that varies between 0 and a top value corresponding to the maximum on−time. The VF value is 0.5 V typically. VREGUL (VREGUL)max VCONTROL Figure 67. a) Regulation Block Figure (left), b) Correspondence Between VCONTROL and VREGUL (right) Given the low bandwidth of the regulation loop, abrupt variations of the load, may result in excessive over or under−shoot. Over−shoot is limited by the Over−Voltage Protection connected to pin 8. The NCP1611 embeds a “dynamic response enhancer” circuitry (DRE) that contains under−shoots. An internal comparator monitors the feed−back (Vpin8) and when Vpin8 is lower than 95.5% of its nominal value, it connects a 200 mA current source to speed−up the charge of the compensation network. Effectively this appears as a 10x increase in the loop gain. In A version, DRE is disabled during the start−up sequence until the PFC stage has stabilized (that is when the “pfcOK” signal of the block diagram, is high). The resulting slow and gradual charge of the pin1 voltage (VCONTROL ) softens the soft start−up sequence. In B version, DRE is enabled during start−up to speed−up this phase and allow for the use of smaller VCC capacitors. The circuit also detects overshoot and immediately reduces the power delivery when the output voltage exceeds 105% of its desired level. The NCP1611 does not abruptly interrupt the switching. Instead, the signal VTON that controls the on−time is gradually decreased by grounding the VREGUL signal applied to the VTON processing block (see Figure 66). Doing so, the on−time smoothly decays to zero in four to five switching periods typically. If the output voltage still increases, a second comparator immediately disables the driver if the output voltage exceeds 107% of its desired level. The error amplifier OTA and the OVP, UVP and DRE comparators share the same input information. Based on the typical value of their parameters and if (Vout,nom) is the output voltage nominal value (e.g., 390 V), we can deduce: − Output Regulation Level: Vout,nom − Output UVP Level: Vout,uvp = 12% x Vout,nom − Output DRE Level: Vout,dre = 95.5% x Vout,nom − Output Soft OVP Level: Vout,sovp = 105% x Vout,nom − Output Fast OVP level: Vout,fovp = 107% x Vout,nom Current Sense and Zero Current Detection The NCP1611 is designed to monitor the current flowing through the power switch. A current sense resistor (Rsense ) is inserted between the MOSFET source and ground to generate a positive voltage proportional to the MOSFET current (VCS ). The VCS voltage is compared to a 500 mV internally reference. When VCS exceeds this threshold, the http://onsemi.com 24 NCP1611 input and output high−voltage rails to divert this inrush current. If this diode is accidently shorted, the MOSFET will also see a high current when it turns on. In both cases, the current can be large enough to trigger the ZCD comparator. An AND gate detects that this event occurs while the drive signal is high. In this case, the “OverStress” signal goes high and disables the driver for an 800 ms delay. This long delay leads to a very low duty−ratio operation in case of “OverStress” fault in order to limit the risk of overheating. When no signal is received that triggers the ZCD comparator during the off−time, an internal 200−ms watchdog timer initiates the next drive pulse. At the end of this delay, the circuit senses the CS/ZCD pin impedance to detect a possible grounding of this pin and prevent operation. The CS/ZCD external components must be selected to avoid false fault detection. 3.9 kW is the recommended minimum impedance to be applied to the CS/ZCD pin when considering the NCP1611 parameters tolerance over the −40°C to 125°C temperature range. Practically, Rcs must be higher than 3.9 kW in the application of Figure 68. OCP signal turns high to reset the PWM latch and forces the driver low. A 200 ns blanking time prevents the OCP comparator from tripping because of the switching spikes that occur when the MOSFET turns on. The CS pin is also designed to receive a signal from an auxiliary winding for Zero Current Detection. As illustrated in Figure TBD, an internal ZCD comparator monitors the pin4 voltage and if this voltage exceeds 750 mV, a demagnetization phase is detected (signal ZCD is high). The auxiliary winding voltage is applied thought a diode to prevent this signal from distorting the current sense information during the on−time. Thus, the OCP protection is not impacted by the ZCD sensing circuitry. This comparator incorporates a 500 mV hysteresis and is able to detect ZCD pulses longer than 200 ns. When pin4 voltage drops below the lower ZCD threshold, the driver can turn high within 200 ns. It may happen that the MOSFET turns on while a huge current flows through the inductor. As an example such a situation can occur at start−up when large in−rush currents charge the bulk capacitor to the line peak voltage. Traditionally, a bypass diode is generally placed between the Figure 68. Current Sense and Zero Current Detection Blocks Brown−Out Detection By default, when the circuit starts operation, the circuit is in a fault state (“BO_NOK” high) until Vpin2 exceeds 1 V. When “BO_NOK” is high, the drive is not disabled. Instead, a 50 mA current source is applied to pin 1 to gradually reduce VCONTROL . As a result, the circuit only stops pulsing when the staticOVP function is activated (that is when VCONTROL reaches the skip detection threshold). At that moment, the circuit turns off (see Figure 2). This method limits any risk of false triggering. The input of the PFC stage has some impedance that leads to some sag of the input voltage when the input current is large. If the PFC stage suddenly stops while a high current is drawn from the mains, the abrupt decay of the current may make the input voltage rise and the circuit detect a correct line level. Instead, the The VSENSE pin (pin2) receives a portion of the instantaneous input voltage (Vin ). As Vin is a rectified sinusoid, the monitored signal varies between zero or a small voltage and a peak value. For the brown−out block, we need to ensure that the line magnitude is high enough for operation. This is done as follows: − The VSENSE pin voltage is compared to a 1 V reference. − If Vpin2 exceeds 1 V, the input voltage is considered sufficient − If Vpin2 remains below 0.9 V for 50 ms, the circuit detects a brown−out situation (100 mV hysteresis). http://onsemi.com 25 NCP1611 gradual decrease of VCONTROL avoids a line current discontinuity and limits the risk of false triggering. Pin2 is also used to sense the line for feed−forward. A similar method is used: − The VSENSE pin voltage is compared to a 2.2 V reference. − If Vpin2 exceeds 2.2 V, the circuit detects a high−line condition and the loop gain is divided by three (the internal PWM ramp slope is three times steeper) − Once this occurs, if Vpin2 remains below 1.7 V for 25 ms, the circuit detects a low−line situation (500 mV hysteresis). At startup, the circuit is in low−line state (“LLine” high”) until Vpin2 exceeds 2.2 V. The line range detection circuit allows more optimal loop gain control for universal (wide input mains) applications. As portrayed in Figure 69, the pin 2 voltage is also utilized to generate the current information required for the frequency fold−back function. Vsense pin Figure 69. Input Line Sense Monitoring Thermal Shutdown (TSD) Output Drive Section An internal thermal circuitry disables the circuit gate drive and keeps the power switch off when the junction temperature exceeds 150°C. The output stage is then enabled once the temperature drops below about 100°C (50°C hysteresis). The temperature shutdown remains active as long as the circuit is not reset, that is, as long as VCC is higher than VCC(RESET). The reset action forces the TSD threshold to be the upper one (150°C), thus ensuring that any cold start−up will be done with the proper TSD level. The output stage contains a totem pole optimized to minimize the cross conduction current during high frequency operation. The gate drive is kept in a sinking mode whenever the Under−Voltage Lockout is active or more generally whenever the circuit is off (i.e., when the “Fault Latch” of the block diagram is high). Its high current capability (−500 mA/+800 mA) allows it to effectively drive high gate charge power MOSFET. As the circuit exhibits a large VCC range (up to 35 V), the drive pin voltage http://onsemi.com 26 NCP1611 is clamped not to provide the MOSFET gate with more than 14 V. smoke nor big noise. The NCP1611 integrates functions that ease meet this requirement. Among them, we can list: • Floating feedback pin A 250 nA sink current source pulls down the voltage on the feedback pin if it is floating so that the UVP protection trips and prevents the circuit from operating. This current source is small (450 nA maximum) so that its impact on the bulk voltage regulation level remains negligible with typical feedback resistor dividers. • Fault of the GND connection If the GND pin is properly connected, the supply current drawn from the positive terminal of the VCC capacitor, flows out of the GND pin to return to the negative terminal of the VCC capacitor. If the GND pin is not connected, the circuit ESD diodes offer another return path. The accidental non connection of the GND pin can hence be detected by detecting that one of this ESD diode is conducting. Practically, the CS/ZCD ESD diode is monitored. If such a fault is detected for 200 ms, the circuit stops operating. • Detection the CS/ZCD pin improper connection The CS/ZCD pin sources a 1 mA current to pull up the pin voltage and hence disable the part when the pin is floating. If the CS/ZCD pin is grounded, the circuit cannot monitor the ZCD signal and the 200 ms watchdog timer is activated. When the watchdog time has elapsed, the circuit sources a 250 mA current source to pull−up the CS/ZCD pin voltage. No drive pulse is initiated until the CS/ZCD pin voltage exceeds the ZCD 0.75 V threshold. Hence, if the pin is grounded, the circuit stops operating. Circuit proper operation requires the pin impedance to be 3.9 kW or more, the tolerance of the NCP1611 impedance testing function being considered over the −40°C to 125°C temperature range. • Boost or bypass diode short The NCP1611 addresses the short situations of the boost and bypass diodes (a bypass diode is generally placed between the input and output high−voltage rails to divert this inrush current). Practically, the overstress protection is implemented to detect such conditions and forces a low duty−cycle operation until the fault is gone. Reference Section The circuit features an accurate internal 2.5 V reference voltage (VREF ) optimized to be ±2.4% accurate over the temperature range. OFF Mode As previously mentioned, the circuit turns off when one of the following faults is detected: • Incorrect feeding of the circuit (“UVLO” high when VCC < VCC(off), VCC(off) equating 9 V typically). • Excessive die temperature detected by the thermal shutdown. • Under−Voltage Protection. • Brown−Out Fault and static OVP (see block diagram) Generally speaking, the circuit turns off when the conditions are not proper for desired operation. In this mode, the controller stops operating. The major part of the circuit sleeps and its consumption is minimized. More specifically, when the circuit is in OFF state: • The drive output is kept low • All the blocks are off except: • • • − The UVLO circuitry that keeps monitoring the VCC voltage and controlling the start−up current source accordingly. − The TSD (thermal shutdown) − The Under−Voltage Protection (“UVP”). − The brown−out circuitry VCONTROL is grounded so that when the fault is removed, the device starts−up under the soft start mode (B Version). The internal “pfcOK” signal is grounded. The output of the “VTON processing block” is grounded Failure detection When manufacturing a power supply, elements can be accidentally shorted or improperly soldered. Such failures can also happen to occur later on because of the components fatigue or excessive stress, soldering defaults or external interactions. In particular, adjacent pins of controllers can be shorted, a pin can be grounded or badly connected. Such open/short situations are generally required not to cause fire, Refer to application note ANDxxxx for more details. ORDERING INFORMATION Circuit Version Package Shipping† NCP1611ADR2G NCP1611A NCP1611BDR2G NCP1611B SOIC−8 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 27 NCP1611 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J SOLDERING FOOTPRINT* S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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