ONSEMI NDF03N80ZH

NDD03N80Z, NDF03N80Z
N‐Channel Power MOSFET
800 V, 4.5 W
Features
•
•
•
•
ESD Diode−Protected Gate
100% Avalanche Tested
100% Rg Tested
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
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V(BR)DSS
RDS(ON) MAX
800 V
4.5 W @ 10 V
ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Symbol
NDD
VDSS
NDF
Unit
800
Continuous Drain Current RqJC
ID
2.9
3.3
(Note 1)
A
Continuous Drain Current
RqJC, TA = 100°C
ID
1.9
2.1
(Note 1)
A
Pulsed Drain Current, VGS @ 10 V
IDM
12
13
A
Power Dissipation RqJC
PD
96
25
W
Gate−to−Source Voltage
VGS
±30
V
Single Pulse Avalanche Energy, ID =
2.5 A
EAS
100
mJ
ESD (HBM) (JESD22−A114)
Vesd
2300
V
RMS Isolation Voltage (t = 0.3 sec.,
R.H. ≤ 30%, TA = 25°C) (Figure 14)
VISO
Peak Diode Recovery (Note 2)
dv/dt
4.5
V/ns
Continuous Source Current
(Body Diode)
IS
3.3
A
Maximum Temperature for Soldering
Leads
TL
260
°C
TJ, Tstg
−55 to 150
°C
Operating Junction and
Storage Temperature Range
N-Channel
V
4500
D (2)
G (1)
S (3)
V
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Limited by maximum junction temperature
2. IS = 3.3 A, di/dt ≤ 100 A/ms, VDD ≤ BVDSS, TJ = +150°C
4
1
1
2
2
3
3
NDD03N80Z−1G
IPAK
CASE 369D
NDF03N80ZH
TO−220FP
CASE 221AH
4
1 2
3
NDD03N80ZT4G
DPAK
CASE 369AA
MARKING AND ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
August, 2012 − Rev. 0
1
Publication Order Number:
NDD03N80Z/D
NDD03N80Z, NDF03N80Z
THERMAL RESISTANCE
Parameter
Symbol
Value
Unit
NDF03N80Z
NDD03N80Z
RqJC
4.0
1.3
°C/W
(Note 3) NDF03N80Z
(Note 4) NDD03N80Z
(Note 3) NDD03N80Z−1
RqJA
50
33
96
Junction−to−Case (Drain)
Junction−to−Ambient Steady State
3. Insertion mounted
4. Surface mounted on FR4 board using 1” sq. pad size (Cu area = 1.127” sq [2 oz] including traces).
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Test Conditions
Min
Drain-to-Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 1 mA
800
Drain-to-Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Reference to 25°C, ID = 1 mA
Characteristic
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Leakage Current
Gate-to-Source Leakage Current
IDSS
VDS = 800 V, VGS = 0 V
V
870
mV/°C
TJ = 25°C
1.0
TJ = 125°C
50
IGSS
VGS = ±20 V
VGS(TH)
VDS = VGS, ID = 50 mA
±10
mA
mA
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature
Coefficient
Static Drain-to-Source On Resistance
Forward Transconductance
3.0
4.1
4.5
V
VGS(TH)/TJ
Reference to 25°C, ID = 50 mA
11
mV/°C
RDS(ON)
VGS = 10 V, ID = 1.2 A
3.7
gFS
VDS = 15 V, ID = 1.2 A
2.1
S
440
pF
4.5
W
DYNAMIC CHARACTERISTICS
Input Capacitance (Note 6)
Ciss
Output Capacitance (Note 6)
Coss
Reverse Transfer Capacitance
(Note 6)
Crss
Total Gate Charge (Note 6)
Qg
VDS = 25 V, VGS = 0 V, f = 1 MHz
52
9.0
nC
17
Gate-to-Source Charge (Note 6)
Qgs
Gate-to-Drain (“Miller”) Charge
(Note 6)
Qgd
3.5
Plateau Voltage
VGP
6.5
V
Gate Resistance
Rg
5.5
W
9.0
ns
VDS = 400 V, ID = 3.3 A, VGS = 10 V
9.1
RESISTIVE SWITCHING CHARACTERISTICS (Note 7)
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
td(on)
tr
td(off)
VDD = 400 V, ID = 3.3 A,
VGS = 10 V, RG = 0 W
tf
7.0
17
9.0
SOURCE−DRAIN DIODE CHARACTERISTICS
Diode Forward Voltage
VSD
Reverse Recovery Time
trr
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
Qrr
IS = 3.0 A, VGS = 0 V
TJ = 25°C
TJ = 100°C
0.9
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2
ns
81
280
1.3
5. Pulse Width ≤ 380 ms, Duty Cycle ≤ 2%.
6. Guaranteed by design.
7. Switching characteristics are independent of operating junction temperatures.
V
0.8
360
VGS = 0 V, VDD = 30 V
IS = 3.3 A, di/dt = 100 A/ms
1.6
nC
NDD03N80Z, NDF03N80Z
TYPICAL CHARACTERISTICS
3.0
VGS = 6.8 V to 10 V
2.5
VDS = 25 V
6.4 V
2.0
6.2 V
1.5
6.0 V
1.0
5.8 V
5.0 V
0.5
0.0
0
5.2 V
5.6 V
5.4 V
5
10
15
20
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TJ = −55°C
3.0
TJ = 150°C
2.0
1.0
0.0
25
1
2
ID = 1.2 A
TJ = 25°C
11
10
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5 10
VGS, GATE−TO−SOURCE VOLTAGE (V)
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
ID, DRAIN CURRENT (A)
1.15
BVDSS, NORMALIZED BREAKDOWN
VOLTAGE (V)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
Figure 4. On−Resistance versus Drain
Current and Gate Voltage
2.75
2.25
10
VGS = 10 V
TJ = 25°C
Figure 3. On−Region versus Gate−to−Source
Voltage
2.50
3
4
5
6
7
8
9
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 1. On−Region Characteristics
12
TJ = 25°C
4.0
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
5.0
6.6 V
ID = 1.2 A
VGS = 10 V
1.10
2.00
1.05
1.75
1.50
1.00
1.25
1.00
0.95
0.75
0.50
0.25
−50
ID = 1 mA
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
150
0.90
−50
Figure 5. On−Resistance Variation with
Temperature
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125 150
Figure 6. BVDSS Variation with Temperature
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3
NDD03N80Z, NDF03N80Z
TYPICAL CHARACTERISTICS
10000
C, CAPACITANCE (pF)
TJ = 150°C
1.0
TJ = 125°C
0.1
0
50
1000
Ciss
Coss
100
Crss
10
1
100 150 200 250 300 350 400 450 500
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TJ = 25°C
VGS = 0 V
f = 1 MHz
1
Figure 7. Drain−to−Source Leakage Current
versus Voltage
VGS, GATE−TO−SOURCE VOLTAGE (V)
15.0
14.0
13.0
12.0
11.0
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
100
Figure 8. Capacitance Variation
450
QT
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
IDSS, LEAKAGE (mA)
10.0
400
VDS
350
VGS
QGS
QGD
300
250
200
150
VDS = 400 V
ID = 3.3 A
TJ = 25°C
0
2
4
6
8
10 12 14 16
Qg, TOTAL GATE CHARGE (nC)
18
100
50
0
20
Figure 9. Gate−to−Source Voltage and
Drain−to−Source Voltage versus Total Charge
100
VDD = 400 V
ID = 3 A
VGS = 10 V
100
IS, SOURCE CURRENT (A)
t, TIME (ns)
1000
td(off)
tr
tf
td(on)
10
1.0
1
10
RG, GATE RESISTANCE (W)
10
1.0
0.1
0.3
100
Figure 10. Resistive Switching Time Variation
versus Gate Resistance
TJ = 150°C
125°C
25°C
−55°C
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 11. Diode Forward Voltage versus
Current
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4
1.2
NDD03N80Z, NDF03N80Z
TYPICAL CHARACTERISTICS
ID, DRAIN CURRENT (A)
100
10
VGS ≤ 30 V
SINGLE PULSE
TC = 25°C
100 ms 10 ms
1 ms
10 ms
dc
1
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
1
10
100
1000
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area − NDD03N80Z
10
R(t) (C/W)
1
50% (DUTY CYCLE)
20%
10%
0.1 5.0%
2.0%
RqJC = 1.3°C/W
Steady State
1.0%
0.01
0.000001
SINGLE PULSE
0.00001
0.0001
0.001
0.01
0.1
1
10
PULSE TIME (s)
Figure 13. Thermal Impedance (Junction−to−Case) − NDD03N80Z
LEADS
HEATSINK
0.110″ MIN
Figure 14. Isolation Test Diagram
Measurement made between leads and heatsink with all leads shorted together.
*For additional mounting information, please download the ON Semiconductor
Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
5
100
1000
NDD03N80Z, NDF03N80Z
Table 1. ORDERING INFORMATION
Package
Shipping†
NDD03N80Z−1G
IPAK
(Pb-Free, Halogen-Free)
75 Units / Rail
NDD03N80ZT4G
DPAK
(Pb-Free, Halogen-Free)
2500 / Tape & Reel
NDF03N80ZH
(In Development)
TO−220FP
(Pb-Free, Halogen-Free)
50 Units / Rail
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
4
Drain
YWW
3N
80ZG
YWW
3N
80ZG
4
Drain
1 2 3
Gate Drain Source
IPAK
NDF03N80ZH
AYWW
Gate
2
1 Drain 3
Gate Source
DPAK
A
Y
WW
G, H
= Location Code
= Year
= Work Week
= Pb−Free, Halogen−Free Package
http://onsemi.com
6
Source
Drain
TO−220FP
NDD03N80Z, NDF03N80Z
PACKAGE DIMENSIONS
TO−220 FULLPACK, 3−LEAD
CASE 221AH
ISSUE C
A
E
B
P
E/2
0.14
Q
D
M
B A
M
A
H1
A1
C
NOTE 3
1 2 3
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. CONTOUR UNCONTROLLED IN THIS AREA.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH
AND GATE PROTRUSIONS. MOLD FLASH AND GATE
PROTRUSIONS NOT TO EXCEED 0.13 PER SIDE. THESE
DIMENSIONS ARE TO BE MEASURED AT OUTERMOST
EXTREME OF THE PLASTIC BODY.
5. DIMENSION b2 DOES NOT INCLUDE DAMBAR
PROTRUSION. LEAD WIDTH INCLUDING PROTRUSION
SHALL NOT EXCEED 2.00.
DIM
A
A1
A2
b
b2
c
D
E
e
H1
L
L1
P
Q
L1
3X
3X
SEATING
PLANE
b2
c
b
0.25
B A
M
M
C
A2
e
MILLIMETERS
MIN
MAX
4.30
4.70
2.50
2.90
2.50
2.70
0.54
0.84
1.10
1.40
0.49
0.79
14.70
15.30
9.70
10.30
2.54 BSC
6.70
7.10
12.70
14.73
--2.80
3.00
3.40
2.80
3.20
IPAK
CASE 369D
ISSUE C
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
D
G
H
3 PL
0.13 (0.005)
M
T
http://onsemi.com
7
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
NDD03N80Z, NDF03N80Z
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA
ISSUE B
A
E
b3
c2
B
Z
D
1
L4
A
4
L3
b2
e
2
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
H
DETAIL A
3
c
b
0.005 (0.13)
M
H
C
L2
GAUGE
PLANE
C
L
SEATING
PLANE
A1
L1
DETAIL A
ROTATED 905 CW
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.030 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.108 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.76
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.74 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.102
5.80
0.228
3.00
0.118
1.60
0.063
6.17
0.243
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
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8
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For additional information, please contact your local
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NDD03N80Z/D