INTEGRATED CIRCUITS NE56610/11/12-XX System reset Product data Supersedes data of 2001 Apr 24 File under Integrated Circuits, Standard Analog 2001 Jun 19 Philips Semiconductors Product data System reset NE56610/11/12-XX GENERAL DESCRIPTION The NE56610/11/12-XX series is a family of devices designed to generate a reset signal for a variety of microprocessor and logic systems. Accurate reset signals are generated during momentary power interruptions or when ever power supply voltages sag to intolerable levels. The NE56610/11/12 incorporates an internal timer to provide reset delay and ensure proper operating voltage has been attained. In addition, a manual reset pin (M/R) is available. An Open Collector output topology provides adaptability for a wide variety of logic and microprocessor systems. NE56610/11/12 is available in the SOT23-5 surface mount package. FEATURES APPLICATIONS • 12 VDC maximum operating voltage • Low operating voltage (0.65 V) • Manual Reset input • SOT23-5 surface mount package • Offered in reset thresholds of 2.5, 2.7, 2.9, 3.9, 4.2, 4.5 VDC • Internal reset delay timer • Microcomputer systems • Logic systems • Battery monitoring systems • Back-up power supply circuits • Voltage detection circuits • Mechanical reset circuits – NE56610 (50 ms typical) – NE56611 (100 ms typical) – NE56612 (200 ms typical) SIMPLIFIED DEVICE DIAGRAM VDD M/R 1 VCC NE56610/11/12-XX VDD RPU 5 4 R RESET DELAY VOUT RESET CPU R VREF 3 2 SUB GND GND SL01362 Figure 1. Simplified device diagram. 2001 Jun 19 2 853–2246 26559 Philips Semiconductors Product data System reset NE56610/11/12-XX ORDERING INFORMATION PACKAGE NAME DESCRIPTION TEMPERATURE RANGE TYPICAL RESET DELAY NE56610-XXGW SOT23-5, SOT25, SO5 plastic small outline package; 5 leads (see dimensional drawing) –20 to +75 °C 50 ms NE56611-XXGW SOT23-5, SOT25, SO5 plastic small outline package; 5 leads (see dimensional drawing) –20 to +75 °C 100 ms NE56612-XXGW SOT23-5, SOT25, SO5 plastic small outline package; 5 leads (see dimensional drawing) –20 to +75 °C 200 ms TYPE NUMBER NOTE: Each device has six detection voltage options, indicated by the XX on the ‘Type number’. XX DETECT VOLTAGE (Typical) 25 2.5 V 27 2.7 V 29 2.9 V 39 3.9 V 42 4.2 V 45 4.5 V Part number marking Each device is marked with a four letter code. The first three letters designate the product. The fourth letter, represented by ‘x’, is a date tracking code. For example, ACNB is device ACN (the NE56610-25 reset) produced in time period ‘B’. Part number Marking Part number Marking Part number Marking NE56610-25 ACNx NE56611-25 ACVx NE56612-25 ACBx NE56610-27 ACMx NE56611-27 ACUx NE56612-27 ACAx NE56610-29 ACLx NE56611-29 ACTx NE56612-29 ACZx NE56610-39 ACKx NE56611-39 ACSx NE56612-39 ACYx NE56610-42 ACJx NE56611-42 ACRx NE56612-42 ACXx NE56610-45 ACHx NE56611-45 ACPx NE56612-45 ACWx PIN CONFIGURATION PIN DESCRIPTION PIN M/R 1 SUB 2 GND 5 VCC NE56610-XX NE56611-XX NE56612-XX 3 4 VOUT SYMBOL DESCRIPTION 1 M/R Manual Reset input. Connect to ground when not using. 2 SUB Substrate pin. Connect to ground. 3 GND Ground 4 VOUT Reset HIGH output pin 5 VCC Positive power supply input SL01361 Figure 2. Pin configuration. MAXIMUM RATINGS MIN. MAX. UNIT VCC SYMBOL Power supply voltage –0.3 12 V VM/R Manual Reset input voltage –0.3 12 V Tamb Operating ambient temperature –20 75 °C Tstg Storage temperature –40 125 °C P Power dissipation – 150 mW 2001 Jun 19 PARAMETER 3 Philips Semiconductors Product data System reset NE56610/11/12-XX ELECTRICAL CHARACTERISTICS Characteristics noted with M/R pin connected to ground. Typical values reflect appropriate average value at Tamb = 25 °C. SYMBOL VS PARAMETER Threshold detection CONDITIONS TEST CIRCUIT VCC falling; RL = 470 Ω; VOL ≤ 0.4 V PART # MIN. TYP. MAX. UNIT –45 4.3 4.5 4.7 V –42 4.0 4.2 4.4 V –39 3.7 3.9 4.1 V –29 2.75 2.90 3.05 V –27 2.55 2.70 2.85 V –25 2.35 2.50 2.65 V All 30 50 100 mV RL = 470 Ω; –20 °C ≤ Tamb ≤ +75 °C All – ±0.01 – %/°C VCC = VS(min) – 0.05 V; RL = 470 Ω All – 0.01 0.4 V VCC = 10 V All – – ±0.1 µA ∆VS = VSH (rising VCC) – VSL (falling VCC); RL = 470 Ω 1 Fig. 20 ∆VS Hysteresis ∆TC/∆VS Threshold temperature coefficient VOL LOW-level output voltage ILO Output leakage current ICCL Circuit current (output LOW) VCC = VS(min) – 0.05 V; RL = ∞ All – 300 500 µA ICCH Circuit current (output HIGH) VCC = VS(typ) / 0.85 V; RL = ∞ All – 15 25 µA tDLH Reset delay time HIGH (Note 1) RL = 4.7 kΩ; CL = 100 pF NE56610 30 50 75 ms NE56611 60 100 150 ms NE56612 120 200 300 ms 2 Fig. 21 tDHL Reset delay time LOW (Note 2) RL = 4.7 kΩ; CL = 100 pF All – 20 – µs VOPL Operating supply voltage RL = 4.7 kΩ; VOL ≤ 0.4 V All – 0.65 0.85 V IOL1 Output sink current 1 VCC = VS(min) – 0.05 V; RL = 0 All –8.0 – – mA IOL2 Output sink current 2 VCC = VS(min) – 0.05 V; RL = 0; –20 °C ≤ Tamb ≤ +75 °C All –6.0 – – mA VM/RH HIGH-level M/R threshold voltage (Note 3) All 2.0 – – V IM/RH HIGH-level M/R threshold current All – 10 60 µA VM/RL LOW-level M/R threshold voltage All –0.3 – 0.8 V tM/R M/R pulse width (Note 4) All 15 – – µs VM/RH = 2.0 V 1 Fig. 20 Fig NOTES: 1. tDLH measured with VCC = (VS(typ) – 0.4 V) and abruptly transitioning to (VS(typ) + 0.4 V). tDLH is the duration from VCC transition HIGH to output transition HIGH. 2. tDHL measured with VCC = (VS(typ) + 0.4 V) and abruptly transitioning to (VS(typ) – 0.4 V). tDHL is the duration from VCC transition LOW to output transition LOW. 3. Ramp M/R voltage until output RESET goes LOW. 4. Minimum M/R pulse width for detection. 2001 Jun 19 4 Philips Semiconductors Product data System reset NE56610/11/12-XX TYPICAL PERFORMANCE CURVES 500 0.10 0.05 0.00 –0.05 –0.10 –50 –25 0 25 50 VCC = VS(min) – 0.05 V RL = ∞ I CCL, CIRCUIT ON CURRENT (µA) VS, NORMALIZED DETECTION (V) THRESHOLD NORMALIZED TO 25 °C RL (PULL-UP TO VCC) 470 Ω VOL ≤ 0.4 V 75 100 400 300 200 100 –50 125 –25 Tamb, AMBIENT TEMPERATURE (°C) 0 25 50 75 100 SL01363 SL01334 Figure 3. Normalized detection versus temperature. Figure 4. Circuit ON current versus temperature. 30 80 I CCH , CIRCUIT OFF CURRENT (µA) ∆ VS , DETECTION HYSTERESIS (mV) ∆VS = VSH – VSL RL (PULL-UP TO VCC) = 470 Ω 70 60 50 40 –50 –25 0 25 50 75 100 VCC = VS(typ) + 0.85 V RL = ∞ 25 20 15 10 –50 125 –25 Tamb, AMBIENT TEMPERATURE (°C) 0 25 50 75 100 SL01366 Figure 5. Detection hysteresis versus temperature. Figure 6. Circuit OFF current versus temperature. 900 120 VOL ≤ 0.4 V RL = 4.7 kΩ VOPL, OPERATING SUPPLY (mV) VOL, LOW-LEVEL OUTPUT (mV) VCC = VS(min) – 0.05 V RL (PULL-UP TO VCC) = 470 Ω 100 80 60 –25 0 25 50 75 100 800 700 600 500 400 –50 125 Tamb, AMBIENT TEMPERATURE (°C) –25 0 25 50 75 100 125 Tamb, AMBIENT TEMPERATURE (°C) SL01367 SL01368 Figure 7. LOW-level output voltage versus temperature. 2001 Jun 19 125 Tamb, AMBIENT TEMPERATURE (°C) SL01365 40 –50 125 Tamb, AMBIENT TEMPERATURE (°C) Figure 8. Operating supply voltage versus temperature. 5 Philips Semiconductors Product data System reset NE56610/11/12-XX 70 I M/RH , M/R INPUT HIGH CURRENT ( µA) 25 60 50 40 30 –50 –25 0 25 50 75 100 VCC = 5.0 V VM/RH = 2.0 V 20 15 10 5 –50 125 –25 Tamb, AMBIENT TEMPERATURE (°C) 0 25 50 75 100 SL01369 SL01370 Figure 9. Output ON current versus temperature. Figure 10. M/R input HIGH current versus temperature. 1.6 RL = 4.7 kΩ CL = 100 pF VCC = 5.0 V SA56612 VM/RH, M/R THRESHOLD HIGH (V) t DLH , RESET DELAY TIME HIGH (ms) 250 225 200 175 150 125 SA56611 100 75 SA56610 50 25 –50 –25 0 25 50 75 100 1.4 1.2 1.0 0.8 0.6 –50 125 –25 Tamb, AMBIENT TEMPERATURE (°C) 0 25 50 75 Figure 12. M/R threshold HIGH versus temperature. 5.0 500 14 RL = 470 Ω Tamb = 25 °C RL = 4.7 kΩ CL = 100 pF I CC, SUPPLY CURRENT ( µA) t DHL, RESET DELAY TIME LOW (µs) 125 SL01377 Figure 11. Reset delay time HIGH versus temperature. 13 12 11 VOUT 4.0 400 300 3.0 ∆VS ICC 200 2.0 100 1.0 0 –25 0 25 50 75 100 125 0 Tamb, AMBIENT TEMPERATURE (°C) 1.0 2.0 3.0 4.0 0 5.0 VCC, SUPPLY VOLTAGE (V) SL01378 SL01379 Figure 13. Reset delay time LOW versus temperature. 2001 Jun 19 100 Tamb, AMBIENT TEMPERATURE (°C) SL01376 10 –50 125 Tamb, AMBIENT TEMPERATURE (°C) VOUT , OUTPUT VOLTAGE (V) I OL, CIRCUIT ON CURRENT (µA) VCC = VS(min) – 0.05 V RL = 0 Figure 14. ICC and VOUT versus supply voltage. 6 Philips Semiconductors Product data System reset NE56610/11/12-XX t OUT , OUTPUT SINK CURRENT (mA) 40 VCC = VS(min) – 0.05 V RL = 0 Tamb = 25 °C 35 30 25 20 15 10 5 0 0 –0.2 –0.4 –0.6 –0.8 –1.0 VOUT, OUTPUT VOLTAGE (V) SL01378 Figure 15. Output sink current versus output voltage. 2001 Jun 19 7 Philips Semiconductors Product data System reset NE56610/11/12-XX TECHNICAL DESCRIPTION Incorporating a delay in the output RESET prevents output oscillations from occurring and helps ensure system supply voltages are adequate and stabilized before the microprocessor is placed into full operation. Where there is little or no delay in output RESET, there is a possibility of output oscillations occurring, particularly where high impedance supply sources are used. The NE56610/11/12-XX devices comprise a family of devices designed to monitor the supply voltage and output a RESET signal whenever the supply voltage sags below an acceptable system level or when supply voltage interruptions occur. Each of the three devices of the family are available with a fixed detection threshold voltage (2.5, 2.7, 2.9, 3.9, 4.2, 4.5 V). The device family is very versatile and adaptable for a wide variety of applications. In addition, the devices have a manual reset (M/R) pin, which when pulled to a HIGH voltage state, forces a RESET signal at the output. The M/R pin should always be connected to ground when manual reset is not used. The devices are designed to have a detection threshold hysteresis of 50 mV typical. When the supply voltage delivered to the device falls to the detection sense level (VS), a RESET is output and not released until the supply voltage rises to the level of VS or greater. These levels are termed VL (synonymous with VS) and VH, and the difference of VH – VL = VHYS (the hysteresis voltage value). The output of the NE56610/11/12 utilizes a low side open collector topology, requiring the user to use an external pull-up resistor (RPU) to the VCC power source. Although this may be regarded as a disadvantage, it is an advantage in many sensitive applications. The open drain output topology does not have the capability of sourcing reset current to a microprocessor when both are operated from a common supply. It is for this reason the device family offers a safe inter-connect to a wide variety of microprocessors. Internally, the devices incorporate a fixed internal digital timer which, when activated, produces a fixed internal delay before a RESET signal is output. This delay can not be influenced externally. The NE56510 has an internal delay of 50 ms, while the NE56611 and NE56612 have internal delays of 100 ms and 200 ms respectively. VCC 5 DELAY R OSC T Q R R R M/R 1 R R NE56610/11/12-XX 4 VOUT RESET 3 GND 2 SUB R R SL01382 Figure 16. Functional diagram 2001 Jun 19 8 Philips Semiconductors Product data System reset NE56610/11/12-XX TIMING DIAGRAM E-F: Between ‘E’ and ‘F’, VCC recovers and starts to rise. The Timing Diagram shown in Figure 17 depicts the operation of the device. Letters indicate events on the TIME axis. F: At event ‘F’, VCC reaches the upper threshold (VSH). Once again, the tDLH fixed internal delay time is initiated. A: At start-up, event ‘A’, the VCC and VOUT (RESET) voltages begin to rise. The reset voltage initially starts to rise but then abruptly returns to a LOW voltage state. This is due to VCC reaching a level (approximately 0.8 V) which activates the internal bias circuitry asserting a RESET state at VOUT. G: At event ‘G’, VCC is above the VSL undervoltage detection voltage and the tDLH fixed internal delay time has elapsed. At this point the device releases the hold on VOUT and VOUT goes to a HIGH state. B: At event ‘B’, the fixed internal delay time (tDLH) is initiated. This is caused and coincident to VCC rising to the threshold level of VSH. At this level the device is in full operation. The output remains in a low voltage state as VCC rises above VSH. This is normal. H-K: At event ‘H’, VCC is normal, but a manual reset voltage (HIGH voltage state) has been applied to the M/R pin. This forces the output into a reset (LOW voltage state). Removal of the manual reset voltage, at ‘J’, from the M/R pin initiates the fixed internal delay time, and at ‘K’, the internal delay time has elapsed and VOUT goes to a HIGH voltage state. C: At event ‘C’, VCC is above the undervoltage detection threshold (VSL) and the fixed internal delay time (tDLH) has elapsed. At this instant the device releases the hold on VOUT and VOUT (RESET) goes to a high state. L: At event ‘L’, VCC sags to the VSL undervoltage threshold level and the output goes into low voltage reset condition. In a microprocessor-based system these events remove the reset from the microprocessor, allowing the microprocessor to be fully functional. M: At event ‘M’, the VCC voltage has deteriorated to a level where normal internal circuit bias is no longer able to maintain the device and VOUT reset assertion is no longer be guaranteed. As a result, VOUT may exhibit a slight rise to something less than 0.8 V. As VCC decays even further, VOUT reset also decays to zero. D-E: At event ‘D’, VCC begins to ramp down and VOUT follows. VCC continues to fall until the undervoltage threshold (VSL) is reached at ‘E’. This causes the device to generate a reset signal. ∆VS VSH VSS = VSL V VCC V VOUT RESET tDLH tDLH tDLH V M/R VRES 0 A B C D E F G H J K L M TIME SL01381 Figure 17. Timing diagram. 2001 Jun 19 9 Philips Semiconductors Product data System reset NE56610/11/12-XX APPLICATION INFORMATION When the manual reset is not needed, the M/R, manual reset pin is connected to ground as shown in Figure 18. A capacitor connected from VCC to ground is recommended when the VCC supply impedance is appreciably high. This may be the situation with a poor quality or aged battery. RPU MANUAL SWITCH TO CPU RESET PIN TO VCC RPU 5 4 VCC VOUT M/R 5 4 VCC VOUT SUB 1 SUB 1 CLAMP DIODE M/R TO CPU RESET PIN TO VCC 2 GND 3 RPD GND 2 SL01384 3 Figure 19. Manual Reset circuit When a manual reset is used, it is suggested a resistor (RPU) be connected from the M/R pin to ground so as to provide a pull-down ground reference for the M/R pin when not in use. This will reduce the possibility of an induced erroneous voltage being imposed on the M/R pin. This can be a solution in noisy applications where the manual reset line is of considerable length and subject to picking up induced voltages. The M/R pin can be pulled to a HIGH voltage state whenever a manual reset is imposed. The only disadvantage to this is a small amount of additional current flow through the pull-down ground reference resistor when the M/R pin is pulled to a HIGH state. SL01383 Figure 18. Typical hard reset circuit Figure 19 shows a circuit with a manual reset switch. When the manual switch is closed, VOUT reset is a low voltage state. Conversely, when it is opened, VOUT reset is a HIGH voltage state. As a precaution, a clamp diode is placed from the M/R pin to ground to ensure that the pin does not go below –0.3 V. TEST CIRCUITS A2 RPU A1 5 4 VCC VOUT 5 4 VCC VOUT RPU 10 µF/10 V V1 INPUT PULSE M/R 1 VCC M/R SUB GND 10 µF/10 V SUB 2 GND 5.0 V 3 V2 CRT 1 2 3 CL 100 pF VM/R CRT = OSCILLOSCOPE INPUT PULSE VS(typ) + 0.4 V A = DC AMPMETER V = DC VOLTMETER VS(typ) – 0.4 V SL01385 0V Figure 20. Test circuit 1 SL01386 Figure 21. Test circuit 2 2001 Jun 19 10 Philips Semiconductors Product data System reset NE56610/11/12-XX PACKING METHOD The NE56610/11/12 is packed in reels, as shown in Figure 22. GUARD BAND TAPE REEL ASSEMBLY TAPE DETAIL COVER TAPE CARRIER TAPE BARCODE LABEL BOX SL01305 Figure 22. Tape and reel packing method 2001 Jun 19 11 Philips Semiconductors Product data System reset NE56610/11/12-XX SOT23-5: plastic small outline package; 5 leads; body width 1.5 mm 1.35 2001 Jun 19 1.2 1.0 0.025 0.55 0.41 0.22 0.08 3.00 2.70 1.70 1.50 0.55 0.35 12 Philips Semiconductors Product data System reset NE56610/11/12-XX NOTES 2001 Jun 19 13 Philips Semiconductors Product data System reset NE56610/11/12-XX Data sheet status Data sheet status [1] Product status [2] Definitions Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] Please consult the most recently issued datasheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 06-01 Document order number: 2001 Jun 19 14 9397 750 08452