ETC NT5DS32M8AW-7K

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Features
•
•
•
•
CAS Latency and Frequency
Maximum Operating Frequency (MHz)*
DDR266A
DDR266B
DDR200
(-7K)
(-75B)
(-8B)
2
133
100
100
2.5
143
133
125
* Values are nominal (exact tCK should be used).
CAS Latency
•
•
•
•
•
•
•
•
•
• Double data rate architecture: two data transfers per
clock cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is centeraligned with data for writes
• Differential clock inputs (CK and CK)
Four internal banks for concurrent operation
Data mask (DM) for write data
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
Burst lengths: 2, 4, or 8
CAS Latency: 2, 2.5
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
7.8µs Maximum Average Periodic Refresh Interval
2.5V (SSTL_2 compatible) I/O
VDDQ = 2.5V ± 0.2V
VDD = 2.5V ± 0.2V
-7K parts support PC2100 modules.
-75B parts support PC2100 modules
-8B parts support PC1600 modules
Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic
random-access memory containing 268,435,456 bits. It is
internally configured as a quad-bank DRAM.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4 or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst access.
The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate
architecture is essentially a 2n prefetch architecture with an
interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 256Mb
DDR SDRAM effectively consists of a single 2n-bit wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided along with a power-saving
power-down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edgealigned with data for Reads and center-aligned with data for
Writes.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode
of operation.
The 256Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write command. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Pin Configuration - 256Mb DDR SDRAM (x4 / x8)
VDD
VDD
1
66
VSS
VSS
NC
DQ0
2
65
DQ7
NC
VDDQ
VDDQ
3
64
VSSQ
VSSQ
NC
NC
4
63
NC
NC
DQ0
DQ1
5
62
DQ6
DQ3
VSSQ
VSSQ
6
61
VDDQ
VDDQ
NC
NC
7
60
NC
NC
NC
DQ2
8
59
DQ5
NC
VDDQ
VDDQ
9
58
VSSQ
VSSQ
NC
NC
10
57
NC
NC
DQ1
DQ3
11
56
DQ4
DQ2
VSSQ
VSSQ
12
55
VDDQ
VDDQ
NC
NC
13
54
NC
NC
NC
NC
14
53
NC
NC
VDDQ
VDDQ
15
52
VSSQ
VSSQ
NC
NC
16
51
DQS
DQS
NC
NC
17
50
NC
NC
VDD
VDD
18
49
VREF
VREF
NU
NU
19
48
VSS
VSS
NC
NC
20
47
DM*
DM*
WE
CAS
WE
CAS
21
46
22
45
CK
CK
CK
CK
RAS
RAS
23
44
CKE
CKE
CS
CS
24
43
NC
NC
NC
NC
25
42
A12
A12
BA0
26
A11
27
41
40
A11
BA1
BA0
BA1
A10/AP
A10/AP
28
39
A9
A8
A9
A8
A0
A0
29
38
A7
A7
A1
A1
30
37
A6
A6
A2
A2
31
36
A5
A5
A3
A3
VDD
VDD
32
33
35
34
A4
VSS
A4
VSS
66-pin Plastic TSOP-II 400mil
32Mb x 8
NT5DS32M8AT
64Mb x 4
NT5DS64M4AT
Column Address Table
Organization
Column Address
64Mb x 4
A0-A9, A11
32Mb x 8
A0-A9
*DM is internally loaded to match DQ and DQS identically.
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CSP Package
<Top View >
See the balls through the package.
64 X 4
1
2
3
7
8
9
VSSQ
NC
VSS
A
VDD
NC
VDDQ
NC
VDDQ
DQ3
B
DQ0
VSSQ
NC
NC
VSSQ
NC
C
NC
VDDQ
NC
NC
VDDQ
DQ2
D
DQ1
VSSQ
NC
NC
VSSQ
DQS
E
NC
VDDQ
NC
VREF
VSS
DQM
F
NC
VDD
NC
CLK
CLK
G
WE
CAS
A12
CKE
H
RAS
CS
A11
A9
J
BA1
BA0
A8
A7
K
A0
A10/AP
A6
A5
L
A2
A1
A4
VSS
M
VDD
A3
7
8
9
32 X 8
REV 1.1
12/2001
1
2
3
VSSQ
DQ7
VSS
A
VDD
DQ0
VDDQ
NC
VDDQ
DQ6
B
DQ1
VSSQ
NC
NC
VSSQ
DQ5
C
DQ2
VDDQ
NC
NC
VDDQ
DQ4
D
DQ3
VSSQ
NC
NC
VSSQ
DQS
E
NC
VDDQ
NC
VREF
VSS
DQM
F
NC
VDD
NC
CLK
CLK
G
WE
CAS
A12
CKE
H
RAS
CS
A11
A9
J
BA1
BA0
A8
A7
K
A0
A10/AP
A6
A5
L
A2
A1
A4
VSS
M
VDD
A3
3
© NANYA TECHNOLOGY CORP. All rights reserved.
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Input/Output Functional Description
Symbol
Type
Function
Input
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing).
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self
Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self
refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE, are
disabled during self refresh. The standard pinout includes one CKE pin. Optional pinouts might
include CKE1 on a different pin, in addition to CKE0, to facilitate independent power down control
of stacked devices.
CS, CS0, CS1
Input
Chip Select: All commands are masked when CS is registered high. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code. The
standard pinout includes one CS pin. Optional pinouts might include CS1 on a different pin, in
addition to CS0, to allow upper or lower deck selection on stacked devices.
RAS, CAS, WE
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DM
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled high coincident with that input data during a Write access. DM is sampled on both edges
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. During a Read, DM can be driven high, low, or floated.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. BA0 and BA1 also determines if the mode register or extended mode
register is to be accessed during a MRS or EMRS cycle.
A0 - A12
Input
Address Inputs: Provide the row address for Active commands, and the column address and
Auto Precharge bit for Read/Write commands, to select one location out of the memory array in
the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged,
the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode
Register Set command.
DQ
Input/Output
Data Input/Output: Data bus.
DQS
Input/Output
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered
in write data. Used to capture write data.
CK, CK
CKE, CKE0, CKE1
NC
No Connect: No internal electrical connection is present.
NU
Electrical connection is present. Should not be connected at second level of assembly.
VDDQ
Supply
DQ Power Supply: 2.5V ± 0.2V.
VSSQ
Supply
DQ Ground
VDD
Supply
Power Supply: 2.5V ± 0.2V.
VSS
Supply
Ground
VREF
Supply
SSTL_2 reference voltage: (VDDQ / 2) ± 1%.
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Ordering Information
Part Number
Org.
NT5DS64M4AT-7K
x4
NT5DS32M8AT-7K
x8
NT5DS64M4AT-75B
x4
NT5DS32M8AT-75B
x8
NT5DS64M4AT-8B
x4
NT5DS32M8AT-8B
x8
NT5DS64M4AW-7K
x4
NT5DS32M8AW-7K
x8
NT5DS64M4AW-75B
x4
NT5DS32M8AW-75B
x8
NT5DS64M4AW-8B
x4
NT5DS32M8AW-8B
x8
CAS
Latency
Clock
(MHz)
CAS
Latency
Clock
(MHz)
Speed
133
DDR266A
100
DDR266B
125
100
DDR200
143
133
DDR266A
100
DDR266B
100
DDR200
143
2.5
2.5
133
2
133
2
125
Package
66 pin TSOP-II
60 ball CSP
Note: At the present time, there are no plans to support DDR SDRAMs with the QFC function. All reference to QFC are for information.
REV 1.1
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Control Logic
2
Bank2
Bank3
CK, CK
DLL
2
8192
4
4
4
1
DQS
Generator
COL0
I/O Gating
DM Mask Logic
8
8
1024
(x8)
Write
FIFO
&
Drivers
1
1
4
4
4
clk clk
out in Data
4
10
Column-Address
Counter/Latch
Input
Register
1
Mask 1
2
8
Column
Decoder
11
Drivers
8
Sense Amplifiers
Data
MUX
Bank0
Memory
Array
(8192 x 1024 x 8)
Read Latch
8192
CK,
CK
COL0
DQS
DQ0-DQ3,
DM
DQS
1
Receivers
15
Refresh Counter 13
A0-A12,
BA0, BA1
13
Address Register
15
13
Bank Control Logic
Mode
Registers
Bank0
Row-Address Latch
& Decoder
Bank1
Row-Address MUX
CKE
CK
CK
CS
WE
CAS
RAS
Command
Decode
Block Diagram (64Mb x 4)
4
COL0
1
1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
REV 1.1
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Control Logic
CK, CK
DLL
16
Sense Amplifiers
2
Data
8
8
16
16
512
(x16)
1
DQS
Generator
Write
FIFO
&
Drivers
1
1
8
8
8
clk clk
out in Data
8
9
Column-Address
Counter/Latch
Input
Register
1
Mask 1
2
16
Column
Decoder
10
8
COL0
I/O Gating
DM Mask Logic
CK,
CK
COL0
Drivers
Bank0
Memory
Array
(8192 x 512 x 16)
MUX
8192
DQS
DQ0-DQ7,
DM
DQS
1
Receivers
2
Bank3
Read Latch
Refresh Counter 13
15
Address Register
A0-A12,
BA0, BA1
Bank2
8192
13
15
13
Bank Control Logic
Mode
Registers
Bank0
Row-Address Latch
& Decoder
Bank1
Row-Address MUX
CKE
CK
CK
CS
WE
CAS
RAS
Command
Decode
Block Diagram (32Mb x 8)
8
COL0
1
1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
REV 1.1
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Functional Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456 bits. The 256Mb
DDR SDRAM is internally configured as a quad-bank DRAM.
The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O
pins. A single read or write access for the 256Mb DDR SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at
the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is
then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select
the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident
with the Read or Write command are used to select the starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed infor-mation covering
device initialization, register definition, command descriptions and device operation.
Initialization
Only one of the following two conditions must be met.
• No power sequencing is specified during power up or power down given the following criteria:
VDD and VDDQ are driven from a single power converter output
VTT meets the specification
A minimum resistance of 42 ohms limits the input current from the VTT supply into any pin and
VREF tracks VDDQ /2
or
• The following relationships must be followed:
VDDQ is driven after or with VDD such that V DDQ < VDD + 0.3V
VTT is driven after or with V DDQ such that V TT < VDDQ + 0.3V
VREF is driven after or with V DDQ such that V REF < VDDQ + 0.3V
The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read access). Afterall power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to
applying an executable command.
Once the 200µs delay has been satisfied, a Deselect or NOP command should be applied, and CKE must be brought HIGH.
Following the NOP command, a Precharge ALL command must be applied. Next a Mode Register Set command must be
issued for the Extended Mode Register, to enable the DLL, then a Mode Register Set command must be issued for the Mode
Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and
any read command. A Precharge ALL command should be applied, placing the device in the “all banks idle” state
Once in the idle state, two auto refresh cycles must be performed. Additionally, a Mode Register Set command for the Mode
Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must be performed.
Following these cycles, the DDR SDRAM is ready for normal operation.
DDR SDRAM’s may be reinitialized at any time during normal operation by asserting a valid MRS command to either the base
or extended mode registers without affecting the contents of the memory array. The contents of either the mode register or
extended mode register can be modified at any valid time during device operation without affecting the state of the internal
address refresh counters used for device refresh.
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Register Definition
Mode Register
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of
a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is programmed via the Mode Register
Set command (with BA0 = 0 and BA1 = 0) and retains the stored information until it is programmed again or the device loses
power (except for bit A8, which is self-clearing).
Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the
CAS latency, and A7-A12 specify the operating mode.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the
subsequent operation. Violating either of these requirements results in unspecified operation.
Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length
determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths
of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for
that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is
uniquely selected by A1-Ai when the burst length is set to two, by A 2-Ai when the burst length is set to four and by A3-Ai when
the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining
(least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length
applies to both Read and Write bursts.
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Mode Register Operation
BA1
BA0
0*
0*
A12 - A9
A8
A12
A11 A10
A9
A8
A7
A6 - A0
Operating Mode
0
0
0
Valid
Normal operation
Do not reset DLL
0
1
0
Valid
Normal operation
in DLL Reset
0
0
1
−
−
−
A5
A4
CAS Latency
Operating Mode
A7
A6
A3
A2
BT
A1
Burst Length
A3
Burst
Type
0
Sequential
1
Interleave
A0
Address Bus
Mode Register
Vendor-Specific
Test Mode
VS**
Reserved
CAS Latency
Burst Length
A6
A5
A4
Latency
A2
A1
A0
Burst Length
0
0
0
Reserved
0
0
0
Reserved
0
0
1
Reserved
0
0
1
2
0
1
0
2
0
1
0
4
0
1
1
Reserved
0
1
1
8
1
0
0
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
0
1
Reserved
1
1
0
2.5
1
1
0
Reserved
1
1
1
Reserved
1
1
1
Reserved
VS** Vendor Specific
* BA0 and BA1 must be 0, 0 to select the Mode Register
(vs. the Extended Mode Register).
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Burst Definition
Starting Column Address
Order of Accesses Within a Burst
Burst Length
A2
A1
A0
Type = Sequential
Type = Interleaved
0
0-1
0-1
1
1-0
1-0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
2
4
8
Notes:
1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type
and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definition on page 11.
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability
of the first burst of output data. The latency can be programmed 2 or 2.5 clocks.
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with
clock edge n + m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
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Operating Mode
The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to zero, and bits A0-A6 set
to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to
zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register Set command issued to reset the DLL should
always be followed by a Mode Register Set command to select normal operating mode.
All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states
should not be used as unknown operation or incompatibility with future versions may result.
CAS Latencies
CAS Latency = 2, BL = 4
CK
CK
Command
Read
NOP
NOP
NOP
NOP
NOP
CL=2
DQS
DQ
CAS Latency = 2.5, BL = 4
CK
CK
Command
Read
NOP
NOP
NOP
NOP
NOP
CL=2.5
DQS
DQ
Shown with nominal t AC , tDQSCK, and tDQSQ.
REV 1.1
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Extended Mode Register
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions
include DLL enable/disable, bit A0; output drive strength selection, bit A1; and QFC output enable/disable, bit A2 (NTC
optional). These functions are controlled via the bit settings shown in the Extended Mode Register Definition. The Extended
Mode Register is programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are
idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements result in unspecified operation.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when
entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled,
200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before a Read command
can be issued. This is the reason for introducing timing parameter tXSRD for DDR SDRAM’s (Exit Self Refresh to Read Command). Non- Read commands can be issued 2 clocks after the DLL is enabled via the EMRS command (t MRD) or 10 clocks after
the DLL is enabled via self refresh exit command (t XSNR, Exit Self Refresh to Non-Read Command).
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II.
QFC Enable/Disable
The QFC signal is an optional DRAM output control used to isolate module loads (DIMMs) from the system memory bus by
means of external FET switches when the given module (DIMM) is not being accessed. The QFC function is an optional feature
for NTC and is not included on all DDR SDRAM devices. Refer to the DDR SDRAM Device Labeling Table for proper differentiation when ordering DDR devices with or without the QFC function. The QFC output is an open drain driver and must be connected to V DDQ through a pull up resistor at the board level if the QFC function is enabled. The recommended pull up resistance
is 150 ohms.
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Extended Mode Register Definition
BA1
BA0
0*
1*
A12
A11
A10
A8
A9
A7
A6
A5
A4
A3
Operating Mode
A2
A1
A0
Address Bus
QFC
DS
DLL
Extended
Mode Register
Drive Strength
A12 - A3
A2 - A0
Operating Mode
0
Valid
Normal Operation
−
−
All other states
Reserved
A2
QFC
0
Disable
* BA0 and BA1 must be 1, 0 to select the Extended Mode Register
(vs. the base Mode Register)
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A1
Drive Strength
0
Normal
1
Reserved
A0
DLL
0
Enable
1
Disable
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Commands
Truth Tables 1a and 1b provide a reference of the commands supported by DDR SDRAM devices. A verbal description of each
commands follows.
Truth Table 1a: Commands
Name (Function)
CS
RAS
CAS
WE
Address
MNE
Notes
Deselect (Nop)
H
X
X
X
X
NOP
1, 9
No Operation (Nop)
L
H
H
H
X
NOP
1, 9
Active (Select Bank And Activate Row)
L
L
H
H
Bank/Row
ACT
1, 3
Read (Select Bank And Column, And Start Read Burst)
L
H
L
H
Bank/Col
Read
1, 4
Write (Select Bank And Column, And Start Write Burst)
L
H
L
L
Bank/Col
Write
1, 4
Burst Terminate
L
H
H
L
X
BST
1, 8
Precharge (Deactivate Row In Bank Or Banks)
L
L
H
L
Code
PRE
1, 5
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)
L
L
L
H
X
AR / SR
1, 6, 7
Mode Register Set
L
L
L
L
Op-Code
MRS
1, 2
1. CKE is high for all commands shown except Self Refresh.
2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects
Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode
Register.)
3. BA0-BA1 provide bank address and A0-A12 provide row address.
4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 9 for x8 and 9, 11 for x4); A10 high enables the Auto Precharge feature (nonpersistent), A10 low disables the Auto Precharge feature.
5. A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care.”
6. This command is auto refreshif CKE is high; Self Refresh if CKE is low.
7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto
Precharge enabled or for write bursts
9. Deselect and NOP are functionally interchangeable.
Truth Table 1b: DM Operation
Name (Function)
DM
DQs
Notes
Write Enable
L
Valid
1
Write Inhibit
H
X
1
1. Used to mask write data; provided coincident with the corresponding data.
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Deselect
The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is
effectively deselected. Operations already in progress are not affected.
No Operation (NOP)
The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted commands from
being registered during idle or wait states. Operations already in progress are not affected.
Mode Register Set
The mode registers are loaded via inputs A0-A12, BA0 and BA1 while issuing the Mode Register Set Command. See mode register descriptions in the Register Definition section. The Mode Register Set command can only be issued when all banks are idle
and no bursts are in progress. A subsequent executable command cannot be issued until t MRD is met.
Active
The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0,
BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for
accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that bank. A Precharge (or Read or Write with
Auto Precharge) command must be issued and completed before opening a different row in the same bank.
Read
The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8; where [i = 9, j = 11] for x4) selects the
starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is
selected, the row being accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains
open for subsequent accesses.
Write
The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8; where [i = 9, j = 11] for x4) selects the
starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is
selected, the row being accessed is precharged at the end of the Write burst; if Auto Precharge is not selected, the row remains
open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic
level appearing coincident with the data. If a given DM signal is registered low, the corresponding data is written to memory; if
the DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that byte/column
location.
Precharge
The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. The
bank(s) will be available for a subsequent row access a specified time (tRP) after the Precharge command is issued. Input A10
determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs
BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle
state and must be activated prior to any Read or Write commands being issued to that bank. A precharge command is treated
as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging.
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Auto Precharge
Auto Precharge is a feature which performs the same individual-bank precharge function described above, but without requiring
an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific Read or Write
command. A precharge of the bank/row that is addressed with the Read or Write command is automatically performed upon
completion of the Read or Write burst. Auto Precharge is nonpersistent in that it is either enabled or disabled for each individual
Read or Write command. Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This is
determined as if an explicit Precharge command was issued at the earliest possible time without violating t RAS(min). The user
must not issue another command to the same bank until the precharge (tRP) is completed.
The NTC DDR SDRAM devices supports the optional tRAS lockout feature. This feature allows a Read command with Auto Precharge to be issued to a bank that has been activated (opened) but has not yet satisfied the tRAS(min) specification. The t RAS
lockout feature essentially delays the onset of the auto precharge operation until two conditions occur. One, the entire burst
length of data has been successfully prefetched from the memory array; and two, tRAS(min) has been satisfied.
As a means to specify whether a DDR SDRAM device supports the tRAS lockout feature, a new parameter has been defined,
tRAP (RAS Command to Read Command with Auto Precharge or better stated Bank Activate to Read Command with Auto Precharge). For devices that support the t RAS lockout feature, t RAP = tRCD(min). This allows any Read Command (with or without
Auto Precharge) to be issued to an open bank once tRCD(min) is satisfied.
tRAP Definition
CL=2, tCK=10ns
CK
CK
Command
NOP
ACT
NOP
RD A
NOP
NOP
DQ (BL=2)
DQ0
tRASmin
Command
NOP
ACT
NOP
RD A
NOP
NOP
DQ (BL=4)
Command
DQ0
NOP
ACT
NOP
RD A
NOP
NOP
DQ (BL=8)
DQ0
NOP
NOP
ACT
NOP
NOP
ACT
NOP
NOP
NOP
ACT
NOP
DQ1
*
tRPmin
NOP
DQ1
NOP
DQ2
tRPmin
*
NOP
DQ1
DQ3
NOP
DQ2
tRCDmin
tRAPmin
*
DQ3
*
DQ4
DQ5
DQ6
DQ7
tRPmin
Indicates Auto Precharge begins here
The above timing diagrams show the effects of tRAP for devices that support t RAS lockout. In these cases, the Read
with Auto Precharge command (RDA) is issued with t RCD (min) and dataout is available with the shortest latency from the
Bank Activate command (ACT). The internal precharge operation, however, does not begin until after tRAS(min) is satisfied.
Burst Terminate
The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most re-cently registered
Read command prior to the Burst Terminate command is truncated, as shown in the Operation section of this data sheet. Write
burst cycles are not to be terminated with the Burst Terminate command.
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Auto Refresh
Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS (CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a refresh is required.
The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an Auto
Refresh command. The 256Mb DDR SDRAM requires Auto Refresh cycles at an average periodic interval of 7.8µs (maximum).
Self Refresh
The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down.
When in the self refresh mode, the DDR SDRAM retains data without external clocking. The Self Refresh command is initiated
as an Auto Refresh command coincident with CKE transitioning low. The DLL is automatically disabled upon entering Self
Refresh, and is automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before a Read command can
be issued). Input signals except CKE (low) are “Don’t Care” during Self Refresh operation.
The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to CKE returning
high. Once CKE is high, the SDRAM must have NOP commands issued for t XSNR because time is required for the completion of
any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200
clock cycles before applying any other command.
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Operations
Bank/Row Activation
Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must be “opened”
(activated). This is accomplished via the Active command and addresses A0-A12, BA0 and BA1 (see Activating a Specific Row
in a Specific Bank), which decode and select both the bank and the row to be activated. After opening a row (issuing an Active
command), a Read or Write command may be issued to that row, subject to the tRCD specification. A subsequent Active command to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The
minimum time interval between successive Active commands to the same bank is defined by t RC. A subsequent Active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access
overhead. The minimum time interval between successive Active commands to different banks is defined by t RRD.
Activating a Specific Row in a Specific Bank
CK
CK
CKE
HIGH
CS
RAS
CAS
WE
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A0-A12
RA
BA0, BA1
BA
RA = row address.
BA = bank address.
Don’t Care
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tRCD and tRRD Definition
CK
CK
NOP
ACT
NOP
ACT
A0-A12
ROW
ROW
COL
BA0, BA1
BA x
BA y
BA y
tRRD
NOP
RD/WR
Command
NOP
NOP
tRCD
Don’t Care
Reads
Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a
Read command.
The starting column and bank addresses are provided with the Read command and Auto Precharge is either enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge at the completion of the
burst, provided tRAS has been satisfied. For the generic Read commands used in the following illustrations, Auto Precharge is
disabled.
During Read bursts, the valid data-out element from the starting column address is available following the CAS latency after the
Read command. Each subsequent data-out element is valid nominally at the next positive or negative clock edge (i.e. at the
next crossing of CK and CK). The following timing figure entitled “Read Burst: CAS Latencies (Burst Length=4)” illustrates the
general timing for each supported CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial low
state on DQS is known as the read preamble; the low state coincident with the last data-out element is known as the read postamble. Upon completion of a burst, assuming no other commands have been initiated, the DQs and DQS goes High-Z. Data
from any Read burst may be concatenated with or truncated with data from a subsequent Read command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed
burst or the last desired data element of a longer burst which is being truncated. The new Read command should be issued x
cycles after the first Read command, where x equals the number of desired data element pairs (pairs are required by the 2n
prefetch architecture). This is shown in timing figure entitled “Consecutive Read Bursts: CAS Latencies (Burst Length =4 or 8)”.
A Read command can be initiated on any positive clock cycle following a previous Read command. Nonconsecutive Read data
is shown in timing figure entitled “Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)”. Full-speed Random Read
Accesses: CAS Latencies (Burst Length = 2, 4 or 8) within a page (or pages) can be performed as shown on page 25.
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Read Command
CK
CK
CKE
HIGH
CS
RAS
CAS
WE
x4: A0-A9, A11
x8: A0-A9
CA
EN AP
A10
DIS AP
BA0, BA1
BA
CA = column address
BA = bank address
EN AP = enable Auto Precharge
DIS AP = disable Auto Precharge
Don’t Care
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Read Burst: CAS Latencies (Burst Length = 4)
CAS Latency = 2
CK
CK
Command
Address
Read
NOP
NOP
NOP
NOP
NOP
BA a,COL n
CL=2
DQS
DOa-n
DQ
CAS Latency = 2.5
CK
CK
Command
Address
Read
NOP
NOP
NOP
NOP
NOP
BA a,COL n
CL=2.5
DQS
DOa-n
DQ
DO a-n = data out from bank a, column n.
3 subsequent elements of data out appear in the programmed order following DO a-n.
Shown with nominal tAC, tDQSCK, and t DQSQ.
REV 1.1
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Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8)
CAS Latency = 2
CK
CK
Command
Address
Read
NOP
Read
BAa, COL n
NOP
NOP
NOP
BAa, COL b
CL=2
DQS
DQ
DOa-b
DOa-n
CAS Latency = 2.5
CK
CK
Command
Address
Read
NOP
Read
BAa, COL n
NOP
NOP
NOP
BAa,COL b
CL=2.5
DQS
DOa- n
DQ
DOa- b
DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).
When burst length = 4, the bursts are concatenated.
When burst length = 8, the second burst interrupts the first.
3 subsequent elements of data out appear in the programmed order following DO a-n.
3 (or 7) subsequent elements of data out appear in the programmed order following DO a-b.
Shown with nominal t AC , tDQSCK, and tDQSQ.
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Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)
CAS Latency = 2
CK
CK
Read
Command
NOP
NOP
Read
BAa, COL n
Address
NOP
NOP
BAa, COL b
CL=2
DQS
DO a-n
DQ
DOa- b
CAS Latency = 2.5
CK
CK
Command
Address
Read
NOP
BAa, COL n
NOP
Read
NOP
NOP
NOP
BAa, COL b
CL=2.5
DQS
DQ
DO a-n
DOa- b
DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).
3 subsequent elements of data out appear in the programmed order following DO a-n (and following DO a-b).
Shown with nominal tAC, tDQSCK, and tDQSQ.
REV 1.1
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Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)
CAS Latency = 2
CK
CK
Command
Address
Read
Read
Read
Read
NOP
BAa, COL n
BAa, COL x
BAa, COL b
BAa, COL g
NOP
CL=2
DQS
DQ
DOa-n
DOa-n'
DOa-x
DOa-x'
DOa-b
DOa-b’
DOa-g
CAS Latency = 2.5
CK
CK
Command
Address
Read
Read
Read
Read
BAa, COL n
BAa, COL x
BAa, COL b
BAa, COL g
NOP
NOP
CL=2.5
DQS
DQ
DOa-n
DO a-n, etc. = data out from bank a, column n etc.
n' etc. = odd or even complement of n, etc. (i.e., column address LSB inverted).
Reads are to active rows in any banks.
Shown with nominal t AC , tDQSCK, and tDQSQ .
REV 1.1
12/2001
DOa-n'
DOa-x
DOa-x'
DOa-b
DOa-b’
Don’t Care
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Data from any Read burst may be truncated with a Burst Terminate command, as shown in timing figure entitled Terminating a
Read Burst: CAS Latencies (Burst Length = 8) on page 27. The Burst Terminate latency is equal to the read (CAS) latency, i.e.
the Burst Terminate command should be issued x cycles after the Read command, where x equals the number of desired data
element pairs.
Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If truncation is
necessary, the Burst Terminate command must be used, as shown in timing figure entitled Read to Write: CAS Latencies (Burst
Length = 4 or 8) on page 28. The example is shown for tDQSS(min). The t DQSS(max) case, not shown here, has a longer bus idle
time. tDQSS(min) and t DQSS(max) are defined in the section on Writes.
A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto Precharge
was not activated). The Precharge command should be issued x cycles after the Read command, where x equals the number of
desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown in timing figure Read to Precharge: CAS Latencies (Burst Length = 4 or 8) on page 29 for Read latencies of 2 and 2.5. Following the Precharge command,
a subsequent command to the same bank cannot be issued until t RP is met. Note that part of the row precharge time is hidden
during the access of the last data elements.
In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as described above)
provides the same operation that would result from the same Read burst with Auto Precharge enabled. The disadvantage of the
Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the
command. The advantage of the Precharge command is that it can be used to truncate bursts.
REV 1.1
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© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Terminating a Read Burst: CAS Latencies (Burst Length = 8)
CAS Latency = 2
CK
CK
Command
Address
Read
NOP
BST
NOP
NOP
NOP
BAa, COL n
CL=2
DQS
DQ
DOa-n
No further output data after this point.
DQS tristated.
CAS Latency = 2.5
CK
CK
Command
Address
Read
NOP
BST
NOP
NOP
NOP
BAa, COL n
CL=2.5
DQS
DQ
DOa-n
No further output data after this point.
DQS tristated.
DO a-n = data out from bank a, column n.
Cases shown are bursts of 8 terminated after 4 data elements.
3 subsequent elements of data out appear in the programmed order following DO a-n.
Shown with nominal tAC, tDQSCK, and tDQSQ.
REV 1.1
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Read to Write: CAS Latencies (Burst Length = 4 or 8)
CAS Latency = 2
CK
CK
Command
Address
Read
BST
NOP
BAa, COL n
Write
NOP
NOP
BAa, COL b
CL=2
tDQSS (min)
DQS
DQ
DI a-b
DOa-n
DM
CAS Latency = 2.5
CK
CK
Command
Address
Read
BST
NOP
NOP
BAa, COL n
Write
NOP
BAa, COL b
CL=2.5
tDQSS (min)
DQS
Dla-b
DOa-n
DQ
DM
DO a-n = data out from bank a, column n
.DI a-b = data in to bank a, column b
1 subsequent elements of data out appear in the programmed order following DO a-n.
Data In elements are applied following Dl a-b in the programmed order, according to burst length.
Shown with nominal tAC, tDQSCK, and t DQSQ.
REV 1.1
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Read to Precharge: CAS Latencies (Burst Length = 4 or 8)
CAS Latency = 2
CK
CK
Command
Read
NOP
PRE
NOP
NOP
ACT
tRP
Address
BA a, COL n
BA a or all
BA a, ROW
CL=2
DQS
DOa-n
DQ
CAS Latency = 2.5
CK
CK
Command
Read
NOP
PRE
NOP
NOP
ACT
tRP
Address
BA a or all
BA a, COL n
BA a, ROW
CL=2.5
DQS
DQ
DOa-n
DO a-n = data out from bank a, column n.
Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8.
3 subsequent elements of data out appear in the programmed order following DO a-n.
Shown with nominal t AC , tDQSCK, and tDQSQ .
REV 1.1
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Writes
Write bursts are initiated with a Write command, as shown in timing figure Write Command on page 31.
The starting column and bank addresses are provided with the Write command, and Auto Precharge is either enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the completion of the burst. For
the generic Write commands used in the following illustrations, Auto Precharge is disabled.
During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following the write command, and
subsequent data elements are registered on successive edges of DQS. The Low state on DQS between the Write command
and the first rising edge is known as the write preamble; the Low state on DQS following the last data-in element is known as
the write postamble. The time between the Write command and the first corresponding rising edge of DQS (t DQSS) is specified
with a relatively wide range (from 75% to 125% of one clock cycle), so most of the Write diagrams that follow are drawn for the
two extreme cases (i.e. t DQSS (min) and tDQSS(max)). Timing figure Write Burst (Burst Length = 4) on page 32 shows the two
extremes of tDQSS for a burst of four. Upon completion of a burst, assuming no other commands have been initiated, the DQs
and DQS enters High-Z and any additional input data is ignored.
Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either case, a continuous
flow of input data can be maintained. The new Write command can be issued on any positive edge of clock following the previous Write command. The first data element from the new burst is applied after either the last element of a completed burst or
the last desired data element of a longer burst which is being truncated. The new Write command should be issued x cycles
after the first Write command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch
architecture). Timing figure Write to Write (Burst Length = 4) on page 33 shows concatenated bursts of 4. An example of nonconsecutive Writes is shown in timing figure Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4) on page 34. Fullspeed random write accesses within a page or pages can be performed as shown in timing figure Random Write Cycles (Burst
Length = 2, 4 or 8) on page 35. Data for any Write burst may be followed by a subsequent Read command. To follow a Write
without truncating the write burst, tWTR (Write to Read) should be met as shown in timing figure Write to Read: Non-Interrupting
(CAS Latency = 2; Burst Length = 4) on page 36.
Data for any Write burst may be truncated by a subsequent (interrupting) Read command. This is illustrated in timing figures
“Write to Read: Interrupting (CAS Latency =2; Burst Length = 8)”, “Write to Read: Minimum DQSS, Odd Number of Data (3 bit
Write), Interrupting (CAS Latency = 2; Burst Length = 8)”, and “Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2;
Burst Length = 8)”. Note that only the data-in pairs that are registered prior to the t WTR period are written to the internal array,
and any subsequent data-in must be masked with DM, as shown in the diagrams noted previously.
Data for any Write burst may be followed by a subsequent Precharge command. To follow a Write without truncating the write
burst, tWR should be met as shown in timing figure Write to Precharge: Non-Interrupting (Burst Length = 4) on page 40.
Data for any Write burst may be truncated by a subsequent Precharge command, as shown in timing figures Write to Precharge: Interrupting (Burst Length = 4 or 8) on page 41 to Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst
Length = 4 or 8) on page 43. Note that only the data-in pairs that are registered prior to the t WR period are written to the internal
array, and any subsequent data in should be masked with DM. Following the Precharge command, a subsequent command to
the same bank cannot be issued until t RP is met.
In the case of a Write burst being executed to completion, a Precharge command issued at the optimum time (as described
above) provides the same operation that would result from the same burst with Auto Precharge. The disadvantage of the Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the Precharge command is that it can be used to truncate bursts.
REV 1.1
12/2001
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Write Command
CK
CK
CKE
HIGH
CS
RAS
CAS
WE
x4: A0-A9, A11
x8: A0-A9
CA
EN AP
A10
DIS AP
BA0, BA1
BA
CA = column address
BA = bank address
EN AP = enable Auto Precharge
DIS AP = disable Auto Precharge
Don’t Care
REV 1.1
12/2001
31
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Write Burst (Burst Length = 4)
Maximum DQSS
T1
T2
T3
T4
CK
CK
Command
Address
Write
NOP
NOP
NOP
BA a, COL b
tDQSS (max)
DQS
Dla-b
DQ
DM
tQCSW(max)
tQCHW(min)
QFC
(Optional)
Minimum DQSS
T1
T2
T3
T4
CK
CK
Command
Address
Write
NOP
NOP
NOP
BA a, COL b
tDQSS (min)
DQS
DQ
Dla-b
DM
tQCSW(max)
tQCHW(max)
QFC
DI a-b = data in for bank a, column b.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
A non-interrupted burst is shown.
A10 is Low with the Write command (Auto Precharge is disabled).
QFC is an open drain driver. Its output high level is achieved through an externally connected pull up resistor connected to VDDQ.
Don’t Care
REV 1.1
12/2001
32
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Write to Write (Burst Length = 4)
Maximum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Address
Write
NOP
Write
BAa, COL b
NOP
NOP
NOP
BAa, COL n
tDQSS (max)
DQS
DI a-b
DQ
DI a-n
DM
Minimum D QSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Address
Write
NOP
BA, COL b
Write
NOP
NOP
NOP
BA, COL n
tDQSS (min)
DQS
DQ
DI a-b
DI a-n
DM
DI a-b = data in for bank a, column b, etc.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
3 subsequent elements of data in are applied in the programmed order following DI a-n.
A non-interrupted burst is shown.
Each Write command may be to any bank.
REV 1.1
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4)
T1
T2
T3
T4
T5
CK
CK
Command
Address
Write
NOP
NOP
BAa, COL b
Write
NOP
BAa, COL n
tDQSS (max)
DQS
DQ
DI a-b
DI a-n
DM
DI a-b, etc. = data in for bank a, column b, etc.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
3 subsequent elements of data in are applied in the programmed order following DI a-n.
A non-interrupted burst is shown.
Each Write command may be to any bank.
REV 1.1
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Random Write Cycles (Burst Length = 2, 4 or 8)
Maximum DQSS
T1
T2
T3
T4
T5
CK
CK
Command
Address
Write
Write
BAa, COL b
Write
BAa, COL x
Write
BAa, COL n
Write
BAa, COL a
BAa, COL g
tDQSS (max)
DQS
DQ
DI a-b
DI a-b’
DI a-x
DI a-n
DI a-x’
DI a-n’
DI a-a
DI a-a’
DM
Minimum D QSS
T1
T2
T3
T4
T5
CK
CK
Command
Address
Write
Write
BAa, COL b
Write
BAa, COL x
Write
BAa, COL n
Write
BAa, COL a
BAa, COL g
tDQSS (min)
DQS
DQ
DI a-b
DI a-b’
DI a-x
DI a-x’
DI a-n
DI a-n’
DI a-a
DI a-a’
DI a-g
DM
DI a-b, etc. = data in for bank a, column b, etc.
b', etc. = odd or even complement of b, etc. (i.e., column address LSB inverted).
Each Write command may be to any bank.
REV 1.1
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4)
Maximum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
Read
NOP
tWTR
Address
BAa, COL b
BAa, COL n
CL = 2
tDQSS (max)
DQS
DQ
DI a-b
DM
Minimum D QSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
Read
NOP
tWTR
Address
BAa, COL n
BAa, COL b
CL = 2
tDQSS (min)
DQS
DQ
DI a-b
DM
DI a-b = data in for bank a, column b.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
A non-interrupted burst is shown.
tWTR is referenced from the first positive CK edge after the last data in pair.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands may be to any bank.
REV 1.1
12/2001
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8)
Maximum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
Read
NOP
tWTR
Address
BAa, COL n
BAa, COL b
CL = 2
tDQSS (max)
DQS
DQ
DIa- b
1
DM
1
Minimum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
Read
NOP
tWTR
Address
BAa, COL n
BAa, COL b
CL = 2
tDQSS (min)
DQS
DQ
DI a-b
DM
1
1
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 4 data elements are written.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
tWTR is referenced from the first positive CK edge after the last data in pair.
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
1 = These bits are incorrectly written into the memory array if DM is low.
REV 1.1
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Write to Read: Minimum DQSS, Odd Number of Data (3 bit Write), Interrupting (CAS
Latency = 2; Burst Length = 8)
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
Read
NOP
tWTR
Address
BAa, COL n
BAa, COL b
CL = 2
tDQSS (min)
DQS
DQ
DI a-b
1
DM
2
2
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 3 data elements are written.
2 subsequent elements of data in are applied in the programmed order following DI a-b.
tWTR is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element)
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
1 = This bit is correctly written into the memory array if DM is low.
Don’t Care
2 = These bits are incorrectly written into the memory array if DM is low.
REV 1.1
12/2001
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8)
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
Read
NOP
tWTR
Address
BAa, COL n
BAa, COL b
CL = 2
tDQSS (nom)
DQS
DQ
DI a-b
DM
1
1
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 4 data elements are written.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
tWTR is referenced from the first positive CK edge after the last desired data in pair.
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
1 = These bits are incorrectly written into the memory array if DM is low.
REV 1.1
12/2001
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39
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Write to Precharge: Non-Interrupting (Burst Length = 4)
Maximum D QSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
NOP
PRE
tWR
Address
BA (a or all)
BA a, COL b
tRP
tDQSS (max)
DQS
DQ
DI a-b
DM
Minimum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
NOP
PRE
tWR
Address
BA (a or all)
BA a, COL b
tRP
tDQSS (min)
DQS
DQ
DI a-b
DM
DI a-b = data in for bank a, column b.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
A non-interrupted burst is shown.
tWR is referenced from the first positive CK edge after the last data in pair.
A10 is Low with the Write command (Auto Precharge is disabled).
REV 1.1
12/2001
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40
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Write to Precharge: Interrupting (Burst Length = 4 or 8)
Maximum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
PRE
NOP
tWR
Address
BA a, COL b
BA (a or all)
tDQSS (max)
tRP
2
DQS
DI a-b
DQ
3
DM
1
3
1
Minimum D QSS
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
PRE
NOP
tWR
Address
BA a, COL b
BA (a or all)
tDQSS (min)
tRP
2
DQS
DQ
DM
DI a-b
3
3
1
1
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 2 data elements are written.
1 subsequent element of data in is applied in the programmed order following DI a-b.
tWR is referenced from the first positive CK edge after the last desired data in pair.
The Precharge command masks the last 2 data elements in the burst, for burst length = 8.
A10 is Low with the Write command (Auto Precharge is disabled).
1 = Can be don't care for programmed burst length of 4.
2 = For programmed burst length of 4, DQS becomes don't care at this point.
3 = These bits are incorrectly written into the memory array if DM is low.
REV 1.1
12/2001
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41
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Write to Precharge: Minimum DQSS, Odd Number of Data (1 bit Write), Interrupting
(Burst Length = 4 or 8)
T1
T2
T3
T4
T5
T6
CK
CK
Command
Write
NOP
NOP
NOP
PRE
NOP
tWR
Address
BA a, COL b
BA (a or all)
tDQSS (min)
tRP
2
DQS
DQ
DM
DI a-b
3
4
4
1
1
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 1 data element is written.
tWR is referenced from the first positive CK edge after the last desired data in pair.
The Precharge command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
1 = Can be don't care for programmed burst length of 4.
2 = For programmed burst length of 4, DQS becomes don't care at this point.
3 = This bit is correctly written into the memory array if DM is low.
4 = These bits are incorrectly written into the memory array if DM is low.
REV 1.1
12/2001
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42
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst Length = 4 or 8)
T1
T2
T3
T4
T5
T6
CK
CK
Write
Command
NOP
NOP
NOP
PRE
NOP
tWR
Address
BA (a or all)
BA a, COL b
tDQSS (nom)
tRP
2
DQS
DQ
DM
DI a-b
3
3
1
1
DI a-b = Data In for bank a, column b.
An interrupted burst is shown, 2 data elements are written.
1 subsequent element of data in is applied in the programmed order following DI a-b.
tWR is referenced from the first positive CK edge after the last desired data in pair.
The Precharge command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
1 = Can be don't care for programmed burst length of 4.
2 = For programmed burst length of 4, DQS becomes don't care at this point.
3 = These bits are incorrectly written into the memory array if DM is low.
REV 1.1
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Precharge Command
CK
CK
CKE
HIGH
CS
RAS
CAS
WE
A0-A9, A11, A12
All Banks
A10
BA0, BA1
One Bank
BA
BA = bank address
(if A10 is Low, otherwise Don’t Care).
Don’t Care
Precharge
The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The
bank(s) is available for a subsequent row access some specified time (tRP) after the Precharge command is
issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank
is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are
treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any
Read or Write commands being issued to that bank.
REV 1.1
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NT5DS64M4AT NT5DS64M4AW
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256Mb Double Data Rate SDRAM
Power-Down
Power-down is entered when CKE is registered low (no accesses can be in progress). If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode
is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK and CKE.
The DLL is still running in Power Down mode, so for maximum power savings, the user has the option of disabling the DLL prior
to entering Power-down. In that case, the DLL must be enabled after exiting power-down, and 200 clock cycles must occur
before a Read command can be issued. In Power Down mode, CKE Low and a stable clock signal must be maintained at the
inputs of the DDR SDRAM, and all other input signals are “Don’t Care”. However, power-down duration is limited by the refresh
requirements of the device, so in most applications, the self refresh mode is preferred over the DLL-disabled power-down
mode.
The power-down state is synchronously exited when CKE is registered high (along with a Nop or Deselect command). A valid,
executable command may be applied one clock cycle later.
Power Down
CK
CK
tIS
CKE
Command
VALID
tIS
NOP
NOP
No column
access in
progress
Exit
power down
mode
Enter Power Down mode
(Burst Read or Write operation
must not be in progress)
REV 1.1
12/2001
VALID
Don’t Care
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256Mb Double Data Rate SDRAM
Truth Table 2: Clock Enable (CKE)
1.
2.
3.
4.
CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
Current state is the state of the DDR SDRAM immediately prior to clock edge n.
Command n is the command registered at clock edge n, and action n is a result of command n.
All states and sequences not shown are illegal or reserved.
CKE n-1
CKEn
Current State
Previous
Cycle
Current
Cycle
Command n
Self Refresh
L
L
X
Self Refresh
L
H
Deselect or NOP
Power Down
L
L
X
Power Down
L
H
Deselect or NOP
Exit Power-Down
All Banks Idle
H
L
Deselect or NOP
Precharge Power-Down Entry
All Banks Idle
H
L
Auto Refresh
Bank(s) Active
H
L
Deselect or NOP
H
H
See “Truth Table 3: Current State
Bank n - Command to Bank n (Same
Bank)” on page 47
Action n
Notes
Maintain Self-Refresh
Exit Self-Refresh
1
Maintain Power-Down
Self Refresh Entry
Active Power-Down Entry
1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (t XSNR) period. A minimum of
200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
REV 1.1
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256Mb Double Data Rate SDRAM
Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)
Current State
CS
RAS
CAS
WE
Command
Action
Notes
H
X
X
X
Deselect
NOP. Continue previous operation
1-6
L
H
H
H
No Operation
NOP. Continue previous operation
1-6
L
L
H
H
Active
Select and activate row
1-6
L
L
L
H
Auto Refresh
L
L
L
L
Mode Register Set
L
H
L
H
Read
Select column and start Read burst
1-6, 10
L
H
L
L
Write
Select column and start Write burst
1-6, 10
L
L
H
L
Precharge
Deactivate row in bank(s)
1-6, 8
L
H
L
H
Read
Select column and start new Read burst
1-6, 10
L
L
H
L
Precharge
Truncate Read burst, start Precharge
1-6, 8
L
H
H
L
Burst Terminate
Burst Terminate
1-6, 9
L
H
L
H
Read
Select column and start Read burst
1-6, 10, 11
L
H
L
L
Write
Select column and start Write burst
1-6, 10
L
L
H
L
Precharge
Any
Idle
Row Active
Read
(Auto Precharge
Disabled)
Write
(Auto Precharge
Disabled)
1-7
1-7
Truncate Write burst, start Precharge
1-6, 8, 11
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t XSNR / tXSRD has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed
to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active:
A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in
progress.
Read:
A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write:
A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank.
Precharging:
Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle
state.
Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the “row
active” state.
Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when t RP has been
met. Once tRP is met, the bank is in the idle state.
Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these
states. Allowable commands to the other bank are determined by its current state and according to Truth Table 4.
5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive
clock edge during these states.
Refreshing:
Starts with registration of an Auto Refresh command and ends when tRFC is met. Once t RFC is met, the DDR SDRAM is
in the “all banks idle” state.
Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once t MRD is
met, the DDR SDRAM is in the “all banks idle” state.
Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle
state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
9. Not bank-specific; Burst terminate affects the most recent Read burst, regardless of bank.
10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
11. Requires appropriate DM masking.
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256Mb Double Data Rate SDRAM
Truth Table 4: Current State Bank n - Command to Bank m (Different bank)
(Part 1 of 2)
Current State
CS
RAS
CAS
WE
Command
Action
Notes
H
X
X
X
Deselect
NOP/continue previous operation
1-6
L
H
H
H
No Operation
NOP/continue previous operation
1-6
X
X
X
X
Any Command Otherwise
Allowed to Bank m
L
L
H
H
Active
Select and activate row
1-6
L
H
L
H
Read
Select column and start Read burst
1-7
L
H
L
L
Write
Select column and start Write burst
1-7
L
L
H
L
Precharge
L
L
H
H
Active
Select and activate row
1-6
L
H
L
H
Read
Select column and start new Read burst
1-7
L
L
H
L
Precharge
L
L
H
H
Active
Select and activate row
1-6
L
H
L
H
Read
Select column and start Read burst
1-8
L
H
L
L
Write
Select column and start new Write burst
1-7
L
L
H
L
Precharge
Any
Idle
Row Activating,
Active, or
Precharging
Read
(Auto Precharge
Disabled)
Write
(Auto Precharge
Disabled)
1-6
1-6
1-6
1-6
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t XSNR / tXSRD has been
met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are
those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active:
A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are
in progress.
Read:
A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write:
A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled: See note 10.
Write with Auto Precharge Enabled: See note 10.
4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle.
5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
8. Requires appropriate DM masking.
9. A Write command may be applied after the completion of data output.
10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access
period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with
Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst.
For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The
access period starts with registration of the command and ends where the precharge period (or t RP) begins. During the precharge period
of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands
to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In
either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).
REV 1.1
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256Mb Double Data Rate SDRAM
Truth Table 4: Current State Bank n - Command to Bank m (Different bank)
(Part 2 of 2)
Current State
Read (With
Auto Precharge)
Write (With
Auto Precharge)
CS
RAS
CAS
WE
Command
L
L
H
H
Active
Select and activate row
Action
Notes
L
H
L
H
Read
Select column and start new Read burst
L
H
L
L
Write
Select column and start Write burst
L
L
H
L
Precharge
L
L
H
H
Active
Select and activate row
L
H
L
H
Read
Select column and start Read burst
1-7,10
L
H
L
L
Write
Select column and start new Write burst
1-7,10
L
L
H
L
Precharge
1-6
1-7,10
1-7,9,10
1-6
1-6
1-6
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t XSNR / tXSRD has been
met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are
those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active:
A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are
in progress.
Read:
A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write:
A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled: See note 10.
Write with Auto Precharge Enabled: See note 10.
4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle.
5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
8. Requires appropriate DM masking.
9. A Write command may be applied after the completion of data output.
10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access
period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with
Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst.
For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The
access period starts with registration of the command and ends where the precharge period (or t RP) begins. During the precharge period
of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands
to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In
either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).
REV 1.1
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Simplified State Diagram
Power
Applied
Power
On
Self
Refresh
Precharge
Preall
REFS
REFSX
MRS
EMRS
MRS
Auto
Refresh
REFA
Idle
CKEL
CKEH
Active
Power
Down
ACT
Precharge
Power
Down
CKEH
CKEL
Burst Stop
Row
Active
Write
Write A
Write
Read
Read A
Read
Read
Read A
Write A
Read
A
PRE
Write
A
PRE
PRE
PRE
Read
A
Precharge
Preall
Automatic Sequence
Command Sequence
PREALL = Precharge All Banks
MRS = Mode Register Set
EMRS = Extended Mode Register Set
REFS = Enter Self Refresh
REFSX = Exit Self Refresh
REFA = Auto Refresh
REV 1.1
12/2001
CKEL = Enter Power Down
CKEH = Exit Power Down
ACT = Active
Write A = Write with Autoprecharge
Read A = Read with Autoprecharge
PRE = Precharge
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Absolute Maximum Ratings
Symbol
VIN, VOUT
Parameter
Voltage on I/O pins relative to VSS
Rating
Units
−0.5 to VDDQ+ 0.5
V
VIN
Voltage on Inputs relative to V SS
−0.5 to +3.6
V
VDD
Voltage on VDD supply relative to VSS
−0.5 to +3.6
V
Voltage on VDDQ supply relative to VSS
−0.5 to +3.6
V
0 to +70
°C
−55 to +150
°C
Power Dissipation
1.0
W
Short Circuit Output Current
50
mA
VDDQ
TA
TSTG
PD
IOUT
Operating Temperature (Ambient)
Storage Temperature (Plastic)
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Capacitance
Parameter
Input Capacitance: CK, CK
Delta Input Capacitance: CK, CK
Symbol
Min.
Max.
Units
Notes
CI1
2.0
3.0
pF
1
0.25
pF
1
3.0
pF
1
0.5
pF
1
5.0
pF
1, 2
0.5
pF
1
delta CI1
Input Capacitance: All other input-only pins (except DM)
CI2
Delta Input Capacitance: All other input-only pins (except DM)
2.0
delta CI2
Input/Output Capacitance: DQ, DQS, DM
CIO
Delta Input/Output Capacitance: DQ, DQS, DM
4.0
delta CIO
1. VDDQ = VDD = 2.5V ± 0.2V (minimum range to maximum range), f = 100MHz, TA = 25°C, VODC = VDDQ/2 , VOPeak -Peak = 0.2V.
2. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is
required to match input propagation times of DQ, DQS and DM in the system.
DC Electrical Characteristics and Operating Conditions
(0°C ≤ TA ≤ 70°C; VDDQ = 2.5V ± 0.2V, VDD = + 2.5V ± 0.2V, see AC Characteristics)
Symbol
Min
Max
Units
Notes
Supply Voltage
2.3
2.7
V
1
VDDQ
I/O Supply Voltage
2.3
2.7
V
1
VSS, VSSQ
Supply Voltage
I/O Supply Voltage
0
0
V
I/O Reference Voltage
0.49 x VDDQ
0.51 x VDDQ
V
1, 2
I/O Termination Voltage (System)
VREF − 0.04
VREF + 0.04
V
1, 3
VIH(DC)
Input High (Logic1) Voltage
VREF + 0.15
VDDQ + 0.3
V
1
VIL(DC)
Input Low (Logic0) Voltage
− 0.3
VREF − 0.15
V
1
VIN(DC)
Input Voltage Level, CK and CK Inputs
− 0.3
VDDQ + 0.3
V
1
VID(DC)
Input Differential Voltage, CK and CK Inputs
0.30
VDDQ + 0.6
V
1, 4
VIRatio
V-I Matching Pullup Current to Pulldown Current Ratio
0.71
1.4
Input Leakage Current
Any input 0V ≤ VIN ≤ VDD ; (All other pins not under test = 0V)
−5
5
µA
1
Output Leakage Current
(DQs are disabled; 0V ≤ Vout ≤ VDDQ
−5
5
µA
1
mA
1
mA
1
VDD
VREF
VTT
II
IOZ
IOH
IOL
IOHW
IOLW
Parameter
Output Current: Nominal Strength Driver
High current (VOUT = VDDQ -0.373V, min VREF, min VTT )
Low current (VOUT= 0.373V, max VREF, max V TT)
− 16.8
Output Current: Half- Strength Driver
High current (VOUT = VDDQ -0.763V, min VREF, min VTT )
Low current (VOUT= 0.763V, max VREF, max V TT)
− 9.0
5
16.8
9.0
1. Inputs are not recognized as valid until VREF stabilizes.
2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak
noise on V REF may not exceed ± 2% of the DC value.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in tHalf-he DC level of V REF.
4. VID is the magnitude of the difference between the input level on CK and the input level on CK.
5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire tempera-ture and
voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference
between pullup and pulldown drivers due to process variation.
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256Mb Double Data Rate SDRAM
Normal Strength Driver Pulldown and Pullup Characteristics
1. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the
outer bounding lines of the V-I curve.
2. It is recommended that the “typical” IBIS pulldown V-I curve lie within the shaded region of the V-I curve.
Normal Strength Driver Pulldown Characteristics
140
IOUT (mA)
Maximum
Typical High
Typical Low
Minimum
0
0
2.7
VOUT (V)
3. The full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the
outer bounding lines of the V-I curve.
4. It is recommended that the “typical” IBIS pullup V-I curve lie within the shaded region of the V-I curve.
Normal Strength Driver Pullup Characteristics
0
Minimum
IOUT (mA)
Typical Low
Typical High
Maximum
-200
0
2.7
VOUT (V)
5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will
not exceed 1.7, for device
drain to source voltages from 0.1 to 1.0.
6. The full variation in the ratio of the “typical” IBIS pullup to “typical” IBIS pulldown current should be unity + 10%, for device
drain to source voltages from 0.1 to 1.0. This specification is a design objective only. It is not guaranteed.
7. These characteristics are intended to obey the SSTL_2 class II standard.
8. This specification is intended for DDR SDRAM only.
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256Mb Double Data Rate SDRAM
Normal Strength Driver Pulldown and Pullup Currents
Pulldown Current (mA)
Pullup Current (mA)
Voltage (V)
Typical
Low
Typical
High
Min
Max
Typical
Low
Typical
High
Min
Max
0.1
6.0
6.8
4.6
9.6
-6.1
-7.6
-4.6
-10.0
0.2
12.2
13.5
9.2
18.2
-12.2
-14.5
-9.2
-20.0
0.3
18.1
20.1
13.8
26.0
-18.1
-21.2
-13.8
-29.8
0.4
24.1
26.6
18.4
33.9
-24.0
-27.7
-18.4
-38.8
0.5
29.8
33.0
23.0
41.8
-29.8
-34.1
-23.0
-46.8
0.6
34.6
39.1
27.7
49.4
-34.3
-40.5
-27.7
-54.4
0.7
39.4
44.2
32.2
56.8
-38.1
-46.9
-32.2
-61.8
0.8
43.7
49.8
36.8
63.2
-41.1
-53.1
-36.0
-69.5
0.9
47.5
55.2
39.6
69.9
-43.8
-59.4
-38.2
-77.3
1.0
51.3
60.3
42.6
76.3
-46.0
-65.5
-38.7
-85.2
1.1
54.1
65.2
44.8
82.5
-47.8
-71.6
-39.0
-93.0
1.2
56.2
69.9
46.2
88.3
-49.2
-77.6
-39.2
-100.6
1.3
57.9
74.2
47.1
93.8
-50.0
-83.6
-39.4
-108.1
1.4
59.3
78.4
47.4
99.1
-50.5
-89.7
-39.6
-115.5
1.5
60.1
82.3
47.7
103.8
-50.7
-95.5
-39.9
-123.0
1.6
60.5
85.9
48.0
108.4
-51.0
-101.3
-40.1
-130.4
1.7
61.0
89.1
48.4
112.1
-51.1
-107.1
-40.2
-136.7
1.8
61.5
92.2
48.9
115.9
-51.3
-112.4
-40.3
-144.2
1.9
62.0
95.3
49.1
119.6
-51.5
-118.7
-40.4
-150.5
2.0
62.5
97.2
49.4
123.3
-51.6
-124.0
-40.5
-156.9
2.1
62.9
99.1
49.6
126.5
-51.8
-129.3
-40.6
-163.2
2.2
63.3
100.9
49.8
129.5
-52.0
-134.6
-40.7
-169.6
2.3
63.8
101.9
49.9
132.4
-52.2
-139.9
-40.8
-176.0
2.4
64.1
102.8
50.0
135.0
-52.3
-145.2
-40.9
-181.3
2.5
64.6
103.8
50.2
137.3
-52.5
-150.5
-41.0
-187.6
2.6
64.8
104.6
50.4
139.2
-52.7
-155.3
-41.1
-192.9
2.7
65.0
105.4
50.5
140.8
-52.8
-160.1
-41.2
-198.2
Normal Strength Driver Evaluation Conditions
REV 1.1
12/2001
Typical
Minimum
Maximum
Temperature (T ambient)
25 °C
70 °C
0 °C
VDDQ
2.5V
2.3V
2.7V
Process conditions
typical process
slow-slow process
fast-fast process
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, I DD
Specifications and Conditions, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to VSS.
2. Tests for AC timing, I DD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage
levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and I DD tests may use a V IL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced
to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels
under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between V IL(AC) and
VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a
result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above
(below) the DC input low (high) level.
AC Output Load Circuit Diagrams
VTT
50Ω
Output
(VOUT )
Timing Reference Point
30pF
REV 1.1
12/2001
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
DQS/DQ/DM Slew Rate
Parameterl
DCS/DQ/DM
input slew rate
DDR266A
(-7K)
Symbol
DCSLEW
1. Measured between V IH (DC), V
IL (DC),
DDR266B
(-75B)
DDR200
(-8B)
Min
Max
Min
Max
Min
Max
TBD
TBD
TBD
TBD
0.5
4.0
and V
IL (DC),
V
Unit
Notes
V/ns
1,2
IH (DC).
2. DQS, DQ, and DM input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal tran-sition
through the DC region must be monotonic..
REV 1.1
12/2001
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
AC Input Operating Conditions (0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC
Characteristics)
Symbol
Parameter/Condition
VIH(AC)
Input High (Logic 1) Voltage, DQ, DQS, and DM Signals
VIL(AC)
Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals
VID(AC)
Input Differential Voltage, CK and CK Inputs
VIX(AC)
Input Crossing Point Voltage, CK and CK Inputs
1.
2.
3.
4.
Min
Max
Unit
Notes
V
1, 2
VREF − 0.31
V
1, 2
0.62
VDDQ + 0.6
V
1, 2, 3
0.5*V DDQ − 0.2
0.5*VDDQ + 0.2
V
1, 2, 4
VREF + 0.31
Input slew rate = 1V/ns.
Inputs are not recognized as valid until VREF stabilizes.
VID is the magnitude of the difference between the input level on CK and the input level on CK.
The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
IDD Specifications and Conditions (0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC
Characteristics)
Symbol
Parameter/Condition
DDR200
(8B)
tCK=10ns
DDR266A/B
(7K/75B)
tCK=7.5ns
Unit
Notes
IDD0
Operating Current: one bank; active / precharge; tRC = tRC (min); DQ, DM, and
DQS inputs changing twice per clock cycle; address and control inputs changing
once per clock cycle
75
85
mA
1
IDD1
Operating Current: one bank; active / read / precharge; Burst = 2; tRC = tRC
(min); CL = 2.5; IOUT = 0mA; address and control inputs changing once per clock
cycle
90
110
mA
1
IDD2P
Precharge Power-Down Standby Current: all banks idle; power-down mode;
CKE ≤ VIL (max)
15
15
mA
1
IDD2N
Idle Standby Current: CS ≥ VIH (min); all banks idle; CKE ≥ VIH (min);
address and control inputs changing once per clock cycle
30
35
mA
1
IDD3P
Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ VIL (max)
15
15
mA
1
IDD3N
Active Standby Current: one bank; active / precharge; CS ≥ VIH (min);
CKE ≥ VIH (min); tRC = tRAS (max); DQ, DM, and DQS inputs changing twice per
clock cycle; address and control inputs changing once per clock cycle
50
60
mA
1
IDD4R
Operating Current: one bank; Burst = 2; reads; continuous burst; address and
control inputs changing once per clock cycle; DQ and DQS outputs changing
twice per clock cycle; CL = 2.5; IOUT = 0mA
130
165
mA
1
IDD4W
Operating Current: one bank; Burst = 2; writes; continuous burst; address and
control inputs changing once per clock cycle; DQ and DQS inputs changing twice
per clock cycle; CL = 2.5
115
150
mA
1
IDD5
Auto-Refresh Current: tRC = t RFC (min)
160
170
mA
1
IDD6
Self-Refresh Current: CKE ≤ 0.2V
2
2
mA
1, 2
IDD7
Operating current: four bank; four bank interleaving with BL = 4, address and
control inputs randomly changing; 50% of data changing at every transfer;
t RC = t RC (min); I OUT = 0mA.
TBD
TBD
mA
1
1. IDD specifications are tested after the device is properly initialized.
2. Enables on-chip refresh and address counters.
REV 1.1
12/2001
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Electrical Characteristics & AC Timing for DDR266/DDR200 - Absolute Specifications
(0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; V DD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)
Symbol
tAC
DDR266A
(-7K)
Parameter
DQ output access time from CK/CK
tDQSCK DQS output access time from CK/CK
DDR266B
(-75B)
DDR200
(-8B)
Unit
Notes
+ 0.8
ns
1-4
− 0.8
+ 0.8
ns
1-4
Min
Max
Min
Max
Min
Max
− 0.75
+ 0.75
− 0.75
+ 0.75
− 0.8
− 0.75
+ 0.75
− 0.75
+ 0.75
tCH
CK high-level width
0.45
0.55
0.45
0.55
0.45
0.55
tCK
1-4
tCL
CK low-level width
0.45
0.55
0.45
0.55
0.45
0.55
tCK
1-4
7
12
7.5
12
8
12
ns
1-4
7.5
12
10
12
10
12
ns
1-4
10
12
CL = 2.5
tCK
Clock cycle time
CL = 2.0
tCK
tDH
DQ and DM input hold time
0.5
0.5
0.6
ns
1-4,
15,16
tDS
DQ and DM input setup time
0.5
0.5
0.6
ns
1-4,
15,16
tDIPW
DQ and DM input pulse width (each input)
1.75
1.75
2
ns
1-4
tHZ
Data-out high-impedance time from CK/CK
− 0.75
+ 0.75
− 0.75
+ 0.75
− 0.8
+ 0.8
ns
1-4, 5
tLZ
Data-out low-impedance time from CK/CK
− 0.75
+ 0.75
− 0.75
+ 0.75
− 0.8
+ 0.8
ns
1-4, 5
tDQSQ
DQS-DQ skew (DQS & associated DQ signals)
tDQSQA DQS-DQ skew (DQS & all DQ signals)
tHP
minimum half clk period for any given cycle;
defined by clk high (t CH) or clk low (tCL) time
tQH
Data output hold time from DQS
+ 0.5
+ 0.5
+ 0.6
ns
1-4
+ 0.5
+ 0.5
+ 0.6
ns
1-4
tCH
or
tCL
tCH
or
tCL
tCH
or
tCL
tCK
1-4
tHP0.75ns
tHP0.75ns
tHP-1.0ns
tCK
1-4
tCK
1-4
Write command to 1st DQS latching
transition
0.75
tDQSL,H DQS input low (high) pulse width (write cycle)
0.35
0.35
0.35
tCK
1-4
tDQSS
1.25
0.75
1.25
0.75
1.25
tDSS
DQS falling edge to CK setup time (write cycle)
0.2
0.2
0.2
tCK
1-4
tDSH
DQS falling edge hold time from CK (write cycle)
0.2
0.2
0.2
tCK
1-4
tMRD
Mode register set command cycle time
14
15
16
ns
1-4
0
0
0
ns
1-4, 7
tCK
1-4, 6
tWPRES Write preamble setup time
tWPST
Write postamble
0.40
tWPRE
Write preamble
0.25
0.25
0.25
tCK
1-4
tIH
Address and control input hold time
(fast slew rate)
0.9
0.9
1.1
ns
2-4,
9,11,12
tIS
Address and control input setup time
(fast slew rate)
0.9
0.9
1.1
ns
2-4,
9,11,12
tIH
Address and control input hold time
(slow slew rate)
1.0
1.0
1.1
ns
2-4,
11,12,
14
tIS
Address and control input setup time
(slow slew rate)
1.0
1.0
1.1
ns
2-4,
11,12,
14
REV 1.1
12/2001
0.60
0.40
0.60
0.40
0.60
58
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Electrical Characteristics & AC Timing for DDR266/DDR200 - Absolute Specifications
(0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; V DD = 2.5V ± 0.2V, See AC Characteristics) (Part 2 of 2)
Symbol
Parameter
DDR266A
(-7K)
Min
tIPW
Max
DDR266B
(-75B)
Min
DDR200
(-8B)
Max
Min
Unit
Notes
ns
2-4, 12
Max
Input pulse width
2.2
tRPRE
Read preamble
0.9
1.1
0.9
1.1
0.9
1.1
tCK
1-4
tRPST
Read postamble
0.40
0.60
0.40
0.60
0.40
0.60
tCK
1-4
tRAS
Active to Precharge command
45
120,000
45
120,000
50
120,000
ns
1-4
tRC
Active to Active/Auto-refresh command period
65
65
70
ns
1-4
tRFC
Auto-refresh to Active/Auto-refresh
command period
75
75
80
ns
1-4
tRCD
Active to Read or Write delay
20
20
20
ns
1-4
tRAP
Active to Read Command with Autoprecharge
20
20
20
ns
1-4
tRP
Precharge command period
20
20
20
ns
1-4
tRRD
Active bank A to Active bank B command
15
15
15
ns
1-4
tWR
Write recovery time
15
15
15
ns
1-4
tDAL
Auto precharge write recovery
+ precharge time
(tWR /tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
tCK
1-4,13
tWTR
Internal write to read command delay
1
1
1
tCK
1-4
tXSNR
Exit self-refresh to non-read command
75
75
80
ns
1-4
tXSRD
Exit self-refresh to read command
200
200
200
tCK
1-4
tREFI
Average Periodic Refresh Interval
µs
1-4, 8
REV 1.1
12/2001
2.2
7.8
7.8
7.8
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Electrical Characteristics & AC Timing for DDR266 - Applicable Specifications
Expressed in Clock Cycles (0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)
tCK = 7.5ns
Symbol
Parameter
Units
Notes
2
tCK
1-4
0.25
tCK
1-4
tCK
1-4
Min
tMRD
tWPRE
Mode register set command cycle time
Write preamble
Max
tRAS
Active to Precharge command
6
16000
tRC
Active to Active/Auto-refresh command period
9
tCK
1-4
tRFC
Auto-refresh to Active/Auto-refresh
command period
10
tCK
1-4
tRCD
Active to Read or Write delay
3
tCK
1-4
tRAP
Active to Read Command with Autoprecharge
3
tCK
1-4
tRP
Precharge command period
3
tCK
1-4
tRRD
Active bank A to Active bank B command
2
tCK
1-4
tWR
Write recovery time
2
tCK
1-4
tDAL
Auto precharge write recovery + precharge time
5
tCK
1-5
tWTR
Internal write to read command delay
1
tCK
1-4
tXSNR
Exit self-refresh to non-read command
10
tCK
1-4
tXSRD
Exit self-refresh to read command
200
tCK
1-4
1. Input slew rate = 1V/ns
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF.
3. Inputs are not recognized as valid until VREF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT .
5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
REV 1.1
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Electrical Characteristics & AC Timing for DDR266/DDR200 - Absolute Specifications
Notes
1. Input slew rate = 1V/ns.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross:
the input reference level for signals other than CK/CK, is VREF.
3. Inputs are not recognized as valid until VREF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V TT .
5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A
valid
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS
could be HIGH, LOW, or transitioning from high to low at this time, depending on t DQSS .
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For command/address input slew rate ≥ 1.0V/ns. Slew rate is measured between V OH (AC) and V OL (AC).
10. For command/address input slew rate ≥ 0.5V/ns and < 1.0V/ns. Slew rate is measured between V OH (AC) and V OL (AC)
11. CK/CK slew rates are ≥ 1.0V/ns.
12.These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization.
13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t CK is equal to the actual
system clock cycle time.
For example, for DDR266B at CL = 2.5, t DAL = (15ns/7.5ns) +(20ns/7.5ns) = 2 + 3 = 5.
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256Mb Double Data Rate SDRAM
14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew
rate is below 0.5 V/ns.
Input Slew Rate
delta ( t IS)
delta ( t IH)
Unit
Notes
0.5 V/ns
0
0
ps
1,2
0.4 V/ns
+50
0
ps
1,2
0.3 V/ns
+100
0
ps
1,2
1. Input slew rate is based on the lesser of the slew rates determined by either V
IH (AC) to
V
IL (AC) or
V IH (DC) to V IL (DC) , similarly for rising
transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on eachdevice.
15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below
0.5 V/ns.
Input Slew Rate
delta ( t DS)
delta ( t DH)
Unit
Notes
0.5 V/ns
0
0
ps
1,2
0.4 V/ns
+75
+75
ps
1,2
0.3 V/ns
+150
+150
ps
1,2
1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V
IL (AC) or
V IH (DC) to V
IL (DC) ,
similarly for rising
transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on eachdevice.
16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH) in the case where DQ, DM, and DQS slew rates
differ.
Input Slew Rate
delta ( t DS)
delta ( t DH)
Unit
Notes
0.0 V/ns
0
0
ps
1,2,3,4
0.25 V/ns
+50
+50
ps
1,2,3,4
0.5 V/ns
+100
+100
ps
1,2,3,4
1. Input slew rate is based on the lesser of the slew rates determined by either V
IH (AC) to
V
IL (AC) or
V IH (DC) to V IL (DC) , similarly for rising
transitions.
2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.
3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]
For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns
Delta rise, fall = (1/0.5) - (1/0.4) [ns/V]
= -0.5 ns/V
Using the table above, this would result in an increase in t
DS and
t
DH of
100 ps.
4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
REV 1.1
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Data Input (Write)
(Timing Burst Length = 4)
tDSL
tDSH
DQS
tDH
tDS
DI n
DQ
tDH
tDS
DM
DI n = Data In for column n.
3 subsequent elements of data in are applied in programmed order following DI n.
Data Output (Read)
Don’t Care
(Timing Burst Length = 4)
CK
CK
tHP
tHP
tHP
tHP1
tHP2
tHP3
tHP4
DQS
tDQSQ
tQH2
tQH1
DQ
tDQSQ
tDQSQ
tQH4
tQH3
tDQSQ
tHP is the half cycle pulse width for each half cycle clock. tHP is referenced to the clock duty cycle only
and not to the data strobe (DQS) duty cycle.
Data Output hold time from Data Strobe is shown as t QH . tQH is a function of the clock high or low time (tHP)
for that given clock cycle. Note correlation of tHP to tQH in the diagram above (tHP1 to t QH1, etc.).
tDQSQ (max)occurs when DQS is the earliest among DQS and DQ signals to transition.
REV 1.1
12/2001
63
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
REV 1.1
12/2001
tVTD
High-Z
High-Z
200µs
Power-up:
VDD and CK
stable
LVCMOS LOW LEVEL
Don’t Care
DQ
DQS
BA0, BA1
A10
A0-A9, A11
DM
Command
CKE
CK
CK
VREF
VTT (System*)
VDDQ
VDD
tIH
tIH
NOP
tIS
tIS
tCH
tIS
tIH
PRE
tCL
tIH
tIH
tIH
BA1=L
BA0=H
tIS
CODE
tIS
CODE
tIS
EMRS
tIH
CODE
CODE
MRS
tMRD
Load Mode
Register
(with A8 = L)
BA0=L
AR
tRFC
BA1=L
AR
tRFC
200 cycles of CK**
BA0=L
ALL BANKS
tIS
PRE
tRP
BA1=L
CODE
CODE
MRS
tMRD
Load Mode
Register, Reset DLL
tMRD
Extended Mode
Register Set
ALL BANKS
tCK
The two Autorefresh commands may be moved to follow the first MRS,
but precede the second Precharge All command.
** t MRD is required before any command can be applied and
200 cycles of CK are required before a Read command can be applied.
* VTT is not applied directly to the device, however tVTD must be
greater than or equal to zero to avoid device latchup.
BA
RA
RA
ACT
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Initialize and Mode Register Sets
64
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© NANYA TECHNOLOGY CORP. All rights reserved.
REV 1.1
12/2001
tIH
tIH
tIH
VALID
tIS
VALID*
tIS
tIS
tCK
Enter Power
Down Mode
NOP
tIS
tCH
tCL
No column accesses are allowed to be in progress at the time power down is entered.
* = If this command is a Precharge (or if the device is already in the idle state) then the power down mode
shown is Precharge power down. If this command is an Active (or if at least one row is already active), then
the power down mode shown is Active power down.
DM
DQ
DQS
ADDR
Command
CKE
CK
CK
Exit Power
Down Mode
NOP
tIS
Don’t Care
VALID
VALID
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Power Down Mode
65
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© NANYA TECHNOLOGY CORP. All rights reserved.
REV 1.1
12/2001
tIH
tIH
NOP
AR
NOP
AR
NOP
VALID
tRFC
NOP
ACT
tIH
BANK(S)
tIS
ONE BANK
PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address; AR = Autorefresh.
NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
DM, DQ, and DQS signals are all don't care/high-Z for operations shown.
DM
DQ
DQS
BA0, BA1
A10
Don’t Care
BA
RA
RA
ALL BANKS
NOP
tRFC
A9, A11,A12
PRE
VALID
tCL
RA
NOP
tIS
tIS
tCK
tRP
A0-A8
Command
CKE
CK
CK
tCH
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Auto Refresh Mode
66
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP. All rights reserved.
REV 1.1
12/2001
DM
DQ
DQS
ADDR
Command
CKE
CK
CK
NOP
tIH
tIH
tCH
tCK
tIS
AR
Enter Self
Refresh Mode
tCL
* = Device must be in the all banks idle state before entering Self Refresh Mode.
** = tXSNR is required before any non-read command can be applied, and tXSRD (200 cycles of CK).
are required before a Read command can be applied.
tIS
tIS
tRP*
Exit Self
Refresh Mode
NOP
tXSRD, tXSRN
tIS
200 cycles
tIH
Don’t Care
VALID
tIS
VALID
Clock must be stable before exiting Self Refresh Mode
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Self Refresh Mode
67
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© NANYA TECHNOLOGY CORP. All rights reserved.
REV 1.1
12/2001
Case 2:
tAC/tDQSCK = max
Case 1:
t AC/tDQSCK = min
tIH
tIH
NOP
tIS
tIS
tIH
tLZ (max)
tLZ (max)
tRPRE
DO n
tAC (max)
DO n
tAC (min)
NOP
NOP
tDQSCK (max)
NOP commands are shown for ease of illustration; other commands may be valid at these times.
DIS AP = Disable Auto Precharge.
* = Don't care if A10 is High at this point.
PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address.
BA x
RA
RA
ACT
tHZ (max)
tRPST
tHZ (min)
tIH
tDQSCK (min)
tRPST
tRP
3 subsequent elements of data out are provided in the programmed order following DO n.
CL=2
tLZ (min)
tRPRE
BA x*
BA x
ALL BANKS
PRE
tCL
ONE BANK
tIH
NOP
tCH
DIS AP
tIH
tIS
tIS
COL n
tIS
Read
DO n = data out from column n.
DQ
DQS
DQ
DQS
DM
BA0, BA1
A10
A0-A9, A11, A12
Command
CKE
CK
CK
tCK
NOP
VALID
NOP
VALID
Don’t Care
NOP
VALID
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Read without Auto Precharge (Burst Length = 4)
68
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© NANYA TECHNOLOGY CORP. All rights reserved.
REV 1.1
12/2001
Case 2:
tAC/tDQSCK = max
Case 1:
tAC/tDQSCK = min
DQ
DQS
DQ
DQS
DM
BA0, BA1
A10
A0-A9, A11, A12
Command
CKE
CK
CK
tIH
tIH
tIH
tIH
tIH
BA x
tIS
EN AP
tIS
COL n
tIS
Read
tLZ (max)
tRPRE
tLZ (max)
CL=2
tHZ (min)
NOP
DO n
tAC (max)
DO n
tAC (min)
NOP
tCL
tLZ (min)
tRPRE
NOP
tCH
tHZ (min)
BA x
RA
RA
ACT
tDQSCK (max)
tHZ (max)
tRPST
NOP
tIH
tDQSCK (min)
tRPST
tRP
NOP
VALID
DO n = data out from column n.
3 subsequent elements of data out are provided in the programmed order following DO n.
EN AP = enable Auto Precharge.
ACT = active; RA = row address.
NOP commands are shown for ease of illustration; other commands may be valid at these times.
NOP
tIS
tIS
tCK
NOP
VALID
Don’t Care
NOP
VALID
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Read with Auto Precharge (Burst Length = 4)
69
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© NANYA TECHNOLOGY CORP. All rights reserved.
REV 1.1
12/2001
tIH
tIH
DQ
DQS
DQ
BA x
tIH
tCK
tRCD
NOP
tCH
tIH
tRAS
BA x
DIS AP
tIS
COL n
Read
tCL
tLZ (max)
NOP
DO n
tAC (max)
DO n
tAC (min)
BA x*
ONE BANK
tLZ (max)
tRPRE
tLZ (min)
CL=2
PRE
ALL BANKS
tRC
tLZ (min)
tRPRE
NOP
DO n = data out from column n.
3 subsequent elements of data out are provided in the programmed order following DO n.
DIS AP = disable Auto Precharge.
* = Don't care if A10 is High at this point.
PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address.
NOP commands are shown for ease of illustration; other commands may be valid at these times.
Case 2:
tAC/tDQSCK = max
Case 1:
t AC/tDQSCK = min
DQS
DM
BA0, BA1
tIS
RA
tIH
A10
tIS
ACT
RA
NOP
tIS
tIS
A0-A9, A11, A12
Command
CKE
CK
CK
BA x
RA
RA
ACT
tHZ (max)
tHZ (min)
tRPST
tDQSCK (max)
tDQSCK (min)
tRPST
tRP
NOP
Don’t Care
NOP
VALID
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Bank Read Access (Burst Length = 4)
70
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© NANYA TECHNOLOGY CORP. All rights reserved.
REV 1.1
12/2001
DM
DQ
DQS
BA0, BA1
A10
A0-A9, A11, A12
Command
CKE
CK
CK
tIH
tIH
tIH
tIH
tWPRES
tDQSS
tIH
BA x
tIS
DIS AP
tIS
COL n
tIS
Write
DIn
tDQSH
tWPRE
NOP
tDQSL
tCH
tCL
NOP
tWPST
tDSH
NOP
tIH
NOP
tWR
PRE
BA x*
ONE BANK
ALL BANKS
tDQSS = min.
DIn = Data in for column n.
3 subsequent elements of data in are applied in the programmed order following DIn.
DIS AP = Disable Auto Precharge.
* = Don't care if A10 is High at this point.
PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address.
NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
NOP
tIS
tIS
tCK
NOP
VALID
tRP
NOP
Don’t Care
BA
RA
RA
ACT
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Write without Auto Precharge (Burst Length = 4)
71
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© NANYA TECHNOLOGY CORP. All rights reserved.
REV 1.1
12/2001
DM
DQ
DQS
BA0, BA1
A10
A0-A9, A11, A12
Command
CKE
CK
CK
tIH
tIH
tWPRE
tWPRES
tDQSS
tIH
BA x
tIS
EN AP
tIS
COL n
tIS
Write
DIn
tDQSH
NOP
tCH
tDQSL
NOP
tCL
tWPST
tDSH
NOP
NOP
VALID
tWR
DIn = Data in for column n.
3 subsequent elements of data in are applied in the programmed order following DIn.
EN AP = Enable Auto Precharge.
ACT = Active; RA = Row address; BA = Bank address.
NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
tDQSS = min.
tIH
tIH
NOP
tIS
tIS
tCK
NOP
VALID
tDAL
NOP
VALID
tRP
NOP
Don’t Care
BA
RA
RA
ACT
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Write with Auto Precharge (Burst Length = 4)
72
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© NANYA TECHNOLOGY CORP. All rights reserved.
REV 1.1
12/2001
tIH
tIH
DM
DQ
DQS
BA0, BA1
tIH
tIH
tRCD
NOP
tCH
tIH
tWPRES
BA x
tDQSS
DIS AP
tIS
Col n
Write
tCL
DIn
tDSH
tDQSL
tWPRE
tDQSH
NOP
tRAS
NOP
tWPST
NOP
tDQSS = min.
DI n = data in for column n.
3 subsequent elements of data in are applied in the programmed order following DI n.
DIS AP = Disable Auto Precharge.
* = don't care if A10 is High at this point.
PRE = Precharge; ACT = Active; RA = Row address.
NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
BA x
tIS
RA
A10
tIS
ACT
RA
NOP
tIS
tIS
A0-A9, A11, A12
Command
CKE
CK
CK
tCK
tWR
NOP
BA x
ONE BANK
ALL BANKS
PRE
Don’t Care
NOP
VALID
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Bank Write Access (Burst Length = 4)
73
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP. All rights reserved.
REV 1.1
12/2001
DM
DQ
DQS
BA0, BA1
A10
A0-A9, A11, A12
Command
CKE
CK
CK
tIH
tIH
tIH
tIH
tIH
tWPRES
BA x
tIS
tDQSS
DIS AP
tIS
COL n
tIS
Write
DIn
tDQSH
NOP
tCH
tDQSL
tCL
NOP
tWPST
tDSH
NOP
tWR
NOP
BA x*
ONE BANK
ALL BANKS
PRE
NOP
VALID
DI n = data in for column n.
3 subsequent elements of data in are applied in the programmed order following DI n (the second element of the 4 is masked).
DIS AP = Disable Auto Precharge.
* = Don't care if A10 is High at this point.
PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address.
NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
tDQSS = min.
NOP
tIS
tIS
tCK
tRP
NOP
Don’t Care
BA
RA
RA
ACT
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Write DM Operation (Burst Length = 4)
74
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© NANYA TECHNOLOGY CORP. All rights reserved.
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Package Dimensions (400mil; 66 lead; Thin Small Outline Package)
Detail A
11.76 ± 0.20
10.16 ±. 0.13
22.22 ± 0.10
Lead #1
Seating Plane
0.10
0.65 Basic
0.30
+ 0.03
- 0.08
0.71REF
1.20 Max
Detail A
0.25 Basic
Gage Plane
0.5 ± 0.1
0.05 Min
REV 1.1
12/2001
75
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Package Dimensions (
60 balls ; 0.8mmx1.0mm Pitch ; CSP Package)
8.5
0.80
15.50
0.50
1.00
1.05
2.25
Dia.
0.45
0.35
1.60
1.15
Note : All dimensions are typical unless otherwise stated.
Unit : Millimeters
REV 1.1
12/2001
76
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
Revision Log
Rev
Contents of Modification
01/01
Preliminary
05/01
Changed to Revision 1.0
Changed to Revision 1.1
Added CSP ball configuration
12/01
Added CSP package dimensions
Removed the QFC function
REV 1.1
12/2001
77
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
®
© Nanya Technology Corporation.
All rights reserved.
Printed in Taiwan, R.O.C. December 2001
The following are trademarks of NANYA TECHNOLOGY CORPORATION in R.O.C , or other countries, or both.
NANYA NANYA logo
Other company, product and service names may be trademarks or services maeks of others.
NANYA TECHNOLOGY CORPORATION (NTC) reserves the right to make changes without notice. NTC warrants performance
of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with NTC’s
standard warranty. Testing and other quality control techniques are utilize to the extent NTC deems necessary to support this
warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or
environmental damage (“Critical Applications”).
NTC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTEND, AUTHORIZED, OR WARRANTED TO BE SUITABLE
FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of NTC products in such applications is understood to be fully at the risk of the customer. Use of NTC products in such
applications requires the written approval of an appropriate NTC officer. Question concerning potential risk applications should
be directed to NTC through a local sales office.
In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards should be
provided by customer to minimize the inherent or procedural hazards.
NTC assumes no liability of applications assistance, customer product design, software performance, or infringement of patents
or services described herein. Nor does NTC warrant or represent that any license, either express or implied, is granted under
any patent right, copyright, mask work right, or other intellectual property right of NTC covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.
NANYA TECHNOLOGY CORPORATION
HWA YA Technology Park
669, FU HSING 3rd Rd., Kueishan,
Taoyuan, Taiwan, R.O.C.
The NANYA TECHNOLOGY CORPORATION home page can be found at
http:\\www.nanya.com