PI6C2308 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Zero-Delay Clock Buffer Product Features Functional Description • • • • Maximum rated frequency: 133 MHz Low cycle-to-cycle jitter Input to output delay, less than 200ps External feedback pin allows outputs to be synchronized to the clock input 5V tolerant input* Operates at 3.3V VDD Test mode allows bypass of the PLL for system testing purposes (e.g., IBIS measurements) Clock frequency multipliers ½x to 4x dependent on option Space-saving Packages: 16-pin, 150-mil SOIC (W) 16-pin 173-mil TSSOP (L) The PI6C2308 is a PLL-based, zero-delay buffer, with the ability to distribute eight outputs of up to 133 MHz at 3.3 V. Two banks of four outputs exist, and, depending on product option ordered, can supply either reference frequency, prescaled half frequency, or multiplied 2x or 4x input clock frequencies. The PI6C2308 family has a power-sparing feature: when input SEL2 is 0, the component will 3-state one or both banks of outputs depending on the state of input SEL1. A PLL bypass test mode also exists. This product line is available in high-drive and industrial environment versions. * FB_IN and CLKIN must reference the same voltage thresholds for the PLL to deliver zero delay skewing Notice: This device is subject to import restriction. Please refer • • • • • An external feedback pin is used to synchronize the outputs to the input; the relationship between loading of this signal and the other outputs determines the input-output delay. The PI6C2308 is characterized for both commercial and industrial operation. to the Import Restriction Notice under the Ordering Information section. Block Diagram FB_IN CLKIN ÷2 Pin Configuration PI6C2308 PLL OUTA1 MUX SEL1 SEL2 CLKIN OUTA1 OUTA2 VDD GND OUTB1 OUTB2 SEL2 OUTA2 Option (-3, -4) OUTA3 OUTA4 Decode Logic ÷2 OUTB1 OUTB2 Option (-2, -3) OUTB3 PI6C2308 (-1, -1H, -2, -3, -4) 16 1 15 2 3 16-Pin 14 4 W, L 13 12 5 11 6 10 7 9 8 FB_IN OUTA4 OUTA3 VDD GND OUTB4 OUTB3 SEL1 OUTB4 FB_IN CLKIN PLL OUTA1 MUX OUTA2 OUTA3 SEL2 SEL1 OUTA4 Decode Logic ÷2 MUX PI6C2308-6 OUTB1 OUTB2 OUTB3 OUTB4 1 PS8384D 12/07/01 PI6C2308 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Zero Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Input Select Decoding for PI6C2308 (-1, -1H,-4) SEL2 SEL1 OUTA [1-4] OUTB [1-4] Output Source PLL 0 0 3- State 3- State PLL O FF 0 1 PLL 3- State PLL ON 1 0 CLK IN CLK IN CLK IN O FF 1 1 PLL PLL PLL ON Input Select Decoding for PI6C2308 (-2,-3) SEL2 SEL1 OUTA [1-4] OUTB [1-4] Output Source PLL 0 0 3- State 3- State PLL O FF 0 1 PLL 3- State PLL ON 1 0 CLK IN CLK IN/2 CLK IN O FF 1 1 PLL PLL PLL ON Input Select Decoding for PI6C2308-6 SEL2 SEL1 OUTA [1-4] OUTB [1-4] Output Source PLL 0 0 3- State 3- State PLL O FF 0 1 CLK IN CLK IN/2 CLK IN O FF 1 0 PLL PLL PLL ON 1 1 PLL PLL/2 PLL ON PI6C2308 Configurations D e vice Fe e dback From OUTA [1-4] Fre que ncy OUTB [1-4] Fre que ncy PI6C2308- 1 O UTA or O UTB CLK IN CLK IN PI6C2308- 1H O UTA or O UTB CLK IN CLK IN PI6C2308- 2 O UTA CLK IN CLK IN/2 PI6C2308- 2 O UTB 2X CLK IN CLK IN PI6C2308- 3 O UTA 2X CLK IN CLK IN or CLK IN(1) PI6C2308- 3 O UTB 4X CLK IN 2X CLK IN PI6C2308- 4 O UTA or O UTB 2X CLK IN 2XCLK IN PI6C2308- 6 O UTA CLK IN CLK IN or CLK IN/2 PI6C2308- 6 O UTB CLK IN or 2X CLK IN CLK IN Note: 1. Output phase is indeterminant (0° or 180° from CLKIN) 2 PS8384D 12/07/01 PI6C2308 Zero Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Description Pin Signal 1 D e s cription C LK IN Input clock reference frequency (weak pull- down) O UTA[1- 4] C lock output, Bank A (weak pull- down) 4 , 13 VDD 3.3V supply 5 , 12 GN D Ground O UTB[1- 4] C lock output, Bank B (weak pull- down) 8 SEL2 Select input, bit 2 (weak pull- up) 9 SEL1 Select input, bit 1 (weak pull- up) 16 FB_IN PLL feedback input 2 , 3 , 14 , 15 6, 7, 10 ,11 Zero Delay and Skew Control CLKIN - Input to OUTA/OUTB Delay (ps) CLKIN Input to Output Bank Delay vs. Difference in Loading between FB_IN pin and OUTA/OUTB pins 800 600 400 200 0 -25 -20 -15 -10 0 -5 5 10 15 20 25 -200 -400 PI6C2308-1H -600 -800 PI6C2308-1,2,3,4,6 -900 -1000 Output Load Difference: FB_IN Load - OUTA/OUTB Load (pF) The relationship between loading of the FB_IN signal and other outputs determines the input-output delay. Zero delay is achieved when all outputs, including feedback, are loaded equally. Maximum Ratings Supply Voltage to Ground Potential ............................................................................................................................. 0.5V to +7.0V DC Input Voltage (Except CLKIN) ........................................................................................................................ 0.5V to VDD +0.5V DC Input Voltage CLKIN ...................................................................................................................................................... 0.5 to 7V Storage Temperature ................................................................................................................................................... 65ºC to +150ºC Maximum Soldering Temperature (10 seconds) ........................................................................................................................... 260ºC Junction Temperature .................................................................................................................................................................. 150ºC Static Discharge Voltage (per MIL-STD-883, Method 3015) .................................................................................................... >2000V 3 PS8384D 12/07/01 PI6C2308 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Zero Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Operating Conditions (VCC = 3.3V ±0.3V) Parame te r VDD TA CL CIN De s cription Supply Voltage Commerical Operating Temperature Industrial Operating Temperature Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance M in. M ax. Units 3.0 3.6 V 0 70 40 85 ¾ ¾ ¾ ºC 30 15 pF 7 DC Electrical Characteristics for Industrial Temperature Devices Parame te r De s cription Te s t Conditions M in. M ax. VIL Input LOW Voltage VIH Input HIGH Voltage IIL Input LOW Current VIN = 0V 50.0 IIH Input HIGH Current VIN = VDD 100.0 VOL Output LOW Voltage IOL = 8mA (1, 2, 3,4, 6); IOL = 12mA (1H) VOH Output HIGH Voltage IOH = 8mA (1, 2, 3,4, 6); IOH = 12mA (1H) IDD (PD mode) Pwr Dwn Supply Current SEL1 = 0 (1, 2, 3, 4, 1H); SEL2 = 0 (6) 25.0 IDD Supply Current Unloaded outputs 100 MHz, Select inputs at VDD or GND 54.0 0.8 2.0 0.4 2.4 70.0 (1H) Unloaded outputs 66 MHz, CLKIN, except (1H) 39.0 Unloaded outputs 33MHz, CLKIN, except (1H) 20.0 4 PS8384D Units V mA V mA mA 12/07/01 PI6C2308 Zero Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 AC Electrical Characteristics for Industial Temperature Devices Parame te rs N ame Te s t Conditions M in. Typ. 30pF load FO O utput Frequency tDC C ycle(1) 10 0 20pF load, (1H) 10 . 0 13 3 15pF load, (1, 2, 3, 4, 6) Duty (1, 2, 3, 4, 6) Duty tR tF (1H) Measured at VDD/2, FO UT <66.67MHz 30pF load Measured at VDD/2, FO UT <133MHz 15pF load 40. 0 Measured at VDD/2, FO UT <45MHz 15pF load 45. 0 Measured at VDD/2, FO UT <66.67MHz 30pF load 45. 0 Measured at VDD/2, FO UT <133MHz 15pF load 40. 0 60. 0 Measured at VDD/2V, FO UT <45MHz 30pF load 45. 0 55. 0 50 Measured between 0.8V and 2.0V, 15pF load 1. 5 0 Rise Time(1) (1H) Measured between 0.8V and 2.0V, 30pF load 1. 5 0 Fall Time(1) (1, 2, 3, 4,) Measured between 0.8V and 2.0V, 30pF load 2. 50 Measured between 0.8V and 2.0V, 15pF load 1. 5 0 Measured between 0.8V and 2.0V, 30pF load 1. 2 5 (1H) O utput to O utput Skew within same Bank (1,2,3,4,6)(1) O UTA to O UTB (1,1H,4) 200 400 Delay, C LK IN Rising Edge to FB_IN Rising Edge(1) Measured at VDD/2 tSK (D) Device- to- Device Skew(1) Measured at VDD/2 on FB_IN pins of devices tJIT Rate(1) C ycle- to- C ycle Jitter(1) (1,1H,4) C ycle- to- C ycle Jitter(1) (2,3,6) tLO CK ns Skew(1) t0 O utput Slew % All outputs equally loaded O UTA to O UTB Skew(1) (2,3,6) tSLEW 55. 0 2. 2 Time(1) MHz 60. 0 Measured between 0.8V and 2.0V, 30pF load Rise Time(1) (1, 2, 3, 4,) Fall tSK (O ) C ycle(1) M ax. Units PLL Lock Time(1) Measured between 0.8V & 2.0V on 1H device using Test C rt #2 0 ± 200 0 600 1 ps V/ns Measured at 66.67 MHz, loaded 30pF load 200 Measured at 133 MHz, loaded 15pF load 10 0 Measured at 66.67 MHz, loaded 30pF load 400 Stable power supply, valid clocks presented on C LK IN and FB_IN pins 1. 0 ps ms Notes: 1. See Switching Waveforms on page 7. 5 PS8384D 12/07/01 PI6C2308 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Zero Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics for Commercial Temperature Devices Parame te r De s cription Te s t Conditions M in. ¾ ¾ ¾ VIL Input LOW Voltage VIH Input HIGH Voltage IIL Input LOW Current VIN = 0V IIH Input HIGH Current VIN = VDD VOL Output LOW Voltage VOH Output HIGH Voltage IDD (PD mode) Power Down Supply Current SEL1 = 0 (- 1,- 2,- 3,- 4,- 1H); SEL2 = 0 (- 6) IDD Supply Current Unloaded outputs, 66.67 MHz, Select inputs at VDD or GND IDD Supply Current Unloaded outputs 100 MHz Select Inputs @ VDD or GND 2.0 ¾ M ax. 0.8 ¾ 50 100 IOL = 8mA (1, 2, 3,4, 6); IOL = 12mA (1H) ¾ ¾ IOH = 8mA (1, 2, 3,4, 6); IOH = 12mA (1H) 2.4 ¾ ¾ ¾ ¾ 25 0.4 39 54 Units V mA V mA mA AC Electrical Characteristics for Commercial Temperature Device Parame te rs N ame Te s t Conditions M in. Typ. 30pF load M ax. Units 10 0 FO O utput Frequency 20pF load, (1H) 10 tDC Duty C ycle(1) (1H) Measured at VDD/2, for high drive output 45 50 55 Duty C ycle (1, 2, 3, 4, 6) Measured at VDD/2, for normal drive output 40 50 60 13 3 15pF load, (1, 2, 3, 4, 6) tR tF Rise Time(1) @30pF Rise @ 15 p F Rise Time(1) @30pF (1H) Fall Time(1) 1. 5 @ 30pF 1. 5 Measured between 0.8V and 2.0V 2. 2 Fall Time(1) @15pF Fall tSK (O ) @30pF (1H) t0 tSK (D) tSLEW tJIT tLO CK 1. 2 5 All outputs equally loaded, VDD/2 200 O UTA to O UTB Skew(1) (1,1H,4) All outputs equally loaded, VDD/2 200 O UTA to O UTB (2,3,6) All outputs equally loaded, VDD/2 400 Input to O utput Delay, C LK IN Rising Edge to FB_IN Rising Edge(1) Measured at VDD/2 0 ± 200 Device to Device Skew(1) Measured at VDD/2 on FB_IN pins of devices 0 600 O utput Slew ns 1. 5 O utput to O utput Skew(1) within same bank (1,1H,2,3,4,6) Skew(1) % 2. 2 Time(1) Time(1) MHz Rate(1) C ycle- to- C ycle Jitter(1) (1,1H,4) Measured between 0.8V and 2.0V on 1H device using Test C ircuit #2 Measured at 66.67 MHz, loaded 30pF outputs 1 ps V/ns 200 Measured at 133 MHz, loaded 15pF outputs 10 0 C ycle- to- C ycle Jitter(1) (2,3,6) Measured at 66.7 MHz, loaded 30pF outputs 400 PLL Lock Time(1) Stable power supply, valid clocks presented on C LK IN and FB_IN pins 1. 0 ps ms Notes: 1. See Switching Waveforms on page 7. 6 PS8384D 12/07/01 PI6C2308 Zero Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Waveforms tHIGH Duty Cycle Timing VDD/2 VDD/2 tLOW tDC = VDD/2 tHIGH tHIGH + tLOW All Outputs Rise/Fall Time OUTPUT Output-Output Skew OUTPUT 2.0V 0.8V tR 3.3V 2.0V 0.8V tF 0V VDD/2 VDD/2 OUTPUT tSK(O) Device-Device Skew OUTPUT Device 1 VDD/2 VDD/2 OUTPUT Device 2 tSK(D) Input-Output Propagation Delay INPUT VDD/2 VDD/2 FB_IN t0 Test Circuit 1 0.1µF Test Circuit 2 0.1µF VDD OUTPUTS CLK out 1kW VDD 1kW CLOAD 0.1µF VDD GND CLK out OUTPUTS 0.1µF VDD GND GND 10pF GND Test Circuit for tSLEW ,Output slew rate on –1H device Test Circuit for all parameters except tSLEW 7 PS8384D 12/07/01 PI6C2308 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Zero Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 16-Pin SOIC (W) Package 16 .149 .157 3.78 3.99 .0099 .0196 0.25 x 45˚ 0.50 1 .0075 .0098 0-8˚ .386 .393 9.80 10.00 0.41 1.27 .053 .068 .0155 .0260 0.393 0.660 REF 1.35 1.75 .016 .050 .2284 .2440 5.80 6.20 SEATING PLANE .050 BSC 1.27 0.19 0.25 .0040 0.10 .0098 0.25 .013 .020 0.330 0.508 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 16-Pin TSSOP (L) Package 16 .169 .177 4.3 4.5 1 .193 .201 4.9 5.1 .004 .008 .047 max. 1.20 0.45 .018 0.75 .030 SEATING PLANE .0256 BSC 0.65 .007 .012 .002 .006 0.09 0.20 .252 BSC 6.4 0.05 0.15 X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS 0.19 0.30 Note: Controlling dimensions in millimeters. Ref: JEDEC MS - 012 AC 8 PS8384D 12/07/01 PI6C2308 Zero Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Ordering Information (Commercial Temperature Device) Orde ring Code Package Name Package Type W16 16- pin 150- mil SOIC Ope rating Range PI6C2308- 1W PI6C2308- 1HW PI6C2308- 2W PI6C2308- 3W Commercial PI6C2308- 4W PI6C2308- 6W PI6C2308- 1L PI6C2308- 1HL L16 16- pin TSSO P Ordering Information (Industrial Temperature Device) Orde ring Code Package Name Package Type W16 16- pin 150- mil SOIC Ope rating Range PI6C2308- 1WI PI6C2308- 1HWI PI6C2308- 2WI PI6C2308- 3WI Industrial PI6C2308- 4WI PI6C2308- 6WI PI6C2308- 1LI PI6C2308- 1HLI L16 16- pin TSSO P Import Restriction Notice: Due to an agreement to settle a patent dispute, this device is only available for sale outside of the US and may not be subsequently re-imported into the US as an individual component or as incorporated into equipment. Any sale is expressly conditioned on the customer's agreement not to export the device or any product or equipment containing the device to the United States. Pericom disclaims any liability for indemnity or other obligation or warranty if the devices or any product or equipment containing the devices are imported in violation of this agreement. Pericom Semiconductor Corporation 2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com 9 PS8384D 12/07/01