ETC P4C16935PC

P4C168, P4C169, P4C170
P4C168, P4C169, P4C170
ULTRA HIGH SPEED 4K x 4
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
Fully TTL Compatible, Common I/O Ports
High Speed (Equal Access and Cycle Times)
– 12/15/20/25ns (Commercial)
– 20/25/35ns (P4C168 Military)
Three Options
– P4C168 Low Power Standby Mode
– P4C169 Fast Chip Select Control
– P4C170 Fast Chip Select, Output Enable
Controls
Low Power Operation (Commercial)
– 715 mW Active
– 193 mW Standby (TTL Input) P4C168
– 83 mW Standby (CMOS Input) P4C168
Standard Pinout (JEDEC Approved)
– P4C168: 20-pin DIP, SOJ and SOIC
– P4C169: 20-pin DIP and SOIC
– P4C170: 22-pin DIP
Single 5V±10% Power Supply
DESCRIPTION
The P4C168, P4C169 and P4C170 are a family of 16,384bit ultra high-speed static RAMs organized as 4K x 4. All
three devices have common input/output ports.The
P4C168 enters the standby mode when the chip enable
(CE) control goes high; with CMOS input levels, power
consumption is only 83mW in this mode. Both the P4C169
and the P4C170 offer a fast chip select access time that is
only 67% of the address access time. In addition, the
P4C170 includes an output enable (OE) control to eliminate data bus contention. The RAMs operate from a single
5V ± 10% tolerance power supply.
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption to a low 715
mW active, 193 mW standby.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
The P4C168 and P4C169 are available in 20-pin (P4C170
in 22-pin) 300 mil DIP packages providing excellent board
level densities. The P4C168 is also available in 20-pin 300
mil SOIC and SOJ packages.
The P4C169 is also available in a 20-pin 300 mil SOIC
package. The P4C170 is also available in a 22-pin 300 mil
SOJ package.
A
16,384-BIT
MEMORY
ARRAY
ROW
SELECT
(7)
A
I/O 1
I/O 2
I/O 3
INPUT
DATA
CONTROL
COLUMN I/O
I/O 4
POWER
DOWN
COLUMN
SELECT
CE or CS
WE
P4C168
ONLY
A
A0
1
20
V CC
A0
1
22
V CC
A1
2
19
A 11
A1
2
21
A 11
A2
3
18
A 10
A2
3
20
A 10
A3
4
17
A9
A3
4
19
A9
A4
5
16
A8
A4
5
18
A8
A5
6
15
I/O4
A5
6
17
A6
7
14
I/O3
A6
7
16
NC
I/O4
A7
8
13
I/O2
A7
8
15
I/O3
CE, CS
GND
9
12
I/O1
CS
9
14
I/O2
10
11
WE
OE
GND
10
13
I/O1
11
12
WE
P4C168
P4C169
DIP (P2, D2) DIP (P2)
SOIC (S2)
SOIC (S2)
SOJ (J2)
TOP VIEW
A
(5)
OE
NOTES: CE USED ON P4C168 ALSO FOR POWER DOWN FUNCTIONS
CE USED ON P4C169 FAST CHIP SELECT
OE OUTPUT ENABLE FUNCTION ON P4C170 ONLY
P4C170
DIP (P3)
TOP VIEW
Means Quality, Service and Speed
1Q97
33
P4C168, P4C169, P4C170
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
VCC
Power Supply Pin with
Respect to GND
– 0.5 to +7
V
VTERM
Terminal Voltage with
Respect to GND
(up to 7.0V)
– 0.5 to
VCC +0.5
V
TA
Operating Temperature
–55 to +125
°C
Symbol
Value
Unit
TBIAS
Temperature Under
Bias
– 55 to +125
°C
TSTG
Storage Temperature
– 65 to +150
°C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
50
mA
CAPACITANCES(4)
RECOMMENDED OPERATING CONDITIONS
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
Grade(2)
Ambient Temp
Gnd
VCC
Commercial
0°C to 70°C
0V
5.0V ± 10%
–55°C to +125°C
0V
5.0V ± 10%
Military
Parameter
Symbol
Parameter
Conditions Typ. Unit
CIN
Input Capacitance
VIN = 0V
5
pF
COUT
Output Capacitance VOUT= 0V
7
pF
DC ELECTRICAL CHARACTERISTICS
P4C168/169/170
Symbol
Parameter
Test Conditions
Min
Max
Unit
VIH
Input High Voltage
2.2
VCC +0.5
V
VIL
Input Low Voltage
–0.5(3)
0.8
V
VHC
CMOS Input High Voltage
VCC –0.2
VCC +0.5
V
VLC
CMOS Input Low Voltage
–0.5(3)
0.2
V
VCD
Input Clamp Diode Voltage
VCC = Min., IIN = –18 mA
–1.2
V
VOL
Output Low Voltage
(TTL Load)
IOL = +8 mA, VCC = Min.
0.4
V
VOLC
Output Low Voltage
(CMOS Load)
IOLC = +100 µA, VCC = Min.
0.2
V
VOH
Output High Voltage
(TTL Load)
IOH = –4 mA, VCC = Min.
VOHC
Output High Voltage
(CMOS Load)
IOHC = –100 µA, VCC = Min.
ILI
Input Leakage Current
VCC = Max., VIN = GND to VCC
ILO
Output Leakage Current
VCC = Max., CS = VIH,
VOUT = GND to VCC
ICC
Dynamic Operating
Current
Standby Power Supply
Current (TTL Input Levels)
P4C168 only
Standby Power
Supply Current
(CMOS Input Levels)
P4C168 only
ISB
ISB1
2.4
V
VCC –0.2
V
–10
–5
–10
–5
+10
+5
+10
+5
µA
VCC = Max., f = Max., Outputs Open
___
130
mA
CE ≥ VIH, VCC = Max., f = Max.,
Outputs Open
___
35
mA
CE ≥ VHC, VCC = Max., f = 0,
Outputs Open
VIN ≤ VLC or VIN ≥ VHC
___
15
mA
34
Mil.
Comm’l
Mil.
Comm’l
µA
P4C168, P4C169, P4C170
AC CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym.
–12
Parameter
–15
–25
–20
–35
Unit
Min Max Min Max Min Max Min Max Min Max
tRC
Read Cycle Time
tAA
Address Access Time
12
15
20
25
35
ns
tAC§
Chip Enable Access Time
12
15
20
25
35
ns
tAC‡
Chip Select Access Time
8
9
12
15
20
ns
tOH
Output Hold from Address Change
2
2
2
2
2
ns
tLZ‡
Chip Enable to Output in Low Z
2
2
2
2
2
ns
tHZ†
Chip Disable to Output in High Z
6
7
9
10
15
ns
tOE†
Output Enable to Data Valid
8
10
12
15
15
ns
t
†
OLZ
12
Output Enable to Output in Low Z
20
15
0
0
0
35
25
0
ns
ns
0
tOHZ†
Output Disable to Output in High Z
tRCS
Read Command Setup Time
0
0
0
0
0
ns
tRCH
Read Command Hold Time
0
0
0
0
0
ns
Chip Enable to Power Up Time
0
0
0
0
0
ns
t
§
PU
tPD§
6
7
12
Chip Disable to Power Down Time
15
11
9
20
25
§ P4C168 only
† P4C170 only
‡ Chip Select/Deselect for P4C169 and P4C170
TIMING WAVEFORM OF READ CYCLE NO. 1 (ADDRESS CONTROLLED)(5,6)
t RC
(9)
ADDRESS
t AA
t OH
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
5. WE is HIGH for READ cycle.
6. CE/CS and OE are LOW for READ cycle.
35
15
35
ns
ns
P4C168, P4C169, P4C170
CE
CS CONTROLLED)(5,7)
TIMING WAVEFORM OF READ CYCLE NO. 2 (CE
CE/CS
READ CYCLE WAVEFORM NO. 2 (CS Controlled)
(5,7)
tRC
CE/CS
(7)
t HZ
t AC
(7)
t LZ
DATA VALID
DATA OUT
(7)
t OLZ
t OHZ
HIGH IMPEDANCE
(7)
t OE
OE
(P4C170)
t RCS
t RCH
WE
I CC
VCC SUPPLY
CURRENT
(P4C168 ONLY)
t PU
t PD
I SB
OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CYCLE NO. 3—P4C170 ONLY (OE
t RC
(9)
ADDRESS
t AA
OE
t
t OH
OE
(8)
t OLZ
CS
t
t
AC
(8)
t LZ
(8)
OHZ
(8)
t HZ
DATA OUT
Notes:
7. ADDRESS must be valid prior to, or coincident with CE/CS transition
low. For Fast CS, tAA must still be met.
8. Transition is measured ±200mV from steady state voltage prior to
change, with loading as specified in Figure 1.
1521
05 valid address to the first
9. Read Cycle Time is measured from the
last
transitioning address.
36
P4C168, P4C169, P4C170
AC ELECTRICAL CHARACTERISTICS - WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym.
–12
Parameter
–20
–15
–35
–25
Min Max Min Max Min Max Min Max Min Max
Unit
tWC
Write Cycle Time
12
15
18
20
35
ns
tCW
Chip Enable Time to
End of Write
12
15
18
20
30
ns
tAW
Address Valid to
End of Write
12
15
18
20
30
ns
tAS
Address Set-up Time
0
0
0
0
0
ns
tWP
Write Pulse Width
12
15
18
20
30
ns
tAH
Address Hold Time
0
0
0
0
0
ns
tDW
Data Valid to End
of Write
7
8
10
10
15
ns
tDH
Data Hold Time
0
0
0
0
0
ns
tWZ
Write Enable to
Output in High Z
tOW
Output Active from
End of Write
4
0
5
7
0
7
0
0
13
ns
ns
0
WE CONTROLLED)(10)
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE
t WC
(12)
ADDRESS
t CW
CE/CS
t AW
t WR
t AH
t WP
WE
t AS
t DW
DATA IN
DATA VALID
t OW(8,11)
(8)
t WZ
DATA OUT
t DH
DATA UNDEFINED
HIGH IMPEDANCE
Notes:
10. CE/CS and WE must be LOW for WRITE cycle.
11. If CE/CS goes HIGH simultaneously with WE HIGH, the output
remains in a high impedance state.
12. Write Cycle Time is measured from the last valid address to the first
transitioning address.
37
P4C168, P4C169, P4C170
CE
CS CONTROLLED)(10)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE
CE/CS
t WC
(12)
ADDRESS
t AS
t CW
CE/CS
t AH
t WR
t AW
t WP
WE
t DW
DATA IN
t DH
DATA VALID
DATA OUT
HIGH IMPEDANCE
TRUTH TABLES
P4C168 (P4C169)
P4C170
CE
WE
OE
Output
Deselect
H
X
X
High Z
DOUT
Read
L
H
L
DOUT
High Z
Output Inhibit
L
H
H
High Z
Write
L
L
X
High Z
Mode
CE (CS
CS
CS)
WE
Output
Standby (Deselect)
H
X
High Z
Read
L
H
Write
L
L
Mode
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
+5
R
480Ω
DOUT
TH = 166.5 Ω
VTH = 1.73 V
D OUT
255Ω
30pF(5pF* for tHZ, tLZ, tOHZ,
tOLZ , tWZ and tOW
300pF(5pF* for tHZ, tLZ, tOHZ,
tOLZ, tWZ and tOW)
Figure 2. Thevenin Equivalent
Figure 1. Output Load
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C168, P4C169 AND P4C170
care must be taken when testing these devices; an inadequate setup can
cause a normal functioning part to be rejected as faulty. Long highinductance leads that cause supply bounce must be avoided by bringing
the VCC and ground planes directly up to the contactor fingers. A 0.01 µF
high frequency capacitor is also required between VCC and ground. To
avoid signal reflections, proper termination must be used; for example,
a 50Ω test environment should be terminated into a 50Ω load with 1.73V
(Thevenin Voltage) at the comparator input, and a 116Ω resistor must be
used in series with DOUT to match 166Ω (Thevenin Resistance).
38
P4C168, P4C169, P4C170
TEMPERATURE RANGE SUFFIX
PACKAGE SUFFIX
Package
Suffix
P
S
J
D
Temperature
Range Suffix
Description
C
Plastic DIP, 300 mil wide standard
Plastic SOIC, 300 mil wide standard
Plastic SOJ, 300 mil wide standard
CERDIP, 300 mil wide standard
Description
Commercial Temperature Range,
0°C – +70°C.
Military Temperature Range,
–55°C – +125°C.
Mil. Temp. with MIL-STD-883D
Class B compliance
M
MB
ORDERING INFORMATION
P4C
168
169
170 —
ss
p
t
Temperature Range
Package Code
Speed (Access/Cycle Time)
Device Number
Static RAM Prefix
ss = Speed (access/cycle time in ns), e.g., 15, 20
p = Package code, i.e., P, S,D, J.
t = Temperature range, i.e., C, M, MB.
The P4C168 is also available per SMD #5962-86705
SELECTION GUIDE
The P4C168, P4C169 and P4C170 are available in the following temperature, speed and package options.
Temperature
Range
Package
Speed (ns)
12
15
20
25
35
-12PC
-12SC
-12JC
-15PC
-15SC
-15JC
-20PC
-20SC
-20JC
-25PC
-25SC
-25JC
N/A
N/A
N/A
Military Temp. CERDIP
(P4C168 only)
N/A
N/A
-20DM
-25DM
-35DM
CERDIP
Military
Processed*
(P4C168 only)
N/A
N/A
-20DMB
Commercial
Plastic DIP
Plastic SOIC†
Plastic SOJ††
† P4C168 and P4C169 only.
†† P4C168
* Military temperature range with MIL-STD-883, Class B processing.
N/A = Not available
39
-25DMB -35DMB
P4C168, P4C169, P4C170
40