P4C187/P4C187L ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell Data Retention with 2.0V Supply (P4C187L Military) High Speed (Equal Access and Cycle Times) – 10/12/15/20/25/35/45 ns (Commercial) – 12/15/20/25/35 /45 ns (Industrial) – 15/20/25/35/45/55/70/85 ns (Military) Separate Data I/O Three-State Output TTL Compatible Output Low Power Operation – 743 mW Active -10 – 660/770 mW Active for -12/15 – 550/660 mW Active for -20/25/35 – 193/220 mW Standby (TTL Input) – 83/110 mW Standby (CMOS Input) P4C187 – 5.5 mW Standby (CMOS Input) P4C187L (Military) Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved) – 22-Pin 300 mil DIP – 24-Pin 300 mil SOJ – 22-Pin 290x490 mil LCC – 28-Pin 350x550 mil LCC Single 5V±10% Power Supply DESCRIPTION consumption to a low 743mW active, 193/83mW standby for TTL/CMOS inputs and only 5.5 mW standby for the P4C187L. The P4C187/P4C187L are 65, 536-bit ultra high speed static RAMs organized as 64K x 1. The CMOS memories require no clocks or refreshing and have equal access and cycle times. The RAMs operate from a single 5V ± 10% tolerance power supply. Data integrity is maintained for supply voltages down to 2.0V, typically drawing 10µA. The P4C187/P4C187L are available in 22-pin 300 mil DIP, 24-pin 300 mil SOJ, 22-pin and 28-pin LCC packages providing excellent board level densities. Access times as fast as 10 nanoseconds are available, greatly enhancing system speeds. CMOS reduces power FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS DIP (P3, D3, C3) SOJ (J4) LCC Pin configurations at end of datasheet. Document # SRAM111 REV B 1 Revised April 2007 P4C187/187L MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND –0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) –0.5 to VCC +0.5 V TA Operating Temperature –55 to +125 °C RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade(2) Ambient Temperature GND VCC 0V 0V 0V 5.0V ± 10% 5.0V ± 10% 5.0V ± 10% Military –55°C to +125°C –40°C to +85°C Industrial 0°C to +70°C Commercial Symbol Parameter Value Unit TBIAS Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA CAPACITANCES(4) VCC = 5.0V, TA = 25°C, f = 1.0MHz Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Typ. Unit VIN = 0V 5 pF VOUT = 0V 7 pF DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol Parameter VIH Input High Voltage VIL Input Low Voltage VHC CMOS Input High Voltage VLC CMOS Input Low Voltage VCD Input Clamp Diode Voltage VCC = Min., IIN = 18 mA VOL Output Low Voltage (TTL Load) Output High Voltage (TTL Load) Input Leakage Current VOH ILI –0.5(3) –0.5(3) IOL = +8 mA, VCC = Min. IOH = –4 mA, VCC = Min. VCC = Max. ISB1 –0.5(3) 0.8 V 0.2 V –1.2 –1.2 V 0.4 0.4 V 0.2 2.4 Mil. V –0.5(3) V 2.4 –10 –5 +10 +5 –5 n/a +5 n/a µA –10 –5 +10 +5 –5 n/a +5 n/a µA Standby Power Supply CE ≥ VIH Mil. Current (TTL Input Levels) VCC = Max ., Ind./Com’l. f = Max., Outputs Open ___ ___ 40 ___ ___ 40 n/a mA CE ≥ VHC Mil. VCC = Max., Ind./Com’l. f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC ___ ___ 20 ___ ___ 1.0 n/a mA Output Leakage Current VCC = Max., CE = VIH, VOUT = GND to VCC ISB 0.8 P4C187L Unit Min Max 2.2 VCC +0.5 V VCC –0.2 VCC +0.5 VCC –0.2 VCC +0.5 VIN = GND to VCC ILO P4C187 Min Max 2.2 VCC +0.5 Test Conditions Standby Power Supply Current (CMOS Input Levels) Com’l. Mil. Com’l. 35 15 n/a = Not Applicable Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. Document # SRAM111 REV B 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. Page 2 of 12 P4C187/187L POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter ICC Dynamic Operating Current* Temperature Range Commercial –10 –12 –15 –20 –25 –35 –45 –55 –70 –85 Unit 180 170 160 155 150 N/A N/A N/A N/A N/A mA Industrial N/A 180 170 160 155 150 N/A N/A N/A N/A mA Military N/A N/A 170 160 155 150 145 145 145 145 mA *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL. DATA RETENTION CHARACTERISTICS (P4C187L Military Temperature Only) Symbol Parameter VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR† Operation Recovery Time Test Conditons Min Typ.* VCC = 2.0V 3.0V Max VCC = 2.0V 3.0V V 2.0 10 CE ≥ VCC –0.2V, VIN ≥ VCC –0.2V or VIN ≤ 0.2V Unit 15 600 900 µA 0 ns tRC§ ns *TA = +25°C §tRC = Read Cycle Time † This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM Document # SRAM111 REV B Page 3 of 12 P4C187/187L AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Symbol Parameter t RC Read Cycle Time -10 -12 -15 -20 -25 -35 -45 -55 -70 -85 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max 10 12 15 20 25 35 45 55 70 85 t AA Address Access Time 10 12 15 20 25 35 45 55 70 85 t AC Chip Enable Access Time 10 12 15 20 25 35 45 65 70 85 t OH Output Hold from Address Change 2 2 2 2 2 2 2 2 2 2 t LZ Chip Enable to Output in Low Z 2 2 2 2 2 2 2 2 2 2 t HZ Chip Disable to Output in High Z t PU Chip Enable to Power Up Time t PD Chip Disable to Power Down Time 5 0 6 0 10 8 0 12 10 0 15 12 0 20 17 0 25 20 0 35 25 0 45 30 0 55 35 0 70 85 TIMING WAVEFORM OF READ CYCLE NO. 1(5) TIMING WAVEFORM OF READ CYCLE NO. 2(6) Notes: 5. CE is LOW and WE is HIGH for READ cycle. 6. WE is HIGH, and address must be valid prior to or coincident with CE transition LOW. Document # SRAM111 REV B 7. Transition is measured ±200mV from steady state voltage prior to change with specified loading in Figure 1. This parameter is sampled and not 100% tested. 8. Read Cycle Time is measured from the last valid address to the first transitioning address. Page 4 of 12 P4C187/187L AC CHARACTERISTICS - WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Symbol Parameter t WC t CW t AW Write Cycle Time -10 -12 -15 -20 -25 -35 -45 -55 -70 -85 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max 10 12 15 20 25 35 45 55 70 85 8 10 12 15 20 25 30 35 40 45 8 10 12 15 20 25 30 35 40 45 Chip Enable Time to End of Write Address Valid to End of Write tAS Address Set-up Time 0 0 0 0 0 0 0 0 0 0 t WP Write Pulse Width 8 10 12 15 20 25 30 35 40 45 0 0 0 0 0 0 0 0 0 0 6 7 10 13 15 20 25 30 35 40 0 0 0 0 0 0 0 0 0 0 t AH t DW t DH t WZ t OW Address Hold Time from End of Write Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write 6 0 7 0 8 0 12 0 15 0 17 0 20 0 25 0 30 0 35 0 WE CONTROLLED)(9) TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE Notes: 9. CE and WE must be LOW for WRITE cycle. 10. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. 11. Write Cycle Time is measured from the last valid address to the first transition address. Document # SRAM111 REV B Page 5 of 12 P4C187/187L CE CONTROLLED)(9) TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE AC TEST CONDITIONS TRUTH TABLE Input Pulse Levels GND to 3.0V Mode CE WE Output Power Standby Input Rise and Fall Times 3ns Standby H X High Z Input Timing Reference Level 1.5V Read L H DOUT Active Output Timing Reference Level 1.5V Write L L High Z Active Output Load See Figures 1 and 2 Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Due to the ultra-high speed of the P4C187/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. To avoid signal reflections, Document # SRAM111 REV B proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). Page 6 of 12 P4C187/187L LCC PIN CONFIGURATIONS 22-PIN LCC (L3) Document # SRAM111 REV B 28-PIN LCC (L5) Page 7 of 12 P4C187/187L ORDERING INFORMATION SELECTION GUIDE The P4C187 is available in the following temperature, speed and package options. The P4C187L is only available over the military temperature range. Temperature Range Commercial Industrial Military Temperature Military Processed* Package Speed (ns) 10 12 15 20 25 35 45 55 70 85 Plastic DIP -10PC -12PC -15PC -20PC -25PC -35PC -45PC N/A N/A N/A Plastic SOJ -10JC -12JC -15JC -20JC -25JC -35JC -45JC N/A N/A N/A Plastic DIP N/A -12PI -15PI -20PI -25PI -35PI -45PI N/A N/A N/A Plastic SOJ N/A -12JI -15JI -20JI -25JI -35JI -45JI N/A N/A N/A Side Brazed DIP N/A N/A -15CM -20CM -25CM -35CM -45CM -55CM -70CM -85CM CERDIP N/A N/A -15DM -20DM -25DM -35DM -45DM -55DM -70DM -85DM LCC (28 Pin) N/A N/A -15L28M -20L28M -25L28M -35L28M -45L28M -55L28M -70L28M -85L28M LCC (22 Pin) N/A N/A -15LM -20LM -25LM -35LM -45LM -55LM -70LM -85LM Side Brazed DIP N/A N/A -15CMB -20CMB -25CMB -35CMB -45CMB -55CMB -70CMB -85CMB CERDIP N/A N/A -15DMB -20DMB -25DMB -35DMB -45DMB -55DMB -70DMB -85DMB LCC (28 Pin) N/A N/A -15L28MB -20L28MB -25L28MB -35L28MB -45L28MB -55L28MB -70L28MB -85L28MB LCC (22 Pin) N/A N/A -15LMB -20LMB -25LMB -35LMB -45LMB -55LMB -70LMB -85LMB * Military temperature range with MIL-STD-883, Class B processing. N/A = Not Available Document # SRAM111 REV B Page 8 of 12 P4C187/187L Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 α C3 SIDE BRAZED DUAL IN-LINE PACKAGES 22 (300 mil) Min Max 0.100 0.200 0.014 0.023 0.030 0.060 0.008 0.015 1.050 1.260 0.260 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0.005 - D3 CERDIP DUAL IN-LINE PACKAGE 22 (300 mil) Min Max 0.225 0.015 0.020 0.045 0.065 0.009 0.012 1.060 1.110 0.290 0.320 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0° 15° Document # SRAM111 REV B Page 9 of 12 P4C187/187L Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L1 ND NE J4 SOJ SMALL OUTLINE IC PACKAGE 24 (300 mil) Min Max 0.128 0.148 0.082 0.016 0.020 0.007 0.010 0.620 0.630 0.050 BSC 0.335 BSC 0.292 0.300 0.267 BSC 0.025 - L3 RECTANGULAR LEADLESS CHIP CARRIER 22 Min Max 0.060 0.080 0.050 0.068 0.022 0.028 0.284 0.296 0.150 BSC 0.075 BSC 0.296 0.484 0.496 0.300 BSC 0.150 BSC 0.496 0.050 BSC R = .012 R = .012 0.039 0.051 0.039 0.051 0.058 0.072 4 7 Document # SRAM111 REV B Page 10 of 12 P4C187/187L Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L α L5 RECTANGULAR LEADLESS CHIP CARRIER 28 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.342 0.358 0.200 BSC 0.100 BSC 0.358 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 5 9 P3 PLASTIC DUAL IN-LINE PACKAGE 22 (300 Mil) Min Max 0.210 0.015 0.014 0.022 0.045 0.070 0.008 0.014 1.145 1.165 0.240 0.280 0.300 0.325 0.100 BSC 0.430 0.115 0.150 0° 15° Document # SRAM111 REV B Page 11 of 12 P4C187/187L REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM111 P4C187 / P4C187L ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS REV. ISSUE DATE ORIG. OF CHANGE OR 1997 DAB New Data Sheet A Oct-05 JDB Change logo to Pyramid B Apr-07 JDB Added 55, 70, and 85 ns speeds Document # SRAM111 REV B DESCRIPTION OF CHANGE Page 12 of 12