FINAL COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25 Advanced Micro Devices PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS ■ Pin and function compatible with all GAL ■ ■ ■ ■ ■ ■ Peripheral Component Interconnect (PCI) 20V8/As Electrically erasable CMOS technology provides reconfigurable logic and full testability High-speed CMOS technology — 5-ns propagation delay for “-5” version — 7.5-ns propagation delay for “-7” version Direct plug-in replacement for a wide range of 24-pin PAL devices Programmable enable/disable control Outputs individually programmable as registered or combinatorial compliant ■ Preloadable output registers for testability ■ Automatic register reset on power-up ■ Cost-effective 24-pin plastic SKINNYDIP and 28-pin PLCC packages ■ Extensive third-party software and programmer support through FusionPLD partners ■ Fully tested for 100% programming and func- tional yields and high reliability ■ Programmable output polarity ■ 5-ns version utilizes a split leadframe for improved performance GENERAL DESCRIPTION complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The equations are programmed into the device through floatinggate cells in the AND logic array that can be erased electrically. The PALCE20V8 is an advanced PAL device built with low-power, high-speed, electrically-erasable CMOS technology. Its macrocells provide a universal device architecture. The PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series devices and most 24-pin combinatorial PAL devices. Device logic is automatically configured according to the user’s design specification. A design is implemented using any of a number of popular design software packages, allowing automatic creation of a programming file based on Boolean or state equations. Design software also verifies the design and can provide test vectors for the finished device. Programming can be accomplished on standard PAL device programmers. The fixed OR array allows up to eight data product terms per output for logic functions. The sum of these products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an active-high or active-low output. The output configuration is determined by two global bits and one local bit controlling four multiplexers in each macrocell. The PALCE20V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement I1 – I10 BLOCK DIAGRAM CLK/I0 10 Programmable AND Array 40 x 64 Input Mux. OE/I11 I12 Publication# 16491 Rev. D Issue Date: February 1996 MACRO MC0 MACRO MC1 MACRO MC2 MACRO MC3 MACRO MC4 MACRO MC5 MACRO MC6 MACRO MC7 Input Mux. I/O0 I/O1 I/O2 I/O4 I/O4 I/O5 I/O6 I/O7 I13 Amendment /0 16491D-1 2-155 AMD CONNECTION DIAGRAMS (Top View) 2 23 I13 I2 3 22 I/O7 I3 4 21 I/O6 I4 5 20 I/O5 I5 6 19 I/O4 I6 7 18 I/O3 I7 I8 8 17 I/O2 9 16 I/O1 I9 10 15 I/O0 I10 11 14 I12 GND 12 13 OE/I11 4 I3 I4 I5 NC I6 I7 I8 PIN DESIGNATIONS = Clock = Ground I = Input I/O = Input/Output NC = No Connect OE = Output Enable VCC = Supply Voltage 2-156 5 25 24 6 7 8 23 22 9 10 21 20 19 11 I/O6 I/O5 I/O4 NC I/O3 I/O2 I/O1 16491D-3 Note: Pin 1 is marked for orientation. GND 3 2 1 28 27 26 12 13 14 15 16 17 18 16491D-2 CLK I/O7 VCC I1 I13 24 GND NC OE/I11 I12 I/O0 1 I9 I10 CLK/I0 CLK/I0 NC VCC PLCC/LCC I2 I1 SKINNYDIP PALCE20V8 Family AMD ORDERING INFORMATION Commercial and Industrial Products AMD programmable logic products for commercial and industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: PAL CE FAMILY TYPE PAL = Programmable Array Logic TECHNOLOGY CE = CMOS Electrically Erasable 20 V 8 H -5 P C /5 PROGRAMMING DESIGNATOR Blank = Initial Algorithm /4 = First Revision /5 Second Revision (Same algorithm as /4) NUMBER OF ARRAY INPUTS OPERATING CONDITIONS C = Commercial (0°C to +75°C) I = Industrial (–40°C to +85°C) OUTPUT TYPE V = Versatile NUMBER OF FLIP-FLOPS POWER H = Half Power (90-125 mA ICC) Q = Quarter Power (55 mA ICC) PACKAGE TYPE P = 24-Pin 300 mil Plastic SKINNYDIP (PD3024) J = 28-Pin Plastic Leaded Chip Carrier (PL 028) SPEED -5 = 5 ns tPD -7 = 7.5 ns tPD -10 = 10 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD -25 = 25 ns tPD Valid Combinations PALCE20V8H-5 JC /5 PALCE20V8H-7 Blank, /4 PALCE20V8H-10 PC, JC /5 PALCE20V8Q-10 PALCE20V8H-15 PC, JC, PI, JI PALCE20V8Q-15 PC, JC Blank, /4 PALCE20V8Q-20 PI, JI PALCE20V8H-25 PC, JC, PI, JI PALCE20V8Q-25 Valid Combinations Valid Combinations lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. PALCE20V8H-5/7/10/15/25, Q-10/15/25 (Com’l) PALCE20V8H-15/25, Q-20/25 (Ind) 2-157 AMD FUNCTIONAL DESCRIPTION The PALCE20V8 is a universal PAL device. It has eight independently configurable macrocells (MC0..MC7). Each macrocell can be configured as a registered output, combinatorial output, combinatorial I/O, or dedicated input. The programming matrix implements a programmable AND logic array, which drives a fixed OR logic array. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Pins 1 and 13 serve either as array inputs or as clock (CLK) and output enable (OE) for all flip-flops. Unused input pins should be tied directly to VCC or GND. Product terms with all bits unprogrammed (disconnected) assume the logical HIGH state and product terms with both true and complement of any input signal connected assume a logical LOW state. The programmable functions on the PALCE20V8 are automatically configured from the user’s design specification, which can be in a number of formats. The design specification is processed by development software to verify the design and create a programming file. This file, once downloaded to a programmer, configures the device according to the user’s desired function. The user is given two design options with the PALCE20V8. First, it can be programmed as an emulated PAL device. This includes the PAL20R8 series and most 24-pin combinatorial PAL devices. The PAL device programmer manufacturer will supply device codes for the standard PAL architectures to be used with the PALCE20V8. The programmer will program the PALCE20V8 to the corresponding PAL device architecture. This allows the user to use existing standard PAL device JEDEC files without making any changes to them. Alternatively, the device can be programmed directly as a PALCE20V8. Here the user must use the PALCE20V8 device code. This option provides full utilization of the macrocells, allowing non-standard architectures to be built. OE VCC 1 1 0 X 1 0 1 1 0 0 To Adjacent Macrocell 1 0 0 1 SL0X SG1 1 1 0 X D SL1X CLK I/OX 1 0 Q Q 1 0 1 1 0 X *SG1 SL0X From Adjacent Pin 16491D-4 * In Macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer. Figure 1. PALCE20V8 Macrocell 2-158 PALCE20V8 Family AMD Configuration Options Each macrocell can be configured as one of the following: registered output, combinatorial output, combinatorial I/O or dedicated input. In the registered output configuration, the output buffer is enabled by the OE pin. In the combinatorial configuration, the buffer is either controlled by a product term or always enabled. In the dedicated input configuration, the buffer is always disabled. A macrocell configured as a dedicated input derives the input signal from an adjacent I/O. The macrocell configurations are controlled by the configuration control word. It contains 2 global bits (SG0 and SG1) and 16 local bits (SL00 through SL07 and SL10 through SL17). SG0 determines whether registers will be allowed. SG1 determines whether the PALCE20V8 will emulate a PAL20R8 family or a combinatorial device. Within each macrocell, SL0x, in conjunction with SG1, selects the configuration of the macrocell and SL1x sets the output as either active low or active high. The configuration bits work by acting as control inputs for the multiplexers in the macrocell. There are four multiplexers: a product term input, an enable select, an output select, and a feedback select multiplexer. SG1 and SL0x are the control signals for all four multiplexers. In MC0 and MC7, SG0 replaces SG1 on the feedback multiplexer. These configurations are summarized in table 1 and illustrated in figure 2. If the PALCE20V8 is configured as a combinatorial device, the CLK and OE pins may be available as inputs to the array. If the device is configured with registers, the CLK and OE pins cannot be used as data inputs. Dedicated Output in a Non-Registered Device The control settings are SG0 = 1, SG1 = 0, and SL0x = 0. All eight product terms are available to the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the exception of pins 18(21) and 19(23). Pins 18(21) and 19(23) do not use feedback in this mode. Dedicated Input in a Non-Registered Device The control bit settings are SG0 = 1, SG1 = 0 and SL0x = 1. The output buffer is disabled. The feedback signal is an adjacent I/O pin. Combinatorial I/O in a Non-Registered Device The control settings are SG0 = 1, SG1 = 1, and SL0x = 1. Only seven product terms are available to the OR gate. The eighth product term is used to enable the output buffer. The signal at the I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used as an input. Combinatorial I/O in a Registered Device The control bit settings are SG0=0,SG1=1 and SL0x =1. Only seven product terms are available to the OR gate. The eighth product term is used as the output enable. The feedback signal is the corresponding I/O signal. Table 1. Macrocell Configurations SG0 SG1 SL0x Cell Configuration Devices Emulated Device has registers Registered Output Configuration The control bit settings are SG0 = 0, SG1 = 1 and SL0x = 0. There is only one registered configuration. All eight product terms are available as inputs to the OR gate. Data polarity is determined by SL1x. SL1x is an input to the exclusive-OR gate which is the D input to the flipflop. SL1x is programmed as 1 for inverted output or 0 for non-inverted output. The flip-flop is loaded on the LOW-to-HIGH transition of CLK. The feedback path is from Q on the register. The output buffer is enabled by OE. 0 1 0 Registered Output Combinatorial I/O 0 1 1 1 0 0 1 0 1 Combinatorial Output Dedicated Input 1 1 1 Combinatorial I/O PAL20R8, 20R6, 20R4 PAL20R6, 20R4 Device has no registers PAL20L2, 18L4,16L6,14L8 PAL20L2,18L4, 16L6 PAL20L8 Combinatorial Configurations Programmable Output Polarity The PALCE20V8 has three combinatorial output configurations: dedicated output in a non-registered device, I/O in a non-registered device and I/O in a registered device. The polarity of each macrocell output can be active high or active low, either to match output signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save “DeMorganizing” efforts. Selection is made through a programmable bit SL1x which controls an exclusive-OR gate at the output of the AND/OR logic. The output is active high if SL1x is a 0 and active low if SL1x is a 1. PALCE20V8 Family 2-159 AMD OE OE D CLK Q D Q Q CLK Registered Active Low Q Registered Active High Combinatorial I/O Active Low Combinatorial I/O Active High VCC VCC Note 1 Combinatorial Output Active Low Note 1 Combinatorial Output Active High Notes: 1. Feedback is not available on pins 18 (21) and 19 (23) in the combinatorial output mode. Note 2 2. This macrocell configuration is not available on pins 18 (21) and 19 (23). Adjacent I/O pin Dedicated Input Figure 2. Macrocell Configurations 2-160 PALCE20V8 Family 16491D-5 AMD Power-Up Reset Programming and Erasing All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the PALCE20V8 depend on whether they are selected as registered or combinatorial. If registered is selected, the output will be HIGH. If combinatorial is selected, the output will be a function of the logic. The PALCE20V8 can be programmed on standard logic programmers. It also may be erased to reset a previously configured device back to its virgin state. Erasure is automatically performed by the programming hardware. No special erase operation is required. Register Preload The register on the PALCE20V8 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. Security Bit A security bit is provided on the PALCE20V8 as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback and verification of the programmed pattern by a device programmer, securing proprietary designs from competitors. The bit can only be erased in conjunction with the array during an erase cycle. Electronic Signature Word An electronic signature word is provided in the PALCE20V8. It consists of 64 bits of programmable memory that can contain any user-defined data. The signature data is always available to the user independent of the security bit. Quality and Testability The PALCE20V8 offers a very high level of built-in quality. The erasability of the device provides a direct means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to provide the highest programming and post-programming functional yields in the industry. Technology The high-speed PALCE20V8H is fabricated with AMD’s advanced electrically erasable (EE) CMOS process. The array connections are formed with proven EE cells. Inputs and outputs are designed to be compatible with TTL devices. This technology provides strong input clamp diodes, output slew-rate control, and a grounded substrate for clean switching. PCI Compliance The PALCE20V8H-7/10 is fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The PALCE20V8H-7/10’s predictable timing ensures compliance with the PCI AC specifications independent of the design. On the other hand, in CPLD and FPGA architectures without predictable timing, PCI compliance is dependent upon routing and product term distribution. PALCE20V8 Family 2-161 AMD LOGIC DIAGRAM SKINNYDIP (PLCC and LCC) Pinouts 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 24 VCC (28) CLK/I0 1 (2) 23 (27) 1 0 I1 2 (3) SG0 11 VCC 0X 10 I 13 11 10 00 01 SL0 7 0 SG1 11 0X D 7 Q 22 I/O7 (26) 10 Q 10 11 0X I2 3 (4) SG0 11 VCC 0X 10 SL07 11 10 00 01 SL06 8 SG1 11 0X D 15 Q 21 I/O6 (25) 10 Q 10 11 0X I3 4 (5) SG1 11 VCC 0X 10 SL06 11 10 00 01 SL05 16 SG1 11 0X D 23 Q 20 I/O5 (24) 10 Q 10 11 0X I4 5 (6) SG1 11 VCC 0X 10 SL05 11 10 00 01 SL04 24 SG1 11 0X D Q 19 I/O4 (23) 10 Q 31 10 11 0X I5 6 (7) SG1 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 SL04 CLK OE 16491D-6 2-162 PALCE20V8 Family AMD LOGIC DIAGRAM (continued) SKINNYDIP (PLCC and LCC) Pinouts 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 CLK OE 11 VCC 0X 10 11 10 00 01 SL03 32 SG1 11 0X D 39 Q 18 I/O3 (21) 10 Q 10 11 0X I6 7 (9) SG1 11 VCC 0X 10 SL0 3 11 10 00 01 SL02 40 SG1 11 0X D 47 Q 17 I/O2 (20) 10 Q 10 11 0X I7 8 (10) SG1 11 VCC 0X 10 SL02 11 10 00 01 SL01 48 SG1 11 0X D 55 Q 16 I/O 1 (19) 10 Q 10 11 0X I8 9 (11) SL01 SG1 11 VCC 0X 10 11 10 00 01 SL00 56 SG1 11 0X D 63 Q 15 I/O0 (18) 10 Q 10 11 0X I 9 10 (12) SG0 0 1 10 11 (13) SG0 SL00 14 I12 (17) 13 OE/I11 (16) 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 16491D-6 (concluded) PALCE20V8 Family 2-163 AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Commercial (C) Devices Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC Output or I/O Pin Voltage . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0°C to +75°C) . . . . . . . . . . . . . . . . . . . . 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = –3.2 mA VCC = Min VOL Output LOW Voltage IOL = 24 mA VCC = Min VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –100 µA IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) 10 µA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) –100 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –150 mA ICC Supply Current Outputs Open (IOUT = 0 mA) VCC = Max, f = 15 MHz 90 55 mA VIN = VIH or VIL Max Unit 2.4 VIN = VIH or VIL V 0.5 V 2.0 –30 H Q V Notes: 1. These are absolute values with respect to device ground all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-172 PALCE20V8H-15/25 Q-15/25 (Com’l) AMD CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Typ Unit Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25°C, 5 pF Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol -15 Parameter Description Min -25 Max Min Max Unit 25 ns tPD Input or Feedback to Combinatorial Output tS Setup Time from Input or Feedback to Clock 12 15 ns tH Hold Time 0 0 ns tCO Clock to Output tWL tWH fMAX 15 10 LOW Clock Width Maximum Frequency (Note 3) HIGH External Feedback 1/(tS + tCO) Internal Feedback (fCNT) 1/(tS + tCF) (Note 4) No Feedback 1/(tWH + tWL) 12 ns 8 12 ns 8 12 ns 45.5 37 MHz 50 40 MHz 62.5 41.6 MHz tPZX OE to Output Enable 15 20 ns tPXZ OE to Output Disable 15 20 ns tEA Input to Output Enable Using Product Term Control 15 25 ns tER Input to Output Disable Using Product Term Control 15 25 ns Notes: 2. See Switching Test Circuit for test conditions. 3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) – tS. PALCE20V8H-15/25 Q-15/25 (Com’l) 2-173 AMD SWITCHING WAVEFORMS Input or Feedback VT tS Input or Feedback VT tH VT Clock tCO tPD Combinatorial Output Registered Output VT VT 16491D-8 16491D-7 Combinatorial Output Registered Output tWH VT Input VT Clock tER Output tWL tEA VOH - 0.5V VOL + 0.5V 16491D-9 VT 16491D-10 Clock Width Input to Output Disable/Enable VT OE tPXZ Output tPZX VOH - 0.5V VT VOL + 0.5V 16491D-11 OE to Output Disable/Enable Notes: 1. VT = 1.5 V 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns – 5 ns typical. 2-176 PALCE20V8 Family AMD KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010-PAL SWITCHING TEST CIRCUIT 5V S1 R1 Output R2 CL Switching Test Circuit 16491D-12 Commercial Specification S1 CL tPD, tCO Closed tPZX, tEA Z → H: Open Z → L: Closed 50 pF H → Z: Open 5 pF tPXZ, tER R1 R2 Measured Output Value 1.5 V 200 Ω L → Z: Closed PALCE20V8 Family 390 Ω 1.5 V H-5: H → Z: VOH – 0.5 V 200 Ω L → Z: VOL + 0.5 V 2-177 AMD TYPICAL ICC CHARACTERISTICS VCC = 5.0 V, TA = 25°C 150 20V8H-5 125 100 20V8H-7 ICC (mA) 75 20V8H-10 20V8H-15/25 50 20V8Q-10 20V8Q-15/25 25 0 0 10 20 30 Frequency (MHz) 40 50 16491D-13 ICC vs. Frequency The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and the other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector, half of the outputs were switching. By utilizing 50% of the device, a midpoint is defined for ICC. From this midpoint, a designer may scale the ICC graphs up or down to estimate the ICC requirements for a particular design. 2-178 PALCE20V8 Family AMD ENDURANCE CHARACTERISTICS The PALCE20V8 is manufactured using AMD’s advanced electrically erasable process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed—a feature which allows 100% testing at the factory. Endurance Characteristics Symbol tDR N Parameter Test Conditions Min Pattern Data Retention Time Max Storage Temperature Min Reprogramming Cycles Min Unit 10 Years Max Operating Temperature 20 Years Normal Programming Conditions 100 Cycles PALCE20V8 Family 2-179 AMD POWER-UP RESET The PALCE20V8 has been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will be HIGH independent of the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Parameter Symbol Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: ■ The VCC rise must be monotonic. ■ Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Description Min tPR Power-Up Reset Time tS Input or Feedback Setup Time tWL Clock Width LOW Max Unit 1000 ns See Switching Characteristics VCC 4V Power tPR Registered Output tS Clock tWL 16491D-16 Power-Up Reset Waveforms 2-182 PALCE20V8 Family