PC87410 PCI-IDE Interface Controller General Description The PCI-IDE Interface Controller is designed to interface the IDE drive directly onto the PCI bus. It provides write posting and read pre-fetches, allowing the CPU to run concurrently with IDE cycles. It connects IDE drIves ‘‘gluelessly’’ into the PCI bus and supports faster ATA devices using modes 1, 2 and 3 through PIO accesses. It supports dual IDE channels for up to four drives, and works seamlessly with the National Semiconductor’s SuperI/OTM family of products. A full suite of software drives included with device are fully tested with DOS 5.0–6.x, Windows 3.x–4.x, Windows NT, OS/2 2.x, Novell Netware 3.1x–4.x, and SCO UNIX 3.x. Y Y Y Y Y Y Y Key Features Y Y Y Y Fully compatible with PCI specifications rev 2.0 (April, 1993) Programmable Base Address registers Interfaces with the 32 bits PCI local bus to IDE drives Support IDE PIO timing mode 0, 1, 2 of ANSI ATA specifications Y Y Y Support Mode 3 (11 MB/s) timing proposal on enhanced IDE (IDE-2 or ATA-2) specifications Two IDE-2 channel supported (each channel supports 2 devices) Supports primary IDE or secondary IDE address 16-Byte FIFO provide 4-level Posted Write and Read ahead buffers per channel for concurrent system operation Programmable command and recovery timing for reads and writes per channel Independent timings for command registers and data registers Slew rate controlled output directly interface with IDE devices Supports either IRQ14/15 or INTAÝ/BÝ Hardware and Software chip enable/disable capability 100 pin PQFP package, NO other glue logic needed and 12 mA transceivers are built in Block Diagram TL/F/12073 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. SuperI/OTM is a trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL/F/12073 RRD-B30M75/Printed in U. S. A. PC87410 PCI-IDE Interface Controller October 1994 Absolute Maximum Ratings 5V g 10% Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VDD) Input Voltage (VI) Output Voltage (VO) Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) Supply Voltage Operating Temperature (TA) b 0.5V to a 7.0V b 0.5V to VDD a 0.5V Min Typ 4.5 5.0 0 Max 5.5 a 70 Units V §C b 0.5V to VDD a 0.5V b 65§ C to a 165§ C a 260§ C DC Electrical Characteristics Symbol VIL Parameter Conditions Min CMOS TTL VIH VOH VOL Units 0.3VDD V 0.8 V 0.7 VDD TTL IIL Max Input High Voltage CMOS IIH Typ Input Low Voltage V 2.0 Input High Current VIN e VDD Input with Pull-Down V b 10 10 VIN e VDD 10 200 mA Input Low Current VIN e VSS b 10 10 mA Input with Pull-Down VIN e VSS b 10 mA Type B8 IOH e 8 mA 2.4 Type B12 IOH e 12 mA 2.4 Type B8 IOL e 8 mA 0.4 V 0.4 V 10 mA 10 mA Type B12 IOL e 12 mA IOZ Output TRI-STATE Leakage Current VOH e VSS or VDD IDD VDD Average Supply Current No Load b 200 b 10 2 mA V V PCIÐBased System TL/F/12073 – 2 Basic Configuration The following diagram shows how the PCI-IDE Interface Controller is used in a system. TL/F/12073 – 3 Note 1. Second IDE connector is optional Note 2. Legacy header is needed under the following conditions: a. The device is on a PCI adapter card. b. IDE compatibility is required. 3 Connection Diagram Plastic Quad Flatpak, EIAJ TL/F/12073 – 4 Order Number PC87410VLK See NS Package Number VLK100A 4 Pin Description PCI Interface Name AD[31:0] Type IOL I/O 8 mA Description MULTIPLEXED ADDRESS AND DATA. The direction of these pins are defined below: Phase Address Phase Data Phase Read Write C/BE [3:0] I PAR I/O FRAMEÝ input output input COMMAND/BYTE ENABLE are multiplexed Bus command and Byte enables. 8 mA I PARITY is even parity across AD[31:0] and C/BE[3:0]. PAR is an input during writes and an output during reads. CYCLE FRAME is driven by the initiator to indicate the beginning and duration of an access. TRDYÝ O/TRI-STATEÉ IRDYÝ I STOPÝ O/TRI-STATE 8 mA STOP indicates that the current target is requesting the initiator to stop the current transaction. DEVSELÝ O/TRI-STATE 8 mA DEVICE SELECT, when actively drive, indicates the driving device has decoded its adderss as the target of the current access. IDSEL 12 mA INITIATOR READY indicates that the initiator is ready to complete the current data phase of the transaction. I PERRÝ O/TRI-STATE SERRÝ O/TRI-STATE INTAÝ, BÝ O/TRI-STATE TARGET READY indicates that the current data phase of the transaction is ready to be completed. INITIALIZATION DEVICE SELECT is used as a chip select during configuration read and write transactions. 8 mA PARITY ERROR is used for reporting data parity errors during all PCI transactions except a Special Cycle. PERRÝ is an output during writes and an input during reads. 8 mA SYSTEM ERROR is used for reporting address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be castrophic. When reporting address parity errors, SERRÝ is an output. When reporting data parity errors for the Special Cycle command, SERRÝ is an output during writes and an input during needs. 8 mA, Slew Rate Control INTERRUPT. Interrupt request A and B CLK I CLOCK. Up to 33 MHz PCI Clock RSTÝ I RESET. PCI Reset Power and Ground Name Type Description GND I VSS or GROUND VCC I VDD or a 5V. Power to PCI buffers, core and IDE buffers. Note: All signals are TTL except CH0ÐINT (Pin 48) and CH1ÐINT (Pin 87) are CMOS. 5 Pin Description (Continued) IDE Interface Type IOL Description IDEÐD[15:0] Name I/O 12 mA, Slew Rate Control DRIVE DATA BUS. This is an 8- or 16-bit bi-direction data between the PCI-IDE chip and the drive. The lower 8 bits are used for 8-bit transfers (e.g. command registers, ECC bytes). CH0ÐDA[2:0] O 12 mA, Slew Rate Control CHANNEL 0 ADDRESS LINES. This is the 3-bit binary coded address asserted by the host to access a register or data port in the drive. CH1ÐDA [2:0] O 12 mA, Slew Rate Control CHANNEL 1 ADDRESS LINES. This is the 3-bit binary coded address asserted by the host to access a register or data port in the drive. IORDY0 I CHANNEL 0 I/O CHANNEL READY. This signal is negated to extend the disk transfer cycle of any register access (read or write) when the drive is not ready to respond to a data transfer request. IORDY1 I CHANNEL 1 I/O CHANNEL READY. This signal is negated to extend the disk transfer cycle of any register access (read or write) when the drive is not ready to respond to a data transfer request. CH0ÐIORÝ O 12 mA, Slew Rate Control CHANNEL 0 I/O READ. This is the read strobe signal. The falling edge of CH0ÐIORÝ enables data from a register or the data port of the drive onto the PCI bus. CH0ÐIOWÝ O 12 mA, Slew Rate Control Channel 0 I/O Read. This is the write strobe signal. The rising edge of CH0Ð IOWÝ clocks data from the PCI-IDE chip into the register or the data port of the drive. CH1ÐIORÝ O 12 mA, Slew Rate Control CHANNEL 1 I/O READ. This is the read strobe signal. The falling edge of the CH1ÐIORÝ enables data from a register or the data port of the drive onto the PCI bus. CH1ÐIOWÝ O 12 mA, Slew Rate Control CHANNEL 1 I/O WRITE. This is the write strobe signal. The rising edge of CH1ÐIOWÝ clocks data from the PCI-IDE chip into the register or the data port of the drive. HDDRSTÝ O 12 mA, Slew Rate Control DRIVE RESET. This signal from the PCI-IDE chip is triggered by RSTÝ or under software control which generates IDE reset for a min time of 62 ms. CH0ÐCS1Ý, CH0ÐCS3Ý O 12 mA, Slew Rate Control CHANNEL 0 CHIP SELECT 1 AND 3. CH0ÐCS1Ý is the chip select signal to select the Command Block Register. CH0ÐCS3Ý is the chip select signal to select the Control Block Register. CH1ÐCS1Ý, CH1ÐCS3Ý O 12 mA, Slew Rate Control CHANNEL 1 CHIP SELECT 1 AND 3. CH1ÐCS1Ý is the chip select signal to select the Command Block Registers. CH1ÐCS3Ý is the chip select to select the Control Block Registers. CH0ÐINT CH1ÐINT I CHANNEL INTERRUPTS. These signals are used to interrupt the host system. CH0ÐINT is asserted only when the drive(s) on channel 0 has a pending interrupt, and the host has cleared nIEN in the Device Control Register. CH1Ð INT is asserted only when the drive(s) on channel 1 has a pending interrupt, and the host has cleared nIEN in the Device Control Register. ENABLE I CHIP ENABLE PIN. Logic low will disable this chip. If this pin is tied to Logic High or not connected then the chip is enabled. HEADER I HEADER PIN. See page 13. IRQ14 O/TRI-STATE 8 mA, Slew Rate Control The output of this pin is equivalent to ISA IRQ14 if HEADER is ‘‘not connected’’ or Logic High. However, this pin will go to TRI-STATE if HEADER is tied to Logic low. IRQ15 O/TRI-STATE 8 mA, Slew Rate Control The output of this pin is equivalent to ISA IRQ15 if HEADER is ‘‘Not connected’’ or Logic High. However, this pin will go to TRI-STATE if HEADER is tied to Logic low. 6 Configuration Registers The configuration register map is shown in Table I. TABLE I Reg. Ý (in HEX) Description R/W 00 R VENDOR ID (100Bh) 02 – 3 R DEVICE ID (D001h) 04 – 5 R/W COMMAND REGISTER. The command register provides coarse control over a device’s ability to generate and respond to PCI cycles. bit 0Ðcontrols the response to the I/O space accesses specified in the Base Address Register. Default value is determined by the ENABLE pin. 1: Chip enable 0: Chip enable bit 6Ð allows the controller to detect parity errors on the PCI bus and report these errors to the system. 1: enable parity checking 0: disable parity checking (default) bit 8Ðallows the controller to detect system errors on the PCI bus and report these errors to the system. 1: enable system error checking 0: disable system error checking (default) 06 R/W STATUS REGISTER. This register is used to record status information for PCI bus related events. ‘‘Reads’’ from this register behaves normally. However, ‘‘write’’ to this register is slightly different respect to the ordinary register. This register can be reset but not set. In order to reset this register, a logical High need to write to the corresponding bit. For details, please check P.156 of the PCI specification 2.0 (April 30, 1993). bit 9–10: These bit encode the timing of DEVSELÝ. (read only) 00: fast 01: medium, Default bit 14: 1 means system error bit 15: This bit will be set by a device whenever that device detects a data parity error. This bit is disabled when parity error handling is disabled. A logical one means detection of parity error. Please check P. 157 of the PCI specification 2.0 (April 30, 1993). Reg. Ý (in HEX) R/W Description 08 R REV. ID (00h) 09 R PROGRAMMING INTERFACE, default is 00h 0A R SUB-CLASS CODE, default is 01h (means IDE controller) 0B R BASIC CLASS CODE, default is 01h (means mass storage) 0C – 0D 0E Not Used R HEADER TYPE, default is 00h 10 – 13 R/W BASE ADDRESS REGISTERS 0. For Primary IDE Data Control Ports (Default: 000001F0h – 000001F7h) bit0: fixed to 1 bit1: fixed to 0 bit2: fixed to 0 14 – 17 R/W BASE ADDRESS REGISTERS 1. For Primary IDE Control Status Ports (Default: 000003F6h) Note: only ‘‘3F6’’ byte is accessible bit0: fixed to 1 bit1: fixed to 0 18 – 1B R/W BASE ADDRESS REGISTER 2. For Secondary IDE Data Control Ports. (Default: 00000170h – 0000177h) bit0: fixed to 1 bit1: fixed to 0 bit2: fixed to 0 1C – 1F R/W BASE ADDRESS REGISTER 3. For Secondary IDE Control Status Ports. (Default: 00000376h) Note: only ‘‘376’’ byte is accessible bit0: fixed to 1 bit1: fixed to 0 7 Configuration Registers The configuration register map is shown in Table I. (Continued) TABLE I (Continued) Reg. Ý (in HEX) R/W 20 – 27 Description Not used. 3C R/W 3D R INTERRUPT LINE, default is 0Eh INTERRUPT PIN Default is 00h if HEADER pin is HIGH Default is 01h if HEADER pin is LOW 3E – 3F Not used 40 IDE CHANNEL 0 TIMING CONTROL REGISTER. This register is the cycle control register for 1F0h port. Default is set at B5H. (Note 1) bit 7, 6: address/chip select setup time 00 1 PCI clk 01 2 PCI clk 10 3 PCI clk (default) 11 4 PCI clk bit 5 4 3: address/chip select/write data hold time 000 1 PCI clk 001 2 PCI clk 010 3 PCI clk 011 4 PCI clk 100 5 PCI clk 101 6 PCI clk 110 8 PCI clk (default) 111 12 PCI clk bit 2 1 0: Command active time 000 2 PCI clk (Note 3) 001 3 PCI clk 010 4 PCI clk 011 5 PCI clk 100 6 PCI clk 101 8 PCI clk (default) 110 12 PCI clk 111 16 PCI clk 41 W/O 42 Bit 7 is R/W, others are W/O IDE CHANNEL 0 READÐAHEAD COUNTER, LOW BYTE. It provides values for loading bit0–bit7 of readÐahead counter. bit0: bit0 of the readÐahead counter bit1: bit1 of the readÐahead counter bit2: bit2 of the readÐahead counter bit3: bit3 of the readÐahead counter bit4: bit4 of the readÐahead counter bit5: bit5 of the readÐahead counter bit6: bit6 of the readÐahead counter bit7: bit7 of the readÐahead counter IDE CHANNEL 9 READÐAHEAD COUNTER, HIGH BYTE. It provides values for loading bit8–bit9 readÐahead counter. bit0: bit8 of the readÐahead counter bit1: bit9 of the readÐahead counter bit7: readÐahead function control 1: enable 0: disable (default) 8 Configuration Registers The configuration register map is shown in Table I. (Continued) TABLE I (Continued) Reg. Ý (in HEX) R/W Description 43 IDE CHANNEL 0 FUNCTION REGISTER. bit3: channel 0 I/O decode enable bit 1: enable (default) 0: disable bit2: IORDY0 function control 1: enable 0: disable (default) bit1: CH0ÐINT status (read only) 1: interrupt pending 0: no interrupt pending bit0: CH0ÐINT request to be masked or not 1: be masked 0: not be masked (default) 44 IDE CHANNEL 1 TIMING CONTROL REGISTER. This register is the cycle control register for 170h port. Default is set at B5h. (Note 1) bit 7, 6: address/chip select setup time 00 1 PCI clk 01 2 PCI clk 10 3 PCI clk (default) 11 4 PCI clk bit 5 4 3: address/chip select/write data hold time 000 1 PCI clk 001 2 PCI clk 010 3 PCI clk 011 4 PCI clk 100 5 PCI clk 101 6 PCI clk 110 8 PCI clk (default) 111 12 PCI clk bit 2 1 0: Command active time 000 2 PCI clk 001 3 PCI clk 010 4 PCI clk 011 5 PCI clk 100 6 PCI clk 101 8 PCI clk (default) 110 12 PCI clk 111 16 PCI clk 45 W/O IDE CHANNEL 1 READÐAHEAD COUNTER, LOW BYTE. It provides values for loading bit0– bit7 of readÐahead counter. bit0: bit0 of the readÐahead counter bit1: bit1 of the readÐahead counter bit2: bit2 of the readÐahead counter bit3: bit3 of the readÐahead counter bit4: bit4 of the readÐahead counter bit5: bit5 of the readÐahead counter bit6: bit6 of the readÐahead counter bit7: bit7 of the readÐahead counter 9 Configuration Registers The configuration register map is shown in Table I. (Continued) TABLE I (Continued) Reg. Ý (in HEX) 46 R/W Bit 7 is R/W, others are W/O Description IDE CHANNEL 1 READÐAHEAD COUNTER, HIGH BYTE. It provides values for loading bit8–bit9 of readÐahead counter bit0: bit8 of the readÐahead counter bit1: bit9 of the readÐahead counter bit7: readÐahead function control 1: enable 0: disable (default) 47 IDE CHANNEL 1 FUNCTION REGISTER. bit3: channel 1 I/O decode enable bit 1: enable (default) 0: disable bit2: IORDY1 function control 1: enable 0: disable (default) bit1: CH1ÐINT status (read only) 1: interrupt pending 0: no interrupt pending bit0: CH1ÐINT request to be masked or not 1: be masked 0: not be masked (default) 48 PCI CONTROL REGISTER. bit3: host posted write cycle timing select 1: min. 1 wait state (default) 0: min. 0 wait state (Note 2) bit2: active HDDRSTÝ output active control 1: activate HDDRSTÝ(default) 0: No action bit1: DEVSELÝ timing select 1: medium (default) 0: fast bit0: Header for IDE support on PCI is present or not 1: present 0: absent, Default Values is determined by the ‘‘Header Pin’’. 49 – 4F Not used. Note 1: Total cycle time is calculated by adding setup time, hold time, and active time plus 1 clk. Note 2: When 0 wait state is used then DEVSELÝ timing select bit should be set to 0 (fast). Note 3: If register 40 is 00, then IORDY0 should be disabled. If register 44 is 00, then IORDY1 should be disabled. 10 Relation Table for INTAÝ, INTBÝ, IRQ14/15 with HEADER and channel I/O base registers Condition Outcome When chip is disabled (HEADER is ‘‘don’t care’’) and the setting of channel 0/1 I/O base register setting is ‘‘don’t care’’ IRQ14: off IRQ15: off INTAÝ: off INTBÝ: off16 HEADER is absent (Note 1), chip is enabled and the setting of channel 0/1 I/O base register setting is ‘‘don’t care’’ IRQ14: off IRQ15: off INTAÝ: inversion of CH0ÐINT, if CH0ÐINT is not masked by the bit0 of register 43h. Otherwise, it is at TRI-STATE. INTBÝ: inversion of CH1ÐINT, if CH1ÐINT is not masked by the bit0 of register 47h. Otherwise, it is at TRI-STATE. HEADER is present, chip is enabled Channel 0 I/O is set at ‘‘primary IDE port’’ IRQ14: same value of CH0ÐINT, if CH0ÐINT is not masked by the bit0 of register 43h. Otherwise, it is at TRI-STATE. HEADER is present, chip is enabled Channel 0 I/O is set at ‘‘other I/O port’’ INTAÝ: inversion of CH0ÐINT, if CH0ÐINT is not masked by the bit0 of register 43h. Otherwise, it is at TRI-STATE. IRQ14: off HEADER is present, chip is enabled Channel 1 I/O is set at ‘‘secondary IDE port’’ IRQ15: same value of CH1ÐINT, if CH1ÐINT is not masked by the bit0 of register 47h. Otherwise, it is at TRI-STATE. HEADER is present, chip is enabled Channel 1 I/O is set at ‘‘other I/O port’’ INTAÝ: inversion of CH1ÐINT, if CH1ÐINT is not masked by the bit0 of register 47h. Otherwise, it is at TRI-STATE. IRQ15: TRI-STATE HEADER is present, chip is enabled Channel 0 is not primary port and Channel 1 is not secondary port IRQ14: TRI-STATE IRQ15: TRI-STATE INTAÝ: Inversion of ORed value of CH0ÐINT and CH1ÐINT, if none of the CH0ÐINT and CH1ÐINT is masked by the bit0 of their respective registers. Otherwise, it is at TRI-STATE. Note: INTBÝ is always at TRI-STATE when HEADER is present. Note 1: HEADER absent means Logic Low. 11 Timing Specification Symbol Parameter Conditions Min Max Units t0 CLK period 30 t1 PCI signals input setup time (Note) 7 t2 PCI signals CLK to output valid 6 12 ns t3 CLK to CHxÐDA[2:0], CHxÐCS1, 3Ý, CHxÐIORÝ, CHxÐIOWÝ, IDEÐD[15:0] valid 6 15 ns t4 IORDYx setup time to CLK rising 6 ns t5 IORDYx hold time from CLK rising 0 ns t6 CHxÐDA[2:0], CHxÐCS1, 3Ý setup time to CHxÐIORÝ, CHxÐIOWÝ falling 1 4 CLK t7 CHxÐIORÝ, CHxÐIOWÝ active pulse width 2 16 CLK t8 CHxÐDA[2:0], CHxÐCS1, 3Ý hold time from CHxÐIORÝ, ChxÐIOWÝ rising 1 12 CLK t9 IDEÐD[15:0] read data setup time to CLK rising 10 ns t10 IDEÐD[15:0] read data hold time from CLK rising 0 ns t11 CLK to AD[31:0] read data valid delay 0 14 ns t12 CHxÐDA[2:0], CHxÐCS1, 3Ý setup time to CHxÐIORÝ, CHxÐIOWÝ falling (Non Data Cycle) 4 4 CLK CHxÐDA[2:0], CHxÐCS1, 3Ý hold time from CHxÐIORÝ, CHxÐIOWÝ rising (Non Data Cycle) 5 6 CLK CHxÐIORÝ, CHxÐIOWÝ, active pulse width (Non Data Cycle) 15 16 CLK t13 t14 Note: If fast decode is enabled, the address setup time (t1 min) is 12 ns. 12 ns ns Timing Diagrams Configuration Register Read Cycle Configuration Register Write Cycle TL/F/12073 – 5 TL/F/12073 – 6 Read Ahead Cycles (Read Buffer Miss) TL/F/12073 – 7 13 Timing Diagrams (Continued) Read Ahead Cycles (read buffer hit) TL/F/12073 – 8 PCI Posted Write Cycles (medium decode) TL/F/12073 – 9 14 Timing Diagrams (Continued) PCI Posted Write Cycles (fast decode) TL/F/12073 – 10 IDE Non Data Cycles (read or write) TL/F/12073 – 11 15 PC87410 PCI-IDE Interface Controller Physical Dimensions inches (millimeters) 100-Lead (14m x 20 mm) Molded Quad Flat Package, EIAJ Order Number PC87410VLK NS Package Number VLK100A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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