PCA8550 NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE www.ti.com SCPS050C – MARCH 1999 – REVISED MAY 2005 FEATURES • • • • • • • • D, DB, OR PW PACKAGE (TOP VIEW) EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process Useful for Jumperless Configuration of PC Motherboard Inputs Accept Voltages to 5.5 V MUX OUT Signals are 2.5-V Outputs NON-MUXED OUT Signal is a 3.3-V Output Minimum of 1000 Write Cycles Minimum of 10 Years Data Retention Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages I2C SCL I2C SDA OVERRIDE MUX IN A MUX IN B MUX IN C MUX IN D GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC WP NON-MUXED OUT MUX SELECT MUX OUT A MUX OUT B MUX OUT C MUX OUT D DESCRIPTION/ORDERING INFORMATION This 4-bit 1-of-2 multiplexer with I2C input interface is designed for 3-V to 3.6-V VCC operation. The PCA8550 is designed to multiplex four bits of data from parallel inputs or from I2C input data stored in a nonvolatile register. An additional bit of register output also is provided, which is latched to prevent changes in the output value during the write cycle. The factory default for the contents of the register is all low. These stored values can be read from, or written to, using the I2C bus. The ability to control writing to the register is provided by the write protect (WP) input. The override (OVERRIDE) input forces all the register outputs to a low. This device provides a fast-mode (400 kbit/s) or standard-mode (100 kbit/s) I2C serial interface for data input and output. The implementation is as a slave. The device address is specified in the I2C interface definition table. Both of the I2C Schmitt-trigger inputs (SCL and SDA) provide integrated pullup resistors and are 5-V tolerant. The PCA8550 requires a monotonic power-supply ramp at start-up in the region of 1.1 V to 2.5 V. The nonvolatile registers and I2C state machine initialize to their default states after this VCC level is passed. The PCA8550 is characterized for operation from 0°C to 70°C. ORDERING INFORMATION PACKAGE (1) TA SOIC – D 0°C to 70°C (1) ORDERABLE PART NUMBER Tube of 40 PCA8550D Reel of 2500 PCA8550DR SSOP – DB Reel of 2000 PCA8550DBR TSSOP – PW Reel of 2000 PCA8550PWR TOP-SIDE MARKING PCA8550 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2005, Texas Instruments Incorporated PCA8550 NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE www.ti.com SCPS050C – MARCH 1999 – REVISED MAY 2005 FUNCTION TABLE INPUTS OUTPUTS MUX SELECT OVERRIDE MUX OUT L L L L L H Nonvolatile register Nonvolatile register H X MUX IN Latched NON-MUXED OUT (1) (1) NON-MUXED OUT The latched NON-MUXED OUT state is the value present on the NON-MUXED OUT output at the time the MUX SELECT input transitions from the low to the high state. LOGIC DIAGRAM (POSITIVE LOGIC) VCC SCL I2C Interface Logic 1 2 5-Bit Nonvolatile Register Address: 1001110 SDA VCC VCC 15 WP OVERRIDE 3 1-Bit Transparent Latch VCC 14 MUX IN A MUX IN B MUX IN C MUX IN D 4 12 5 11 MUX OUT A 4-Bit 1-of-2 Multiplexer 6 2 13 10 9 7 VCC MUX SELECT NON-MUXED OUT MUX OUT B MUX OUT C MUX OUT D PCA8550 NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE www.ti.com SCPS050C – MARCH 1999 – REVISED MAY 2005 I2C Interface I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on the serial data (SDA) input/output while the serial clock (SCL) input is high. After the start condition, the device address byte is sent, MSB first, including the data-direction bit (R/W). This device does not respond to the general call address. After receiving the valid address byte, this device responds with an acknowledge, a low on the SDA input/output during the high of the acknowledge-related clock pulse. The data byte follows the address acknowledge. If the R/W bit is high, the data from this device are the values read from the nonvolatile register. If the R/W bit is low, the data are from the master, to be written into the register. A valid data byte is one in which the three high-order bits are low. The first valid data byte that is received is written into the register, following the stop condition. If an invalid data byte is received, it is acknowledged, but is not written into the register. The data byte is followed by an acknowledge sent from this device. If other data bytes are sent from the master, following the acknowledge, they are ignored by this device. A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master. If the WP input is low during the falling edge of the first valid data byte acknowledge on the SCL input and the R/W bit is low, the stop condition causes the I2C interface logic to write the data byte value into the nonvolatile register. Data are written only if complete bytes are received and acknowledged. Writing to the register takes time (twr), during which the device does not respond to its slave address. If the WP input is high, the I2C interface logic does not write to the register. I2C Interface Definition Table BYTE Address Data BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) H L L H H H L R/W L NONMUXED OUT MUX OUT D MUX OUT C MUX OUT B MUX OUT A L L Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 –0.5 2.9 –0.5 VCC + 0.5 SDA (2) VO Output voltage range MUX OUT outputs (2) NON-MUXED OUT output (2) (3) IIK Input clamp current VI < 0 IOK Output clamp current VO < 0 or VO > VCC (3) IIOK Input/output clamp current IO Continuous output current –50 mA –50, +10 mA VO < 0 –50 mA VO = 0 to VCC (3) ±15 mA ±30 mA Continuous current through VCC or GND θJA Tstg (1) (2) (3) (4) Package thermal impedance (4) Storage temperature range V D package 113 DB package 131 PW package 149 –65 85 °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51. 3 PCA8550 NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE www.ti.com SCPS050C – MARCH 1999 – REVISED MAY 2005 Recommended Operating Conditions VCC MIN MAX Supply voltage VIH High-level input voltage VIL Low-level input voltage IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature 3 3.6 2.7 4 2 4 SCL, SDA –0.5 0.9 OVERRIDE, MUX IN, MUX SELECT, WP –0.5 0.8 SCL, SDA OVERRIDE, MUX IN, MUX SELECT, WP MUX OUT, NON-MUXED OUT –2 SDA 6 MUX OUT, NON-MUXED OUT 2 OVERRIDE, MUX IN, MUX SELECT, WP 0 UNIT V V V mA mA 10 ns/V 70 °C MAX UNIT Electrical Characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER VIK Input diode clamp voltage Vhys (1) SCL, SDA MIN II = –18 mA –1.5 IOH = –100 µA MUX OUT NON-MUXED OUT MUX OUT NON-MUXED OUT 2.625 IOH = –1 mA 1.7 2.625 IOH = –100 µA 2.4 3.6 IOH = –2 mA 2 3.6 IOL = 100 µA –0.3 0.4 IOL = 2 mA –0.3 0.7 IOL = 100 µA –0.5 0.4 IOL = 2 mA –0.5 0.7 –1.5 –12 –20 –100 –0.166 –0.75 –7 –32 –86 –267 –0.72 –2 mA 10 mA 500 µA 10 pF VIH = 2.4 V MUX IN SCL, SDA OVERRIDE, MUX SELECT, WP VIL = 0.4 V MUX IN ICC During read or write cycle VI = 0 to VCC, IO = 0, Not during read or write cycle VI = VCC, IO = 0 Ci (1) VCC = 3.3 V VI = VCC or GND Vhys is the hysteresis of Schmitt-trigger inputs. Nonvolatile Storage Specifications PARAMETER 4 V 0.6 SCL, SDA IIL V 0.4 IOL = 6 mA OVERRIDE, MUX SELECT, WP V 2 IOL = 3 mA SDA IIH V 0.19 VOH VOL TEST CONDITIONS SPECIFICATIONS Write time (twr) 10 ms, typical Memory-cell data retention 10 years, minimum Maximum number of memory-cell write cycles 1000 cycles, minimum µA mA µA PCA8550 NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE www.ti.com SCPS050C – MARCH 1999 – REVISED MAY 2005 I2C Interface Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 3.3 V ± 0.3 V MIN MAX 10 400 UNIT fscl I2C clock frequency tsch I2C tscl I2C clock low time tsp I2C spike time tsds I2C tsdh I2C serial data hold time ticr I2C input rise time ticf I2C tocf I2C output fall time (10-pF to 400-pF bus) tbuf I2C bus free time between stop and start 1.3 µs tsts I2C start or repeated start condition setup 600 ns tsth I2C 600 ns tsps I2C stop condition setup Cb (1) I2C bus capacitive load (1) clock high time 600 ns 1.3 µs 0 serial data setup time kHz 50 100 ns ns 0 900 ns 20 300 ns 20 300 ns 20 + 0.1 Cb (1) 250 input fall time start or repeated start condition hold 600 ns ns 400 pF Cb = capacitance of one bus line in pF Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) PARAMETER tmpd Mux input to output propagation delay tsov MUX SELECT to output valid tovn OVERRIDE to NON-MUXED OUT output delay tovm OVERRIDE to MUX OUT output delay VCC = 3.3 V ± 0.3 V FROM (INPUT) TO (OUTPUT) MUX IN MUX OUT 20 ns MUX SELECT Output valid 22 ns OVERRIDE NON-MUXED OUT 15 ns OVERRIDE MUX OUT 25 ns MIN UNIT MAX tsu Setup time WP Falling edge of first valid data byte acknowledge on the SCL input 30 ns th Hold time WP Falling edge of first valid data byte acknowledge on the SCL input 120 ns tr Output rise time 1 3 ns/V tf Output fall time 1 3 ns/V 5 PCA8550 NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE www.ti.com SCPS050C – MARCH 1999 – REVISED MAY 2005 PARAMETER MEASUREMENT INFORMATION VO = 3.3 V RL = 1 kΩ DUT CL = 10 pF or CL = 400 pF GND LOAD CIRCUIT 2 Bytes for Complete Device Programming Stop Condition (P) Start Condition (S) Bit 7 MSB Bit 0 LSB (R/W) Bit 6 Acknowledge (A) Stop Condition (P) 2.7 V 1.5 V WP 1.5 V 0V tsu Tscl th Tsts Tsch 0.7 × VCC SCL 0.3 × VCC ticr tPHL ticf Tbuf Tsp tPLH 0.7 × VCC SDA 0.3 × VCC Ticf Ticr Tsth Tsdh Tsds Tsps Repeat Start Condition Start or Repeat Start Condition VOLTAGE WAVEFORMS BYTE DESCRIPTION 1 I2C 2 Nonvolatile register data address Figure 1. I2C Interface Load Circuit and Voltage Waveforms 6 Stop Condition PCA8550 NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE www.ti.com SCPS050C – MARCH 1999 – REVISED MAY 2005 PARAMETER MEASUREMENT INFORMATION From Output Under Test CL = 15 pF (see Note A) LOAD CIRCUIT 2.7 V Input 1.5 V 1.5 V 2.7 V Input 1.5 V 1.5 V 0V 0V tPHL tPLH Output (see Note D) VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES FOR NON-MUXED OUT OUTPUT NOTES: A. B. C. D. E. tPHL tPLH VOH Output (see Note E) 1.25 V 1.25 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES FOR MUXED OUT OUTPUTS CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. The outputs are measured one at a time, with one transition per measurement. tPLH and tPHL are the same as tsov and tovn. tPLH and tPHL are the same as tmpd, tsov, and tovm. Figure 2. Load Circuit and Voltage Waveforms 7 PACKAGE OPTION ADDENDUM www.ti.com 26-Dec-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) PCA8550D ACTIVE SOIC D 16 TBD Call TI Call TI PCA8550DBR ACTIVE SSOP DB 16 TBD Call TI Call TI PCA8550DBRE4 ACTIVE SSOP DB 16 TBD Call TI Call TI PCA8550DE4 ACTIVE SOIC D 16 TBD Call TI Call TI PCA8550DR ACTIVE SOIC D 16 TBD Call TI Call TI PCA8550DRE4 ACTIVE SOIC D 16 TBD Call TI Call TI PCA8550PWR ACTIVE TSSOP PW 16 TBD Call TI Call TI PCA8550PWRE4 ACTIVE TSSOP PW 16 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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