TI PCA9515AD

PCA9515A
DUAL BIDIRECTIONAL I2C BUS AND SMBus REPEATER
www.ti.com
SCPS150A – DECEMBER 2005 – REVISED JUNE 2006
FEATURES
•
•
•
•
•
•
•
•
•
•
Two-Channel Bidirectional Buffers
I2C Bus and SMBus Compatible
Active-High Repeater-Enable Input
Open-Drain I2C I/O
5.5-V Tolerant I2C I/O and Enable Input
Support Mixed-Mode Signal Operation
Lockup-Free Operation
Accommodates Standard Mode and Fast
Mode I2C Devices and Multiple Masters
Supports Arbitration and Clock Stretching
Across the Repeater
Powered-Off High-Impedance I2C Pins
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
•
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D, DCT, DGK, OR PW PACKAGE
(TOP VIEW)
NC
SCL0
SDA0
GND
1
8
2
7
3
6
4
5
VCC
SCL1
SDA1
EN
NC – No internal connection
DESCRIPTION/ORDERING INFORMATION
This dual bidirectional I2C buffer is operational at 2.3-V to 3.6-V VCC.
The PCA9515A is a BiCMOS integrated circuit intended for I2C bus and SMBus systems applications. The
device contains two identical bidirectional open-drain buffer circuits that enable I2C and similar bus systems to
be extended without degradation of system performance. Both buffers specifically are designed to support the
standard low-level-contention arbitration of the I2C bus and support clock stretching.
The PCA9515A buffers both the serial data (SDA) and serial clock (SCL) signals on the I2C bus, while retaining
all the operating modes and features of the I2C system. This enables two buses of 400-pF bus capacitance to be
connected in an I2C application.
The I2C bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the PCA9515A
enables the system designer to isolate two halves of a bus, accommodating more I2C devices or longer trace
lengths.
ORDERING INFORMATION
PACKAGE (1)
TA
SOIC – D
–40°C to 85°C
SSOP – DCT
TSSOP – PW
VSSOP – DGK
(1)
(2)
ORDERABLE PART NUMBER
Tube of 75
PCA9515AD
Reel of 2500
PCA9515ADR
Reel of 250
PCA9515ADT
Reel of 3000
PCA9515ADCTR
Reel of 250
PCA9515ADCTT
Tube of 150
PCA9515APW
Reel of 2000
PCA9515APWR
Reel of 250
PCA9515APWT
Reel of 2500
PCA9515ADGKR
TOP-SIDE MARKING (2)
PD515A
PREVIEW
PD515A
7B_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DGK: The actual top-side marking has one additional character that designates the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated
PCA9515A
DUAL BIDIRECTIONAL I2C BUS AND SMBus REPEATER
www.ti.com
SCPS150A – DECEMBER 2005 – REVISED JUNE 2006
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The PCA9515A has an active-high enable (EN) input with an internal pullup, which allows the user to select
when the repeater is active. This can be used to isolate a badly behaved slave on power-up reset. It never
should change state during an I2C operation, because disabling during a bus operation hangs the bus, and
enabling part way through a bus cycle could confuse the I2C parts being enabled. The EN input should change
state only when the global bus and the repeater port are in an idle state, to prevent system failures.
The PCA9515A also can be used to run two buses: one at 5-V interface levels and the other at 3.3-V interface
levels, or one at 400-kHz operating frequency and the other at 100-kHz operating frequency. If the two buses
are operating at different frequencies, the 100-kHz bus must be isolated when the 400-kHz operation of the
other bus is required. If the master is running at 400 kHz, the maximum system operating frequency may be less
than 400 kHz, because of the delays that are added by the repeater.
The output low levels for each internal buffer are approximately 0.5 V, but the input voltage of each internal
buffer must be 70 mV or more below the output low level, when the output internally is driven low. This prevents
a lockup condition from occurring when the input low condition is released.
Two or more PCA9515A devices cannot be used in series. The PCA9515A design does not allow this
configuration. Because there is no direction pin, slightly different valid low-voltage levels are used to avoid
lockup conditions between the input and the output of each repeater. A valid low applied at the input of a
PCA9515A is propagated as a buffered low with a slightly higher value on the enabled outputs. When this
buffered low is applied to another PCA9515A-type device in series, the second device does not recognize it as a
valid low and does not propagate it as a buffered low again.
The device contains a power-up control circuit that sets an internal latch to prevent the output circuits from
becoming active until VCC is at a valid level (VCC = 2.3 V).
As with the standard I2C system, pullup resistors are required to provide the logic high levels on the buffered
bus. The PCA9515A has standard open-collector configuration of the I2C bus. The size of these pullup resistors
depends on the system, but each side of the repeater must have a pullup resistor. The device is designed to
work with Standard Mode and Fast Mode I2C devices in addition to SMBus devices. Standard Mode I2C devices
only specify 3 mA in a generic I2C system where Standard Mode devices and multiple masters are possible.
Under certain conditions, high termination currents can be used.
TERMINAL FUNCTIONS
NO.
NAME
DESCRIPTION
1
NC
2
SCL0
No internal connection
Serial clock bus 0
3
SDA0
Serial data bus 0
4
GND
Supply ground
5
EN
6
SDA1
Serial data bus 1
7
SCL1
Serial clock bus 1
8
VCC
Active-high repeater enable input
Supply power
FUNCTION TABLE
2
INPUT
EN
FUNCTION
L
Outputs disabled
H
SDA0 = SDA1,
SCL0 = SCL1
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PCA9515A
DUAL BIDIRECTIONAL I2C BUS AND SMBus REPEATER
www.ti.com
SCPS150A – DECEMBER 2005 – REVISED JUNE 2006
LOGIC DIAGRAM (POSITIVE LOGIC)
VCC
8
PCA9515A
SDA0
SCL0
3
6
2
7
SDA1
SCL1
Pullup
Resistor
EN
5
4
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3
PCA9515A
DUAL BIDIRECTIONAL I2C BUS AND SMBus REPEATER
www.ti.com
SCPS150A – DECEMBER 2005 – REVISED JUNE 2006
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
7
V
VI
Enable input voltage range (2)
–0.5
7
V
VI/O
I2C
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
bus voltage
range (2)
–0.5
Continuous current through VCC or GND
D package
θJA
Package thermal impedance (3)
Tstg
Storage temperature range
(2)
(3)
V
97
DCT package
220
DGK package
172
PW package
(1)
7
UNIT
°C/W
149
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions
VCC
High-level input voltage
VIL (1)
Low-level input voltage
VILc (1)
SDA and SCL low-level input voltage contention
IOL
Low-level output current
TA
Operating free-air temperature
MAX
2.3
3.6
0.7 × VCC
5.5
2
5.5
SDA and SCL inputs
–0.5
0.3 × VCC
EN input
–0.5
0.8
–0.5
0.4
SDA and SCL inputs
VIH
(1)
4
Supply voltage
MIN
EN input
VCC = 2.3 V
6
VCC = 3 V
6
–40
85
UNIT
V
V
V
V
mA
°C
VIL specification is for the EN input and the first low level seen by the SDAx and SCLx lines. VILc is for the second and subsequent low
levels seen by the SDAx and SCLx lines. VILc must be at least 70 mV below VOL.
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PCA9515A
DUAL BIDIRECTIONAL I2C BUS AND SMBus REPEATER
www.ti.com
SCPS150A – DECEMBER 2005 – REVISED JUNE 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
Input diode clamp voltage
II = –18 mA
2.3 V to 3.6 V
2.3 V to 3.6 V
2.3 V to 3.6 V
VOL
Low-level output voltage
SDAx,
IOL = 20 µA or 6 mA
SCLx
VOL – VILc
Low-level input voltage below
low-level output voltage
SDAx,
II = 10 µA
SCLx
ICC
Quiescent supply current
II
V
0.6
V
70
mV
0.52
0.5
3
3.6 V
0.5
3
Both channels low,
SDA0 = SCL0 = GND and
SDA1 = SCL1 = open; or
SDA0 = SCL0 = open and
SDA1 = SCL1 = GND
2.7 V
1
4
3.6 V
1
4
In contention,
SDAx = SCLx = GND
2.7 V
1
4
3.6 V
1
Ioff
Leakage current
II(ramp)
Leakage current during
power up
SDAx,
VI = 3.6 V
SCLx
Cin
Input capacitance
mA
4
±1
3
2.3 V to 3.6 V
µA
±1
VI = 0.2 V
SDAx, VI = 3.6 V
SCLx VI = GND
(1)
UNIT
–1.2
2.7 V
VI = VCC
EN
0.47
MAX
Both channels high,
SDAx = SCLx = VCC
SDAx, VI = 3.6 V
SCLx VI = 0.2 V
Input current
MIN TYP (1)
VCC
–10
–20
0.5
EN = L or H
0V
EN = L or H
0 V to 2.3 V
µA
0.5
µA
1
EN
3.3 V
7
9
SDAx, VI = 3 V or GND
EN = H
SCLx
3.3 V
7
9
pF
All typical values are at nominal supply voltage (VCC = 2.5 V or 3.3 V) and TA = 25°C.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V
MIN
VCC = 3.3 V
± 0.3 V
MAX
MIN
UNIT
MAX
tsu
Setup time, EN↑ before Start condition
100
100
ns
th
Hold time, EN↓ after Stop condition
130
100
ns
Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted)
PARAMETER
tPZL
tPLZ
ttHL
ttLH
(1)
(2)
Propagation delay time (2)
Output transition time (2)
(SDAx, SCLx)
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
SDA0, SCL0 or
SDA1, SCL1
SDA1, SCL1 or
SDA0, SCL0
80%
20%
57
58
20%
80%
148
147
TYP (1)
MAX
MIN
45
82
130
33
113
190
MIN
TYP (1)
MAX
45
68
120
33
102
180
UNIT
ns
ns
All typical values are at nominal supply voltage (VCC = 2.5 V or 3.3 V) and TA = 25°C.
Different load resistance and capacitance alter the RC time constant, thereby changing the propagation delay and transition times.
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5
PCA9515A
DUAL BIDIRECTIONAL I2C BUS AND SMBus REPEATER
www.ti.com
SCPS150A – DECEMBER 2005 – REVISED JUNE 2006
PARAMETER MEASUREMENT INFORMATION
VCC
VIN
VCC
VOUT
PULSE
GENERATOR
RL = 1.35 kΩ
S1
DUT
GND
CL = 50 pF
(see Note B)
RT
(see Note A)
TEST
S1
tPLZ/tPZL
VCC
TEST CIRCUIT FOR OPEN-DRAIN OUTPUT
Input
VCC
1.5 V
1.5 V
0V
tPZL
Output
tPLZ
80%
1.5 V
1.5 V
20%
20%
80%
ttHL
VCC
VOL
ttLH
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
A.
RT termination resistance should be equal to ZOUT of pulse generators.
B.
CL includes probe and jig capacitance.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
slew rate ≥ 1 V/ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
tPLH and tPHL are the same as tpd.
F.
tPLZ and tPHZ are the same as tdis.
G.
tPZL and tPZH are the same as ten.
Figure 1. Test Circuit and Voltage Waveforms
6
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PCA9515A
DUAL BIDIRECTIONAL I2C BUS AND SMBus REPEATER
www.ti.com
SCPS150A – DECEMBER 2005 – REVISED JUNE 2006
APPLICATION INFORMATION
A typical application is shown in Figure 2. In this example, the system master is running on a 3.3-V bus, while
the slave is connected to a 5-V bus. Both buses run at 100 kHz, unless the slave bus is isolated, and then the
master bus can run at 400 kHz. Master devices can be placed on either bus.
3.3 V
5V
SDA
SDA0
SDA1
SDA
SCL
SCL0
SCL1
SCL
PCA9515A
I2C BUS MASTER
400 kHz
I2C BUS SLAVE
100 kHz
EN
BUS 0
BUS 1
Figure 2. Typical Application
The PCA9515A is 5.5-V tolerant, so it does not require any additional circuitry to translate between the different
bus voltages.
When one side of the PCA9515A is pulled low by a device on the I2C bus, a CMOS hysteresis-type input detects
the falling edge and causes an internal driver on the other side to turn on, thus causing the other side also to go
low. The side driven low by the PCA9515A typically is at VOL = 0.5 V.
Figure 3 and Figure 4 show the waveforms that are seen in a typical application. If the bus master in Figure 2
writes to the slave through the PCA9515A, Bus 0 has the waveform shown in Figure 3. This looks like a normal
I2C transmission until the falling edge of the eighth clock pulse. At that point, the master releases the data line
(SDA) while the slave pulls it low through the PCA9515A. Because the VOL of the PCA9515A typically is around
0.5 V, a step in the SDA is seen. After the master has transmitted the ninth clock pulse, the slave releases the
data line.
9th Clock Pulse
SCL
SDA
VOL of Master
VOL of PCA9515A
Figure 3. Bus 0 Waveforms
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PCA9515A
DUAL BIDIRECTIONAL I2C BUS AND SMBus REPEATER
www.ti.com
SCPS150A – DECEMBER 2005 – REVISED JUNE 2006
APPLICATION INFORMATION (continued)
9th Clock Pulse
SCL
SDA
VOL of PCA9515A
VOL of Slave
Figure 4. Bus 1 Waveforms
On the Bus 1 side of the PCA9515A, the clock and data lines have a positive offset from ground equal to the
VOL of the PCA9515A. After the eighth clock pulse, the data line is pulled to the VOL of the slave device, which is
very close to ground in the example.
It is important to note that any arbitration or clock-stretching events on Bus 1 require that the VOL of the devices
on Bus 1 be 70 mV below the VOL of the PCA9515A (see VOL – VILc in Electrical Characteristics) to be
recognized by the PCA9515A and transmitted to Bus 0.
8
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
PCA9515AD
ACTIVE
SOIC
D
8
PCA9515ADGKR
ACTIVE
MSOP
DGK
PCA9515ADGKRG4
ACTIVE
MSOP
PCA9515ADR
ACTIVE
PCA9515ADT
75
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
SOIC
D
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9515APW
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9515APWR
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PCA9515APWT
ACTIVE
TSSOP
PW
8
250
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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