PI74LPT16501 18-BIT REGISTERED TRANSCEIVERS 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74LPT16501 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Fast CMOS 18-Bit Registered Transceivers 1 2 Product Features Product Description • Compatible with LCX™ and LVT™ families of products • Supports 5V Tolerant Mixed Signal Mode Operation – Input can be 3V or 5V – Output can be 3V or connected to 5V bus • Advanced Low Power CMOS Operation • Excellent output drive capability: Balanced drives (24 mA sink and source) • Pin compatible with industry standard double-density pinouts • Low ground bounce outputs • Hysteresis on all inputs • Industrial operating temperature range: –40°C to +85°C • Multiple center pins and distributed Vcc/GND pins minimize switching noise • Packages available: – 56-pin 240 mil wide plastic TSSOP (A) – 56-pin 300 mil wide plastic SSOP (V) Pericom Semiconductor’s PI74LPT series of logic circuits are produced in the Company’s advanced 0.6 micron CMOS technology, achieving industry leading speed grades. The PI74LPT16501 is an 18-bit registered bus transceiver designed with D-type latches and flip-flops to allow data flow in transparent, latched, and clocked modes. The Output Enable (OEAB and OEBA, Latch Enable (LEAB and LEBA) and Clock (CLKAB and CLKBA) inputs control the data flow in each direction. When LEAB is HIGH, the device operates in transparent mode for A-toB data flow. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. The A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB, if LEAB is LOW. OEAB performs the output enable function on the B port. Data flow from B port to A port is similar using OEBA, LEBA and CLKBA. This high-speed, low power device offers a flow-through organization for ease of board layout. The PI74LPT16501 can be driven from either 3.3V or 5.0V devices allowing this device to be used as a translator in a mixed 3.3V/5.0V system. 3 4 5 6 7 8 Logic Block Diagram 9 OEAB CLKBA 10 LEBA OEBA 11 CLKAB 12 LEAB C C D D B1 A1 C C D D 13 14 15 TO 17 OTHER CHANNELS 1 PS2071A 01/16/97 PI74LPT16501 18-BIT REGISTERED TRANSCEIVERS 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Truth Table(1,4) Product Pin Description Pin Name OEAB OEBA LEAB LEBA CLKAB CLKBA Ax Bx GND VCC Description A-to-B Output Enable Input B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs or B-to-A 3-State Outputs B-to-A Data Inputs or A-to-B 3-State Outputs Ground Power OEAB L H H H H H H LEAB A0 GND A1 1 2 3 4 5 6 56 GND 55 54 53 52 CLKAB B0 GND B1 51 50 49 48 B2 47 46 45 44 43 42 B5 41 40 39 B10 38 37 36 35 34 B12 33 B16 32 31 30 GND OEBA 25 26 27 LEBA 28 29 GND A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND A12 A13 A14 VCC A15 A16 GND A17 7 8 9 10 11 56-PIN 12 V56 13 A56 14 15 16 17 18 19 20 21 22 23 24 Ax X L H L H X X Outputs Bx Z L H L H B(2) B(3) Notes: 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA. 2. Output level before the indicated steady-state input conditions were established. 3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. 4. H = High Voltage Level L = Low Voltage Level Z = High Impedance ↑ = LOW-to-HIGH Transition Product Pin Configuration OEAB Inputs LEAB CLKAB X X H X H X L ↑ L ↑ L L L H VCC B3 B4 GND B6 B7 B8 B9 B11 GND B13 B14 VCC B15 B17 CLKBA 2 PS2071A 01/16/97 PI74LPT16501 18-BIT REGISTERED TRANSCEIVERS 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ............................................................. –55°C to +125°C Ambient Temperature with Power Applied ............................ –40°C to +85°C Supply Voltage to Ground Potential (Inputs & Vcc Only) ...... –0.5V to +7.0V Supply Voltage to Ground Potential (Outputs & D/O Only) .. –0.5V to +7.0V DC Input Voltage .................................................................... –0.5V to +7.0V DC Output Current .............................................................................. 120 mA Power Dissipation .................................................................................... 1.0W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. VIH IOZH IOZL VIK IODH IODL VOH Input HIGH Voltage (Input pins) Input HIGH Voltage (I/O pins) Input LOW Voltage (Input and I/O pins) Input HIGH Current (Input pins) Input HIGH Current (I/O pins) Input LOW Current (Input pins) Input LOW Current (I/O pins) High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Output HIGH Current Output LOW Current Output HIGH Voltage VOL Output LOW Voltage IOS IOFF VH Short Circuit Current(4) Power Down Disable Input Hysteresis VIL IIH IIL Test Conditions(1) Description Guaranteed Logic HIGH Level Guaranteed Logic LOW Level Min. Typ(2) Max. Units 2.2 2.0 –0.5 — — — 5.5 5.5 0.8 V V V — — — — — — –0.7 –60 90 — 3.0 3.0 — — 0.2 0.3 –85 — 150 ±1 ±1 ±1 ±1 ±1 ±1 –1.2 –110 200 — — — — 0.2 0.4 0.5 –240 ±100 — µA µA µA µA µA µA V mA mA V V V VCC = Max. VIN = 5.5V — VCC = Max. VIN = VCC — VCC = Max. VIN = GND — VCC = Max. VIN = GND — VCC = Max. VOUT = 5.5V — VCC = Max. VOUT = GND — VCC = Min., IIN = –18 mA — VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) –36 VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3) 50 VCC = Min. IOH = –0.1 mA Vcc-0.2 VIN = VIH or VIL IOH = –3 mA 2.4 VCC = 3.0V, IOH = –8 mA 2.4(5) VIN = VIH or VIL IOH = –24 mA 2.0 VCC = Min. IOL = 0.1 mA — VIN = VIH or VIL IOL = 16 mA — IOL = 24 mA — VCC = Max.(3), VOUT = GND –60 VCC = 0V, VIN or VOUT ≤ 4.5V — — 2 3 4 DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 2.7V to 3.6V) Parameters 1 V V V mA µA mV Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, +25°C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC – 0.6V at rated current. 5 6 7 8 9 10 11 12 13 14 15 3 PS2071A 01/16/97 PI74LPT16501 18-BIT REGISTERED TRANSCEIVERS 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Power Supply Characteristics Parameters Description Test Conditions(1) Min. Typ(2) Max. Units ICC Quiescent Power Supply Current VCC = Max. VIN = GND or VCC 0.1 10 µA ∆ICC Quiescent Power Supply Current TTL Inputs HIGH VCC = Max. VIN = VCC – 0.6V(3) 2.0 30 µA ICCD Dynamic Power Supply(4) VCC = Max., Outputs Open XOE = GND One Bit Toggling 50% Duty Cycle VIN = VCC VIN = GND 50 75 µA/ MHz IC Total Power Supply Current(6) VCC = Max., Outputs Open fI = 10 MHZ 50% Duty Cycle XOE = GND One Bit Toggling VIN = VCC – 0.6V VIN = GND 0.6 2.3 mA VCC = Max., Outputs Open fI = 2.5 MHZ 50% Duty Cycle XOE = GND 16 Bits Toggling VIN = VCC – 0.6V VIN = GND 2.1 4.7(5) Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at Vcc = 3.3V, +25°C ambient. 3. Per TTL driven input; all other inputs at Vcc or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested. 6. IC =IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fI = Input Frequency NI = Number of Inputs at fI All currents are in milliamps and all frequencies are in megahertz. 4 PS2071A 01/16/97 PI74LPT16501 18-BIT REGISTERED TRANSCEIVERS 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74LPT16501 Switching Characteristics over Operating Range(1) Parameters Description 1 LPT16501 LPT16501A LPT16501C Com. Com. Com. Preliminary Conditions(2) Min(3) Max Min(3) Max Min(3) Max Unit 2 tMAX CLKAB or CLKBA frequency CL = 50 pF — 100 — 150 — 150 MHz tPLH tPHL Propagation Delay AX to BX or AX to BX RL = 500 Ω 1.5 6.5 1.5 5.1 1.5 4.6 ns tPLH tPHL Propagation Delay LEBA to AX, LEAB to BX 1.5 7.5 1.5 5.6 1.5 5.3 ns tPLH tPHL Propagation Delay CLKBA to AX, CLKAB to BX 1.5 8.0 1.5 5.6 1.5 5.3 ns tPZH tPZL Output Enable Time OEBA to AX, OEAB to BX 1.5 8.0 1.5 6.0 1.5 5.6 ns 4 tPHZ tPLZ Output Disable Time(4) OEBA to AX, OEAB to BX 1.5 7.5 1.5 5.6 1.5 5.2 ns 5 tSU Setup Time HIGH or LOW Ax to CLKAB, Bx to CLKBA 4.0 — 3.0 — 3.0 — ns tH Hold Time HIGH or LOW Ax to CLKAB, Bx to CLKBA 0 — 0 — 0 — ns tSU Setup Time HIGH or LOW Ax to LEAB, Bx to LEBA Clock HIGH 4.0 — 3.0 — 3.0 — ns Clock LOW 1.5 — 1.5 — 1.5 — ns 7 8 tH Hold Time HIGH or LOW Ax to LEAB, Bx to LEBA 1.5 — 1.5 — 1.5 — ns tW LEAB or LEBA Pulse Width HIGH(4) 3.0 — 3.0 — 3.0 — ns tW CLKAB or CLKBA Pulse Width HIGH or LOW(4) 3.0 — 3.0 — 3.0 — ns tSK(O) Output Skew(5) — 0.5 — 0.5 — 0.5 ns 3 6 9 10 Notes: 1. Propagation Delays and Enable/Disable times are with Vcc = 3.3V ±0.3V, normal range. For Vcc = 2.7V, extended range, all Propagation Delays and Enable/Disable times should be degraded by 20%. 2. See test circuit and waveforms. 3. Minimum limits are guaranteed but not tested on Propagation Delays. 4. This parameter is guaranteed but not production tested. 5. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design. Capacitance (TA = 25°C, f = 1 MHz) Parameters(1) CIN COUT Description Test Conditions Input Capacitance Output Capacitance VIN = 0V VOUT = 0V Typ. Max. Units 4.5 5.5 6 8 pF pF Note: 1. This parameter is determined by device characterization but is not production tested. Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 5 PS2071A 01/16/97 11 12 13 14 15