ETC PIC16C65B/JW

M
PIC16C63A/65B/73B/74B
28/40-Pin 8-Bit CMOS Microcontrollers
Pins
A/D
PSP
PIC16C63A
PIC16C73B
28
NO
NO
28
YES
NO
PIC16C65B
40
NO
YES
PIC16C74B
40
YES
YES
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 4K x 14 words of Program Memory,
192 x 8 bytes of Data Memory (RAM)
• Interrupt capability (up to 12 internal/external
interrupt sources)
• Eight level deep hardware stack
• Direct, indirect, and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS EPROM
technology
• Fully static design
• In-Circuit Serial Programming™ (ICSP)
• Wide operating voltage range: 2.5V to 5.5V
• High Sink/Source Current 25/25 mA
• Commercial, Industrial and Extended temperature
ranges
• Low-power consumption:
- < 2 mA @ 5V, 4 MHz
- 22.5 µA typical @ 3V, 32 kHz
- < 1 µA typical standby current
 1998 Microchip Technology Inc.
Pin Diagram
PDIP, Windowed CERDIP
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC16C74B
Device
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Two Capture, Compare, PWM modules
• Capture is 16-bit, max. resolution is 12.5 ns,
Compare is 16-bit, max. resolution is 200 ns,
PWM maximum resolution is 10-bit
• 8-bit multi-channel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with Enhanced
SPI and I2C
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
• Parallel Slave Port (PSP) 8-bits wide, with
external RD, WR and CS controls
• Brown-out detection circuitry for
Brown-out Reset (BOR)
DS30605A-page 1
PIC16C63A/65B/73B/74B
Pin Diagrams
SDIP, SOIC, SSOP, Windowed CERDIP
MCLR/VPP
SDIP, SOIC, SSOP, Windowed CERDIP
•1
28
RB7
MCLR/VPP
•1
28
RB7
RA0/AN0
2
27
RB6
RA0
2
27
RB6
RA1/AN1
3
26
RB5
RA1
3
26
RB5
RA2/AN2
4
25
RB4
RA2
4
25
RB4
RA3/AN3/VREF
5
24
RB3
RA3
5
24
RB3
RA4/T0CKI
6
23
RB2
RA4/T0CKI
6
23
RB2
RA5/SS/AN4
VSS
7
8
22
21
RB1
RB0/INT
RA5/SS
VSS
7
8
22
21
RB1
RB0/INT
OSC1/CLKIN
9
20
VDD
OSC1/CLKIN
9
20
VDD
OSC2/CLKOUT
10
19
VSS
OSC2/CLKOUT
10
19
VSS
RC0/T1OSO/T1CKI
11
18
RC7/RX/DT
RC0/T1OSO/T1CKI
11
18
RC7/RX/DT
RC1/T1OSI/CCP2
12
17
RC6/TX/CK
RC1/T1OSI/CCP2
12
17
RC6/TX/CK
RC2/CCP1
13
16
RC5/SDO
RC2/CCP1
13
16
RC5/SDO
RC3/SCK/SCL
14
15
RC4/SDI/SDA
RC3/SCK/SCL
14
15
RC4/SDI/SDA
PIC16C63A
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3
44
43
42
41
40
39
38
37
36
35
34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
11
PIC16C65B
33
32
31
30
29
28
27
26
25
24
23
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
VDD
RE2/CS
RE1/WR
RE0/RD
RA5/SS
RA4/T0CKI
NC
NC
RB4
RB5
RB6
RB7
MCLR/VPP
RA0
RA1
RA2
RA3
MCLR/VPP
RA0
RA1
RA2
RA3
RA4/T0CKI
RA5/SS
RE0/RD
RE1/WR
RE2/CS
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
MQFP
TQFP
12
13
14
15
16
17
18
19
20
21
22
PDIP, Windowed CERDIP
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
NC
PIC16C73B
RA3
RA2
RA1
RA0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
PIC16C65B
6
5
4
3
2
1
44
43
42
41
40
PLCC
7
8
9
10
11
12
13
14
15
16
17
PIC16C65B
39
38
37
36
35
34
33
32
31
30
29
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
NC
18
19
20
21
22
23
24
25
26
27
28
RA4/T0CKI
RA5/SS
RE0/RD
RE1/WR
RE2/CS
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
NC
DS30605A-page 2
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
MQFP
TQFP
PIC16C74B
39
38
37
36
35
34
33
32
31
30
29
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3
1
2
3
4
5
6
7
8
9
10
11
PIC16C74B
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/SS/AN4
RA4/T0CKI
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
7
8
9
10
11
12
13
14
15
16
17
NC
NC
RB4
RB5
RB6
RB7
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
NC
18
19
20
21
22
23
24
25
26
27
28
RA4/T0CKI
RA5/SS/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
NC
44
43
42
41
40
39
38
37
36
35
34
6
5
4
3
2
1
44
43
42
41
40
PLCC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
NC
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
Pin Diagrams (Cont.’d)
Key Features
PICmicro Mid-Range Reference Manual
(DS33023)
PIC16C63A
PIC16C65B
PIC16C73B
PIC16C74B
Operating Frequency
DC - 20 MHz
DC - 20 MHz
DC - 20 MHz
DC - 20 MHz
Resets (and Delays)
POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
Program Memory (14-bit words)
4K
4K
4K
4K
Data Memory (bytes)
192
192
192
192
Interrupts
10
11
11
12
I/O Ports
Ports A,B,C
Ports A,B,C,D,E Ports A,B,C
Ports A,B,C,D,E
Timers
3
3
3
3
Capture/Compare/PWM modules
2
2
2
2
Serial Communications
SSP, USART
SSP, USART
SSP, USART
Parallel Communications
8-bit Analog-to-Digital Module
Instruction Set
 1998 Microchip Technology Inc.
—
—
35 Instructions
PSP
—
—
35 Instructions
SSP, USART
PSP
5 input channels 8 input channels
35 Instructions
35 Instructions
DS30605A-page 3
PIC16C63A/65B/73B/74B
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Memory Organization................................................................................................................................................................. 11
3.0 I/O Ports ..................................................................................................................................................................................... 25
4.0 Timer0 Module ........................................................................................................................................................................... 37
5.0 Timer1 Module ........................................................................................................................................................................... 39
6.0 Timer2 Module ........................................................................................................................................................................... 43
7.0 Capture/Compare/PWM (CCP) Module(s)................................................................................................................................. 45
8.0 Synchronous Serial Port (SSP) Module ..................................................................................................................................... 51
9.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) .................................................................................... 61
10.0 Analog-to-Digital Converter (A/D) Module.................................................................................................................................. 75
11.0 Special Features of the CPU...................................................................................................................................................... 81
12.0 Instruction Set Summary............................................................................................................................................................ 95
13.0 Development Support ................................................................................................................................................................ 97
14.0 Electrical Characteristics.......................................................................................................................................................... 101
15.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 123
16.0 Packaging Information ............................................................................................................................................................. 125
Appendix A: Revision History ........................................................................................................................................................... 137
Appendix B: Device Differences ....................................................................................................................................................... 137
Appendix C: Conversion Considerations .......................................................................................................................................... 137
Appendix D: Migration from Baseline to Midrange Devices.............................................................................................................. 138
Appendix E: Bit/Register Cross-Reference List ................................................................................................................................ 139
Index .................................................................................................................................................................................................. 141
On-Line Support................................................................................................................................................................................. 147
Reader Response .............................................................................................................................................................................. 148
PIC16C63A/65B/73B/74B Product Identification System .................................................................................................................. 149
To Our Valued Customers
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please check our worldwide web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number, found on the bottom outside corner
of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.
Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The
errata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s worldwide web site at http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet
(include literature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time
to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any
information that is missing or appears in error, please:
• Fill out and mail in the reader response form in the back of this data sheet, or
• E-mail us at [email protected].
We appreciate your assistance in making this a better document.
DS30605A-page 4
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
1.0
DEVICE OVERVIEW
There are four devices (PIC16C63A, PIC16C65B,
PIC16C73B, PIC16C74B) covered by this data sheet.
These devices come in 28- and 40-pin packages. The
28-pin devices do not have a Parallel Slave Port implemented. The PIC16C6X devices do not have the A/D
module implemented.
This document contains device-specific information.
Additional information may be found in the PICmicro
Mid-Range Reference Manual (DS33023) which may
be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The
Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
FIGURE 1-1:
The following two figures are device block diagrams
sorted by pin number; 28-pin for Figure 1-1 and 40-pin
for Figure 1-2. The 28-pin and 40-pin pinouts are listed
in Table 1-1 and Table 1-2 respectively.
PIC16C63A/PIC16C73B BLOCK DIAGRAM
13
8
Data Bus
Program Counter
PORTA
RA0/AN0(2)
RA1/AN1(2)
RA2/AN2(2)
RA3/AN3/VREF(2)
RA4/T0CKI
RA5/SS/AN4(2)
EPROM
4K x 14
Program
Memory
Program
Bus
RAM
192 x 8
File
Registers
8 Level Stack
(13-bit)
14
RAM Addr(1)
PORTB
9
Addr MUX
Instruction reg
7
Direct Addr
8
RB0/INT
Indirect
Addr
RB7:RB1
FSR reg
STATUS reg
8
3
MUX
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
MCLR
ALU
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
8
W reg
VDD, VSS
Timer0
Timer1
Timer2
A/D(2)
CCP1
CCP2
Synchronous
Serial Port
USART
Note 1: Higher order bits are from the STATUS register.
2: The A/D module is not available on the PIC16C63A.
 1998 Microchip Technology Inc.
DS30605A-page 5
PIC16C63A/65B/73B/74B
FIGURE 1-2:
PIC16C65B/PIC16C74B BLOCK DIAGRAM
13
4K x 14
Program
Bus
14
PORTA
RA0/AN0(2)
RA1/AN1(2)
RA2/AN2(2)
RA3/AN3/VREF(2)
RA4/T0CKI
RA5/SS/AN4(2)
RAM
8 Level Stack
(13-bit)
Program
Memory
8
Data Bus
Program Counter
EPROM
192 x 8
File
Registers
RAM Addr (1)
PORTB
9
Addr MUX
Instruction reg
Direct Addr
7
8
RB0/INT
Indirect
Addr
RB7:RB1
FSR reg
STATUS reg
8
3
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
Watchdog
Timer
Brown-out
Reset
ALU
PORTD
8
W reg
RD7/PSP7:RD0/PSP0
Parallel Slave Port
MCLR
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
MUX
Oscillator
Start-up Timer
Power-on
Reset
PORTC
VDD, VSS
PORTE
RE0/RD/AN5(2)
RE1/WR/AN6(2)
Timer0
Timer1
Timer2
A/D(2)
CCP1
CCP2
Synchronous
Serial Port
USART
RE2/CS/AN7(2)
Note 1: Higher order bits are from the STATUS register.
2: The A/D module is not available on the PIC16C65B.
DS30605A-page 6
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 1-1:
Pin Name
PIC16C63A/PIC16C73B PINOUT DESCRIPTION
DIP
Pin#
SOIC
Pin#
I/O/P
Type
Buffer
Type
Description
ST/CMOS(3) Oscillator crystal input/external clock source input.
OSC1/CLKIN
9
9
I
OSC2/CLKOUT
10
10
O
—
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
MCLR/VPP
1
1
I/P
ST
Master clear (reset) input or programming voltage input. This
pin is an active low reset to the device.
RA0/AN0(4)
2
2
I/O
TTL
RA0 can also be analog input0
RA1/AN1(4)
3
3
I/O
TTL
RA1 can also be analog input1
RA2/AN2(4)
4
4
I/O
TTL
RA2 can also be analog input2
RA3/AN3/VREF(4)
RA4/T0CKI
5
5
I/O
TTL
RA3 can also be analog input3 or analog reference voltage
6
6
I/O
ST
RA5/SS/AN4(4)
7
7
I/O
TTL
RA4 can also be the clock input to the Timer0 module.
Output is open drain type.
RA5 can also be analog input4 or the slave select for the
synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
PORTA is a bi-directional I/O port.
RB0/INT
21
21
I/O
TTL/ST(1)
RB1
RB2
22
23
22
23
I/O
I/O
TTL
TTL
RB3
RB4
RB5
24
25
26
24
25
26
I/O
I/O
I/O
TTL
TTL
TTL
RB6
RB7
27
28
27
28
I/O
I/O
TTL/ST(2)
TTL/ST(2)
RC0/T1OSO/T1CKI
11
11
I/O
ST
RC1/T1OSI/CCP2
12
12
I/O
ST
RC2/CCP1
13
13
I/O
ST
RC3/SCK/SCL
14
14
I/O
ST
RB0 can also be the external interrupt pin.
Interrupt on change pin.
Interrupt on change pin.
Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.
PORTC is a bi-directional I/O port.
RC0 can also be the Timer1 oscillator output or Timer1
clock input.
RC1 can also be the Timer1 oscillator input or Capture2
input/Compare2 output/PWM2 output.
RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3 can also be the synchronous serial clock input/output
for both SPI and I2C modes.
RC4/SDI/SDA
15
15
I/O
ST
RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO
16
16
I/O
ST
RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK
17
17
I/O
ST
RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
18
18
I/O
ST
RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
VSS
8, 19
8, 19
P
—
Ground reference for logic and I/O pins.
VDD
20
20
P
—
Positive supply for logic and I/O pins.
Legend: I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
4: The A/D module is not available on the PIC16C63A.
 1998 Microchip Technology Inc.
DS30605A-page 7
PIC16C63A/65B/73B/74B
TABLE 1-2:
Pin Name
PIC16C65B/PIC16C74B PINOUT DESCRIPTION
DIP
Pin#
PLCC
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
Description
OSC1/CLKIN
13
14
30
I
ST/CMOS(4)
OSC2/CLKOUT
14
15
31
O
—
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
MCLR/VPP
1
2
18
I/P
ST
Master clear (reset) input or programming voltage input.
This pin is an active low reset to the device.
RA0/AN0(5)
2
3
19
I/O
TTL
RA0 can also be analog input0
RA1/AN1(5)
3
4
20
I/O
TTL
RA1 can also be analog input1
RA2/AN2(5)
4
5
21
I/O
TTL
RA2 can also be analog input2
RA3/AN3/VREF(5)
5
6
22
I/O
TTL
RA3 can also be analog input3 or analog reference
voltage
RA4/T0CKI
6
7
23
I/O
ST
RA4 can also be the clock input to the Timer0 timer/
counter. Output is open drain type.
RA5/SS/AN4(5)
7
8
24
I/O
TTL
RA5 can also be analog input4 or the slave select for
the synchronous serial port.
Oscillator crystal input/external clock source input.
PORTA is a bi-directional I/O port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT
33
36
8
I/O
TTL/ST(1)
RB1
34
37
9
I/O
TTL
RB2
35
38
10
I/O
TTL
RB3
36
39
11
I/O
TTL
RB4
37
41
14
I/O
TTL
RB5
38
42
15
I/O
TTL
RB6
39
43
16
I/O
TTL/ST(2)
RB0 can also be the external interrupt pin.
Interrupt on change pin.
Interrupt on change pin.
Interrupt on change pin. Serial programming clock.
40
44
17
I/O
TTL/ST(2)
Interrupt on change pin. Serial programming data.
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as an external interrupt.
This buffer is a Schmitt Trigger input when used in serial programming mode.
This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
The A/D module is not available on the PIC16C65B.
RB7
Legend: I = input
Note 1:
2:
3:
4:
5:
DS30605A-page 8
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 1-2:
PIC16C65B/PIC16C74B PINOUT DESCRIPTION (Cont.’d)
DIP
Pin#
PLCC
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
RC0/T1OSO/T1CKI
15
16
32
I/O
ST
RC0 can also be the Timer1 oscillator output or a
Timer1 clock input.
RC1/T1OSI/CCP2
16
18
35
I/O
ST
RC1 can also be the Timer1 oscillator input or
Capture2 input/Compare2 output/PWM2 output.
RC2/CCP1
17
19
36
I/O
ST
RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL
18
20
37
I/O
ST
RC3 can also be the synchronous serial clock input/
output for both SPI and I2C modes.
RC4/SDI/SDA
23
25
42
I/O
ST
RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO
24
26
43
I/O
ST
RC5 can also be the SPI Data Out
(SPI mode).
RC6/TX/CK
25
27
44
I/O
ST
RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
26
29
1
I/O
ST
RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
Pin Name
Description
PORTC is a bi-directional I/O port.
PORTD is a bi-directional I/O port or parallel slave port
when interfacing to a microprocessor bus.
RD0/PSP0
RD1/PSP1
RD2/PSP2
19
20
21
21
22
23
38
39
40
I/O
I/O
I/O
ST/TTL(3)
RD3/PSP3
RD4/PSP4
RD5/PSP5
22
27
28
24
30
31
41
2
3
I/O
I/O
I/O
ST/TTL(3)
ST/TTL(3)
ST/TTL(3)
RD6/PSP6
RD7/PSP7
29
30
32
33
4
5
I/O
I/O
ST/TTL(3)
ST/TTL(3)
RE0/RD/AN5(5)
8
9
25
I/O
ST/TTL(3)
RE0 can also be read control for the parallel slave port,
or analog input5.
RE1/WR/AN6(5)
9
10
26
I/O
ST/TTL(3)
RE1 can also be write control for the parallel slave port,
or analog input6.
RE2/CS/AN7(5)
10
11
27
I/O
ST/TTL(3)
RE2 can also be select control for the parallel slave
port, or analog input7.
ST/TTL(3)
ST/TTL(3)
PORTE is a bi-directional I/O port.
VSS
VDD
NC
12,31
11,32
—
Legend:
Note 1:
2:
3:
4:
5:
13,34
6,29
P
—
Ground reference for logic and I/O pins.
12,35
7,28
P
—
Positive supply for logic and I/O pins.
1,17,28, 12,13,
—
These pins are not internally connected. These pins should
40
33,34
be left unconnected.
I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as an external interrupt.
This buffer is a Schmitt Trigger input when used in serial programming mode.
This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
The A/D module is not available on the PIC16C65B.
 1998 Microchip Technology Inc.
DS30605A-page 9
PIC16C63A/65B/73B/74B
NOTES:
DS30605A-page 10
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
2.0
MEMORY ORGANIZATION
There are two memory blocks in each of these PICmicro
microcontrollers. Each block (Program Memory and
Data Memory) has its own bus so that concurrent
access can occur.
Additional information on device memory may be found
in the PICmicro Mid-Range Reference Manual
(DS33023).
Program Memory Organization
2.1
The PIC16C63A/65B/73B/74B microcontrollers have a
13-bit program counter capable of addressing an 8K x
14 program memory space. Each device has 4K x 14
words of program memory. Accessing a location above
the physically implemented address will cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK
2.2
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
RP1(1)
RP0
= 00 →
= 01 →
= 10 →
= 11 →
Bank0
Bank1
Bank2 (not implemented)
Bank3 (not implemented)
CALL, RETURN
RETFIE, RETLW
(STATUS<6:5>)
Note 1: Maintain this bit clear to ensure upward compatibility with future products.
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as
static RAM. All implemented banks contain special
function registers. Some “high use” special function
registers from one bank may be mirrored in another
bank for code reduction and quicker access.
2.2.1
PC<12:0>
Data Memory Organization
GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indirectly through the File Select Register FSR
(Section 2.5).
13
Stack Level 1
User Memory
Space
Stack Level 8
Reset Vector
0000h
Interrupt Vector
0004h
0005h
On-chip Program
Memory (Page 0)
07FFh
On-chip Program
Memory (Page 1)
0800h
0FFFh
1000h
1FFFh
 1998 Microchip Technology Inc.
DS30605A-page 11
PIC16C63A/65B/73B/74B
FIGURE 2-2:
REGISTER FILE MAP
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
2.2.2
File
Address
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD(2)
PORTE(2)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES(3)
ADCON0(3)
INDF(1)
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD(2)
TRISE(2)
PCLATH
INTCON
PIE1
PIE2
PCON
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
ADCON1(3)
General
Purpose
Register
General
Purpose
Register
Bank 0
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
give in Table 2-1.
The special function registers can be classified into two
sets; core (CPU) and peripheral. Those registers associated with the core functions are described in detail in
this section. Those related to the operation of the
peripheral features are described in detail in that
peripheral feature section.
FFh
7Fh
Unimplemented data memory locations, read
as ’0’.
Note 1: Not a physical register.
2: These registers are not implemented on the
PIC16C63A/73B, read as '0'.
3: These registers are not implemented on the
PIC16C63A/65B, read as '0'.
DS30605A-page 12
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 2-1
Addr
SPECIAL FUNCTION REGISTER SUMMARY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other resets
(5)
Bank 0
00h
INDF(1)
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
01h
TMR0
Timer0 module’s register
xxxx xxxx uuuu uuuu
02h
PCL(1)
Program Counter's (PC) Least Significant Byte
03h
STATUS(1)
04h
FSR(1)
05h
PORTA(7)
06h
PORTB(8)
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
07h
PORTC(8)
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx uuuu uuuu
08h
PORTD(3,8)
PORTD Data Latch when written: PORTD pins when read
09h
PORTE(3,8)
—
—
—
0Ah
PCLATH(1,2)
—
—
—
IRP(6)
RP1(6)
RP0
TO
0000 0000 0000 0000
PD
Z
DC
C
Indirect data memory address pointer
—
—
rr01 1xxx rr0q quuu
xxxx xxxx uuuu uuuu
PORTA Data Latch when written: PORTA pins when read
—
—
--0x 0000 --0u 0000
xxxx xxxx uuuu uuuu
RE2
RE1
RE0
Write Buffer for the upper 5 bits of the Program Counter
---- -xxx ---- -uuu
---0 0000 ---0 0000
0Bh
INTCON(1)
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
PSPIF(3)
ADIF(4)
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
0Dh
PIR2
—
—
—
–
—
—
—
CCP2IF
---- ---0 ---- ---0
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
10h
T1CON
11h
TMR2
12h
T2CON
13h
SSPBUF
14h
SSPCON
15h
CCPR1L
Capture/Compare/PWM Register1 (LSB)
16h
CCPR1H
Capture/Compare/PWM Register1 (MSB)
17h
CCP1CON
18h
RCSTA
19h
TXREG
USART Transmit Data Register
0000 0000 0000 0000
1Ah
RCREG
USART Receive Data Register
0000 0000 0000 0000
1Bh
CCPR2L
Capture/Compare/PWM Register2 (LSB)
xxxx xxxx uuuu uuuu
1Ch
CCPR2H
Capture/Compare/PWM Register2 (MSB)
1Dh
CCP2CON
1Eh
ADRES(4)
1Fh
ADCON0(4)
—
—
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
TOUTPS3 TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0 -000 0000 -000 0000
SSPM2
SSPM1
Timer2 module’s register
—
0000 0000 0000 0000
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
SSPOV
--00 0000 --uu uuuu
SSPEN
CKP
SSPM3
xxxx xxxx uuuu uuuu
SSPM0
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000 --00 0000
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
—
—
xxxx xxxx uuuu uuuu
CCP2X
CCP2Y
CCP2M3
CCP2M2
CCP2M1
CCP2M0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
A/D Result Register
ADCS1
ADCS0
--00 0000 --00 0000
xxxx xxxx uuuu uuuu
0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0',
Shaded locations are unimplemented, read as '0'.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
are transferred to the upper byte of the program counter.
3: PORTD and PORTE are not implemented on the PIC16C63A/73B, maintain as ’0’.
4: A/D not implemented on the PIC16C63A/65B, maintain as ’0’.
5: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
6: The IRP and RP1 bits are reserved. Always maintain these bits clear.
7: On any device reset, these pins are configured as inputs.
8: This is the value that will be in the port output latch.
 1998 Microchip Technology Inc.
DS30605A-page 13
PIC16C63A/65B/73B/74B
TABLE 2-1
Addr
SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other resets
(5)
Bank 1
80h
INDF(1)
81h
OPTION_REG
82h
PCL(1)
83h
STATUS(1)
84h
FSR
(1)
85h
TRISA
86h
TRISB
PORTB Data Direction Register
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
88h
TRISD(3)
PORTD Data Direction Register
1111 1111 1111 1111
89h
TRISE(3)
IBF
OBF
IBOV
8Ah
PCLATH(1,2)
—
—
—
8Bh
INTCON(1)
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
8Ch
PIE1
PSPIE(3)
ADIE(4)
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
8Dh
PIE2
—
—
—
—
—
—
—
CCP2IE
---- ---0 ---- ---0
8Eh
PCON
—
—
—
—
—
—
POR
BOR
---- --qq ---- --uu
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
IRP(6)
RP1(6)
RP0
TO
—
1111 1111 1111 1111
0000 0000 0000 0000
PD
Z
DC
C
Indirect data memory address pointer
—
0000 0000 0000 0000
rr01 1xxx rr0q quuu
xxxx xxxx uuuu uuuu
PORTA Data Direction Register
--11 1111 --11 1111
1111 1111 1111 1111
PSPMODE
—
PORTE Data Direction Bits
0000 -111 0000 -111
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
8Fh
—
Unimplemented
—
—
90h
—
Unimplemented
—
—
91h
—
Unimplemented
—
—
92h
PR2
Timer2 Period Register
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
94h
SSPSTAT
SMP
CKE
1111 1111 1111 1111
D/A
P
0000 0000 0000 0000
S
R/W
UA
BF
0000 0000 0000 0000
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
99h
SPBRG
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
Unimplemented
—
—
9Eh
—
Unimplemented
—
—
---- -000
---- -000
9Fh
ADCON1(4)
Baud Rate Generator Register
0000 -010 0000 -010
—
—
—
0000 0000 0000 0000
—
—
PCFG2
PCFG1
PCFG0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0',
Shaded locations are unimplemented, read as '0'.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
are transferred to the upper byte of the program counter.
3: PORTD and PORTE are not implemented on the PIC16C63A/73B, maintain as ’0’.
4: A/D not implemented on the PIC16C63A/65B, maintain as ’0’.
5: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
6: The IRP and RP1 bits are reserved. Always maintain these bits clear.
7: On any device reset, these pins are configured as inputs.
8: This is the value that will be in the port output latch.
DS30605A-page 14
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
2.2.2.1
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions, not affecting any status bits, see the
"Instruction Set Summary."
STATUS REGISTER
The STATUS register, shown in Figure 2-3, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: These devices do not use bits IRP and
RP1 (STATUS<7:6>). Maintain these bits
clear to ensure upward compatibility with
future products.
Note 2: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
FIGURE 2-3:
R/W-0
IRP
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
bit7
bit 7:
R/W-x
C
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh) - not implemented, maintain clear
0 = Bank 0, 1 (00h - FFh) - not implemented, maintain clear
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh) - not implemented, maintain clear
10 = Bank 2 (100h - 17Fh) - not implemented, maintain clear
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0:
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
 1998 Microchip Technology Inc.
DS30605A-page 15
PIC16C63A/65B/73B/74B
2.2.2.2
OPTION_REG REGISTER
The OPTION_REG register is a readable and writable
register which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External
INT Interrupt, TMR0, and the weak pull-ups on PORTB.
FIGURE 2-4:
R/W-1
RBPU
bit7
Note:
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
OPTION_REG REGISTER (ADDRESS 81h)
R/W-1
INTEDG
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
bit0
bit 7:
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6:
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5:
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3:
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
DS30605A-page 16
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
2.2.2.3
INTCON REGISTER
Note:
The INTCON Register is a readable and writable register which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
FIGURE 2-5:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6:
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5:
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4:
IINTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3:
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2:
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1:
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0:
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
 1998 Microchip Technology Inc.
DS30605A-page 17
PIC16C63A/65B/73B/74B
2.2.2.4
PIE1 REGISTER
This register contains the individual enable bits for the
peripheral interrupts.
FIGURE 2-6:
R/W-0
PSPIE(1)
bit7
Note:
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
PIE1 REGISTER (ADDRESS 8Ch)
R/W-0
ADIE(2)
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
CCP1IE
R/W-0
TMR2IE
R/W-0
TMR1IE
bit0
bit 7:
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6:
ADIE(2): A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5:
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4:
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3:
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2:
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1:
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0:
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
Note 1: PIC16C63A/73B devices do not have a Parallel Slave Port implemented. This bit location is reserved on these
devices. Always maintain this bit clear.
2: PIC16C63A/65B devices do not have an A/D module. This bit location is reserved on these devices. Always maintain
this bit clear.
DS30605A-page 18
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
2.2.2.5
PIR1 REGISTER
Note:
This register contains the individual flag bits for the
peripheral interrupts.
FIGURE 2-7:
R/W-0
PSPIF(1)
bit7
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
PIR1 REGISTER (ADDRESS 0Ch)
R/W-0
ADIF(2)
R-0
RCIF
R-0
TXIF
R/W-0
SSPIF
R/W-0
CCP1IF
R/W-0
TMR2IF
R/W-0
TMR1IF
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6:
ADIF(2): A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5:
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full (cleared by reading RCREG)
0 = The USART receive buffer is empty
bit 4:
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty (cleared by writing to TXREG)
0 = The USART transmit buffer is full
bit 3:
SSPIF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2:
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1:
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0:
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1: PIC16C63A/73B devices do not have a Parallel Slave Port implemented. This bit location is reserved on these
devices. Always maintain this bit clear.
2: PIC16C63A/65B devices do not have an A/D module. This bit location is reserved on these devices. Always maintain
this bit clear.
 1998 Microchip Technology Inc.
DS30605A-page 19
PIC16C63A/65B/73B/74B
2.2.2.6
PIE2 REGISTER
This register contains the individual enable bit for the
CCP2 peripheral interrupt.
FIGURE 2-8:
U-0
—
PIE2 REGISTER (ADDRESS 8Dh)
U-0
—
U-0
—
U-0
—
U-0
—
bit7
U-0
—
U-0
—
R/W-0
CCP2IE
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-1: Unimplemented: Read as '0'
bit 0:
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
DS30605A-page 20
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
2.2.2.7
PIR2 REGISTER
.
Note:
This register contains the CCP2 interrupt flag bit.
FIGURE 2-9:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
PIR2 REGISTER (ADDRESS 0Dh)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
CCP2IF
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-1: Unimplemented: Read as '0'
bit 0:
CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused
 1998 Microchip Technology Inc.
DS30605A-page 21
PIC16C63A/65B/73B/74B
2.2.2.8
PCON REGISTER
Note:
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR) to an external MCLR Reset or WDT Reset.
Those devices with brown-out detection circuitry contain an additional bit to differentiate a Brown-out Reset
condition from a Power-on Reset condition.
If the BODEN configuration bit is set, BOR
is ’1’ on Power-on Reset. If the BODEN
configuration bit is clear, BOR is unknown
on Power-on Reset.
The BOR status bit is a "don't care" and is
not necessarily predictable if the brown-out
circuit is disabled (the BODEN configuration bit is clear). BOR must then be set by
the user and checked on subsequent
resets to see if it is clear, indicating a
brown-out has occurred.
FIGURE 2-10: PCON REGISTER (ADDRESS 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
POR
bit7
R/W-q
BOR
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-2: Unimplemented: Read as '0'
bit 1:
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
DS30605A-page 22
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
2.3
PCL and PCLATH
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 13 bits
wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called
the PCH register. This register contains the PC<12:8>
bits and is not directly readable or writable. All updates
to the PCH register go through the PCLATH register.
2.3.1
STACK
The stack allows a combination of up to 8 program calls
and interrupts to occur. The stack contains the return
address from this branch in program execution.
2.4
Program Memory Paging
The CALL and GOTO instructions provide 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALL or GOTO instruction
the upper bit of the address is provided by
PCLATH<3>. When doing a CALL or GOTO instruction,
the user must ensure that the page select bit is programmed so that the desired program memory page is
addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto
the stack. Therefore, manipulation of the PCLATH<3>
bit is not required for the return instructions (which
POPs the address from the stack).
Mid-Range devices have an 8 level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not modified when the stack is PUSHed or
POPed.
After the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
 1998 Microchip Technology Inc.
DS30605A-page 23
PIC16C63A/65B/73B/74B
2.5
Indirect Addressing, INDF and FSR
Registers
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
The INDF register is not a physical register. Addressing INDF actually addresses the register whose
address is contained in the FSR register (FSR is a
pointer). This is indirect addressing.
EXAMPLE 2-1:
EXAMPLE 2-2:
INDIRECT ADDRESSING
movlw
movwf
clrf
incf
btfss
goto
NEXT
•
•
•
•
Register file 05 contains the value 10h
Register file 06 contains the value 0Ah
Load the value 05 into the FSR register
A read of the INDF register will return the value of
10h
• Increment the value of the FSR register by one
(FSR = 06)
• A read of the INDR register now will return the
value of 0Ah.
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
0x20
FSR
INDF
FSR
FSR,4
NEXT
;initialize pointer
; to RAM
;clear INDF register
;inc pointer
;all done?
;NO, clear next
CONTINUE
:
;YES, continue
An effective 9-bit address is obtained by concatenating
the 8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 2-11. However, IRP is not used in the
PIC16C63A/65B/73B/74B.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
FIGURE 2-11: DIRECT/INDIRECT ADDRESSING
Direct Addressing
RP1:RP0
6
Indirect Addressing
from opcode
0
IRP
7
FSR register
0
(2)
(2)
bank select
bank select
location select
00
00h
01
80h
10
100h
location select
11
180h
not used
(3)
(3)
Data
Memory(1)
7Fh
Bank 0
FFh
Bank 1
17Fh
Bank 2
1FFh
Bank 3
Note 1: For register file map detail see Figure 2-2.
2: Maintain RP1 and IRP as clear for upward compatibility with future products.
3: Not implemented.
DS30605A-page 24
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
3.0
I/O PORTS
FIGURE 3-1:
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Additional information on I/O ports may be found in the
PICmicro Mid-Range Reference Manual, (DS33023).
3.1
Q
VDD
Q
CK
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other RA port pins have TTL input levels and full
CMOS output drivers.
On PIC16C73B/74B devices, other PORTA pins are
multiplexed with analog inputs and analog VREF input.
The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1).
On a Power-on Reset, these pins are configured as analog inputs and read as '0'.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 3-1:
INITIALIZING PORTA
BCF
CLRF
STATUS, RP0
PORTA
BSF
MOVLW
STATUS, RP0
0xCF
MOVWF
TRISA
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTA by
clearing output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RA<3:0> as inputs
RA<5:4> as outputs
TRISA<7:6> are always
read as '0'.
P
Data Latch
D
WR
TRIS
N
Q
I/O pin(1)
VSS
Analog
input
mode
(73B/74B
only)
Q
CK
TRIS Latch
On a Power-on Reset, these pins are configured as inputs and read as '0'.
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read. This value is modified and then written to the port
data latch.
Note:
D
WR
Port
PORTA and the TRISA Register
PORTA is a 6-bit wide bi-directional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISA bit (=0) will
make the corresponding PORTA pin an output, i.e., put
the contents of the output latch on the selected pin.
Note:
Data
bus
BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
TTL
input
buffer
RD TRIS
Q
D
EN
RD PORT
To A/D Converter (73B/74B only)
Note 1: I/O pins have protection diodes to VDD and
VSS.
FIGURE 3-2:
Data
bus
WR
PORT
BLOCK DIAGRAM OF
RA4/T0CKI PIN
D
Q
CK
Q
N
I/O pin(1)
Data Latch
WR
TRIS
D
Q
CK
Q
VSS
Schmitt
Trigger
input
buffer
TRIS Latch
RD TRIS
Q
D
EN
EN
RD PORT
TMR0 clock input
Note 1: I/O pin has protection diodes to VSS only.
 1998 Microchip Technology Inc.
DS30605A-page 25
PIC16C63A/65B/73B/74B
TABLE 3-1:
PORTA FUNCTIONS
Name
Bit#
Buffer
Function
RA0/AN0
bit0
TTL
Input/output or analog input(1)
RA1/AN1
bit1
TTL
Input/output or analog input(1)
RA2/AN2
bit2
TTL
Input/output or analog input(1)
RA3/AN3/VREF
bit3
TTL
RA4/T0CKI
bit4
ST
Input/output or analog input(1) or VREF(1)
Input/output or external clock input for Timer0
Output is open drain type
RA5/SS/AN4
bit5
TTL
Input/output or slave select input for synchronous serial port or analog input(1)
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: On PIC16C73B/74B devices only.
TABLE 3-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Address Name
Bit 7 Bit 6
05h
PORTA
—
—
85h
TRISA
—
—
9Fh
ADCON1(1)
—
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other resets
RA5
RA4
RA3
RA2
RA1
RA0
--0x 0000
--0u 0000
PORTA Data Direction Register
—
—
—
PCFG2
PCFG1
PCFG0
--11 1111
--11 1111
---- -000
---- -000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note 1: On PIC16C73B/74B devices only.
DS30605A-page 26
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
3.2
PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a
TRISB bit (=1) will make the corresponding PORTB pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output, i.e., put
the contents of the output latch on the selected pin.
EXAMPLE 3-1:
BCF
CLRF
BSF
MOVLW
MOVWF
INITIALIZING PORTB
STATUS, RP0
PORTB
STATUS, RP0
0xCF
TRISB
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTB by
clearing output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RB<3:0> as inputs
RB<5:4> as outputs
RB<7:6> as inputs
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
FIGURE 3-3:
WR Port
b)
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 3-4:
Data bus
weak
P pull-up
WR Port
Data Latch
D
Q
BLOCK DIAGRAM OF
RB7:RB4 PINS
weak
P pull-up
Data Latch
D
Q
I/O
pin(1)
CK
TRIS Latch
D
Q
I/O
pin(1)
CK
WR TRIS
TRIS Latch
D
Q
WR TRIS
a)
RBPU(2)
VDD
Data bus
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the interrupt in the following manner:
VDD
BLOCK DIAGRAM OF
RB3:RB0 PINS
RBPU(2)
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>).
TTL
Input
Buffer
CK
TTL
Input
Buffer
CK
RD TRIS
Q
RD TRIS
RD Port
Latch
D
EN
RD Port
Q
EN
Q
D
RD Port
EN
RB0/INT
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
 1998 Microchip Technology Inc.
Q1
Set RBIF
D
From other
RB7:RB4 pins
Schmitt Trigger
Buffer
ST
Buffer
Q3
RB7:RB6 in serial programming mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
DS30605A-page 27
PIC16C63A/65B/73B/74B
TABLE 3-3:
Name
PORTB FUNCTIONS
Bit#
Buffer
Function
TTL/ST(1)
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1
bit1
TTL
Input/output pin. Internal software programmable weak pull-up.
RB2
bit2
TTL
Input/output pin. Internal software programmable weak pull-up.
RB3
bit3
TTL
Input/output pin. Internal software programmable weak pull-up.
RB4
bit4
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB5
bit5
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB6
bit6
TTL/ST(2)
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming clock.
RB7
bit7
TTL/ST(2)
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
RB0/INT
bit0
TABLE 3-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Address
Name
06h
PORTB
86h
TRISB
81h
OPTION_
REG
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other resets
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
1111 1111
1111 1111
PORTB Data Direction Register
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS30605A-page 28
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
3.3
PORTC and the TRISC Register
PORTC is an 8-bit wide bi-directional port. The corresponding data direction register is TRISC. Setting a
TRISC bit (=1) will make the corresponding PORTC pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISC bit (=0) will
make the corresponding PORTC pin an output, i.e., put
the contents of the output latch on the selected pin.
PORTC is multiplexed with several peripheral functions
(Table 3-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
EXAMPLE 3-1:
INITIALIZING PORTC
BCF
CLRF
STATUS, RP0
PORTC
BSF
MOVLW
STATUS, RP0
0xCF
MOVWF
TRISC
;
;
;
;
;
;
;
;
;
;
;
Select Bank 0
Initialize PORTC by
clearing output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RC<3:0> as inputs
RC<5:4> as outputs
RC<7:6> as inputs
 1998 Microchip Technology Inc.
FIGURE 3-5:
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE)
PORT/PERIPHERAL Select(2)
Peripheral Data Out
Data bus
WR
PORT
D
VDD
0
Q
P
1
CK
Q
Data Latch
WR
TRIS
D
CK
I/O
pin(1)
Q
Q
N
TRIS Latch
VSS
Schmitt
Trigger
RD TRIS
Peripheral
OE(3)
RD
PORT
Peripheral input
Q
D
EN
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port
data and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
DS30605A-page 29
PIC16C63A/65B/73B/74B
TABLE 3-5:
PORTC FUNCTIONS
Name
Bit#
Buffer Type
Function
RC0/T1OSO/T1CKI
bit0
ST
RC1/T1OSI
bit1
ST
Input/output port pin or Timer1 oscillator input
RC2/CCP1
bit2
ST
Input/output port pin or Capture1 input/Compare1 output/PWM1
output
RC3/SCK/SCL
bit3
ST
RC3 can also be the synchronous serial clock for both SPI and I2C
modes.
RC4/SDI/SDA
bit4
ST
RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode).
Input/output port pin or Timer1 oscillator output/Timer1 clock input
RC5/SDO
bit5
ST
Input/output port pin or Synchronous Serial Port data output
RC6
bit6
ST
Input/output port pin
RC7
bit7
ST
Input/output port pin
Legend: ST = Schmitt Trigger input
TABLE 3-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Address Name
07h
PORTC
87h
TRISC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other resets
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
PORTC Data Direction Register
Legend: x = unknown, u = unchanged.
DS30605A-page 30
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
3.4
PORTD and TRISD Registers
This
section
is
applicable
PIC16C65B/PIC16C74B devices only.
to
the
PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or
output.
PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL.
FIGURE 3-6:
Data
bus
PORTD BLOCK DIAGRAM
(IN I/O PORT MODE)
D
WR
PORT
Q
I/O pin(1)
CK
Data Latch
D
WR
TRIS
Q
Schmitt
Trigger
input
buffer
CK
TRIS Latch
RD TRIS
Q
D
EN
EN
RD PORT
Note 1: I/O pins have protection diodes to VDD and VSS.
 1998 Microchip Technology Inc.
DS30605A-page 31
PIC16C63A/65B/73B/74B
TABLE 3-7:
Name
PORTD FUNCTIONS
Bit#
Buffer Type
RD0/PSP0
bit0
ST/TTL(1)
Function
Input/output port pin or parallel slave port bit0
RD1/PSP1
bit1
ST/TTL(1)
Input/output port pin or parallel slave port bit1
RD2/PSP2
bit2
ST/TTL(1)
Input/output port pin or parallel slave port bit2
RD3/PSP3
bit3
ST/TTL(1)
Input/output port pin or parallel slave port bit3
RD4/PSP4
bit4
ST/TTL(1)
Input/output port pin or parallel slave port bit4
RD5/PSP5
bit5
ST/TTL(1)
Input/output port pin or parallel slave port bit5
RD6/PSP6
bit6
ST/TTL(1)
Input/output port pin or parallel slave port bit6
Input/output port pin or parallel slave port bit7
RD7/PSP7
bit7
ST/TTL(1)
Legend: ST = Schmitt Trigger input TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port Mode.
TABLE 3-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Address Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other resets
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
uuuu uuuu
08h
PORTD
RD7
88h
TRISD
PORTD Data Direction Register
89h
TRISE
IBF
RD6
OBF
IBOV PSPMODE
—
PORTE Data Direction Bits
1111 1111
1111 1111
0000 -111
0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD.
DS30605A-page 32
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
3.5
PORTE and TRISE Register
Note:
This
section
is
applicable
to
the
PIC16C65B/PIC16C74B devices only. The A/D multiplexed functions are available on the PIC16C74B only.
On a Power-on Reset these pins are configured as analog inputs.
FIGURE 3-7:
Data
bus
PORTE has three pins RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7, which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
D
WR
PORT
I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. In
this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs). For the PIC16C74B ensure ADCON1 is configured for digital I/O. In this mode, the input buffers are
TTL.
PORTE BLOCK DIAGRAM
(IN I/O PORT MODE)
Q
I/O pin(1)
CK
Data Latch
D
WR
TRIS
Q
TRIS Latch
Figure 3-8 shows the TRISE register, which also controls the parallel slave port operation.
RD TRIS
PORTE pins for the PIC16C74B only are multiplexed
with analog inputs. When selected as an analog input,
these pins will read as '0's.
Q
R-0
IBF
D
EN
EN
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
FIGURE 3-8:
Schmitt
Trigger
input
buffer
CK
RD PORT
Note 1: I/O pins have protection diodes to VDD and VSS.
TRISE REGISTER (ADDRESS 89h)
R-0
OBF
R/W-0
IBOV
R/W-0
PSPMODE
U-0
—
R/W-1
TRISE2
R/W-1
TRISE1
bit7
R/W-1
TRISE0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
IBF: Input Buffer Full Status bit
1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
bit 6:
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5:
IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared in software)
0 = No overflow occurred
bit 4:
PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel slave port mode
0 = General purpose I/O mode
bit 3:
bit 2:
Unimplemented: Read as '0'
TRISE2: RE2 Direction Control bit
1 = Input
0 = Output
bit 1:
TRISE1: RE2 Direction Control bit
1 = Input
0 = Output
bit 0:
TRISE0: RE2 Direction Control bit
1 = Input
0 = Output
 1998 Microchip Technology Inc.
DS30605A-page 33
PIC16C63A/65B/73B/74B
TABLE 3-9:
PORTE FUNCTIONS
Name
Bit#
Buffer Type
Function
RE0/RD/AN5(2)
bit0
ST/TTL(1)
Input/output port pin or read control input in parallel slave port mode or
analog input:
RD
1 = Not a read operation
0 = Read operation. Reads PORTD register (if chip selected)
RE1/WR/AN6(2)
bit1
ST/TTL(1)
Input/output port pin or write control input in parallel slave port mode or
analog input:
WR
1 = Not a write operation
0 = Write operation. Writes PORTD register (if chip selected)
RE2/CS/AN7(2)
bit2
ST/TTL(1)
Input/output port pin or chip select control input in parallel slave port
mode or analog input:
CS
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Trigger input TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.
2: A/D Converter module multiplexing is implemented on the PIC16C74B only.
TABLE 3-10:
Addr
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
09h
PORTE
—
—
—
—
—
89h
TRISE
IBF
OBF
IBOV
PSPMODE
—
9Fh
ADCON1(1)
—
—
—
—
—
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other resets
RE2
RE1
RE0
---- -xxx
---- -uuu
0000 -111
0000 -111
---- -000
---- -000
PORTE Data Direction Bits
PCFG2
PCFG1
PCFG0
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.
Note 1: A/D Converter module multiplexing is implemented on the PIC16C74B only.
DS30605A-page 34
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
3.6
Parallel Slave Port
FIGURE 3-9:
PORTD AND PORTE BLOCK
DIAGRAM (PARALLEL
SLAVE PORT)
The Parallel Slave Port is implemented on the 40-pin
devices only (PIC16C65B and PIC16C74B).
PORTD operates as an 8-bit wide Parallel Slave Port,
or microprocessor port when control bit PSPMODE
(TRISE<4>) is set. In slave mode it is asynchronously
readable and writable by the external world through RD
control input pin RE0/RD and WR control input pin
RE1/WR.
Data bus
D
WR
PORT
Q
RDx
pin
CK
TTL
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set). For the
PIC16C74B, the A/D port configuration bits
PCFG2:PCFG0 (ADCON1<2:0>) must be set, which
will configure pins RE2:RE0 as digital I/O.
Q
RD
PORT
D
EN
EN
One bit of PORTD
Set interrupt flag
PSPIF (PIR1<7>)
Read
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
RD
TTL
Chip Select
TTL
CS
TTL
WR
Write
Note: I/O pin has protection diodes to VDD and VSS.
FIGURE 3-10: PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
 1998 Microchip Technology Inc.
DS30605A-page 35
PIC16C63A/65B/73B/74B
FIGURE 3-11: PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 3-11:
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Add. Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
xxxx xxxx
uuuu uuuu
RE2
RE1
RE0
---- -xxx
---- -uuu
0000 -111
0000 -111
Port data latch when written: Port pins when read
Value on all
other resets
08h
PORTD
09h
PORTE
89h
TRISE
IBF
OBF
0Ch
PIR1
PSPIF
ADIF(1)
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
8Ch
PIE1
PSPIE
ADIE(1)
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
9Fh
ADCON1(1)
—
—
—
—
—
PCFG2
PCFG1
PCFG0
---- -000
---- -000
—
—
—
—
IBOV PSPMODE
—
—
PORTE Data Direction Bits
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.
Note 1: On PIC16C74B only.
DS30605A-page 36
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
4.0
TIMER0 MODULE
Additional information on external clock requirements
is available in the PICMicro Mid-Range Reference
Manual, (DS33023).
The Timer0 module timer/counter has the following features:
•
•
•
•
•
•
4.2
8-bit timer/counter
Readable and writable
Internal or external clock select
Edge select for external clock
8-bit software programmable prescaler
Interrupt on overflow from FFh to 00h
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 4-2). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available, which is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer and
vice-versa.
Figure 4-1 is a simplified block diagram of the Timer0
module.
Additional information on timer modules is available in
the PICmicro Mid-Range Reference Manual,
(DS33023).
4.1
The prescaler is not readable or writable.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
Timer0 Operation
Timer0 can operate as a timer or as a counter.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
Setting bit PSA will assign the prescaler to the Watchdog Timer (WDT). When the prescaler is assigned to
the WDT, prescale values of 1:1, 1:2, ..., 1:128 are
selectable.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are
discussed below.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the WDT.
Note:
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). There is a delay in the actual incrementing of Timer0 after synchronization.
FIGURE 4-1:
Prescaler
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
TIMER0 BLOCK DIAGRAM
Data bus
FOSC/4
0
PSout
1
1
Programmable
Prescaler
RA4/T0CKI
pin
0
8
Sync with
Internal
clocks
TMR0
PSout
(2 cycle delay)
T0SE
3
PS2, PS1, PS0
T0CS
PSA
Set interrupt
flag bit T0IF
on overflow
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).
 1998 Microchip Technology Inc.
DS30605A-page 37
PIC16C63A/65B/73B/74B
4.2.1
4.3
SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control, i.e., it can be changed “on the fly” during program
execution.
Note:
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0
interrupt cannot awaken the processor from SLEEP
since the timer is shut off during SLEEP.
To avoid an unintended device RESET, a
specific instruction sequence (shown in the
PICmicro Mid-Range Reference Manual,
(DS33023). must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This sequence must be
followed even if the WDT is disabled.
FIGURE 4-2:
Timer0 Interrupt
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
CLKOUT (=Fosc/4)
0
RA4/T0CKI
pin
8
M
U
X
1
M
U
X
0
1
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
0
1
Watchdog
Timer
Set flag bit T0IF
on Overflow
PSA
8-bit Prescaler
M
U
X
8
8 - to - 1MUX
PS2:PS0
PSA
1
0
WDT Enable bit
MUX
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
TABLE 4-1:
REGISTERS ASSOCIATED WITH TIMER0
Address
Name
01h
TMR0
0Bh, 8Bh
INTCON
81h
OPTION_REG
85h
TRISA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 module’s register
GIE
PEIE
RBPU INTEDG
—
—
Value on
POR,
BOR
Value on all
other resets
xxxx xxxx
uuuu uuuu
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
--11 1111
--11 1111
PORTA Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
DS30605A-page 38
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
5.0
TIMER1 MODULE
5.1
The Timer1 module timer/counter has the following features:
• 16-bit timer/counter
(Two 8-bit registers; TMR1H and TMR1L)
• Readable and writable (Both registers)
• Internal or external clock select
• Interrupt on overflow from FFFFh to 0000h
• Reset from CCP module trigger
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
Timer1 has a control register, shown in Figure 5-1.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
Figure 5-2 is a simplified block diagram of the Timer1
module.
Additional information on timer modules is available in
the PICmicro Mid-Range Reference Manual,
(DS33023).
FIGURE 5-1:
Timer1 Operation
In timer mode, Timer1 increments every instruction
cycle. In counter mode, it increments on every rising
edge of the external clock input.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
Timer1 also has an internal “reset input”. This reset can
be generated by the CCP module (Section 7.0).
T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
R/W-0
R/W-0
TMR1CS TMR1ON
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3:
T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off
Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain
bit 2:
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1:
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0:
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
 1998 Microchip Technology Inc.
DS30605A-page 39
PIC16C63A/65B/73B/74B
FIGURE 5-2:
TIMER1 BLOCK DIAGRAM
Set flag bit
TMR1IF on
Overflow
0
TMR1
TMR1H
Synchronized
clock input
TMR1L
1
TMR1ON
on/off
T1SYNC
T1OSC
RC0/T1OSO/T1CKI
RC1/T1OSI
1
T1OSCEN FOSC/4
Enable
Internal
Oscillator(1) Clock
Prescaler
1, 2, 4, 8
Synchronize
det
0
2
T1CKPS1:T1CKPS0
TMR1CS
SLEEP input
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS30605A-page 40
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
5.2
Timer1 Oscillator
5.3
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 5-1 shows the capacitor
selection for the Timer1 oscillator.
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 Interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit TMR1IF (PIR1<0>).
This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
5.4
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 5-1:
Timer1 Interrupt
Resetting Timer1 using a CCP Trigger
Output
If the CCP module is configured in compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
CAPACITOR SELECTION
FOR THE TIMER1
OSCILLATOR
Note:
Osc Type
Freq
C1
C2
LP
32 kHz
100 kHz
200 kHz
33 pF
15 pF
15 pF
33 pF
15 pF
15 pF
Timer1 must be configured for either timer or synchronized counter mode to take advantage of this feature. If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
These values are for design guidance only.
Crystals Tested:
In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence.
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
100 kHz
Epson C-2 100.00 KC-P
± 20 PPM
200 kHz
STD XTL 200.000 kHz
± 20 PPM
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the startup time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropriate values of external components.
TABLE 5-2:
The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for
Timer1.
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
0Bh,8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0Ch
PIR1
(1)
ADIF
(1)
(1)
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
8Ch
PIE1
(1)
ADIE
(1)
(1)
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
0000 000x 0000 000u
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
10h
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: These bits are reserved, maintain as '0'.
 1998 Microchip Technology Inc.
DS30605A-page 41
PIC16C63A/65B/73B/74B
NOTES:
DS30605A-page 42
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
6.0
TIMER2 MODULE
The Timer2 module timer has the following features:
•
•
•
•
•
•
•
8-bit timer (TMR2 register)
8-bit period register (PR2)
Readable and writable (Both registers)
Software programmable prescaler (1:1, 1:4, 1:16)
Software programmable postscaler (1:1 to 1:16)
Interrupt on TMR2 match of PR2
SSP module optional use of TMR2 output to generate clock shift
Timer2 has a control register, shown in Figure 6-1.
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Figure 6-2 is a simplified block diagram of the Timer2
module.
Additional information on timer modules is available in
the PICmicro Mid-Range Reference Manual,
(DS33023).
6.1
Timer2 Operation
Timer2 can be used as the PWM time-base for PWM
mode of the CCP module.
The TMR2 register is readable and writable, and is
cleared on any device reset.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4
or
1:16,
selected
by
control
bits
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device reset (Power-on Reset, MCLR reset,
Watchdog Timer reset, or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
FIGURE 6-1:
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
—
bit7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit0
bit 7:
Unimplemented: Read as '0'
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2:
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
 1998 Microchip Technology Inc.
DS30605A-page 43
PIC16C63A/65B/73B/74B
6.2
Timer2 Interrupt
FIGURE 6-2:
Sets flag
bit TMR2IF
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is initialized to FFh upon reset.
6.3
TIMER2 BLOCK DIAGRAM
TMR2
output (1)
Reset
Postscaler
1:1 to 1:16
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module, which optionally uses
it to generate shift clock.
EQ
4
TMR2 reg
Prescaler
1:1, 1:4, 1:16
FOSC/4
2
Comparator
PR2 reg
Note 1: TMR2 register output can be software selected
by the SSP Module as a baud clock.
TABLE 6-1:
Address
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 2
Bit 1
Bit 6
Bit 5
Bit 4
0Bh,8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
(1)
ADIF
(1)
(1)
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
8Ch
PIE1
(1)
ADIE
(1)
(1)
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
11h
TMR2
12h
T2CON
92h
PR2
Legend:
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2
module.
Note 1:
These bits are reserved, maintain as '0'.
Timer2 module’s register
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1
Timer2 Period Register
Bit 0
Value on
all other
resets
Bit 7
DS30605A-page 44
Bit 3
Value on:
POR,
BOR
Name
0000 0000 0000 0000
T2CKPS0 -000 0000 -000 0000
1111 1111 1111 1111
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
7.0
CAPTURE/COMPARE/PWM
(CCP) MODULE(S)
CCP2 Module
Each CCP (Capture/Compare/PWM) module contains
a 16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register or as a PWM
master/slave Duty Cycle register. Table 7-1 shows the
timer resources of the CCP module modes.
The operation of CCP1 is identical to that of CCP2, with
the exception of the special trigger. Therefore, operation of a CCP module in the following sections is
described with respect to CCP1.
Capture/Compare/PWM Register2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
Additional information on the CCP module is available
in the PICmicro Mid-Range Reference Manual,
(DS33023).
TABLE 7-1:
Table 7-2 shows the interaction of the CCP modules.
CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
TABLE 7-2:
CCP MODE - TIMER
RESOURCE
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
Same TMR1 time-base.
Capture
Compare
The compare should be configured for the special event trigger, which clears TMR1.
Compare
Compare
The compare(s) should be configured for the special event trigger, which clears TMR1.
PWM
PWM
The PWMs will have the same frequency, and update rate (TMR2 interrupt).
PWM
Capture
None
PWM
Compare
None
FIGURE 7-1:
U-0
—
bit7
U-0
—
CCP1CON REGISTER (ADDRESS 17h) / CCP2CON REGISTER (ADDRESS 1Dh)
R/W-0
CCPxX
R/W-0
R/W-0
CCPxY CCPxM3
R/W-0
CCPxM2
R/W-0
R/W-0
CCPxM1 CCPxM0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5-4: CCPxX:CCPxY: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit is set)
1001 = Compare mode, clear output on match (CCPxIF bit is set)
1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected)
1011 = Compare mode, trigger special event (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1
and starts an A/D conversion (if A/D module is enabled))
11xx = PWM mode
 1998 Microchip Technology Inc.
DS30605A-page 45
PIC16C63A/65B/73B/74B
7.1
Capture Mode
7.1.4
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as:
•
•
•
•
every falling edge
every rising edge
every 4th rising edge
every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost.
7.1.1
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in capture mode,
the prescaler counter is cleared. This means that any
reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 7-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 7-1:
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit.
Note:
If the RC2/CCP1 is configured as an output, a write to the port can cause a capture
condition.
FIGURE 7-2:
CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF
MOVLW
CCP1CON
NEW_CAPT_PS
MOVWF
CCP1CON
;Turn CCP module off
;Load the W reg with
; the new prescaler
; mode value and CCP ON
;Load CCP1CON with this
; value
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Prescaler
÷ 1, 4, 16
Set flag bit CCP1IF
(PIR1<2>)
RC2/CCP1
Pin
CCPR1H
and
edge detect
CCPR1L
Capture
Enable
TMR1H
TMR1L
CCP1CON<3:0>
Q’s
7.1.2
TIMER1 MODE SELECTION
Timer1 must be running in timer mode or synchronized
counter mode for the CCP module to use the capture
feature. In asynchronous counter mode, the capture
operation may not work.
7.1.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
DS30605A-page 46
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
7.2
Compare Mode
7.2.1
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• driven High
• driven Low
• remains Unchanged
The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit.
Note:
7.2.2
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 7-3:
CCP PIN CONFIGURATION
COMPARE MODE
OPERATION BLOCK
DIAGRAM
SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
7.2.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
Special Event Trigger (CCP2 only)
Set flag bit CCP1IF
(PIR1<2>)
CCPR1H CCPR1L
Comparator
TMR1H
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
7.2.3
Special event trigger will
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>),
which starts an A/D conversion
Q S Output
Logic
match
RC2/CCP1
R
Pin
TRISC<2>
Output Enable CCP1CON<3:0>
Mode Select
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
TMR1L
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special trigger output of CCP2 resets the TMR1
register pair, and starts an A/D conversion (if the A/D
module is enabled).
Note:
TABLE 7-3:
Address
The special event trigger from the CCP2
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
all other
resets
0Bh,8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
0Ch
PIR1
(1)
ADIF
(1)
(1)
SSPIF
CCP1IF
TMR2IF
TMR1IF 0000 0000 0000 0000
8Ch
PIE1
(1)
ADIE
(1)
(1)
SSPIE
CCP1IE
TMR2IE
TMR1IE 0000 0000 0000 0000
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1register
xxxx xxxx uuuu uuuu
10h
T1CON
15h
CCPR1L
Capture/Compare/PWM register1 (LSB)
16h
CCPR1H
Capture/Compare/PWM register1 (MSB)
17h
CCP1CON
—
—
—
—
RBIF
Value on
POR,
BOR
0000 000x 0000 000u
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCP1X
CCP1Y
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1M3
CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1.
Note 1: These bits/registers are reserved, maintain as '0'.
 1998 Microchip Technology Inc.
DS30605A-page 47
PIC16C63A/65B/73B/74B
7.3
PWM Mode
7.3.1
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
Figure 7-4 shows a simplified block diagram of the CCP
module in PWM mode.
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 7.3.3.
FIGURE 7-4:
SIMPLIFIED PWM BLOCK
DIAGRAM
The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula:
PWM period = [(PR2) + 1] ¥ 4 ¥ TOSC ¥
(TMR2 prescale value)
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note:
CCP1CON<5:4>
Duty cycle registers
CCPR1L
7.3.2
CCPR1H (Slave)
R
Comparator
Q
RC2/CCP1
TMR2
(Note 1)
S
TRISC<2>
Comparator
Clear Timer,
CCP1 pin and
latch D.C.
PR2
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
A PWM output (Figure 7-5) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period (1/
period).
FIGURE 7-5:
PWM OUTPUT
Duty Cycle
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available: the CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM DUTY CYCLE = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 PRESCALE VALUE)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.=
Note:
TMR2 = PR2
TMR2 = Duty Cycle
DS30605A-page 48
The Timer2 postscaler (see Section 6.0) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different frequency than the PWM output.
Maximum PWM resolution (bits) for a given PWM frequency:
F OSC
log  ---------------- 
 F PWM 
= -----------------------------bits
log ( 2 )
Period
TMR2 = PR2
PWM PERIOD
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
For an example PWM period and duty cycle calculation, see the PICmicro Mid-Range Reference Manual
(DS33023).
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
7.3.3
SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
3.
4.
5.
Set the PWM period by writing to the PR2 register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
Make the CCP1 pin an output by clearing the
TRISC<2> bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Configure the CCP1 module for PWM operation.
TABLE 7-4:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency
1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
TABLE 7-5:
Address
16
0xFF
10
4
0xFF
10
1
0xFF
10
1
0x3F
8
1
0x1F
7
1
0x17
5.5
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name
Bit 7
0Bh,8Bh
INTCON
0Ch
PIR1
8Ch
PIE1
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
resets
Bit 6
Bit 5
Bit 4
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
(1)
ADIF
(1)
(1)
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
(1)
ADIE
(1)
(1)
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
0000 000x 0000 000u
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
11h
TMR2
Timer2 module’s register
0000 0000 0000 0000
92h
PR2
Timer2 module’s period register
1111 1111 1111 1111
12h
T2CON
15h
CCPR1L
Capture/Compare/PWM register1 (LSB)
16h
CCPR1H
Capture/Compare/PWM register1 (MSB)
17h
CCP1CON
Legend:
Note 1:
—
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
—
CCP1X
CCP1Y
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
These bits/registers are reserved, maintain as '0'.
 1998 Microchip Technology Inc.
DS30605A-page 49
PIC16C63A/65B/73B/74B
NOTES:
DS30605A-page 50
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
8.0
SYNCHRONOUS SERIAL
PORT (SSP) MODULE
8.1
SSP Module Overview
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other peripheral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can
operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
For more information on SSP operation (including an
I2C Overview), refer to the PICmicro Mid-Range Reference Manual (DS33023). Also, refer to Application
Note AN578, “Use of the SSP Module in the I 2C MultiMaster Environment.”
 1998 Microchip Technology Inc.
DS30605A-page 51
PIC16C63A/65B/73B/74B
FIGURE 8-1:
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0 R/W-0
SMP
CKE
R-0
R-0
R-0
R-0
R-0
R-0
D/A
P
S
R/W
UA
BF
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 7:
SMP: SPI data input sample phase
SPI Master Operation
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
bit 6:
CKE: SPI Clock Edge Select
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
bit 5:
D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4:
P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit is
detected last, SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
bit 3:
S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit is
detected last, SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
bit 2:
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next start bit, stop bit, or ACK bit.
1 = Read
0 = Write
bit 1:
UA: Update Address (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0:
BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
DS30605A-page 52
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 8-2:
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 7:
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6:
SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow,
the data in SSPSR is lost. Overflow can only occur in slave mode. The user must read the SSPBUF, even
if only transmitting data, to avoid setting overflow. In master operation, the overflow bit is not set since
each new reception (and transmission) is initiated by writing to the SSPBUF register.
0 = No overflow
In I2C mode
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care"
in transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
bit 5:
SSPEN: Synchronous Serial Port Enable bit
In SPI mode
1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2C mode
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
bit 4:
CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2C mode
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI master operation, clock = FOSC/4
0001 = SPI master operation, clock = FOSC/16
0010 = SPI master operation, clock = FOSC/64
0011 = SPI master operation, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
0110 = I2C slave mode, 7-bit address
0111 = I2C slave mode, 10-bit address
1011 = I2C firmware controlled master operation (slave idle)
1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled
1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled
 1998 Microchip Technology Inc.
DS30605A-page 53
PIC16C63A/65B/73B/74B
8.2
SPI Mode
This section contains register definitions and operational characteristics of the SPI module.
Additional information on SPI operation may be found
in the PICmicro Mid-Range Reference Manual
(DS33023).
8.2.1
OPERATION OF SSP MODULE IN SPI
MODE
Note:
When the SPI is in Slave Mode with SS pin
control enabled, (SSPCON<3:0> = 0100)
the SPI module will reset if the SS pin is set
to VDD.
Note:
If the SPI is used in Slave Mode with
CKE = '1', then the SS pin control must be
enabled.
FIGURE 8-3:
A block diagram of the SSP Module in SPI Mode is
shown in Figure 8-3.
Internal
data bus
The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
Read
Write
SSPBUF reg
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
Additionally a fourth pin may be used when in a slave
mode of operation:
• Slave Select (SS)
SSP BLOCK DIAGRAM
(SPI MODE)
RA5/SS/AN4
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the following to be specified:
SSPSR reg
RC4/SDI/SDA
RC5/SDO
SS Control
Enable
RA5/SS/AN4
•
•
•
•
Master Operation (SCK is the clock output)
Slave Mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Clock Edge (Output data on rising/falling edge of
SCK)
• Clock Rate (master operation only)
• Slave Select Mode (Slave mode only)
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON register and then set bit SSPEN. This configures the SDI,
SDO, SCK and SS pins as serial port pins. For the pins
to behave as the serial port function, they must have
their data direction bits (in the TRISC register) appropriately programmed. That is:
shift
clock
bit0
Edge
Select
2
Clock Select
SSPM3:SSPM0
4
Edge
Select
RC3/SCK/
SCL
TMR2 output
2
Prescaler TCY
4, 16, 64
TRISC<3>
• SDI must have TRISC<4> set
• SDO must have TRISC<5> cleared
• SCK (master operation) must have TRISC<3>
cleared
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set
DS30605A-page 54
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 8-1:
REGISTERS ASSOCIATED WITH SPI OPERATION
Bit 7
Bit 6
Bit 5
Bit 4
0Bh,8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
0Ch
PIR1
(1)
ADIF
(1)
(1)
SSPIF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch
PIE1
(1)
ADIE
(1)
(1)
SSPIE
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
87h
TRISC
PORTC Data Direction Register
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
14h
SSPCON WCOL
85h
TRISA
94h
SSPSTAT
—
—
SMP
CKE
Bit 2
Bit 1
Bit 0
T0IF
INTF
RBIF
Value on
all other
resets
Name
SSPOV SSPEN
Bit 3
Value on:
POR,
BOR
Address
1111 1111 1111 1111
CKP
SSPM3
SSPM2
xxxx xxxx uuuu uuuu
SSPM1
SSPM0 0000 0000 0000 0000
PORTA Data Direction Register
D/A
0000 000x 0000 000u
P
S
R/W
--11 1111 --11 1111
UA
BF
0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1: Always maintain these bits clear.
 1998 Microchip Technology Inc.
DS30605A-page 55
PIC16C63A/65B/73B/74B
8.3
SSP I 2C Operation
The SSP module in I 2C mode fully implements all slave
functions, except general call support, and provides
interrupts on start and stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the RC3/
SCK/SCL pin, which is the clock (SCL), and the RC4/
SDI/SDA pin, which is the data (SDA). The user must
configure these pins as inputs or outputs through the
TRISC<4:3> bits.
The SSP module functions are enabled by setting SSP
Enable bit SSPEN (SSPCON<5>).
FIGURE 8-4:
SSP BLOCK DIAGRAM
(I2C MODE)
Internal
data bus
Read
SSPSR reg
MSb
LSb
Match detect
Addr Match
SSPADD reg
Start and
Stop bit detect
Set, Reset
S, P bits
(SSPSTAT reg)
SSP Control Register (SSPCON)
SSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
SSP Shift Register (SSPSR) - Not directly accessible
• SSP Address Register (SSPADD)
DS30605A-page 56
Additional information on SSP I2C operation may be
found in the PICMicro Mid-Range Reference Manual
(DS33023).
8.3.1
SLAVE MODE
There are certain conditions that will cause the SSP
module not to give this ACK pulse. These are if either
(or both):
a)
The SSP module has five registers for I2C operation.
These are the:
•
•
•
•
Selection of any I 2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting
the appropriate TRISC bits.
When an address is matched or the data transfer after
an address match is received, the hardware automatically will generate the acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
shift
clock
RC4/
SDI/
SDA
• I 2C Slave mode (7-bit address)
• I 2C Slave mode (10-bit address)
• I 2C Slave mode (7-bit address), with start and
stop bit interrupts enabled
• I 2C Slave mode (10-bit address), with start and
stop bit interrupts enabled
• I 2C Firmware controlled master operation, slave
is idle
In slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
Write
SSPBUF reg
RC3/SCK/SCL
The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow
one of the following I 2C modes to be selected:
b)
The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 8-2 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF register while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification as well as the requirement of the SSP
module is shown in timing parameter #100 and parameter #101.
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
8.3.1.1
ADDRESSING
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
b)
c)
d)
The SSPSR register value is loaded into the
SSPBUF register.
The buffer full bit, BF is set.
An ACK pulse is generated.
SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.
In 10-bit address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address the first byte would equal
TABLE 8-2:
‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs
of the address. The sequence of events for 10-bit
address is as follows with steps 7- 9 for slave-transmitter:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Receive first (high) byte of Address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
Update the SSPADD register with the first (high)
byte of Address. If match releases SCL line, this
will clear bit UA.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive repeated START condition.
Receive first (high) byte of Address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
BF
SSPOV
SSPSR → SSPBUF
Generate ACK
Pulse
0
0
Yes
Yes
Yes
1
0
No
No
Yes
1
1
No
No
Yes
0
1
Yes
No
Yes
Note:
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
 1998 Microchip Technology Inc.
DS30605A-page 57
PIC16C63A/65B/73B/74B
8.3.1.2
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
RECEPTION
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
FIGURE 8-5:
Receiving Address
Receiving Data
R/W=0
Receiving Data
ACK
ACK
ACK
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the
status of the byte.
S
1
2
3
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
Cleared in software
9
P
Bus Master
terminates
transfer
SSPBUF register is read
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
DS30605A-page 58
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
8.3.1.3
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
TRANSMISSION
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register.
Then pin RC3/SCK/SCL should be enabled by setting
bit CKP (SSPCON<4>). The master must monitor the
SCL pin prior to asserting another clock pulse. The
slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the SDA
signal is valid during the SCL high time (Figure 8-6).
I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
FIGURE 8-6:
Receiving Address
SDA
SCL
A7
S
As a slave-transmitter, the ACK pulse from the masterreceiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then the
data transfer is complete. When the ACK is latched by
the slave, the slave logic is reset (resets SSPSTAT register) and the slave then monitors for another occurrence of the START bit. If the SDA line was low (ACK),
the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin
RC3/SCK/SCL should be enabled by setting bit CKP.
A6
1
2
Data in
sampled
R/W = 1
A5
A4
A3
A2
A1
3
4
5
6
7
SSPIF (PIR1<3>)
8
9
ACK
Transmitting Data
ACK
D7
1
SCL held low
while CPU
responds to SSPIF
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
9
P
cleared in software
BF (SSPSTAT<0>)
SSPBUF is written in software
From SSP interrupt
service routine
CKP (SSPCON<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)
 1998 Microchip Technology Inc.
DS30605A-page 59
PIC16C63A/65B/73B/74B
8.3.2
8.3.3
MASTER OPERATION
In multi-master operation, the interrupt generation on
the detection of the START and STOP conditions
allows the determination of when the bus is free. The
STOP (P) and START (S) bits are cleared from a reset
or when the SSP module is disabled. The STOP (P)
and START (S) bits will toggle based on the START and
STOP conditions. Control of the I 2C bus may be taken
when bit P (SSPSTAT<4>) is set, or the bus is idle and
both the S and P bits clear. When the bus is busy,
enabling the SSP Interrupt will generate the interrupt
when the STOP condition occurs.
Master operation is supported in firmware using interrupt generation on the detection of the START and
STOP conditions. The STOP (P) and START (S) bits
are cleared from a reset or when the SSP module is
disabled. The STOP (P) and START (S) bits will toggle
based on the START and STOP conditions. Control of
the I 2C bus may be taken when the P bit is set, or the
bus is idle and both the S and P bits are clear.
In master operation, the SCL and SDA lines are manipulated in firmware by clearing the corresponding
TRISC<4:3> bit(s). The output level is always low, irrespective of the value(s) in PORTC<4:3>. So when
transmitting data, a '1' data bit must have the
TRISC<4> bit set (input) and a '0' data bit must have
the TRISC<4> bit cleared (output). The same scenario
is true for the SCL line with the TRISC<3> bit.
In multi-master operation, the SDA line must be monitored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, these are:
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• Address Transfer
• Data Transfer
• START condition
• STOP condition
• Data transfer byte transmitted/received
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address transfer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be generated. If arbitration was lost during the data transfer
stage, the device will need to re-transfer the data at a
later time.
Master operation can be done with either the slave
mode idle (SSPM3:SSPM0 = 1011) or with the slave
active. When both master operation and slave modes
are used, the software needs to differentiate the
source(s) of the interrupt.
For more information on master operation, see AN554
- Software Implementation of I2C Bus Master.
TABLE 8-3:
Address
MULTI-MASTER OPERATION
For more information on master operation, see AN578
- Use of the SSP Module in the of I2C Multi-Master
Environment.
REGISTERS ASSOCIATED WITH I2C OPERATION
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0000 0000
0000 0000
0000 0000
0000 0000
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
uuuu uuuu
SSPADD Synchronous Serial Port (I2C mode) Address Register
0000 0000
0000 0000
SSPCON
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111
Name
Bit 7
Bit 6
Bit 5
Bit 4
0Bh, 8Bh
INTCON
GIE
PEIE
T0IE
INTE
0Ch
PIR1
(1)
ADIF
(1)
(1)
SSPIF CCP1IF TMR2IF TMR1IF
8Ch
PIE1
(1)
ADIE
(1)
(1)
SSPIE CCP1IE TMR2IE TMR1IE
13h
93h
14h
94h
SSPSTAT
87h
TRISC
WCOL
SMP
SSPOV SSPEN
CKE
D/A
CKP
P
SSPM3 SSPM2 SSPM1 SSPM0
S
R/W
PORTC Data Direction register
UA
BF
Value on
all other
resets
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.
Shaded cells are not used by SSP module in SPI mode.
Note 1: These bits are unimplemented, read as '0'.
DS30605A-page 60
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
9.0
UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The USART can be configured in the following modes:
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Communications Interface or SCI). The USART can be configured as a full duplex asynchronous system that can
communicate with peripheral devices such as CRT terminals and personal computers, or it can be configured
as a half duplex synchronous system that can communicate with peripheral devices such as A/D or D/A integrated circuits, Serial EEPROMs etc.
FIGURE 9-1:
Bit SPEN (RCSTA<7>), and bits TRISC<7:6>, have to
be set in order to configure pins RC6/TX/CK and RC7/
RX/DT as the Universal Synchronous Asynchronous
Receiver Transmitter.
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R-1
R/W-0
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
bit7
bit 7:
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
bit 6:
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5:
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4:
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3:
Unimplemented: Read as '0'
bit 2:
BRGH: High Baud Rate Select bit
Asynchronous mode
1 = High speed
0 = Low speed
Synchronous mode
Unused in this mode
bit 1:
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0:
TX9D: 9th bit of transmit data. Can be parity bit.
 1998 Microchip Technology Inc.
DS30605A-page 61
PIC16C63A/65B/73B/74B
FIGURE 9-2:
RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R-0
R-0
R-x
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 7:
SPEN: Serial Port Enable bit
1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6:
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5:
SREN: Single Receive Enable bit
Asynchronous mode
Don’t care
Synchronous mode - master
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave
Unused in this mode
bit 4:
CREN: Continuous Receive Enable bit
Asynchronous mode
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3:
Unimplemented: Read as '0'
bit 2:
FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1:
OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
bit 0:
RX9D: 9th bit of received data (Can be parity bit)
DS30605A-page 62
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
9.1
USART Baud Rate Generator (BRG)
EXAMPLE 9-1:
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In asynchronous
mode bit BRGH (TXSTA<2>) also controls the baud
rate. In synchronous mode bit BRGH is ignored.
Table 9-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in master mode (internal clock).
Desired Baud rate
CALCULATING BAUD
RATE ERROR
=Fosc / (64 (X + 1))
9600
=16000000 /(64 (X + 1))
X
=25.042 = 25
Calculated Baud Rate =16000000 / (64 (25 + 1))
Error
Given the desired baud rate and Fosc, the nearest integer value for the SPBRG register can be calculated
using the formula in Table 9-1. From this, the error in
baud rate can be determined.
=
9615
=
(Calculated Baud Rate-Desired Baud Rate)
Desired Baud Rate
=
(9615 - 9600) / 9600
=
0.16%
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
Example 9-1 shows the calculation of the baud rate
error for the following conditions:
FOSC = 16 MHz
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before outputting the new baud rate.
9.1.1
SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
TABLE 9-1:
BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1))
X = value in SPBRG (0 to 255)
Baud Rate= FOSC/(16(X+1))
NA
0
1
TABLE 9-2:
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Bit 6
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
SREN CREN —
FERR
OERR RX9D 0000 -00x
0000 -00x
0000 0000
0000 0000
Address
Name
Bit 7
Bit 5
Bit 4
98h
TXSTA
CSRC
TX9
TXEN
SYNC
18h
RCSTA
SPEN
99h
SPBRG
Baud Rate Generator Register
RX9
Bit 3
Value on all
other resets
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used by the BRG.
 1998 Microchip Technology Inc.
DS30605A-page 63
PIC16C63A/65B/73B/74B
TABLE 9-3:
BAUD RATES FOR SYNCHRONOUS MODE
FOSC = 20 MHz SPBRG
BAUD
RATE
(K)
KBAUD
%
16 MHz
value
%
(decimal) KBAUD
0.3
NA
-
-
NA
-
-
NA
-
-
NA
-
-
1.2
NA
-
-
NA
-
-
NA
-
-
NA
-
-
2.4
NA
-
-
NA
-
-
NA
-
-
NA
-
-
9.6
NA
-
-
NA
-
-
9.766
+1.73
255
9.622
+0.23
185
19.2
19.53
+1.73
255
19.23
+0.16
207
19.23
+0.16
129
19.24
+0.23
92
76.8
76.92
+0.16
64
76.92
+0.16
51
75.76
-1.36
32
77.82
+1.32
22
96
96.15
+0.16
51
95.24
-0.79
41
96.15
+0.16
25
94.20
-1.88
18
300
294.1
-1.96
16
307.69
+2.56
12
312.5
+4.17
7
298.3
-0.57
5
500
500
0
9
500
0
7
500
0
4
NA
-
-
HIGH
5000
-
0
4000
-
0
2500
-
0
1789.8
-
0
LOW
19.53
-
255
15.625
-
255
9.766
-
255
6.991
-
FOSC = 5.0688 MHz
255
%
0.3
NA
-
-
NA
-
-
NA
-
-
NA
-
-
0.303
+1.14
26
1.2
NA
-
-
NA
-
-
NA
-
-
1.202
+0.16
207
1.170
-2.48
6
2.4
NA
-
-
NA
-
-
NA
-
-
2.404
+0.16
103
NA
-
-
9.6
9.6
0
131
9.615
+0.16
103
9.622
+0.23
92
9.615
+0.16
25
NA
-
-
19.2
19.2
0
65
19.231
+0.16
51
19.04
-0.83
46
19.24
+0.16
12
NA
-
-
76.8
79.2
+3.13
15
76.923
+0.16
12
74.57
-2.90
11
83.34
+8.51
2
NA
-
-
96
97.48
+1.54
12
1000
+4.17
9
99.43
+3.57
8
NA
-
-
NA
-
-
300
316.8
+5.60
3
NA
-
-
298.3
-0.57
2
NA
-
-
NA
-
-
500
NA
-
-
NA
-
-
NA
-
-
NA
-
-
NA
-
-
HIGH
1267
-
0
100
-
0
894.9
-
0
250
-
0
8.192
-
0
LOW
4.950
-
255
3.906
-
255
3.496
-
255
0.9766
-
255
0.032
-
255
BAUD
RATE
(K)
%
SPBRG
1 MHz
value
%
(decimal) KBAUD
SPBRG
value
(decimal)
KBAUD
SPBRG KBAUD
SPBRG 3.579545 MHz
value
%
(decimal) KBAUD
SPBRG 7.15909 MHz
value
%
(decimal) KBAUD
BAUD
RATE
(K)
TABLE 9-4:
4 MHz
SPBRG
10 MHz
value
%
(decimal) KBAUD
SPBRG
32.768 kHz
value
%
(decimal) KBAUD
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 20 MHz SPBRG
%
16 MHz
value
(decimal)
%
SPBRG
value
(decimal)
10 MHz
%
SPBRG
value
(decimal)
7.15909 MHz
%
SPBRG
value
(decimal)
0.3
NA
-
-
NA
-
-
NA
-
-
NA
-
-
1.2
1.221
+1.73
255
1.202
+0.16
207
1.202
+0.16
129
1.203
+0.23
92
2.4
2.404
+0.16
129
2.404
+0.16
103
2.404
+0.16
64
2.380
-0.83
46
9.6
9.469
-1.36
32
9.615
+0.16
25
9.766
+1.73
15
9.322
-2.90
11
19.2
19.53
+1.73
15
19.23
+0.16
12
19.53
+1.73
7
18.64
-2.90
5
76.8
78.13
+1.73
3
83.33
+8.51
2
78.13
+1.73
1
NA
-
-
96
104.2
+8.51
2
NA
-
-
NA
-
-
NA
-
-
300
312.5
+4.17
0
NA
-
-
NA
-
-
NA
-
-
500
NA
-
-
NA
-
-
NA
-
-
NA
-
-
HIGH
312.5
-
0
250
-
0
156.3
-
0
111.9
-
0
LOW
1.221
-
255
0.977
-
255
0.6104
-
255
0.437
-
255
%
SPBRG
value
(decimal)
%
SPBRG
value
(decimal)
BAUD
RATE
(K)
SPBRG
value
(decimal)
FOSC = 5.0688 MHz
%
SPBRG
4 MHz
3.579545 MHz
%
SPBRG
value
(decimal)
1 MHz
32.768 kHz
%
SPBRG
value
(decimal)
0.3
0.31
+3.13
255
0.3005
-0.17
207
0.301
+0.23
185
0.300
+0.16
51
0.256
-14.67
1
1.2
1.2
0
65
1.202
+1.67
51
1.190
-0.83
46
1.202
+0.16
12
NA
-
-
2.4
2.4
0
32
2.404
+1.67
25
2.432
+1.32
22
2.232
-6.99
6
NA
-
-
9.6
9.9
+3.13
7
NA
-
-
9.322
-2.90
5
NA
-
-
NA
-
-
19.2
19.8
+3.13
3
NA
-
-
18.64
-2.90
2
NA
-
-
NA
-
-
76.8
79.2
+3.13
0
NA
-
-
NA
-
-
NA
-
-
NA
-
-
96
NA
-
-
NA
-
-
NA
-
-
NA
-
-
NA
-
-
300
NA
-
-
NA
-
-
NA
-
-
NA
-
-
NA
-
-
500
NA
-
-
NA
-
-
NA
-
-
NA
-
-
NA
-
-
HIGH
79.2
-
0
62.500
-
0
55.93
-
0
15.63
-
0
0.512
-
0
LOW
0.3094
-
255
3.906
-
255
0.2185
-
255
0.0610
-
255
0.0020
-
255
DS30605A-page 64
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 9-5:
BAUD
RATE
(K)
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 20 MHz
%
SPBRG
value
(decimal)
16 MHz
%
SPBRG
value
(deci-
10 MHz
%
SPBRG
value
(decimal)
7.16 MHz
%
SPBRG
value
(deci-
9.6
9.615
+0.16
129
9.615
+0.16
103
9.615
+0.16
64
9.520
-0.83
46
19.2
19.230
+0.16
64
19.230
+0.16
51
18.939
-1.36
32
19.454
+1.32
22
38.4
37.878
-1.36
32
38.461
+0.16
25
39.062
+1.7
15
37.286
-2.90
11
57.6
56.818
-1.36
21
58.823
+2.12
16
56.818
-1.36
10
55.930
-2.90
7
115.2
113.636
-1.36
10
111.111
-3.55
8
125
+8.51
4
111.860
-2.90
3
250
250
0
4
250
0
3
NA
-
-
NA
-
-
625
625
0
1
NA
-
-
625
0
0
NA
-
-
1250
1250
0
0
NA
-
-
NA
-
-
NA
-
-
BAUD
RATE
(K)
FOSC = 5.068
%
SPBRG
value
(decimal)
%
SPBRG
value
(decimal)
%
SPBRG
value
(decimal)
4 MHz
3.579 MHz
%
SPBRG
value
(decimal)
1 MHz
32.768 kHz
%
SPBRG
value
(decimal)
9.6
9.6
0
32
NA
-
-
9.727
+1.32
22
8.928
-6.99
6
NA
-
-
19.2
18.645
-2.94
16
1.202
+0.17
207
18.643
-2.90
11
20.833
+8.51
2
NA
-
-
38.4
39.6
+3.12
7
2.403
+0.13
103
37.286
-2.90
5
31.25
-18.61
1
NA
-
-
57.6
52.8
-8.33
5
9.615
+0.16
25
55.930
-2.90
3
62.5
+8.51
0
NA
-
-
115.2
105.6
-8.33
2
19.231
+0.16
12
111.860
-2.90
1
NA
-
-
NA
-
-
250
NA
-
-
NA
-
-
223.721 -10.51
0
NA
-
-
NA
-
-
625
NA
-
-
NA
-
-
NA
-
-
NA
-
-
NA
-
-
1250
NA
-
-
NA
-
-
NA
-
-
NA
-
-
NA
-
-
 1998 Microchip Technology Inc.
DS30605A-page 65
PIC16C63A/65B/73B/74B
9.2
USART Asynchronous Mode
(occurs in one TCY), the TXREG register is empty and
flag bit TXIF (PIR1<4>) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
( PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicated the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. Status bit TRMT
is a read only bit which is set when the TSR register is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR register is empty.
In this mode, the USART uses standard non-return-tozero (NRZ) format (one start bit, eight or nine data bits
and one stop bit). The most common data format is
8-bits. An on-chip dedicated 8-bit baud rate generator
can be used to derive standard baud rate frequencies
from the oscillator. The USART transmits and receives
the LSb first. The USART’s transmitter and receiver are
functionally independent, but use the same data format
and baud rate. The baud rate generator produces a
clock, either x16 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA<2>). Parity is not supported by
the hardware, but can be implemented in software (and
stored as the ninth data bit). Asynchronous mode is
stopped during SLEEP.
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
Note 2: Flag bit TXIF is set when enable bit TXEN
is set.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the following important elements:
Steps to follow when setting up an asynchronous transmission:
•
•
•
•
1.
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
9.2.1
2.
3.
USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in
Figure 9-3. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
FIGURE 9-3:
4.
5.
6.
7.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 9.1)
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set transmit
bit TX9.
Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts transmission).
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG register
TXIE
8
MSb
LSb
• • •
(8)
Pin Buffer
and Control
0
TSR register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
DS30605A-page 66
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 9-4:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
Start Bit
Bit 0
Bit 1
TXIF bit
(Transmit buffer
reg. empty flag)
Stop Bit
WORD 1
Transmit Shift Reg
TRMT bit
(Transmit shift
reg. empty flag)
FIGURE 9-5:
Bit 7/8
WORD 1
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
TXIF bit
(interrupt reg. flag)
Word 2
Start Bit
TRMT bit
(Transmit shift
reg. empty flag)
Bit 0
Bit 1
WORD 1
Bit 7/8
WORD 1
Transmit Shift Reg.
Stop Bit
Start Bit
WORD 2
Bit 0
WORD 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 9-6:
Address Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0Ch
PIR1
PSPIF(1)
ADIF(2) RCIF
TXIF
18h
RCSTA
SPEN
RX9
CREN —
19h
TXREG USART Transmit Register
8Ch
PIE1
PSPIE(1)
SREN
ADIE(2) RCIE
TXIE
Bit 2
SSPIF CCP1IF
FERR
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
Resets
TMR2IF
TMR1IF
0000 0000
0000 0000
OERR
RX9D
0000 -00x
0000 -00x
SSPIE CCP1IE TMR2IE
TMR1IE
0000 0000
0000 0000
0000 0000
0000 0000
0000 -010 0000 -010
TXSTA CSRC
TX9
TXEN
SYNC —
BRGH
TRMT
TX9D
0000 0000 0000 0000
99h
SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission.
Note 1: PORTD and PORTE not implemented on the PIC16C63A/73B, maintain as ’0’.
2: A/D not implemented on the PIC16C63A/65B, maintain as ’0’.
98h
 1998 Microchip Technology Inc.
DS30605A-page 67
PIC16C63A/65B/73B/74B
9.2.2
3.
USART ASYNCHRONOUS RECEIVER
The receiver block diagram is shown in Figure 9-6. The
data is received on the RC7/RX/DT pin and drives the
data recovery block. The data recovery block is actually
a high speed shifter operating at x16 times the baud
rate, whereas the main receive serial shifter operates
at the bit rate or at FOSC.
4.
5.
6.
7.
Steps to follow when setting up an Asynchronous
Reception:
1.
2.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 9.1).
Enable the asynchronous serial port by clearing
bit SYNC, and setting bit SPEN.
FIGURE 9-6:
8.
9.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
Enable the reception by setting bit CREN.
Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable
bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
enable bit CREN.
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
SPBRG
÷ 64
or
÷ 16
Baud Rate Generator
RSR register
MSb
Stop (8)
• • •
7
1
LSb
0 Start
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG register
FIFO
8
RCIF
Interrupt
Data Bus
RCIE
FIGURE 9-7:
ASYNCHRONOUS RECEPTION
RX (pin)
Rcv shift
reg
Rcv buffer reg
Read Rcv
buffer reg
RCREG
Start
bit
bit0
bit1
bit7/8 Stop
bit
Start
bit
WORD 1
RCREG
bit0
bit7/8
Stop
bit
Start
bit
bit7/8
Stop
bit
WORD 2
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
DS30605A-page 68
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 9-7:
Address Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
Resets
0Ch
PIR1
PSPIF(1)
ADIF(2)
RCIF
TXIF
SSPIF CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
18h
RCSTA
SPEN
RX9
SREN
CREN
—
OERR
RX9D
0000 -00x
0000 -00x
FERR
1Ah
RCREG USART Receive Register
0000 0000
0000 0000
8Ch
PIE1
PSPIE(1)
ADIE(2) RCIE
TXIE
SSPIE CCP1IE TMR2IE
TMR1IE
0000 0000
0000 0000
98h
TXSTA
CSRC
TX9
SYNC
—
TX9D
0000 -010
0000 -010
99h
SPBRG
Baud Rate Generator Register
0000 0000
0000 0000
TXEN
BRGH
TRMT
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B, always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B, always maintain these bits clear.
 1998 Microchip Technology Inc.
DS30605A-page 69
PIC16C63A/65B/73B/74B
9.3
USART Synchronous Master Mode
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory so it is not
available to the user.
In Synchronous Master mode, the data is transmitted in
a half-duplex manner, i.e. transmission and reception
do not occur at the same time. When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition, enable bit SPEN (RCSTA<7>) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
9.3.1
Steps to follow when setting up a Synchronous Master
Transmission:
USART SYNCHRONOUS MASTER
TRANSMISSION
1.
The USART transmitter block diagram is shown in
Figure 9-3. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and interrupt bit TXIF (PIR1<4>) is set. The interrupt can be
TABLE 9-8:
Address
Name
0Ch
18h
2.
3.
4.
5.
6.
7.
Initialize the SPBRG register for the appropriate
baud rate (Section 9.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREG register.
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other Resets
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
Bit 7
Bit 6
Bit 5
Bit 4
PIR1
PSPIF(1)
ADIF(2)
RCIF
RCSTA
SPEN
RX9
SREN
19h
TXREG
USART Transmit Register
8Ch
PIE1
PSPIE(1)
ADIE(2)
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
99h
SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B, always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B, always maintain these bits clear.
DS30605A-page 70
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 9-8:
SYNCHRONOUS TRANSMISSION
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4
RC7/RX/DT pin
Bit 0
Bit 1
Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
Bit 2
Bit 7
Bit 0
WORD 1
Bit 1
WORD 2
Bit 7
RC6/TX/CK pin
Write to
TXREG reg
Write word1
Write word2
TXIF bit
(Interrupt flag)
TRMT
TRMT bit
TXEN bit
'1'
'1'
Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words
FIGURE 9-9:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit0
bit1
bit2
bit6
bit7
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
 1998 Microchip Technology Inc.
DS30605A-page 71
PIC16C63A/65B/73B/74B
9.3.2
3.
4.
Ensure bits CREN and SREN are clear.
If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
USART SYNCHRONOUS MASTER
RECEPTION
Once synchronous mode is selected, reception is
enabled by setting either enable bit SREN (RCSTA<5>)
or enable bit CREN (RCSTA<4>). Data is sampled on
the RC7/RX/DT pin on the falling edge of the clock. If
enable bit SREN is set, then only a single word is
received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
Steps to follow when setting up a Synchronous Master
Reception:
1.
Initialize the SPBRG register for the appropriate
baud rate. (Section 9.1)
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
2.
TABLE 9-9:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Address
Name
Bit 7
Bit 6
Bit 5
0Ch
PIR1
PSPIF(1)
ADIF(2)
RCIF
18h
RCSTA
SPEN
RX9
SREN
1Ah
RCREG
USART Receive Register
8Ch
PIE1
PSPIE(1)
ADIE(2)
RCIE
98h
TXSTA
CSRC
TX9
TXEN
Bit 4
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other Resets
Bit 3
Bit 2
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
99h
SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B. Always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B. Allways maintain these bits clear.
FIGURE 9-10: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
RC6/TX/CK pin
Write to
bit SREN
SREN bit
CREN bit '0'
'0'
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRGH = '0'.
DS30605A-page 72
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
9.4
USART Synchronous Slave Mode
Synchronous slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
9.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the synchronous master and slave
modes are identical, except in the case of the SLEEP
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt
vector (0004h).
9.4.2
The operation of the synchronous master and slave
modes is identical except in the case of the SLEEP
mode and bit SREN, which is a "don't care" in slave
mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
Steps to follow when setting up a Synchronous Slave
Reception:
1.
2.
3.
4.
5.
6.
Steps to follow when setting up a Synchronous Slave
Transmission:
1.
2.
3.
4.
5.
6.
7.
Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREG register.
 1998 Microchip Technology Inc.
USART SYNCHRONOUS SLAVE
RECEPTION
7.
8.
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is complete. An interrupt will be generated if enable bit
RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
DS30605A-page 73
PIC16C63A/65B/73B/74B
TABLE 9-10:
Address
Name
0Ch
18h
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other Resets
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
TMR1IE
0000 0000
0000 0000
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
Bit 7
Bit 6
Bit 5
Bit 4
PIR1
PSPIF(1)
ADIF(2)
RCIF
RCSTA
SPEN
RX9
SREN
19h
TXREG
USART Transmit Register
8Ch
PIE1
PSPIE(1)
ADIE(2)
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
99h
SPBRG
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B. Always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B. Always maintain these bits clear.
TABLE 9-11:
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address
Name
Bit 7
Bit 6
0Ch
PIR1
PSPIF(1)
ADIF(2)
RCIF
18h
RCSTA
SPEN
1Ah
RCREG
USART Receive Register
8Ch
PIE1
PSPIE(1)
98h
TXSTA
CSRC
RX9
Bit 5
ADIE(2)
TX9
SREN
RCIE
TXEN
Bit 4
TXIF
CREN
TXIE
SYNC
Value on
POR,
BOR
Value on all
other Resets
Bit 3
Bit 2
Bit 1
Bit 0
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
TMR1IE
0000 0000
0000 0000
TX9D
0000 -010
0000 -010
—
SSPIE
—
FERR
CCP1IE
BRGH
OERR
TMR2IE
TRMT
0000 0000
0000 0000
99h
SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B. Always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B. Always maintain these bits clear.
DS30605A-page 74
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
10.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
Additional information on the A/D module is available in
the PICmicro Mid-Range Reference Manual,
(DS33023).
This section applies to the PIC16C73B and
PIC16C74B only. The analog-to-digital (A/D) converter
module has five inputs for the PIC16C73B, and eight for
the PIC16C74B.
The A/D allows conversion of an analog input signal to
a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter). The output
of the sample and hold is the input into the converter,
which generates the result via successive approximation. The analog reference voltage is software selectable to either the device’s positive supply voltage (VDD)
or the voltage level on the RA3/AN3/VREF pin.
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To operate in sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The A/D module has three registers. These registers
are:
• A/D Result Register (ADRES)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off and any
conversion is aborted.
The ADCON0 register, shown in Figure 10-1, controls
the operation of the A/D module. The ADCON1 register, shown in Figure 10-2, configures the functions of
the port pins. The port pins can be configured as analog inputs (RA3 can also be a voltage reference) or as
digital I/O.
FIGURE 10-1: ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0 R/W-0
ADCS1 ADCS0
bit7
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
GO/DONE
U-0
—
R/W-0
ADON
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from an internal RC oscillator)
bit 5-3: CHS2:CHS0: Analog Channel Select bits
000 = channel 0, (RA0/AN0)
001 = channel 1, (RA1/AN1)
010 = channel 2, (RA2/AN2)
011 = channel 3, (RA3/AN3)
100 = channel 4, (RA5/AN4)
bit 2:
GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion
is complete)
bit 1:
Unimplemented: Read as '0'
bit 0:
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shutoff and consumes no operating current
 1998 Microchip Technology Inc.
DS30605A-page 75
PIC16C63A/65B/73B/74B
FIGURE 10-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0
—
bit7
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
PCFG2
R/W-0
PCFG1
R/W-0
PCFG0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented
bit, read as ‘0’
- n = Value at POR reset
bit 7-3: Unimplemented: Read as '0'
bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits
PCFG2:PCFG0
000
001
010
011
100
101
11x
RA0
A
A
A
A
A
A
D
RA1
A
A
A
A
A
A
D
RA2
A
A
A
A
D
D
D
RA5
A
A
A
A
D
D
D
RA3
A
VREF
A
VREF
A
VREF
D
VREF
VDD
RA3
VDD
RA3
VDD
RA3
VDD
A = Analog input
D = Digital I/O
DS30605A-page 76
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
2.
The ADRES register contains the result of the A/D conversion. When the A/D conversion is complete, the
result is loaded into the ADRES register, the GO/DONE
bit (ADCON0<2>) is cleared, and A/D interrupt flag bit
ADIF is set. The block diagram of the A/D module is
shown in Figure 10-3.
3.
4.
The value that is in the ADRES register is not modified
for a Power-on Reset. The ADRES register will contain
unknown data after a Power-on Reset.
5.
After the A/D module has been configured as desired,
the selected channel must be acquired before the conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 10.1.
After this acquisition time has elapsed the A/D conversion can be started. The following steps should be followed for doing an A/D conversion:
1.
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
6.
7.
Configure the A/D module:
• Configure analog pins / voltage reference /
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
• Waiting for the A/D interrupt
Read A/D Result register (ADRES), clear bit
ADIF if required.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
FIGURE 10-3: A/D BLOCK DIAGRAM
CHS2:CHS0
111
110
101
RE2/AN7(1)
RE1/AN6(1)
RE0/AN5(1)
100
RA5/AN4
VIN
011
(Input voltage)
RA3/AN3/VREF
010
RA2/AN2
A/D
Converter
001
RA1/AN1
VDD
000
RA0/AN0
000 or
010 or
100
VREF
(Reference
voltage)
001 or
011 or
101
PCFG2:PCFG0
Note 1: Available on the PIC16C74B only.
 1998 Microchip Technology Inc.
DS30605A-page 77
PIC16C63A/65B/73B/74B
10.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 10-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD). The
source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum
recommended impedance for analog sources is 10
kΩ. After the analog input channel is selected
(changed) this acquisition must be done before the
conversion can be started.
To calculate the minimum acquisition time, TACQ, see
the PICmicro Mid-Range Reference Manual,
(DS33023). This equation calculates the acquisition
time to within 1/2 LSb error (512 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified accuracy.
Note:
When the conversion is started, the holding capacitor is disconnected from the
input pin.
FIGURE 10-4: ANALOG INPUT MODEL
VDD
Rs
ANx
CPIN
5 pF
VA
Sampling
Switch
VT = 0.6V
VT = 0.6V
RIC ≤ 1k
SS RSS
CHOLD
= DAC capacitance
= 51.2 pF
I leakage
± 500 nA
VSS
Legend CPIN
= input capacitance
= threshold voltage
VT
I leakage = leakage current at the pin due to
various junctions
RIC
SS
CHOLD
DS30605A-page 78
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
6V
5V
VDD 4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
( kΩ )
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
10.2
Selecting the A/D Conversion Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.5TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selectable. The four possible options for TAD are:
•
•
•
•
2TOSC
8TOSC
32TOSC
Internal RC oscillator
10.3
Configuring Analog Port Pins
The ADCON1, TRISA, and TRISE registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be
converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
Table 10-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins configured as digital inputs, will convert an analog input. Analog levels on a digitally
configured input will not affect the conversion accuracy.
Note 2: Analog levels on any pin that is defined as
a digital input (including the AN4:AN0
pins) may cause the input buffer to consume current that is out of the devices
specification.
TABLE 10-1:
TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD)
Operation
ADCS1:ADCS0
2TOSC
00
8TOSC
01
32TOSC
10
Device Frequency
20 MHz
100
ns(2)
ns(2)
400
1.6 µs
5 MHz
ns(2)
400
1.6 µs
6.4 µs
333.33 kHz
1.6 µs
6 µs
6.4 µs
24 µs(3)
25.6
µs(3)
96 µs(3)
2-6
2-6
2 - 6 µs(1)
2-6
Shaded cells are outside of recommended range.
The RC source has a typical TAD time of 4 µs.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for
sleep operation only.
5: For extended voltage devices (LC), please refer to Electrical Specifications section.
RC(5)
11
µs(1,4)
µs(1,4)
1.25 MHz
µs(1,4)
Legend:
Note 1:
2:
3:
4:
 1998 Microchip Technology Inc.
DS30605A-page 79
PIC16C63A/65B/73B/74B
10.4
Note:
10.5
A/D Conversions
GO/DONE bit will be set, starting the A/D conversion,
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
with minimal software overhead (moving the ADRES to
the desired location). The appropriate analog input
channel must be selected and the minimum acquisition
done before the “special event trigger” sets the
GO/DONE bit (starts a conversion).
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Use of the CCP Trigger
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as 1011 and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
TABLE 10-2:
Address
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
SUMMARY OF A/D REGISTERS
Name
0Bh,8Bh INTCON
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
Resets
INTF
RBIF
0000 000x
0000 000u
GIE
PEIE
T0IE
INTE
RBIE
T0IF
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF TMR1IF 0000 0000
0000 0000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE TMR1IE 0000 0000
0000 0000
0Dh
PIR2
—
—
—
—
—
—
—
CCP2IF ---- ---0
8Dh
PIE2
—
—
—
—
—
—
—
CCP2IE ---- ---0
---- ---0
1Eh
ADRES
A/D Result Register
xxxx xxxx
uuuu uuuu
1Fh
ADCON0
ADCS1
ADCS0
0000 00-0
0000 00-0
9Fh
ADCON1
—
—
—
—
05h
PORTA
—
—
RA5
RA4
85h
TRISA
—
—
09h
PORTE
—
—
—
—
—
89h
TRISE
IBF
OBF
IBOV
PSPMODE
—
CHS2
CHS1
CHS0
—
GO/DON
E
PCFG2
PCFG1
RA3
RA2
RA1
RA0
RE2
RE1
RE0
—
ADON
---- ---0
PCFG0 ---- -000
---- -000
--0x 0000
--0u 0000
--11 1111
--11 1111
---- -xxx
---- -uuu
0000 -111
0000 -111
PORTA Data Direction Register
PORTE Data Direction Bits
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC6C73B. Always maintain these bits clear.
DS30605A-page 80
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
11.0
SPECIAL FEATURES OF THE
CPU
other is the Power-up Timer (PWRT), which provides a
fixed delay on power-up only, designed to keep the part
in reset while the power supply stabilizes. With these
two timers on-chip, most applications need no external
reset circuitry.
The PIC16C63A/65B/73B/74B devices have a host of
features intended to maximize system reliability, minimize cost through elimination of external components,
provide power saving operating modes and offer code
protection. These are:
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external reset, Watchdog Timer Wake-up or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost, while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
• OSC Selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-circuit serial programming
Additional information on special features is available in
the PICmicro Mid-Range Reference Manual,
(DS33023).
11.1
Configuration Bits
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in program memory location 2007h.
These devices have a Watchdog Timer which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in reset until the crystal oscillator is stable. The
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h 3FFFh), which can be accessed only during programming.
FIGURE 11-1: CONFIGURATION WORD
CP1
CP0
CP1
CP0
CP1
CP0
—
BODEN
CP1
CP0
bit13
PWRTE
WDTE
FOSC1
FOSC0
bit0
bit 13-8
5-4:
CP1:CP0: Code Protection bits (2)
11 = Code protection off
10 = Upper half of program memory code protected
01 = Upper 3/4th of program memory code protected
00 = All memory is code protected
bit 7:
Unimplemented: Read as '1'
bit 6:
BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3:
PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1:
2:
Register:CONFIG
Address2007h
Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
 1998 Microchip Technology Inc.
DS30605A-page 81
PIC16C63A/65B/73B/74B
11.2
Oscillator Configurations
11.2.1
OSCILLATOR TYPES
TABLE 11-1:
Ranges Tested:
The PIC16CXXX can be operated in four different oscillator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
•
•
•
•
LP
XT
HS
RC
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
11.2.2
FIGURE 11-2: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
RF(3)
OSC2
Note1:
2:
3:
To
internal
logic
SLEEP
RS(2)
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
FIGURE 11-3: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
OSC1
PIC16CXXX
Open
DS30605A-page 82
OSC2
OSC2
68 - 100 pF
15 - 68 pF
15 - 68 pF
10 - 68 pF
10 - 22 pF
Panasonic EFO-A455K04B
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
Murata Erie CSA16.00MX
± 0.3%
± 0.5%
± 0.5%
± 0.5%
± 0.5%
All resonators used did not have built-in capacitors.
TABLE 11-2:
Osc Type
LP
XT
HS
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
Crystal
Freq
Cap. Range
C1
Cap. Range
C2
33 pF
32 kHz
33 pF
200 kHz
15 pF
15 pF
200 kHz
47-68 pF
47-68 pF
1 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
8 MHz
15-33 pF
15-33 pF
20 MHz
15-33 pF
15-33 pF
These values are for design guidance only. See
notes at bottom of page.
PIC16CXXX
See Table 11-1 and Table 11-2 for recommended values of C1 and C2.
A series resistor (RS) may be required for
AT strip cut crystals.
RF varies with the crystal chosen.
Clock from
ext. system
OSC1
68 - 100 pF
15 - 68 pF
15 - 68 pF
10 - 68 pF
10 - 22 pF
Resonators Used:
OSC1
XTAL
Freq
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
These values are for design guidance only. See
notes at bottom of page.
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 11-2). The
PIC16CXXX oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can
have an external clock source to drive the OSC1/
CLKIN pin (Figure 11-3).
C2(1)
Mode
XT
HS
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
C1(1)
CERAMIC RESONATORS
Crystals Used
32 kHz
Epson C-001R32.768K-A
± 20 PPM
200 kHz
STD XTL 200.000KHz
± 20 PPM
1 MHz
ECS ECS-10-13-1
± 50 PPM
4 MHz
ECS ECS-40-20-1
± 50 PPM
8 MHz
EPSON CA-301 8.000M-C
± 30 PPM
20 MHz
EPSON CA-301 20.000M-C
± 30 PPM
Note 1: Recommended values of C1 and C2 are
identical to the ranges tested (Table 11-1).
2: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
3: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropriate values of external components.
4: Rs may be required in HS mode, as well as
XT mode, to avoid overdriving crystals with
low drive level specification.
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
11.2.3
11.3
RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C components used. Figure 11-4 shows how the R/C combination is connected to the PIC16CXXX.
FIGURE 11-4: RC OSCILLATOR MODE
VDD
Rext
OSC1
Cext
Internal
clock
PIC16CXXX
VSS
Fosc/4
Recommended values:
OSC2/CLKOUT
3 kΩ ≤ Rext ≤ 100 kΩ
Cext > 20pF
 1998 Microchip Technology Inc.
Reset
The PIC16CXXX differentiates between various kinds
of reset:
•
•
•
•
•
•
Power-on Reset (POR)
MCLR reset during normal operation
MCLR reset during SLEEP
WDT Reset (during normal operation)
WDT Wake-up (during SLEEP)
Brown-out Reset (BOR)
Some registers are not affected in any reset condition.
Their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR reset during SLEEP and Brownout Reset (BOR). They are not affected by a WDT
Wake-up, which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared differently in different reset situations as indicated in
Table 11-4. These bits are used in software to determine the nature of the reset. See Table 11-6 for a full
description of reset states of all registers.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 11-5.
The PICmicros have a MCLR noise filter in the MCLR
reset path. The filter will detect and ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
DS30605A-page 83
PIC16C63A/65B/73B/74B
FIGURE 11-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
WDT
Module
SLEEP
WDT
Time-out
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset
S
BODEN
OST/PWRT
OST
Chip_Reset
R
10-bit Ripple counter
Q
OSC1
(1)
On-chip
RC OSC
PWRT
10-bit Ripple counter
Enable PWRT
Enable OST
Note 1:
This is a separate oscillator from the RC oscillator of the CLKIN pin.
DS30605A-page 84
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
11.4
Power-On Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will eliminate
external RC components usually needed to create a
Power-on Reset. A maximum rise time for VDD is specified (parameter D004). For a slow rise time, see
Figure 11-6.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must
be held in reset until the operating conditions are met.
Brown-out Reset may be used to meet the start-up conditions.
FIGURE 11-6: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
VDD
D
11.5
The Power-up Timer provides a fixed nominal time-out
(parameter #33) on power-up only, from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in reset as long as the PWRT is active.
The PWRT’s time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/disable the PWRT.
The power-up time delay will vary from chip to chip due
to VDD, temperature and process variation. See DC
parameters for details.
11.6
R1
MCLR
C
PIC16CXXX
Note 1: External Power-on Reset circuit is required
only if VDD power-up slope is too slow. The
diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 kΩ is recommended to make sure
that voltage drop across R does not violate
the device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor
C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
 1998 Microchip Technology Inc.
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
11.7
R
Power-up Timer (PWRT)
Brown-Out Reset (BOR)
A configuration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below parameter D005 for greater
than parameter #35, the brown-out situation will reset
the chip. A reset may not occur if VDD falls below
parameter D005 for less than parameter #35. The chip
will remain in Brown-out Reset until VDD rises above
BVDD. The Power-up Timer will then be invoked and will
keep the chip in RESET an additional time delay
(parameter #33). If VDD drops below BVDD while the
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above BVDD, the Power-up Timer
will execute the additional time delay. The Power-up
Timer should always be enabled when Brown-out
Reset is enabled.
DS30605A-page 85
PIC16C63A/65B/73B/74B
11.8
Time-out Sequence
11.9
On power-up, the time-out sequence is as follows: First
PWRT time-out is invoked after the POR time delay has
expired. Then OST is activated. The total time-out will
vary based on oscillator configuration and the status of
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no time-out at all. Figure 11-7,
Figure 11-8, Figure 11-9 and Figure 11-10 depict timeout sequences on power-up.
The Power Control/Status Register, PCON, has up to
two bits, depending upon the device.
Bit0 is Brown-out Reset Status bit, BOR. If the BODEN
configuration bit is set, BOR is ’1’ on Power-on Reset.
If the BODEN configuration bit is clear, BOR is
unknown on Power-on Reset.
The BOR status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (the
BODEN configuration bit is clear). BOR must then be
set by the user and checked on subsequent resets to
see if it is clear, indicating a brown-out has occurred.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 11-9). This is useful for testing purposes or to
synchronize more than one PIC16CXXX device operating in parallel.
Bit1 is POR (Power-on Reset Status bit). It is cleared
on a Power-on Reset and unaffected otherwise. The
user must set this bit following a Power-on Reset.
Table 11-5 shows the reset conditions for some special
function registers, while Table 11-6 shows the reset
conditions for all the registers.
TABLE 11-3:
TIME-OUT IN VARIOUS SITUATIONS
Power-up
Oscillator Configuration
Brown-out
Wake-up from
SLEEP
1024TOSC
72 ms + 1024TOSC
1024TOSC
—
72 ms
—
PWRTE = 0
PWRTE = 1
XT, HS, LP
72 ms + 1024TOSC
RC
72 ms
TABLE 11-4:
Power Control/Status Register
(PCON)
STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
x
1
1
Power-on Reset
0
x
0
x
Illegal, TO is set on POR
0
x
x
0
Illegal, PD is set on POR
1
0
1
1
Brown-out Reset
1
1
0
1
WDT Reset
1
1
0
0
WDT Wake-up
1
1
u
u
MCLR Reset during normal operation
1
1
1
0
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 11-5:
RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
000h
0001 1xxx
---- --0x
MCLR Reset during normal operation
000h
000u uuuu
---- --uu
MCLR Reset during SLEEP
000h
0001 0uuu
---- --uu
Condition
Power-on Reset
WDT Reset
WDT Wake-up
Brown-out Reset
Interrupt wake-up from SLEEP
000h
0000 1uuu
---- --uu
PC + 1
uuu0 0uuu
---- --uu
000h
0001 1uuu
---- --u0
PC + 1(1)
uuu1 0uuu
---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.
Note 1:
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
DS30605A-page 86
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 11-6:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
uuuu uuuu
W
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
INDF
63A
65B
73B
74B
N/A
N/A
N/A
TMR0
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
63A
65B
73B
74B
0000h
0000h
PC + 1(2)
STATUS
63A
65B
73B
74B
0001 1xxx
000q quuu(3)
uuuq quuu(3)
FSR
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA(4)
63A
65B
73B
74B
--0x 0000
--0u 0000
--uu uuuu
PORTB(5)
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC(5)
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTD(5)
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTE(5)
63A
65B
73B
74B
---- -xxx
---- -uuu
---- -uuu
PCLATH
63A
65B
73B
74B
---0 0000
---0 0000
---u uuuu
INTCON
63A
65B
73B
74B
0000 000x
0000 000u
uuuu uuuu(1)
63A
65B
73B
74B
--00 0000
--00 0000
--uu uuuu(1)
63A
65B
73B
74B
-000 0000
-000 0000
-uuu uuuu(1)
63A
65B
73B
74B
0-00 0000
0-00 0000
u-uu uuuu(1)
63A
65B
73B
74B
0000 0000
0000 0000
uuuu uuuu(1)
63A
65B
73B
74B
---- ---0
---- ---0
---- ---u(1)
PIR1
PIR2
TMR1L
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
63A
65B
73B
74B
--00 0000
--uu uuuu
--uu uuuu
TMR2
63A
65B
73B
74B
0000 0000
0000 0000
uuuu uuuu
T2CON
63A
65B
73B
74B
-000 0000
-000 0000
-uuu uuuu
SSPBUF
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPCON
63A
65B
73B
74B
0000 0000
0000 0000
uuuu uuuu
CCPR1L
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1H
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
63A
65B
73B
74B
--00 0000
--00 0000
--uu uuuu
RCSTA
63A
65B
73B
74B
0000 -00x
0000 -00x
uuuu -uuu
TXREG
63A
65B
73B
74B
0000 0000
0000 0000
uuuu uuuu
RCREG
63A
65B
73B
74B
0000 0000
0000 0000
uuuu uuuu
CCPR2L
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2H
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON
63A
65B
73B
74B
0000 0000
0000 0000
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 11-5 for reset value for specific condition.
4: On any device reset, these pins are configured as inputs.
5: This is the value that will be in the port output latch.
 1998 Microchip Technology Inc.
DS30605A-page 87
PIC16C63A/65B/73B/74B
TABLE 11-6:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.’d)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
ADRES
63A
65B
73B
74B
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
63A
65B
73B
74B
0000 00-0
0000 00-0
uuuu uu-u
OPTION_REG
63A
65B
73B
74B
1111 1111
1111 1111
uuuu uuuu
TRISA
63A
65B
73B
74B
--11 1111
--11 1111
--uu uuuu
TRISB
63A
65B
73B
74B
1111 1111
1111 1111
uuuu uuuu
TRISC
63A
65B
73B
74B
1111 1111
1111 1111
uuuu uuuu
TRISD
63A
65B
73B
74B
1111 1111
1111 1111
uuuu uuuu
TRISE
63A
65B
73B
74B
0000 -111
0000 -111
uuuu -uuu
63A
65B
73B
74B
0000 -000
0000 -000
uuuu -uuu
63A
65B
73B
74B
--00 0000
--00 0000
--uu uuuu
63A
65B
73B
74B
0-00 0000
0-00 0000
u-uu uuuu
63A
65B
73B
74B
-000 0000
-000 0000
-uuu uuuu
63A
65B
73B
74B
0000 0000
0000 0000
uuuu uuuu
PIE2
63A
65B
73B
74B
---- ---0
---- ---0
---- ---u
PCON
63A
65B
73B
74B
---- --0q
---- --uq
---- --uq
PR2
63A
65B
73B
74B
1111 1111
1111 1111
1111 1111
SSPADD
63A
65B
73B
74B
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
63A
65B
73B
74B
0000 0000
0000 0000
uuuu uuuu
TXSTA
63A
65B
73B
74B
0000 -010
0000 -010
uuuu -uuu
SPBRG
63A
65B
73B
74B
0000 0000
0000 0000
uuuu uuuu
ADCON1
63A
65B
73B
74B
---- -000
---- -000
---- -uuu
PIE1
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 11-5 for reset value for specific condition.
4: On any device reset, these pins are configured as inputs.
5: This is the value that will be in the port output latch.
FIGURE 11-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS30605A-page 88
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 11-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 11-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 11-10: SLOW RISE TIME (MCLR TIED TO VDD)
5V
VDD
1V
0V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
 1998 Microchip Technology Inc.
DS30605A-page 89
PIC16C63A/65B/73B/74B
11.10
Interrupts
The PIC16CXX family has up to 12 sources of interrupt.
The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
Note:
Individual interrupt flag bits are set regardless of the status of their corresponding
mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register.
The peripheral interrupt flags are contained in the special function registers PIR1 and PIR2. The corresponding interrupt enable bits are contained in special
function registers PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function register INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt flag bits are set regardless of the status of
their corresponding mask bit or the GIE bit.
FIGURE 11-11: INTERRUPT LOGIC
PSPIF
PSPIE
ADIF
ADIE
Wake-up (If in SLEEP mode)
T0IF
T0IE
RCIF
RCIE
INTF
INTE
TXIF
TXIE
SSPIF
SSPIE
Interrupt to CPU
RBIF
RBIE
PEIE
CCP1IF
CCP1IE
GIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
The following table shows which devices have which interrupts.
T0IF
INTF
RBIF
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
CCP2IF
PIC16C63A
Device
Yes
Yes
Yes
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PIC16C65B
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PIC16C73B
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PIC16C74B
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DS30605A-page 90
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
11.10.1 INT INTERRUPT
11.11
External interrupt on RB0/INT pin is edge triggered;
either rising if bit INTEDG (OPTION_REG<6>) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up.
See Section 11.13 for details on SLEEP mode.
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key registers during an interrupt, i.e., W register and STATUS
register. This will have to be implemented in software.
11.10.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 4.0)
Example 11-1 stores and restores the W and STATUS
registers. The register, W_TEMP, must be defined in
each bank and must be defined at the same offset from
the bank base address (i.e., if W_TEMP is defined at
0x20 in bank 0. It must also be defined at 0xA0 in bank
1).
The example:
a)
b)
c)
d)
e)
f)
11.10.3 PORTB INTCON CHANGE
Context Saving During Interrupts
Stores the W register.
Stores the STATUS register in bank 0.
Stores the PCLATH register.
Executes the interrupt service routine code
(User-generated).
Restores the STATUS register (and bank select
bit).
Restores the W and PCLATH registers.
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 3.2)
EXAMPLE 11-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
BCF
MOVF
MOVWF
:
:(ISR)
:
MOVF
MOVWF
SWAPF
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
STATUS, IRP
FSR, W
FSR_TEMP
;Copy W to TEMP register, could be bank one or zero
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
;Return to Bank 0
;Copy FSR to W
;Copy FSR from W to FSR_TEMP
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
 1998 Microchip Technology Inc.
DS30605A-page 91
PIC16C63A/65B/73B/74B
11.12
Watchdog Timer (WDT)
WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
The Watchdog Timer is a free running on-chip RC oscillator, which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. That means that the WDT will
run, even if the clock on the OSC1/CLKIN and OSC2/
CLKOUT pins of the device has been stopped, for
example, by execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the STATUS register
will be cleared upon a Watchdog Timer time-out.
Note:
The CLRWDT and SLEEP instructions clear
the WDT and the postscaler if assigned to
the WDT, and prevent it from timing out and
generating a device RESET condition.
Note:
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 11.1).
FIGURE 11-12: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 4-2)
0
WDT Timer
Postscaler
M
U
X
1
8
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 4-2)
0
1
MUX
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
PSA
WDT
Time-out
FIGURE 11-13: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
2007h
Config. bits
81h
OPTION_REG
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
BODEN(1)
CP1
CP0
PWRTE(1)
WDTE
FOSC1
FOSC0
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 11-1 for operation of these bits.
DS30605A-page 92
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
11.13
Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD, or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down
the A/D, disable external clocks. Pull all I/O pins, that
are hi-impedance inputs, high or low externally to avoid
switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
11.13.1 WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1.
2.
3.
External reset input on MCLR pin.
Watchdog Timer Wake-up (if WDT was
enabled).
Interrupt from INT pin, RB port change, or some
Peripheral Interrupts.
External MCLR Reset will cause a device reset. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO bit
is cleared if a WDT time-out occurred (and caused
wake-up).
The following peripheral interrupts can wake the device
from SLEEP:
1.
2.
3.
4.
5.
6.
7.
8.
Other peripherals cannot generate interrupts since during SLEEP, no on-chip clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
11.13.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
• If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep. The SLEEP instruction
will be completely executed before the wake-up.
Therefore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will
be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction was
executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
PSP read or write.
TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
CCP capture mode interrupt.
Special event trigger (Timer1 in asynchronous
mode using an external clock).
SSP (Start/Stop) bit detect interrupt.
SSP transmit or receive in slave mode (SPI/I2C).
USART RX or TX (synchronous slave mode).
A/D conversion (when A/D clock source is RC).
 1998 Microchip Technology Inc.
DS30605A-page 93
PIC16C63A/65B/73B/74B
FIGURE 11-14: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3
Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst(PC) = SLEEP
Instruction
executed
Inst(PC - 1)
Note 1:
2:
3:
4:
11.14
PC+1
PC+2
PC+2
Inst(PC + 1)
Inst(PC + 2)
SLEEP
Inst(PC + 1)
PC + 2
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
XT, HS or LP oscillator mode assumed.
TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
Program Verification/Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read
out for verification purposes.
Note:
11.15
Microchip Technology does not recommend code protecting windowed devices.
ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are readable and writable during program/verify. It is recommended that only the 4 least significant bits of the ID
location are used.
For ROM devices, these values are submitted along
with the ROM code.
11.16
In-Circuit Serial Programming
PIC16CXXX microcontrollers can be serially programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming voltage. This allows customers to manufacture boards with
unprogrammed devices, and then program the microcontroller just before shipping the product. This also
allows the most recent firmware or a custom firmware
to be programmed.
For complete details of serial programming, please
refer to the In-Circuit Serial Programming (ICSP™)
Guide, (DS30277B).
DS30605A-page 94
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
12.0
INSTRUCTION SET SUMMARY
Each PIC16CXXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 12-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 12-1
shows the opcode field descriptions.
For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
Table 12-2 lists the instructions recognized by the
MPASM assembler.
Figure 12-1 shows the general formats that the instructions can have.
Note:
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
FIGURE 12-1: GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
OPCODE FIELD
DESCRIPTIONS
Field
Register file address (0x00 to 0x7F)
Working register (accumulator)
b
k
x
Bit address within an 8-bit file register
Literal field, constant data or label
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip Technology software tools.
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
d
PC
TO
PD
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
Program Counter
Time-out bit
Power-down bit
The instruction set is highly orthogonal and is grouped
into three basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
0
b = 3-bit bit address
f = 7-bit file register address
Description
f
W
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
TABLE 12-1:
To maintain upward compatibility with
future PIC16CXXX products, do not use
the OPTION and TRIS instructions.
Literal and control operations
General
13
8
7
OPCODE
0
k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only
13
11
OPCODE
10
0
k (literal)
k = 11-bit immediate value
A description of each instruction is available in the
PICmicro
Mid-Range
Reference
Manual,
(DS33023).
All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruction, the instruction execution time is 2 µs.
 1998 Microchip Technology Inc.
DS30605A-page 95
PIC16C63A/65B/73B/74B
TABLE 12-2:
PIC16CXXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1:
When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS30605A-page 96
 1998 Microchip Technology Inc.
PIC16C62X(A)
13.0
DEVELOPMENT SUPPORT
13.1
Development Tools
The PICmicrο microcontrollers are supported with a
full range of hardware and software development tools:
• PICMASTER/PICMASTER CE Real-Time
In-Circuit Emulator
• ICEPIC Low-Cost PIC16C5X and PIC16CXXX
In-Circuit Emulator
• PRO MATE II Universal Programmer
• PICSTART Plus Entry-Level Prototype
Programmer
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
• MPLAB SIM Software Simulator
• MPLAB-C17 (C Compiler)
• Fuzzy Logic Development System
(fuzzyTECH−MP)
13.2
PICMASTER: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
13.3
ICEPIC: Low-Cost PICmicro™
In-Circuit Emulator
ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC12CXXX, PIC16C5X and PIC16CXXX
families of 8-bit OTP microcontrollers.
ICEPIC is designed to operate on PC-compatible
machines ranging from 286-AT through Pentium
based machines under Windows 3.x environment.
ICEPIC features real time, non-intrusive emulation.
13.4
PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program
PIC12CXXX,
PIC14C000,
PIC16C5X,
PIC16CXXX and PIC17CXX devices. It can also set
configuration and code-protect bits in this mode.
The PICMASTER Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC14C000, PIC12CXXX,
PIC16C5X, PIC16CXXX and PIC17CXX families.
PICMASTER is supplied with the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
13.5
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different processors. The universal architecture of the PICMASTER
allows expansion to support all new Microchip microcontrollers.
PICSTART Plus supports all PIC12CXXX, PIC14C000,
PIC16C5X, PIC16CXXX and PIC17CXX devices with
up to 40 pins. Larger pin count devices such as the
PIC16C923, PIC16C924 and PIC17C756 may be supported with an adapter socket. PICSTART Plus is CE
compliant.
The PICMASTER Emulator System has been
designed as a real-time emulation system with
advanced features that are generally found on more
expensive development tools. The PC compatible 386
(and higher) machine platform and Microsoft Windows
3.x environment were chosen to best make these features available to you, the end user.
PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use,
low-cost prototype programmer. It connects to the PC
via one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is
not recommended for production programming.
A CE compliant version of PICMASTER is available for
European Union (EU) countries.
 1998 Microchip Technology Inc.
DS30605A-page 97
PIC16C62X(A)
13.6
PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1
board to the PICMASTER emulator and download
the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
13.7
PICDEM-2 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware.
The PICMASTER emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding additional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
13.8
PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the necessary hardware and software is included to run the
basic demonstration programs. The user can program the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and
easily test firmware. The PICMASTER emulator may
also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
DS30605A-page 98
an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
13.9
MPLAB™ Integrated Development
Environment Software
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application
which contains:
• A full featured editor
• Three operating modes
- editor
- emulator
- simulator
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Debug using:
- source files
- absolute listing file
• Transfer data dynamically via DDE (soon to be
replaced by OLE)
• Run up to four emulators on the same PC
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
13.10
Assembler (MPASM)
The MPASM Universal Macro Assembler is a
PC-hosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX, and PIC17CXX families.
MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
MPASM allows full symbolic debugging from
PICMASTER, Microchip’s Universal Emulator System.
 1998 Microchip Technology Inc.
PIC16C62X(A)
MPASM has the following features to assist in developing software for specific use applications.
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol,
and special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal source
and listing formats.
MPASM provides a rich directive language to support
programming of the PICmicro. Directives are helpful in
making the development of your assemble source code
shorter and more maintainable.
13.11
Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PICmicro series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The
input/output radix can be set by the user and the execution can be performed in; single step, execute until
break, or in a trace mode.
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C and MPASM. The Software Simulator offers
the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
13.12
C Compiler (MPLAB-C17)
13.14
MP-DriveWay – Application Code
Generator
MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can
visually configure all the peripherals in a PICmicro
device and, with a click of the mouse, generate all the
initialization and many functional code modules in C
language. The output is fully compatible with Microchip’s MPLAB-C C compiler. The code produced is
highly modular and allows easy integration of your own
code. MP-DriveWay is intelligent enough to maintain
your code through subsequent code generation.
13.15
SEEVAL Evaluation and
Programming System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in
trade-off analysis and reliability calculations. The total
kit can significantly reduce time-to-market and result in
an optimized system.
13.16
KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
The MPLAB-C Code Development System is a
complete ‘C’ compiler and integrated development
environment for Microchip’s PIC17CXXX family of
microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with
other compilers.
For easier source level debugging, the compiler provides symbol information that is compatible with the
MPLAB IDE memory display.
13.13
Fuzzy Logic Development System
(fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, Edition for implementing more complex systems.
Both versions include Microchip’s fuzzyLAB demonstration board for hands-on experience with fuzzy logic
systems implementation.
 1998 Microchip Technology Inc.
DS30605A-page 99
DS30605A-page 100
ü
PICDEM-3
PICDEM-2
PICDEM-1
SEEVAL Designers Kit
DEMO BOARDS
KEELOQ Programmer
PRO MATE II
Universal Programmer
PICSTARTPlus
Low-Cost
Universal Dev. Kit
PROGRAMMERS
Total Endurance
Software Model
MP-DriveWay
Applications
Code Generator
fuzzyTECH-MP
Explorer/Edition
Fuzzy Logic Dev. Tool
MPLAB C17
Compiler
MPLAB
Integrated
Development
Environment
ü
ü
ü
ü
SOFTWARE PRODUCTS
ICEPIC Low-Cost
In-Circuit Emulator
ü
ü
ü
ü
ü
ü
PIC14000
ü
ü
ü
ü
ü
ü
ü
ü
PIC16C5X
ü
ü
ü
ü
ü
ü
ü
ü
PIC16CXXX
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X
ü
ü
ü
ü
ü
ü
(PIC17C75X only)
PIC17C7XX
ü
ü
ü
ü
ü
24CXX
25CXX
93CXX HCSXXX
TABLE 13-1
MPLAB™-ICE
PICMASTER/
PICMASTER-CE
In-Circuit Emulator
EMULATOR PRODUCTS
PIC12C5XX
PIC16C62X(A)
DEVELOPMENT TOOLS FROM MICROCHIP
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
14.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
Ambient temperature under bias............................................................................................................ .-55˚C to +125˚C
Storage temperature .............................................................................................................................. -65˚C to +150˚C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2).......................................................................................... 0V to +13.25V
Voltage on RA4 with respect to Vss ............................................................................................................... 0V to +8.5V
Total power dissipation (Note 1)................................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)......................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ..............................................................................................................±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (Note 3) (combined)....................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined) ..............................................200 mA
Maximum current sunk by PORTC and PORTD (Note 3) (combined) ..................................................................200 mA
Maximum current sourced by PORTC and PORTD (Note 3) (combined) .............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin rather
than pulling this pin directly to VSS.
Note 3: PORTD and PORTE not available on the PIC16C63A/73B.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 14-1:
OSC
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR MODES AND
FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16C63A-04
PIC16C65B-04
PIC16C73B-04
PIC16C74B-04
PIC16C63A-20
PIC16C65B-20
PIC16C73B-20
PIC16C74B-20
PIC16LC63A-04
PIC16LC65B-04
PIC16LC73B-04
PIC16LC74B-04
Windowed (JW) Devices
RC
VDD: 4.0V to 5.5V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 2.5V to 5.5V
IDD: 3.8 mA max. at 3V
IPD: 5 µA max. at 3V
Freq: 4 MHz max.
VDD: 2.5V to 5.5V
IDD: 3.8 mA max. at 3V
IPD: 5 µA max. at 3V
Freq: 4 MHz max.
XT
VDD: 4.0V to 5.5V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 2.5V to 5.5V
IDD: 3.8 mA max. at 3V
IPD: 5 µA max. at 3V
Freq: 4 MHz max.
VDD: 2.5V to 5.5V
IDD: 3.8 mA max. at 3V
IPD: 5 µA max. at 3V
Freq: 4 MHz max.
HS
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
IDD: 13.5 mA typ. at 5.5V
IDD: 20 mA max. at 5.5V
IPD: 1.5 µA typ. at 4.5V
IPD: 1.5 µA typ. at 4.5V
Freq: 4 MHz max.
Freq: 20 MHz max.
VDD: 4.5V to 5.5V
Not recommended for use in IDD: 20 mA max. at 5.5V
HS mode
IPD: 1.5 µA typ. at 4.5V
Freq: 20 MHz max.
LP
VDD: 4.0V to 5.5V
VDD: 2.5V to 5.5V
VDD: 2.5V to 5.5V
IDD: 52.5 µA typ.
Not recommended for use in IDD: 48 µA max. at 32 kHz, IDD: 48 µA max. at 32 kHz,
at 32 kHz, 4.0V
3.0V
3.0V
LP mode
IPD: 0.9 µA typ. at 4.0V
IPD: 5 µA max. at 3.0V
IPD: 5 µA max. at 3.0V
Freq: 200 kHz max.
Freq: 200 kHz max.
Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.
 1998 Microchip Technology Inc.
Preliminary
DS30605A-page 101
PIC16C63A/65B/73B/74B
14.1
DC Characteristics:
PIC16C63A/65B/73B/74B-04 (Commercial, Industrial, Extended)
PIC16C6A/65B/73B/74B-20 (Commercial, Industrial, Extended)
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0˚C ≤ TA ≤ +70˚C for commercial
-40˚C ≤ TA ≤ +85˚C for industrial
-40˚C ≤ TA ≤ +125˚C for extended
Min
Typ†
Max Units
4.0
4.5
5.5
5.5
5.5
V
V
V
Conditions
D001
D001A
VDD
Supply Voltage
VBOR*
-
D002*
VDR
RAM Data Retention
Voltage (Note 1)
-
1.5
-
V
D003
VPOR
VDD Start Voltage to
ensure internal
Power-on Reset signal
-
VSS
-
V
D004*
SVDD
D004A*
VDD Rise Rate to
ensure internal
Power-on Reset signal
0.05
TBD
-
-
D005
VBOR
Brown-out Reset
voltage trip point
3.65
-
4.35
V
D010
IDD
Supply Current
(Note 2, 5)
-
2.7
5
mA
XT, RC osc modes
FOSC = 4 MHz, VDD = 5.5V (Note 4)
-
10
20
mA
HS osc mode
FOSC = 20 MHz, VDD = 5.5V
D021
D021B
-
10.5
1.5
1.5
2.5
42
16
19
19
µA
µA
µA
µA
VDD = 4.0V, WDT enabled,-40°C to +85°C
VDD = 4.0V, WDT disabled, 0°C to +70°C
VDD = 4.0V, WDT disabled,-40°C to +85°C
VDD = 4.0V, WDT disabled,-40°C to +125°C
Module Differential
Current (Note 6)
D022*
∆IWDT Watchdog Timer
D022A* ∆IBOR Brown-out Reset
-
6.0
350
20
425
µA
µA
WDTE bit set, VDD = 4.0V
BODEN bit set, VDD = 5.0V
D013
IPD
D020
*
†
Note1:
2:
3:
4:
5:
6:
7:
Power-down Current
(Note 3, 5)
XT, RC and LP osc mode
HS osc mode
BOR enabled (Note 7)
See section on Power-on Reset for details
V/ms PWRT enabled (PWRTE bit clear)
PWRT disabled (PWRTE bit set)
See section on Power-on Reset for details
BODEN bit set
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
This is the limit to which VDD can be lowered without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by
the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested.
The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
DS30605A-page 102
Preliminary
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
14.2
DC Characteristics:
PIC16LC63A/65B/73B/74B-04 (Commercial, Industrial)
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
D001
VDD
Supply Voltage
D002*
VDR
D003
VPOR
RAM Data Retention
Voltage (Note 1)
VDD Start Voltage to
ensure internal
Power-on Reset signal
VDD Rise Rate to
ensure internal
Power-on Reset signal
Brown-out Reset
voltage trip point
Supply Current
(Note 2, 5)
D004*
SVDD
D004A*
D005
VBOR
D010
IDD
D010A
D020
D021
D021A
IPD
Power-down Current
(Note 3, 5)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0˚C ≤ TA ≤ +70˚C for commercial
-40˚C ≤ TA ≤ +85˚C for industrial
Min Typ† Max Units
Conditions
2.5
VBOR*
-
1.5
5.5
5.5
-
V
V
V
LP, XT, RC osc modes (DC - 4 MHz)
BOR enabled (Note 7)
-
VSS
-
V
See section on Power-on Reset for details
0.05
TBD
-
-
3.65
-
4.35
-
2.0
3.8
mA
XT, RC osc modes
FOSC = 4 MHz, VDD = 3.0V (Note 4)
-
22.5
48
µA
-
7.5
0.9
0.9
30
5
5
µA
µA
µA
LP osc mode
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
V/ms PWRT enabled (PWRTE bit clear)
PWRT disabled (PWRTE bit set)
See section on Power-on Reset for details
V
BODEN bit set
Module Differential
Current (Note 6)
6.0
20
µA WDTE bit set, VDD = 4.0V
D022*
∆IWDT Watchdog Timer
350
425
µA BODEN bit set, VDD = 5.0V
D022A* ∆IBOR Brown-out Reset
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by
the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached..
 1998 Microchip Technology Inc.
Preliminary
DS30605A-page 103
PIC16C63A/65B/73B/74B
14.3
DC Characteristics:
PIC16C63A/65B/73B/74B-04 (Commercial, Industrial, Extended)
PIC16C63A/65B/73B/74B-20 (Commercial, Industrial, Extended)
PIC16LC63A/65B/73B/74B-04 (Commercial, Industrial)
DC CHARACTERISTICS
Param
No.
Sym
VIL
D030
D030A
D031
D032
D033
VIH
D040
D040A
D041
D042
D042A
D043
D060
IIL
D061
D063
D070
IPURB
D080
VOL
D083
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0˚C ≤ TA ≤ +70˚C for commercial
-40˚C ≤ TA ≤ +85˚C for industrial
-40˚C ≤ TA ≤ +125˚C for extended
Operating voltage VDD range as described in DC spec Section 14.1
and Section 14.2
Min
Typ†
Max
Units
Conditions
VSS
VSS
VSS
Vss
Vss
-
0.15VDD
0.8V
0.2VDD
0.2VDD
0.3VDD
V
V
V
V
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
-
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
with Schmitt Trigger buffer 0.8VDD
MCLR
0.8VDD
OSC1 (XT, HS and LP modes) 0.7VDD
OSC1 (in RC mode)
0.9VDD
Input Leakage Current (Notes
2, 3)
I/O ports
-
-
VDD
VDD
VDD
VDD
V
V
V
V
For entire VDD range
-
±1
µA
MCLR, RA4/T0CKI
OSC1
-
-
±5
±5
µA
µA
50
250
400
µA
Vss ≤ VPIN ≤ VDD,
Pin at hi-impedance
Vss ≤ VPIN ≤ VDD
Vss ≤ VPIN ≤ VDD,
XT, HS and LP osc modes
VDD = 5V, VPIN = VSS
-
-
0.6
V
-
-
0.6
V
-
-
0.6
V
-
-
0.6
V
with Schmitt Trigger buffer
MCLR, OSC1 (in RC mode)
OSC1 (in XT, HS and LP
modes)
Input High Voltage
I/O ports
with TTL buffer
PORTB weak pull-up current
Output Low Voltage
I/O ports
OSC2/CLKOUT (RC osc
mode)
2.0
0.25VDD
+ 0.8V
Note1
Note1
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmicro be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS30605A-page 104
Preliminary
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
DC CHARACTERISTICS
Param
No.
D090
Sym
VOH
D092
Characteristic
Output High Voltage
I/O ports (Note 3)
VDD-0.7
-
-
V
VDD-0.7
-
-
V
VDD-0.7
-
-
V
VDD-0.7
-
-
V
Open-Drain High Voltage
Capacitive Loading Specs
on Output Pins
OSC2 pin
-
-
8.5
V
-
-
15
pF
All I/O pins and OSC2 (in RC
mode)
-
-
50
pF
OSC2/CLKOUT (RC osc
mode)
D150*
VOD
D100
COSC2
D101
CIO
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0˚C ≤ TA ≤ +70˚C for commercial
-40˚C ≤ TA ≤ +85˚C for industrial
-40˚C ≤ TA ≤ +125˚C for extended
Operating voltage VDD range as described in DC spec Section 14.1
and Section 14.2
Min
Typ†
Max
Units
Conditions
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
RA4 pin
In XT, HS and LP modes when
external clock is used to drive
OSC1.
400
pF
Cb
SCL, SDA in I2C mode
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmicro be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
D102
*
†
 1998 Microchip Technology Inc.
Preliminary
DS30605A-page 105
PIC16C63A/65B/73B/74B
14.4
AC (Timing) Characteristics
14.4.1
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
3. TCC:ST
(I2C specifications only)
2. TppS
4. Ts
(I2C specifications only)
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
I2C only
AA
BUF
output access
Bus free
TCC:ST (I2C specifications only)
CC
HD
Hold
ST
DAT
DATA input hold
STA
START condition
DS30605A-page 106
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
High
Low
High
Low
SU
Setup
STO
STOP condition
Preliminary
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
14.4.2
TIMING CONDITIONS
The temperature and voltages specified in Table 14-1
apply to all timing specifications unless otherwise
noted. Figure 14-1 specifies the load conditions for the
timing specifications.
TABLE 14-1:
TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0˚C ≤ TA ≤ +70˚C for commercial
-40˚C ≤ TA ≤ +85˚C for industrial
-40˚C ≤ TA ≤ +125˚C for extended
Operating voltage VDD range as described in DC spec Section 14.1 and Section 14.2.
LC parts operate for commercial/industrial temp’s only.
AC CHARACTERISTICS
FIGURE 14-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
Pin
VSS
CL
Pin
RL = 464Ω
VSS
Note1:
PORTD and PORTE are not implemented on the PIC16C63A/73B.
 1998 Microchip Technology Inc.
CL = 50 pF
15 pF
Preliminary
for all pins except OSC2/CLKOUT
but including D and E outputs as ports
for OSC2 output
DS30605A-page 107
PIC16C63A/65B/73B/74B
14.4.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 14-2: EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
3
1
3
4
4
2
CLKOUT
TABLE 14-2:
Param
No.
1A
Sym
Fosc
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic
Min
Typ†
Max
External CLKIN Frequency
(Note 1)
DC
DC
—
—
4
4
MHz
MHz
RC and XT osc modes
HS osc mode (-04)
DC
DC
—
—
20
200
MHz
kHz
HS osc mode (-20)
LP osc mode
DC
0.1
—
—
4
4
MHz
MHz
RC osc mode
XT osc mode
4
5
250
—
—
—
20
200
—
MHz
kHz
ns
HS osc mode
LP osc mode
RC and XT osc modes
250
50
5
—
—
—
—
—
—
ns
ns
µs
Oscillator Period
(Note 1)
250
—
—
ns
RC osc mode
250
250
50
—
—
—
10,000
250
250
ns
ns
ns
XT osc mode
HS osc mode (-04)
HS osc mode (-20)
Oscillator Frequency
(Note 1)
1
Tosc
External CLKIN Period
(Note 1)
Units Conditions
HS osc mode (-04)
HS osc mode (-20)
LP osc mode
5
—
—
µs
LP osc mode
2
TCY
Instruction Cycle Time (Note 1)
200
—
DC
ns
TCY = 4/FOSC
3*
TosL,
TosH
External Clock in (OSC1) High or
Low Time
100
2.5
—
—
—
—
ns
µs
XT oscillator
LP oscillator
4*
TosR,
TosF
External Clock in (OSC1) Rise or
Fall Time
15
—
—
—
—
25
ns
ns
HS oscillator
XT oscillator
*
†
Note1:
—
—
50
ns
LP oscillator
—
—
15
ns
HS oscillator
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at "min." values with an external
clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
DS30605A-page 108
Preliminary
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 14-3: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 14-1 for load conditions.
TABLE 14-3:
Param
No.
CLKOUT AND I/O TIMING REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units Conditions
10*
TosH2ckL
OSC1↑ to CLKOUT↓
—
75
200
ns
Note 1
11*
TosH2ckH OSC1↑ to CLKOUT↑
—
75
200
ns
Note 1
12*
TckR
CLKOUT rise time
—
35
100
ns
Note 1
13*
TckF
CLKOUT fall time
—
35
100
ns
Note 1
14*
TckL2ioV
CLKOUT ↓ to Port out valid
—
—
0.5TCY + 20
ns
Note 1
15*
TioV2ckH
Port in valid before CLKOUT ↑
Tosc + 200
—
—
ns
Note 1
16*
TckH2ioI
Port in hold after CLKOUT ↑
0
—
—
ns
Note 1
17*
TosH2ioV
OSC1↑ (Q1 cycle) to Port out valid
—
50
150
ns
18*
TosH2ioI
OSC1↑ (Q2 cycle) to Port input
invalid (I/O in hold time)
18A*
Standard
100
—
—
ns
Extended (LC)
200
—
—
ns
19*
TioV2osH
Port input valid to OSC1↑ (I/O in setup time)
0
—
—
ns
20*
TioR
Port output rise time
Standard
—
10
40
ns
Extended (LC)
—
—
80
ns
TioF
Port output fall time
Standard
—
10
40
ns
—
—
80
ns
22††*
Tinp
INT pin high or low time
TCY
—
—
ns
23††*
Trbp
RB7:RB4 change INT high or low time
TCY
—
—
ns
20A*
21*
21A*
Extended (LC)
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
†† These parameters are asynchronous events not related to any internal clock edge.
Note1:
Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
 1998 Microchip Technology Inc.
Preliminary
DS30605A-page 109
PIC16C63A/65B/73B/74B
FIGURE 14-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 14-1 for load conditions.
FIGURE 14-5: BROWN-OUT RESET TIMING
BVDD
VDD
TABLE 14-4:
35
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No.
Sym
30
TmcL
MCLR Pulse Width (low)
2
—
—
µs
VDD = 5V, -40˚C to +125˚C
31*
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7
18
33
ms
VDD = 5V, -40˚C to +125˚C
Typ†
Max
Units
Conditions
Oscillation Start-up Timer Period
—
1024 TOSC
—
—
TOSC = OSC1 period
28
72
132
ms
VDD = 5V, -40˚C to +125˚C
TIOZ
I/O Hi-impedance from MCLR
Low or WDT reset
—
—
2.1
µs
TBOR
Brown-out Reset Pulse Width
100
—
—
µs
Tost
Tpwrt
34
*
†
Min
Power-up Timer Period
32
33*
35
Characteristic
VDD ≤ BVDD (D005)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30605A-page 110
Preliminary
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 14-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 14-1 for load conditions.
TABLE 14-5:
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
40*
Tt0H
T0CKI High Pulse Width
No Prescaler
T0CKI Low Pulse Width
With Prescaler
No Prescaler
With Prescaler
41*
42*
45*
46*
47*
48
*
†
Tt0L
Min
Typ†
Max
Units Conditions
0.5TCY + 20
—
—
ns
10
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
ns
ns
ns
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
ns
ns
ns
0.5TCY + 20
10
Tt0P
T0CKI Period
TCY + 40
No Prescaler
With Prescaler Greater of:
20 or TCY + 40
N
Tt1H
T1CKI High Time Synchronous, Prescaler = 1
0.5TCY + 20
Synchronous, Standard
15
Prescaler =
25
Extended (LC)
2,4,8
Asynchronous Standard
30
50
Extended (LC)
Tt1L
T1CKI Low Time
Synchronous, Prescaler = 1
0.5TCY + 20
Synchronous, Standard
15
Prescaler =
25
Extended (LC)
2,4,8
Asynchronous Standard
30
50
Extended (LC)
Tt1P
T1CKI input period Synchronous Standard
Greater of:
30 OR TCY + 40
N
Extended (LC) Greater of:
50 OR TCY + 40
N
Asynchronous Standard
60
100
Extended (LC)
Ft1
Timer1 oscillator input frequency range
DC
(oscillator enabled by setting bit T1OSCEN)
TCKEZtmr1 Delay from external clock edge to timer increment
2Tosc
Must also meet
parameter 42
Must also meet
parameter 42
N = prescale value
(2, 4,..., 256)
Must also meet
parameter 47
Must also meet
parameter 47
N = prescale value
(1, 2, 4, 8)
N = prescale value
(1, 2, 4, 8)
—
—
—
—
—
200
ns
ns
kHz
—
7Tosc
—
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1998 Microchip Technology Inc.
Preliminary
DS30605A-page 111
PIC16C63A/65B/73B/74B
FIGURE 14-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
CCPx
(Capture Mode)
50
51
52
CCPx
(Compare or PWM Mode)
53
54
Note: Refer to Figure 14-1 for load conditions.
TABLE 14-6:
Param
No.
50*
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Sym Characteristic
TccL CCP1 and CCP2
input low time
Min
No Prescaler
With Prescaler
Standard
Extended (LC)
51*
TccH CCP1 and CCP2
input high time
No Prescaler
With Prescaler
Standard
Extended (LC)
52*
TccP CCP1 and CCP2 input period
53*
TccR CCP1 and CCP2 output rise time
54*
*
†
TccF CCP1 and CCP2 output fall time
Typ† Max Units Conditions
0.5TCY + 20
—
—
ns
10
—
—
ns
ns
20
—
—
0.5TCY + 20
—
—
ns
10
—
—
ns
20
—
—
ns
3TCY + 40
N
—
—
ns
Standard
—
10
25
ns
Extended (LC)
—
25
45
ns
Standard
—
10
25
ns
Extended (LC)
—
25
45
ns
N = prescale value
(1,4, or 16)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30605A-page 112
Preliminary
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 14-8: PARALLEL SLAVE PORT TIMING (PIC16C65B/74B)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 14-1 for load conditions.
TABLE 14-7:
Parameter
No.
PARALLEL SLAVE PORT REQUIREMENTS (PIC16C65B/74B)
Sym
Characteristic
Min
Typ†
Max
Units
62*
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)
20
—
—
ns
63*
TwrH2dtI
WR↑ or CS↑ to data–in invalid
(hold time)
Standard
20
—
—
ns
Extended (LC)
35
—
—
ns
64
TrdL2dtV
RD↓ and CS↓ to data–out valid
—
—
80
ns
TrdH2dtI
RD↑ or CS↑ to data–out invalid
10
—
30
ns
65*
*
†
Conditions
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1998 Microchip Technology Inc.
Preliminary
DS30605A-page 113
PIC16C63A/65B/73B/74B
FIGURE 14-9: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
BIT6 - - - - - -1
MSb
SDO
LSb
75, 76
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
73
Refer to Figure 14-1 for load conditions.
TABLE 14-8:
Param.
No.
70
71
EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Symbol
Characteristic
Min
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TscH
SCK input high time
Continuous
(slave mode)
Single Byte
Typ† Max Units
TCY
—
—
ns
1.25TCY + 30
40
1.25TCY + 30
40
100
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
Conditions
Note 1
Continuous
72A
Single Byte
Note 1
73
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
73A
TB2B
Last clock edge of Byte1 to the 1st clock
1.5TCY + 40
—
—
ns Note 1
edge of Byte2
74
TscH2diL, Hold time of SDI data input to SCK edge
100
—
—
ns
TscL2diL
75
TdoR
SDO data output rise time Standard
—
10
25
ns
Extended (LC)
—
20
45
ns
76
TdoF
SDO data output fall time
—
10
25
ns
78
TscR
SCK output rise time
Standard
—
10
25
ns
(master mode)
Extended (LC)
—
20
45
ns
79
TscF
SCK output fall time (master mode)
—
10
25
ns
80
TscH2doV, SDO data output valid
Standard
—
—
50
ns
TscL2doV after SCK edge
Extended (LC)
—
—
100
ns
† Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note1: Specification 73A is only required if specifications 71A and 72A are used.
71A
72
TscL
DS30605A-page 114
SCK input low time
(slave mode)
Preliminary
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 14-10: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
LSb
BIT6 - - - - - -1
MSb
SDO
75, 76
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
Refer to Figure 14-1 for load conditions.
TABLE 14-9:
Param.
No.
71
EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Symbol
TscH
71A
72
TscL
72A
73
73A
74
75
TdiV2scH,
TdiV2scL
TB2B
TscH2diL,
TscL2diL
TdoR
Characteristic
Min
SCK input high time
(slave mode)
Continuous
Single Byte
SCK input low time
Continuous
(slave mode)
Single Byte
Setup time of SDI data input to SCK
edge
Last clock edge of Byte1 to the 1st clock
edge of Byte2
Hold time of SDI data input to SCK edge
SDO data output rise
time
Typ† Max Units
1.25TCY + 30
40
1.25TCY + 30
40
100
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
1.5TCY + 40
—
—
ns
100
—
—
ns
—
10
20
10
10
20
10
—
—
—
25
45
25
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Standard
Extended (LC)
Note 1
Note 1
Note 1
SDO data output fall time
—
SCK output rise time
Standard
—
(master mode)
Extended (LC)
79
TscF
SCK output fall time (master mode)
—
80
TscH2doV, SDO data output valid
Standard
—
TscL2doV after SCK edge
Extended (LC)
81
TdoV2scH, SDO data output setup to SCK edge
TCY
TdoV2scL
† Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note1: Specification 73A is only required if specifications 71A and 72A are used.
76
78
TdoF
TscR
Conditions
 1998 Microchip Technology Inc.
Preliminary
DS30605A-page 115
PIC16C63A/65B/73B/74B
FIGURE 14-11: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
MSb
SDO
LSb
BIT6 - - - - - -1
77
75, 76
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
73
Refer to Figure 14-1 for load conditions.
TABLE 14-10: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)
Param.
No.
70
71
71A
72
72A
73
73A
74
75
76
77
78
79
80
83
Symbol
Characteristic
Min
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TscH
SCK input high time
Continuous
(slave mode)
Single Byte
TscL
SCK input low time
(slave mode)
Continuous
Single Byte
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
TB2B
Last clock edge of Byte1 to the 1st clock
edge of Byte2
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
TdoR
SDO data output rise time Standard
Extended (LC)
TdoF
SDO data output fall time
TssH2doZ SS↑ to SDO output hi-impedance
TscR
SCK output rise time
Standard
(master mode)
Extended (LC)
TscF
SCK output fall time (master mode)
TscH2doV, SDO data output valid
Standard
TscL2doV after SCK edge
Extended (LC)
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
Typ† Max Units
TCY
—
—
ns
1.25TCY + 30
40
1.25TCY + 30
40
100
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
1.5TCY + 40
—
—
ns
100
—
—
ns
—
10
20
10
—
10
20
10
—
—
—
25
45
25
50
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
10
—
—
—
1.5TCY + 40
Conditions
Note 1
Note 1
Note 1
† Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note1:
Specification 73A is only required if specifications 71A and 72A are used.
DS30605A-page 116
Preliminary
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 14-12: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
SCK
(CKP = 0)
70
83
71
72
SCK
(CKP = 1)
80
MSb
SDO
BIT6 - - - - - -1
LSb
75, 76
SDI
MSb IN
77
BIT6 - - - -1
LSb IN
74
Refer to Figure 14-1 for load conditions.
TABLE 14-11: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param.
No.
70
71
Symbol
Characteristic
Min
SS↓ to SCK↓ or SCK↑ input
TCY
—
—
ns
1.25TCY + 30
40
1.25TCY + 30
40
1.5TCY + 40
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
100
—
—
ns
Standard
Extended (LC)
—
SDO data output fall time
SS↑ to SDO output hi-impedance
SCK output rise time
Standard
(master mode)
Extended (LC)
TscF
SCK output fall time (master mode)
TscH2doV, SDO data output valid
Standard
TscL2doV after SCK edge
Extended (LC)
TssL2doV SDO data output valid
Standard
after SS↓ edge
Extended (LC)
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
—
10
—
—
—
—
—
—
—
10
20
10
—
10
20
10
—
—
—
—
—
25
45
25
50
25
45
25
50
100
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TssL2scH,
TssL2scL
TscH
71A
72
TscL
72A
73A
74
75
76
77
78
79
80
82
83
TB2B
TscH2diL,
TscL2diL
TdoR
SCK input high time
(slave mode)
Continuous
Single Byte
SCK input low time
Continuous
(slave mode)
Single Byte
Last clock edge of Byte1 to the 1st clock
edge of Byte2
Hold time of SDI data input to SCK edge
SDO data output rise
time
TdoF
TssH2doZ
TscR
1.5TCY + 40
Typ† Max Units
Conditions
Note 1
Note 1
Note 1
† Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note1:
Specification 73A is only required if specifications 71A and 72A are used.
 1998 Microchip Technology Inc.
Preliminary
DS30605A-page 117
PIC16C63A/65B/73B/74B
FIGURE 14-13: I2C BUS START/STOP BITS TIMING
SCL
91
93
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 14-1 for load conditions.
TABLE 14-12: I2C BUS START/STOP BITS REQUIREMENTS
Parameter
No.
Sym
90*
TSU:STA
START condition
Setup time
100 kHz mode
400 kHz mode
4700
600
—
—
91*
THD:STA
START condition
Hold time
100 kHz mode
400 kHz mode
4000
600
92*
TSU:STO
93
THD:STO
STOP condition
Setup time
STOP condition
Hold time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
4000
600
*
Characteristic
Min
Typ Max
Units
Conditions
—
—
ns
Only relevant for repeated START
condition
—
—
—
—
ns
After this period the first clock
pulse is generated
—
—
—
—
—
—
—
—
ns
ns
These parameters are characterized but not tested.
DS30605A-page 118
Preliminary
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 14-14: I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 14-1 for load conditions.
TABLE 14-13: I2C BUS DATA REQUIREMENTS
Parameter
No.
Sym
Characteristic
100*
THIGH
Clock high time
101*
102*
103*
TLOW
TR
TF
Min
Max
Units
Conditions
100 kHz mode
4.0
—
µs
400 kHz mode
0.6
—
µs
Device must operate at a minimum of 1.5 MHz
Device must operate at a minimum of 10 MHz
SSP Module
100 kHz mode
1.5TCY
4.7
—
—
µs
400 kHz mode
1.3
—
µs
SSP Module
100 kHz mode
400 kHz mode
1.5TCY
—
20 + 0.1Cb
—
1000
300
ns
ns
SDA and SCL fall time 100 kHz mode
400 kHz mode
—
20 + 0.1Cb
300
300
ns
ns
4.7
0.6
4.0
0.6
0
0
250
100
4.7
0.6
—
—
4.7
1.3
—
—
—
—
—
0.9
—
—
—
—
3500
—
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
—
400
pF
Clock low time
SDA and SCL rise
time
90*
TSU:STA
91*
THD:STA
106*
THD:DAT
Data input hold time
107*
TSU:DAT
Data input setup time
92*
TSU:STO
STOP condition setup
time
109*
TAA
110*
TBUF
*
Note1:
START condition
setup time
START condition hold
time
Output valid from
clock
Bus free time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
Cb
Bus capacitive loading
These parameters are characterized but not tested.
Device must operate at a minimum of 1.5 MHz
Device must operate at a minimum of 10 MHz
Cb is specified to be from
10-400 pF
Cb is specified to be from
10-400 pF
Only relevant for repeated
START condition
After this period the first clock
pulse is generated
Note 2
Note 1
Time the bus must be free
before a new transmission can
start
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement
Tsu:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of
the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line
is released.
 1998 Microchip Technology Inc.
Preliminary
DS30605A-page 119
PIC16C63A/65B/73B/74B
FIGURE 14-15: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
122
Note: Refer to Figure 14-1 for load conditions.
TABLE 14-14: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
120*
121*
122*
*
†
Sym
Characteristic
TckH2dtV
SYNC XMIT (MASTER & SLAVE) Standard
Clock high to data out valid
Extended (LC)
—
—
80
ns
—
—
100
ns
Clock out rise time and fall time
(Master Mode)
Standard
—
—
45
ns
Extended (LC)
—
—
50
ns
Data out rise time and fall time
Standard
—
—
45
ns
Extended (LC)
—
—
50
ns
Tckrf
Tdtrf
Min
Typ†
Max
Units
Conditions
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 14-16: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
RC7/RX/DT
pin
125
126
Note: Refer to Figure 14-1 for load conditions.
TABLE 14-15: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
Sym
Characteristic
125*
TdtV2ckL
SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup time)
15
—
—
ns
126*
TckL2dtl
Data hold after CK ↓ (DT hold time)
15
—
—
ns
*
†
Min
Typ†
Max
Units Conditions
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30605A-page 120
Preliminary
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 14-16: A/D CONVERTER CHARACTERISTICS:
PIC16C73B/74B-04 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC16C73B/74B-20 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC16LC73B/74B-04 (COMMERCIAL, INDUSTRIAL)
Param Sym Characteristic
No.
A01
NR
A02
Resolution
EABS Total Absolute error
Typ†
Max
Units
Conditions
—
—
8-bits
bit
—
—
<±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
—
—
<±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A03
EIL
A04
EDL Differential linearity error
—
—
<±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A05
EFS Full scale error
—
—
<±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A06
EOFF Offset error
—
—
<±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A10
—
Integral linearity error
Min
VSS ≤ VAIN ≤ VREF
Monotonicity
—
guaranteed
—
—
A20
VREF Reference voltage
2.5V
—
VDD + 0.3
V
A25
VAIN Analog input voltage
VSS - 0.3
—
VREF + 0.3
V
A30
ZAIN Recommended impedance of
analog voltage source
—
—
10.0
kΩ
A40
IAD
Standard
—
180
—
µA
Extended (LC)
—
90
—
µA
10
—
1000
µA
During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD, see Section 10.1.
—
—
10
µA
During A/D Conversion
cycle
A/D conversion current
(VDD)
IREF VREF input current (Note 2)
A50
*
†
Note1:
Average current consumption when A/D is on.
(Note 1)
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
When A/D is off, it will not consume any current other than minor leakage current.
The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
 1998 Microchip Technology Inc.
Preliminary
DS30605A-page 121
PIC16C63A/65B/73B/74B
FIGURE 14-17: A/D CONVERSION TIMING
BSF ADCON0, GO
134
1 Tcy
(TOSC/2) (1)
131
Q4
130
132
A/D CLK
7
A/D DATA
6
5
4
3
2
1
NEW_DATA
OLD_DATA
ADRES
0
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This
allows the SLEEP instruction to be executed.
TABLE 14-17: A/D CONVERSION REQUIREMENTS
Param
No.
130
Sym Characteristic
TAD
A/D clock period
Min
Typ†
Max
Units
Conditions
Standard
1.6
—
—
µs
TOSC based, VREF ≥ 3.0V
Extended (LC)
2.0
—
—
µs
TOSC based, VREF full range
Standard
2.0
4.0
6.0
µs
A/D RC Mode
Extended (LC)
3.0
6.0
9.0
µs
A/D RC Mode
131
TCNV Conversion time (not including S/H time)
(Note 1)
11
—
11
TAD
132
TACQ Acquisition time
Note 2
20
—
µs
5*
—
—
µs
The minimum time is the amplifier
settling time. This may be used if
the "new" input voltage has not
changed by more than 1 LSb (i.e.,
20.0 mV @ 5.12V) from the last
sampled voltage (as stated on
CHOLD).
—
TOSC/2 §
—
—
If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
1.5 §
—
—
TAD
134
TGO
Q4 to A/D clock start
TSWC Switching from convert → sample time
135
*
†
§
Note1:
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification ensured by design.
ADRES register may be read on the following TCY cycle.
2: See Section 10.1 for min conditions.
DS30605A-page 122
Preliminary
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
15.0
DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs and Tables not available at this
time.
 1998 Microchip Technology Inc.
DS30605A-page 123
PIC16C63A/65B/73B/74B
NOTES:
DS30605A-page 124
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
16.0
PACKAGING INFORMATION
16.1
Package Marking Information
28-Lead PDIP (Skinny DIP)
MMMMMMMMMMMM
XXXXXXXXXXXXXXX
AABBCDE
28-Lead CERDIP Windowed
Example
PIC16C73B-04/SP
9817HAT
Example
XXXXXXXXXXX
XXXXXXXXXXX
AABBCDE
28-Lead SOIC
MMMMMMMMMMMMMMMM
XXXXXXXXXXXXXXXXXXXX
AABBCDE
28-Lead SSOP
XXXXXXXXXXXX
XXXXXXXXXXXX
AABBCAE
PIC16C73B/JW
9817CAT
Example
PIC16C73B-20/SO
9810/SAA
Example
PIC16C73B
20I/SS025
9817SBP
Legend: XX...X
AA
BB
C
Microchip part number & customer specific information*
Year code (last two digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
C = Chandler, Arizona, U.S.A.,
S = Tempe, Arizona, U.S.A. - 6”
H = Tempe, Arizona, U.S.A. - 8”
D
Mask revision number
E
Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line,
it will be carried over to the next line, thus limiting the number of available
characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week
code, facility code, mask rev# and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
 1998 Microchip Technology Inc.
DS30605A-page 125
PIC16C63A/65B/73B/74B
Package Marking Information (Cont’d)
40-Lead PDIP
Example
MMMMMMMMMMMMMM
XXXXXXXXXXXXXXXXXX
AABBCDE
40-Lead CERDIP Windowed
MMMMMMMMM
XXXXXXXXXXX
XXXXXXXXXXX
AABBCDE
PIC16C74B-04/P
9812SAA
Example
PIC16C74B/JW
9805HAT
Legend: XX...X
AA
BB
C
Microchip part number & customer specific information*
Year code (last two digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
C = Chandler, Arizona, U.S.A.,
S = Tempe, Arizona, U.S.A. - 6”
H = Tempe, Arizona, U.S.A. - 8”
D
Mask revision number
E
Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line,
it will be carried over to the next line, thus limiting the number of available
characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week
code, facility code, mask rev# and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
DS30605A-page 126
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Package Marking Information (Cont’d)
44-Lead TQFP
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
44-Lead MQFP
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
44-Lead PLCC
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
Example
PIC16C74B
-20/PT
9811HAT
Example
PIC16C74B
-20/PQ
9804SAT
Example
PIC16C74B
-20/L
9803SAT
Legend: XX...X
AA
BB
C
Microchip part number & customer specific information*
Year code (last two digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
C = Chandler, Arizona, U.S.A.,
S = Tempe, Arizona, U.S.A. - 6”
H = Tempe, Arizona, U.S.A. - 8”
D
Mask revision number
E
Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line,
it will be carried over to the next line, thus limiting the number of available
characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week
code, facility code, mask rev# and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
 1998 Microchip Technology Inc.
DS30605A-page 127
PIC16C63A/65B/73B/74B
16.2
K04-070 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil
E
D
2
n
α
1
E1
A1
A
R
L
c
β
B1
A2
eB
Units
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
Molded Package Width
Radius to Radius Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
p
B
INCHES*
NOM
0.300
28
0.100
0.019
0.016
0.053
0.040
0.005
0.000
0.010
0.008
0.150
0.140
0.090
0.070
0.020
0.015
0.130
0.125
1.365
1.345
0.288
0.280
0.270
0.283
0.320
0.350
5
10
5
10
MIN
n
p
B
B1†
R
c
A
A1
A2
L
D‡
E‡
E1
eB
α
β
MAX
0.022
0.065
0.010
0.012
0.160
0.110
0.025
0.135
1.385
0.295
0.295
0.380
15
15
MILLIMETERS
NOM
MAX
7.62
28
2.54
0.41
0.56
0.48
1.02
1.65
1.33
0.00
0.25
0.13
0.20
0.30
0.25
3.56
4.06
3.81
1.78
2.79
2.29
0.38
0.64
0.51
3.18
3.43
3.30
34.16
35.18
34.67
7.11
7.30
7.49
7.49
6.86
7.18
8.13
8.89
9.65
5
10
15
5
10
15
MIN
* Controlling Parameter.
†
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
DS30605A-page 128
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
16.3
K04-080 28-Lead Ceramic Dual In-line with Window (JW) – 300 mil
E
D
W2
2
n
1
W1
E1
A
R
A1
L
c
eB
Units
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
Package Width
Radius to Radius Width
Overall Row Spacing
Window Width
Window Length
B1
B
A2
MIN
n
p
B
B1
R
c
A
A1
A2
L
D
E
E1
eB
W1
W2
0.098
0.016
0.050
0.010
0.008
0.170
0.107
0.015
0.135
1.430
0.285
0.255
0.345
0.130
0.290
INCHES*
NOM
0.300
28
0.100
0.019
0.058
0.013
0.010
0.183
0.125
0.023
0.140
1.458
0.290
0.270
0.385
0.140
0.300
p
MAX
0.102
0.021
0.065
0.015
0.012
0.195
0.143
0.030
0.145
1.485
0.295
0.285
0.425
0.150
0.310
MILLIMETERS
NOM
MAX
MIN
7.62
28
2.54
2.59
2.49
0.47
0.53
0.41
1.46
1.65
1.27
0.32
0.38
0.25
0.25
0.30
0.20
4.32
4.64
4.95
3.18
3.63
2.72
0.76
0.00
0.57
3.43
3.56
3.68
36.32
37.02
37.72
7.24
7.37
7.49
6.48
6.86
7.24
8.76
9.78
10.80
0.13
0.14
0.15
0.29
0.3
0.31
* Controlling Parameter.
 1998 Microchip Technology Inc.
DS30605A-page 129
PIC16C63A/65B/73B/74B
16.4
K04-052 28-Lead Plastic Small Outline (SO) – Wide, 300 mil
E1
E
p
D
B
2
1
n
X
α
45 °
L
R2
c
A
β
Units
Dimension Limits
Pitch
Number of Pins
Overall Pack. Height
Shoulder Height
Standoff
Molded Package Length
Molded Package Width
Outside Dimension
Chamfer Distance
Shoulder Radius
Gull Wing Radius
Foot Length
Foot Angle
Radius Centerline
Lead Thickness
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
A1
φ
R1
L1
A2
INCHES*
NOM
0.050
28
0.099
0.093
0.048
0.058
0.004
0.008
0.700
0.706
0.292
0.296
0.394
0.407
0.010
0.020
0.005
0.005
0.005
0.005
0.011
0.016
4
0
0.010
0.015
0.009
0.011
0.014
0.017
0
12
12
0
MIN
p
n
A
A1
A2
D‡
E‡
E1
X
R1
R2
L
φ
L1
c
B†
α
β
MAX
0.104
0.068
0.011
0.712
0.299
0.419
0.029
0.010
0.010
0.021
8
0.020
0.012
0.019
15
15
MILLIMETERS
NOM
MAX
1.27
28
2.36
2.64
2.50
1.22
1.73
1.47
0.10
0.28
0.19
17.78
18.08
17.93
7.42
7.51
7.59
10.64
10.01
10.33
0.50
0.25
0.74
0.13
0.13
0.25
0.13
0.25
0.13
0.53
0.41
0.28
0
4
8
0.38
0.51
0.25
0.27
0.30
0.23
0.36
0.42
0.48
0
12
15
0
12
15
MIN
*
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
DS30605A-page 130
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
16.5
K04-073 28-Lead Plastic Shrink Small Outline (SS) – 5.30 mm
E1
E
p
D
B
2
1
n
α
L
A
R2
c
A1
R1
φ
A2
L1
β
Units
Dimension Limits
Pitch
Number of Pins
Overall Pack. Height
Shoulder Height
Standoff
Molded Package Length
Molded Package Width
Outside Dimension
Shoulder Radius
Gull Wing Radius
Foot Length
Foot Angle
Radius Centerline
Lead Thickness
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
INCHES
NOM
0.026
28
0.073
0.068
0.036
0.026
0.005
0.002
0.396
0.402
0.205
0.208
0.301
0.306
0.005
0.005
0.005
0.005
0.015
0.020
0
4
0.000
0.005
0.005
0.007
0.010
0.012
0
5
0
5
MIN
p
n
A
A1
A2
D‡
E‡
E1
R1
R2
L
φ
L1
c
B†
α
β
MAX
0.078
0.046
0.008
0.407
0.212
0.311
0.010
0.010
0.025
8
0.010
0.009
0.015
10
10
MILLIMETERS*
NOM
MAX
0.65
28
1.99
1.73
1.86
1.17
0.66
0.91
0.21
0.05
0.13
10.33
10.07
10.20
5.38
5.20
5.29
7.90
7.65
7.78
0.25
0.13
0.13
0.25
0.13
0.13
0.64
0.38
0.51
0
4
8
0.25
0.00
0.13
0.22
0.13
0.18
0.38
0.25
0.32
10
0
5
10
0
5
MIN
*
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
 1998 Microchip Technology Inc.
DS30605A-page 131
PIC16C63A/65B/73B/74B
16.6
K04-016 40-Lead Plastic Dual In-line (P) – 600 mil
E
D
α
2
1
n
A1
E1
A
R
L
c
B1
β
eB
Units
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
Molded Package Width
Radius to Radius Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
A2
INCHES*
NOM
0.600
40
0.100
0.018
0.016
0.050
0.045
0.005
0.000
0.010
0.009
0.160
0.110
0.073
0.093
0.020
0.020
0.125
0.130
2.013
2.018
0.530
0.535
0.545
0.565
0.630
0.610
5
10
5
10
MIN
n
p
B
B1†
R
c
A
A1
A2
L
D‡
E‡
E1
eB
α
β
p
B
MAX
0.020
0.055
0.010
0.011
0.160
0.113
0.040
0.135
2.023
0.540
0.585
0.670
15
15
MILLIMETERS
MAX
NOM
15.24
40
2.54
0.51
0.46
0.41
1.40
1.27
1.14
0.25
0.13
0.00
0.28
0.25
0.23
4.06
4.06
2.79
2.36
1.85
2.87
0.51
0.51
1.02
3.18
3.30
3.43
51.13
51.26
51.38
13.46
13.59
13.72
14.35
14.86
13.84
15.49
17.02
16.00
5
10
15
5
10
15
MIN
* Controlling Parameter.
†
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
DS30605A-page 132
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
16.7
K04-014 40-Lead Ceramic Dual In-line with Window (JW) – 600 mil
E
W
D
2
1
n
A1
E1
A
R
L
c
B1
B
eB
A2
Units
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
Package Width
Radius to Radius Width
Overall Row Spacing
Window Diameter
*
MIN
n
p
B
B1
R
c
A
A1
A2
L
D
E
E1
eB
W
0.098
0.016
0.050
0.000
0.008
0.190
0.117
0.030
0.135
2.040
0.514
0.560
0.610
0.340
INCHES*
NOM
0.600
40
0.100
0.020
0.053
0.005
0.011
0.205
0.135
0.045
0.140
2.050
0.520
0.580
0.660
0.350
MAX
0.102
0.023
0.055
0.010
0.014
0.220
0.153
0.060
0.145
2.060
0.526
0.600
0.710
0.360
p
MILLIMETERS
MAX
NOM
15.24
40
2.59
2.49
2.54
0.58
0.41
0.50
1.40
1.27
1.33
0.25
0.00
0.13
0.36
0.20
0.28
5.59
4.83
5.21
3.89
2.97
3.43
1.52
0.00
1.14
3.68
3.43
3.56
52.32
51.82
52.07
13.36
13.06
13.21
15.24
14.22
14.73
18.03
15.49
16.76
9.14
8.64
8.89
MIN
Controlling Parameter.
 1998 Microchip Technology Inc.
DS30605A-page 133
PIC16C63A/65B/73B/74B
16.8
K04-076 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.1 mm Lead Form
E1
E
# leads = n1
p
D
D1
2
1
B
n
X x 45°
L
α
A
R2
c
φ
L1
R1
β
Units
Dimension Limits
Pitch
Number of Pins
Pins along Width
Overall Pack. Height
Shoulder Height
Standoff
Shoulder Radius
Gull Wing Radius
Foot Length
Foot Angle
Radius Centerline
Lead Thickness
Lower Lead Width
Outside Tip Length
Outside Tip Width
Molded Pack. Length
Molded Pack. Width
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
p
n
n1
A
A1
A2
R1
R2
L
φ
L1
c
B†
D1
E1
D‡
E‡
X
α
β
0.039
0.015
0.002
0.003
0.003
0.005
0
0.003
0.004
0.012
0.463
0.463
0.390
0.390
0.025
5
5
A1
A2
INCHES
NOM
0.031
44
11
0.043
0.025
0.004
0.003
0.006
0.010
3.5
0.008
0.006
0.015
0.472
0.472
0.394
0.394
0.035
10
12
MAX
0.047
0.035
0.006
0.010
0.008
0.015
7
0.013
0.008
0.018
0.482
0.482
0.398
0.398
0.045
15
15
MILLIMETERS*
NOM
MAX
0.80
44
11
1.20
1.00
1.10
0.89
0.38
0.64
0.15
0.05
0.10
0.25
0.08
0.08
0.20
0.08
0.14
0.38
0.13
0.25
7
0
3.5
0.33
0.08
0.20
0.20
0.09
0.15
0.45
0.30
0.38
12.25
11.75
12.00
12.25
11.75
12.00
9.90
10.00
10.10
9.90
10.00
10.10
0.64
0.89
1.14
5
10
15
5
12
15
MIN
*
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent: MS-026 ACB
DS30605A-page 134
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
16.9
K04-071 44-Lead Plastic Quad Flatpack (PQ) 10x10x2 mm Body, 1.6/0.15 mm Lead Form
E1
E
# leads = n1
p
D D1
2
1
B
n
X x 45°
α
L
R2
c
A
R1
β
L1
Units
Dimension Limits
Pitch
Number of Pins
Pins along Width
Overall Pack. Height
Shoulder Height
Standoff
Shoulder Radius
Gull Wing Radius
Foot Length
Foot Angle
Radius Centerline
Lead Thickness
Lower Lead Width
Outside Tip Length
Outside Tip Width
Molded Pack. Length
Molded Pack. Width
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
p
n
n1
A
A1
A2
R1
R2
L
φ
L1
c
B†
D1
E1
D‡
E‡
X
α
β
0.079
0.032
0.002
0.005
0.005
0.015
0
0.011
0.005
0.012
0.510
0.510
0.390
0.390
0.025
5
5
φ
A1
A2
INCHES
NOM
0.031
44
11
0.086
0.044
0.006
0.005
0.012
0.020
3.5
0.016
0.007
0.015
0.520
0.520
0.394
0.394
0.035
10
12
MAX
0.093
0.056
0.010
0.010
0.015
0.025
7
0.021
0.009
0.018
0.530
0.530
0.398
0.398
0.045
15
15
MILLIMETERS*
NOM
MAX
0.80
44
11
2.35
2.18
2.00
1.41
1.11
0.81
0.25
0.15
0.05
0.25
0.13
0.13
0.38
0.13
0.30
0.64
0.38
0.51
7
0
3.5
0.53
0.28
0.41
0.23
0.13
0.18
0.45
0.30
0.37
13.45
13.20
12.95
13.45
13.20
12.95
9.90
10.00
10.10
9.90
10.00
10.10
0.89
1.143
0.635
5
10
15
5
12
15
MIN
*
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent: MS-022 AB
 1998 Microchip Technology Inc.
DS30605A-page 135
PIC16C63A/65B/73B/74B
16.10
K04-048 44-Lead Plastic Leaded Chip Carrier (L) – Square
E1
E
# leads = n1
D D1
n12
CH2 x 45°
α
A3
CH1 x 45°
R1
L
35°
A1
R2
β
c
A
B1
B
A2
p
E2
Units
Dimension Limits
Number of Pins
Pitch
Overall Pack. Height
Shoulder Height
Standoff
Side 1 Chamfer Dim.
Corner Chamfer (1)
Corner Chamfer (other)
Overall Pack. Width
Overall Pack. Length
Molded Pack. Width
Molded Pack. Length
Footprint Width
Footprint Length
Pins along Width
Lead Thickness
Upper Lead Width
Lower Lead Width
Upper Lead Length
Shoulder Inside Radius
J-Bend Inside Radius
Mold Draft Angle Top
Mold Draft Angle Bottom
D2
MIN
n
p
A
A1
A2
A3
CH1
CH2
E1
D1
E‡
D‡
E2
D2
n1
c
B1†
B
L
R1
R2
α
β
0.165
0.095
0.015
0.024
0.040
0.000
0.685
0.685
0.650
0.650
0.610
0.610
0.008
0.026
0.015
0.050
0.003
0.015
0
0
INCHES*
NOM
44
0.050
0.173
0.103
0.023
0.029
0.045
0.005
0.690
0.690
0.653
0.653
0.620
0.620
11
0.010
0.029
0.018
0.058
0.005
0.025
5
5
MAX
0.180
0.110
0.030
0.034
0.050
0.010
0.695
0.695
0.656
0.656
0.630
0.630
0.012
0.032
0.021
0.065
0.010
0.035
10
10
MILLIMETERS
NOM
MAX
44
1.27
4.57
4.19
4.38
2.79
2.41
2.60
0.76
0.38
0.57
0.86
0.61
0.74
1.27
1.02
1.14
0.25
0.00
0.13
17.65
17.53
17.40
17.65
17.40
17.53
16.66
16.51
16.59
16.66
16.51
16.59
16.00
15.75
15.49
16.00
15.75
15.49
11
0.30
0.25
0.20
0.81
0.66
0.74
0.38
0.53
0.46
1.65
1.27
1.46
0.08
0.25
0.13
0.38
0.89
0.64
0
5
10
0
5
10
MIN
*
Controlling Parameter.
†
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent: MO-047 AC
DS30605A-page 136
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
APPENDIX A: REVISION HISTORY
Version
Date
Revision Description
A
7/98
This is a new data sheet. However, the devices described in this data sheet are
the upgrades to the devices found in the PIC16C6X Data Sheet, DS30234D, and
the PIC16C7X Data Sheet, DS30390E.
APPENDIX B: DEVICE DIFFERENCES
The differences between the devices in this data sheet
are listed in Table B-1.
TABLE B-1:
DEVICE DIFFERENCES
Difference
PIC16C63A
PIC16C65B
PIC16C73B
PIC16C74B
A/D
no
no
5 channels, 8 bits
8 channels, 8 bits
Parallel Slave Port
no
yes
no
yes
Packages
28-pin PDIP, 28-pin
windowed CERDIP,
28-pin SOIC, 28-pin
SSOP
40-pin PDIP, 40-pin
windowed CERDIP,
44-pin TQFP, 44-pin
MQFP, 44-pin PLCC
28-pin PDIP, 28-pin
windowed CERDIP,
28-pin SOIC, 28-pin
SSOP
40-pin PDIP, 40-pin
windowed CERDIP,
44-pin TQFP, 44-pin
MQFP, 44-pin PLCC
APPENDIX C: CONVERSION CONSIDERATIONS
Considerations for converting from previous versions of
devices to the ones listed in this data sheet are listed in
Table C-1.
TABLE C-1:
CONVERSION CONSIDERATIONS
Difference
PIC16C63/65A/73A/74A
PIC16C63A/65B/73B/74B
Voltage Range
2.5V - 6.0V
2.5V - 5.5V
SSP module
single mode SPI
4-mode SPI
SSP module
Can only transmit one word in SPI mode
of enhanced SSP.
N/A
CCP module
CCP does not reset TMR1 when in special
event trigger mode.
N/A
USART module
USART receiver errata in BRGH=1 mode.
N/A
Timer1 module
Writing to TMR1L register can cause overflow in TMR1H register.
N/A
 1998 Microchip Technology Inc.
DS30605A-page 137
PIC16C63A/65B/73B/74B
APPENDIX D: MIGRATION FROM
BASELINE TO
MIDRANGE DEVICES
This section discusses how to migrate from a baseline
device (i.e., PIC16C5X) to a midrange device (i.e.,
PIC16CXXX).
18. Brown-out protection circuitry has been added.
Controlled by configuration word bit BODEN.
Brown-out reset ensures the device is placed in
a reset condition if VDD dips below a fixed setpoint.
To convert code written for PIC16C5X to PIC16CXXX,
the user should take the following steps:
The following are the list of modifications over the
PIC16C5X microcontroller family:
1.
1.
2.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
Instruction word length is increased to 14-bits.
This allows larger page sizes both in program
memory (2K now as opposed to 512 before) and
register file (128 bytes now versus 32 bytes
before).
A PC high latch register (PCLATH) is added to
handle program memory paging. Bits PA2, PA1,
PA0 are removed from STATUS register.
Data memory paging is redefined slightly.
STATUS register is modified.
Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW.
Two instructions TRIS and OPTION are being
phased out although they are kept for compatibility with PIC16C5X.
OPTION and TRIS registers are made addressable.
Interrupt capability is added. Interrupt vector is
at 0004h.
Stack size is increased to 8 deep.
Reset vector is changed to 0000h.
Reset of all registers is revisited. Five different
reset (and wake-up) types are recognized. Registers are reset differently.
Wake up from SLEEP through interrupt is
added.
Two separate timers, Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) are
included for more reliable power-up. These timers are invoked selectively to avoid unnecessary
delays on power-up and wake-up.
PORTB has weak pull-ups and interrupt on
change feature.
T0CKI pin is also a port pin (RA4) now.
FSR is made a full eight bit register.
“In-circuit serial programming” is made possible.
The user can program PIC16CXX devices using
only five pins: VDD, VSS, MCLR/VPP, RB6 (clock)
and RB7 (data in/out).
PCON status register is added with a Power-on
Reset status bit (POR).
Code protection scheme is enhanced such that
portions of the program memory can be protected, while the remainder is unprotected.
DS30605A-page 138
3.
4.
5.
Remove any program memory page select
operations (PA2, PA1, PA0 bits) for CALL, GOTO.
Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
Eliminate any data memory page switching.
Redefine data variables to reallocate them.
Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
Change reset vector to 0000h.
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
APPENDIX E: BIT/REGISTER CROSSREFERENCE LIST
ADCS1:ADCS0 ..................................ADCON0<7:6>
ADIE ...................................................PIE1<6>
ADIF ...................................................PIR1<6>
ADON .................................................ADCON0<0>
BF ......................................................SSPSTAT<0>
BOR ...................................................PCON<0>
BRGH .................................................TXSTA<2>
C ........................................................STATUS<0>
CCP1IE ..............................................PIE1<2>
CCP1IF ..............................................PIR1<2>
CCP1M3:CCP1M0 .............................CCP1CON<3:0>
CCP1X:CCP1Y ..................................CCP1CON<5:4>
CCP2IE ..............................................PIE2<0>
CCP2IF ..............................................PIR2<0>
CCP2M3:CCP2M0 .............................CCP2CON<3:0>
CCP2X:CCP2Y ..................................CCP2CON<5:4>
CHS2:CHS0 .......................................ADCON0<5:3>
CKE ....................................................SSPSTAT<6>
CKP ....................................................SSPCON<4>
CREN .................................................RCSTA<4>
CSRC .................................................TXSTA<7>
D/A .....................................................SSPSTAT<5>
DC ......................................................STATUS<1>
FERR .................................................RCSTA<2>
GIE .....................................................INTCON<7>
GO/DONE ..........................................ADCON0<2>
IBF .....................................................TRISE<7>
IBOV ...................................................TRISE<5>
INTE ...................................................INTCON<4>
INTEDG .............................................OPTION_REG<6>
INTF ...................................................INTCON<1>
IRP .....................................................STATUS<7>
OBF ....................................................TRISE<6>
OERR .................................................RCSTA<1>
P .........................................................SSPSTAT<4>
PCFG2:PCFG0 ..................................ADCON1<2:0>
PD ......................................................STATUS<3>
PEIE ...................................................INTCON<6>
POR ...................................................PCON<1>
PS2:PS0 ............................................OPTION_REG<2:0>
PSA ....................................................OPTION_REG<3>
PSPIE ................................................PIE1<7>
PSPIF .................................................PIR1<7>
PSPMODE .........................................TRISE<4>
R/W ....................................................SSPSTAT<2>
RBIE ...................................................INTCON<3>
RBIF ...................................................INTCON<0>
RBPU .................................................OPTION_REG<7>
RCIE ..................................................PIE1<5>
RCIF ...................................................PIR1<5>
RP1:RP0 ............................................STATUS<6:5>
RX9 ....................................................RCSTA<6>
RX9D .................................................RCSTA<0>
S .........................................................SSPSTAT<3>
SMP ...................................................SSPSTAT<7>
SPEN .................................................RCSTA<7>
SREN .................................................RCSTA<5>
SSPEN ...............................................SSPCON<5>
SSPIE ................................................PIE1<3>
SSPIF .................................................PIR1<3>
SSPM3:SSPM0 ..................................SSPCON<3:0>
SSPOV ...............................................SSPCON<6>
SYNC .................................................TXSTA<4>
T0CS ..................................................OPTION_REG<5>
 1998 Microchip Technology Inc.
T0IE ................................................... INTCON<5>
T0IF ................................................... INTCON<2>
T0SE .................................................. OPTION_REG<4>
T1CKPS1:T1CKPS0 .......................... T1CON<5:4>
T1OSCEN .......................................... T1CON<3>
T1SYNC ............................................ T1CON<2>
T2CKPS1:T2CKPS0 .......................... T2CON<1:0>
TMR1CS ............................................ T1CON<1>
TMR1IE ............................................. PIE1<0>
TMR1IF .............................................. PIR1<0>
TMR1ON ........................................... T1CON<0>
TMR2IE ............................................. PIE1<1>
TMR2IF .............................................. PIR1<1>
TMR2ON ........................................... T2CON<2>
TO ...................................................... STATUS<4>
TOUTPS3:TOUTPS0 ......................... T2CON<6:3>
TRMT ................................................. TXSTA<1>
TX9 .................................................... TXSTA<6>
TX9D ................................................. TXSTA<0>
TXEN ................................................. TXSTA<5>
TXIE ................................................... PIE1<4>
TXIF ................................................... PIR1<4>
UA ...................................................... SSPSTAT<1>
WCOL ................................................ SSPCON<7>
Z ........................................................ STATUS<2>
DS30605A-page 139
PIC16C63A/65B/73B/74B
NOTES:
DS30605A-page 140
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
INDEX
A
A/D ...................................................................................... 75
A/D Converter Enable (ADIE Bit) ................................ 18
A/D Converter Flag (ADIF Bit) .............................. 19, 77
A/D Converter Interrupt, Configuring .......................... 77
ADCON0 Register................................................. 13, 75
ADCON1 Register........................................... 14, 75, 76
ADRES Register ............................................. 13, 75, 77
Analog Port Pins ....................................... 7, 8, 9, 34, 35
Analog Port Pins, Configuring..................................... 79
Block Diagram............................................................. 77
Block Diagram, Analog Input Model............................ 78
Channel Select (CHS2:CHS0 Bits) ............................. 75
Clock Select (ADCS1:ADCS0 Bits)............................. 75
Configuring the Module............................................... 77
Conversion Clock (TAD) .............................................. 79
Conversion Status (GO/DONE Bit) ....................... 75, 77
Conversions ................................................................ 80
Converter Characteristics ......................................... 121
Module On/Off (ADON Bit).......................................... 75
Port Configuration Control (PCFG2:PCFG0 Bits) ....... 76
Sampling Requirements.............................................. 78
Special Event Trigger (CCP)................................. 47, 80
Timing Diagram......................................................... 122
Absolute Maximum Ratings .............................................. 101
ADCON0 Register......................................................... 13, 75
ADCS1:ADCS0 Bits .................................................... 75
ADON Bit .................................................................... 75
CHS2:CHS0 Bits......................................................... 75
GO/DONE Bit........................................................ 75, 77
ADCON1 Register................................................... 14, 75, 76
PCFG2:PCFG0 Bits .................................................... 76
ADRES Register ..................................................... 13, 75, 77
Architecture
PIC16C63A/PIC16C73B Block Diagram....................... 5
PIC16C65B/PIC16C74B Block Diagram....................... 6
Assembler
MPASM Assembler..................................................... 98
B
Banking, Data Memory ................................................. 11, 15
Brown-out Reset (BOR) .............................. 81, 83, 85, 86, 87
BOR Enable (BODEN Bit)........................................... 81
BOR Status (BOR Bit)................................................. 22
Timing Diagram......................................................... 110
C
Capture (CCP Module) ....................................................... 46
Block Diagram............................................................. 46
CCP Pin Configuration................................................ 46
CCPR1H:CCPR1L Registers...................................... 46
Changing Between Capture Prescalers...................... 46
Software Interrupt ....................................................... 46
Timer1 Mode Selection ............................................... 46
Capture/Compare/PWM (CCP)........................................... 45
CCP1 .......................................................................... 45
CCP1CON Register ...................................... 13, 45
CCPR1H Register......................................... 13, 45
CCPR1L Register ......................................... 13, 45
Enable (CCP1IE Bit) ........................................... 18
Flag (CCP1IF Bit) ............................................... 19
RC2/CCP1 Pin.................................................. 7, 9
CCP2 .......................................................................... 45
CCP2CON Register ...................................... 13, 45
CCPR2H Register......................................... 13, 45
CCPR2L Register ......................................... 13, 45
Enable (CCP2IE Bit) ........................................... 20
 1998 Microchip Technology Inc.
Flag (CCP2IF Bit) ............................................... 21
RC1/T1OSI/CCP2 Pin ...................................... 7, 9
Interaction of Two CCP Modules................................ 45
Timer Resources ........................................................ 45
Timing Diagram ........................................................ 112
CCP1CON Register............................................................ 45
CCP1M3:CCP1M0 Bits .............................................. 45
CCP1X:CCP1Y Bits.................................................... 45
CCP2CON Register............................................................ 45
CCP2M3:CCP2M0 Bits .............................................. 45
CCP2X:CCP2Y Bits.................................................... 45
Code Protection ............................................................ 81, 94
CP1:CP0 Bits.............................................................. 81
Compare (CCP Module) ..................................................... 47
Block Diagram ............................................................ 47
CCP Pin Configuration ............................................... 47
CCPR1H:CCPR1L Registers ..................................... 47
Software Interrupt ....................................................... 47
Special Event Trigger ..................................... 41, 47, 80
Timer1 Mode Selection............................................... 47
Configuration Bits ............................................................... 81
Conversion Considerations .............................................. 137
D
Data Memory ...................................................................... 11
Bank Select (RP1:RP0 Bits) ................................. 11, 15
General Purpose Registers ........................................ 11
Register File Map ....................................................... 12
Special Function Registers................................... 12, 13
DC Characteristics.................................................... 102, 104
Development Support ......................................................... 97
Development Tools............................................................. 97
Device Differences ........................................................... 137
Direct Addressing ............................................................... 24
E
Electrical Characteristics .................................................. 101
Errata .....................................................................................4
External Power-on Reset Circuit ........................................ 85
F
Firmware Instructions ......................................................... 95
ftp site ............................................................................... 147
Fuzzy Logic Dev. System (fuzzyTECH-MP) .................... 99
I
I/O Ports ............................................................................. 25
I2C (SSP Module) ............................................................... 56
ACK Pulse .......................................... 56, 57, 58, 59, 60
Addressing.................................................................. 57
Block Diagram ............................................................ 56
Buffer Full Status (BF Bit)........................................... 52
Clock Polarity Select (CKP Bit)................................... 53
Data/Address (D/A Bit) ............................................... 52
Master Mode............................................................... 60
Mode Select (SSPM3:SSPM0 Bits)............................ 53
Multi-Master Mode...................................................... 60
Read/Write Bit Information (R/W Bit)........ 52, 57, 58, 59
Receive Overflow Indicator (SSPOV Bit).................... 53
Reception ................................................................... 58
Reception Timing Diagram ......................................... 58
Serial Clock (RC3/SCK/SCL) ..................................... 59
Slave Mode................................................................. 56
Start (S Bit) ........................................................... 52, 60
Stop (P Bit) ........................................................... 52, 60
Synchronous Serial Port Enable (SSPEN Bit)............ 53
Timing Diagram, Data............................................... 119
Timing Diagram, Start/Stop Bits ............................... 118
Transmission .............................................................. 59
Update Address (UA Bit) ............................................ 52
ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ............ 97
DS30605A-page 141
PIC16C63A/65B/73B/74B
ID Locations .................................................................. 81, 94
In-Circuit Serial Programming (ICSP) ........................... 81, 94
Indirect Addressing ............................................................. 24
FSR Register .................................................. 11, 13, 24
INDF Register ............................................................. 13
Instruction Format ............................................................... 95
Instruction Set ..................................................................... 95
Summary Table........................................................... 96
INTCON Register .......................................................... 13, 17
GIE Bit......................................................................... 17
INTE Bit....................................................................... 17
INTF Bit ....................................................................... 17
PEIE Bit....................................................................... 17
RBIE Bit ...................................................................... 17
RBIF Bit................................................................. 17, 27
T0IE Bit ....................................................................... 17
T0IF Bit ....................................................................... 17
Interrupt Sources........................................................... 81, 90
A/D Conversion Complete .......................................... 77
Block Diagram............................................................. 90
Capture Complete (CCP)............................................ 46
Compare Complete (CCP).......................................... 47
Interrupt on Change (RB7:RB4 )................................. 27
RB0/INT Pin, External......................................... 7, 8, 91
SSP Receive/Transmit Complete ............................... 51
TMR0 Overflow ..................................................... 38, 91
TMR1 Overflow ..................................................... 39, 41
TMR2 to PR2 Match ................................................... 44
TMR2 to PR2 Match (PWM) ................................. 43, 48
USART Receive/Transmit Complete .......................... 61
Interrupts, Context Saving During ....................................... 91
Interrupts, Enable Bits
A/D Converter Enable (ADIE Bit) ................................ 18
CCP1 Enable (CCP1IE Bit)................................... 18, 46
CCP2 Enable (CCP2IE Bit)......................................... 20
Global Interrupt Enable (GIE Bit) .......................... 17, 90
Interrupt on Change (RB7:RB4) Enable
(RBIE Bit) .............................................................. 17, 91
Peripheral Interrupt Enable (PEIE Bit) ........................ 17
PSP Read/Write Enable (PSPIE Bit) .......................... 18
RB0/INT Enable (INTE Bit) ......................................... 17
SSP Enable (SSPIE Bit) ............................................. 18
TMR0 Overflow Enable (T0IE Bit)............................... 17
TMR1 Overflow Enable (TMR1IE Bit) ......................... 18
TMR2 to PR2 Match Enable (TMR2IE Bit) ................. 18
USART Receive Enable (RCIE Bit) ............................ 18
USART Transmit Enable (TXIE Bit) ............................ 18
Interrupts, Flag Bits
A/D Converter Flag (ADIF Bit) .............................. 19, 77
CCP1 Flag (CCP1IF Bit) ................................. 19, 46, 47
CCP2 Flag (CCP2IF Bit) ............................................. 21
Interrupt on Change (RB7:RB4) Flag
(RBIF Bit) ........................................................ 17, 27, 91
PSP Read/Write Flag (PSPIF Bit)............................... 19
RB0/INT Flag (INTF Bit).............................................. 17
SSP Flag (SSPIF Bit).................................................. 19
TMR0 Overflow Flag (T0IF Bit) ............................. 17, 91
TMR1 Overflow Flag (TMR1IF Bit) ............................. 19
TMR2 to PR2 Match Flag (TMR2IF Bit) ...................... 19
USART Receive Flag (RCIF Bit) ................................. 19
USART Transmit Flag (TXIE Bit) ................................ 19
K
KeeLoq Evaluation and Programming Tools.................... 99
M
Master Clear (MCLR) ........................................................ 7, 8
MCLR Reset, Normal Operation ..................... 83, 86, 87
MCLR Reset, SLEEP...................................... 83, 86, 87
DS30605A-page 142
Memory Organization
Data Memory .............................................................. 11
Program Memory ........................................................ 11
MP-DriveWay™ - Application Code Generator .................. 99
MPLAB C ............................................................................ 99
MPLAB Integrated Development Environment
Software ..................................................................... 98
O
On-Line Support ............................................................... 147
OPCODE Field Descriptions............................................... 95
OPTION_REG Register................................................ 14, 16
INTEDG Bit ................................................................. 16
PS2:PS0 Bits ........................................................ 16, 37
PSA Bit ................................................................. 16, 37
RBPU Bit .................................................................... 16
T0CS Bit ............................................................... 16, 37
T0SE Bit ............................................................... 16, 37
OSC1/CLKIN Pin .............................................................. 7, 8
OSC2/CLKOUT Pin .......................................................... 7, 8
Oscillator Configuration ................................................ 81, 82
HS......................................................................... 82, 86
LP ......................................................................... 82, 86
RC .................................................................. 82, 83, 86
Selection (FOSC1:FOSC0 Bits) ................................. 81
XT ......................................................................... 82, 86
Oscillator, Timer1.......................................................... 39, 41
Oscillator, WDT................................................................... 92
P
Packaging ......................................................................... 125
Paging, Program Memory............................................. 11, 23
Parallel Slave Port (PSP).......................................... 9, 31, 35
Block Diagram ............................................................ 35
RE0/RD/AN5 Pin .............................................. 9, 34, 35
RE1/WR/AN6 Pin ............................................. 9, 34, 35
RE2/CS/AN7 Pin .............................................. 9, 34, 35
Read Waveforms ........................................................ 36
Read/Write Enable (PSPIE Bit) .................................. 18
Read/Write Flag (PSPIF Bit)....................................... 19
Select (PSPMODE Bit) ................................... 31, 33, 35
Timing Diagram ........................................................ 113
Write Waveforms ........................................................ 35
PCON Register ............................................................. 22, 86
BOR Bit....................................................................... 22
POR Bit....................................................................... 22
PICDEM-1 Low-Cost PICmicro Demo Board ..................... 98
PICDEM-2 Low-Cost PIC16CXX Demo Board................... 98
PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 98
PICMASTER In-Circuit Emulator ..................................... 97
PICSTART Plus Entry Level Development System ......... 97
PIE1 Register................................................................ 14, 18
ADIE Bit ...................................................................... 18
CCP1IE Bit ................................................................. 18
PSPIE Bit .................................................................... 18
RCIE Bit ...................................................................... 18
SSPIE Bit .................................................................... 18
TMR1IE Bit ................................................................. 18
TMR2IE Bit ................................................................. 18
TXIE Bit ...................................................................... 18
PIE2 Register................................................................ 14, 20
CCP2IE Bit ................................................................. 20
Pinout Descriptions
PIC16C63A/PIC16C73B............................................... 7
PIC16C65B/PIC16C74B............................................... 8
PIR1 Register ............................................................... 13, 19
ADIF Bit ...................................................................... 19
CCP1IF Bit.................................................................. 19
PSPIF Bit .................................................................... 19
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
RCIF Bit ...................................................................... 19
SSPIF Bit .................................................................... 19
TMR1IF Bit.................................................................. 19
TMR2IF Bit.................................................................. 19
TXIF Bit ....................................................................... 19
PIR2 Register................................................................ 13, 21
CCP2IF Bit .................................................................. 21
Pointer, FSR ....................................................................... 24
PORTA.............................................................................. 7, 8
Analog Port Pins ....................................................... 7, 8
Initialization ................................................................. 25
PORTA Register ................................................... 13, 25
RA3:RA0 and RA5 Port Pins ...................................... 25
RA4/T0CKI Pin.................................................... 7, 8, 25
RA5/SS/AN4 Pin ................................................. 7, 8, 54
TRISA Register ..................................................... 14, 25
PORTB.............................................................................. 7, 8
Initialization ................................................................. 27
PORTB Register ................................................... 13, 27
Pull-up Enable (RBPU Bit) .......................................... 16
RB0/INT Edge Select (INTEDG Bit)............................ 16
RB0/INT Pin, External......................................... 7, 8, 91
RB3:RB0 Port Pins ..................................................... 27
RB7:RB4 Interrupt on Change .................................... 91
RB7:RB4 Interrupt on Change Enable
(RBIE Bit) .............................................................. 17, 91
RB7:RB4 Interrupt on Change Flag
(RBIF Bit) ........................................................ 17, 27, 91
RB7:RB4 Port Pins ..................................................... 27
TRISB Register ..................................................... 14, 27
PORTC ............................................................................. 7, 9
Block Diagram............................................................. 29
Initialization ................................................................. 29
PORTC Register ................................................... 13, 29
RC0/T1OSO/T1CKI Pin ............................................ 7, 9
RC1/T1OSI/CCP2 Pin............................................... 7, 9
RC2/CCP1 Pin .......................................................... 7, 9
RC3/SCK/SCL Pin ........................................ 7, 9, 54, 59
RC4/SDI/SDA Pin ............................................... 7, 9, 54
RC5/SDO Pin...................................................... 7, 9, 54
RC6/TX/CK Pin ................................................... 7, 9, 62
RC7/RX/DT Pin............................................. 7, 9, 62, 63
TRISC Register............................................... 14, 29, 61
PORTD ........................................................................... 9, 35
Block Diagram............................................................. 31
Parallel Slave Port (PSP) Function ............................. 31
PORTD Register ................................................... 13, 31
TRISD Register..................................................... 14, 31
PORTE.................................................................................. 9
Analog Port Pins ............................................... 9, 34, 35
Block Diagram............................................................. 33
Input Buffer Full Status (IBF Bit) ................................. 33
Input Buffer Overflow (IBOV Bit) ................................. 33
Output Buffer Full Status (OBF Bit)............................. 33
PORTE Register ................................................... 13, 33
PSP Mode Select (PSPMODE Bit) ................. 31, 33, 35
RE0/RD/AN5 Pin............................................... 9, 34, 35
RE1/WR/AN6 Pin.............................................. 9, 34, 35
RE2/CS/AN7 Pin............................................... 9, 34, 35
TRISE Register ..................................................... 14, 33
Postscaler, Timer2
Select (TOUTPS3:TOUTPS0 Bits) ............................. 43
Postscaler, WDT ................................................................. 37
Assignment (PSA Bit) ........................................... 16, 37
Block Diagram............................................................. 38
Rate Select (PS2:PS0 Bits) .................................. 16, 37
Switching Between Timer0 and WDT ......................... 38
 1998 Microchip Technology Inc.
Power-on Reset (POR)............................... 81, 83, 85, 86, 87
Oscillator Start-up Timer (OST)............................ 81, 85
POR Status (POR Bit) ................................................ 22
Power Control (PCON) Register................................. 86
Power-down (PD Bit) ............................................ 15, 83
Power-on Reset Circuit, External ............................... 85
Power-up Timer (PWRT) ...................................... 81, 85
PWRT Enable (PWRTE Bit) ....................................... 81
Time-out (TO Bit).................................................. 15, 83
Time-out Sequence .................................................... 86
Time-out Sequence on Power-up......................... 88, 89
Timing Diagram ........................................................ 110
Prescaler, Capture.............................................................. 46
Prescaler, Timer0 ............................................................... 37
Assignment (PSA Bit) ........................................... 16, 37
Block Diagram ............................................................ 38
Rate Select (PS2:PS0 Bits) .................................. 16, 37
Switching Between Timer0 and WDT......................... 38
Prescaler, Timer1 ............................................................... 40
Select (T1CKPS1:T1CKPS0 Bits) .............................. 39
Prescaler, Timer2 ............................................................... 48
Select (T2CKPS1:T2CKPS0 Bits) .............................. 43
PRO MATE II Universal Programmer .............................. 97
Product Identification System ........................................... 149
Program Counter
PCL Register ........................................................ 13, 23
PCLATH Register ........................................... 13, 23, 91
Reset Conditions ........................................................ 86
Program Memory ................................................................ 11
Interrupt Vector........................................................... 11
Paging .................................................................. 11, 23
Program Memory Map................................................ 11
Reset Vector............................................................... 11
Program Verification ........................................................... 94
Programming Pin (VPP) .................................................... 7, 8
Programming, Device Instructions...................................... 95
PWM (CCP Module) ........................................................... 48
Block Diagram ............................................................ 48
CCPR1H:CCPR1L Registers ..................................... 48
Duty Cycle .................................................................. 48
Example Frequencies/Resolutions ............................. 49
Output Diagram .......................................................... 48
Period ......................................................................... 48
Set-Up for PWM Operation......................................... 49
TMR2 to PR2 Match ............................................. 43, 48
TMR2 to PR2 Match Enable (TMR2IE Bit) ................. 18
TMR2 to PR2 Match Flag (TMR2IF Bit) ..................... 19
Q
Q-Clock............................................................................... 48
R
RCSTA Register ................................................................. 62
CREN Bit .................................................................... 62
FERR Bit..................................................................... 62
OERR Bit .................................................................... 62
RX9 Bit ....................................................................... 62
RX9D Bit..................................................................... 62
SPEN Bit............................................................... 61, 62
SREN Bit .................................................................... 62
Reader Response............................................................. 148
Register File ....................................................................... 11
Register File Map ............................................................... 12
Reset ............................................................................ 81, 83
Block Diagram ............................................................ 84
Reset Conditions for All Registers.............................. 87
Reset Conditions for PCON Register ......................... 86
Reset Conditions for Program Counter ...................... 86
Reset Conditions for STATUS Register ..................... 86
DS30605A-page 143
PIC16C63A/65B/73B/74B
Timing Diagram......................................................... 110
Revision History ................................................................ 137
S
SEEVAL Evaluation and Programming System ............... 99
SLEEP..................................................................... 81, 83, 93
Software Simulator (MPLAB-SIM)....................................... 99
Special Features of the CPU............................................... 81
Special Function Registers ........................................... 12, 13
Speed, Operating .......................................................... 1, 101
SPI (SSP Module)
Block Diagram............................................................. 54
Buffer Full Status (BF Bit) ........................................... 52
Clock Edge Select (CKE Bit)....................................... 52
Clock Polarity Select (CKP Bit) ................................... 53
Data Input Sample Phase (SMP Bit)........................... 52
Mode Select (SSPM3:SSPM0 Bits) ............................ 53
Receive Overflow Indicator (SSPOV Bit) .................... 53
Serial Clock (RC3/SCK/SCL)...................................... 54
Serial Data In (RC4/SDI/SDA) .................................... 54
Serial Data Out (RC5/SDO) ........................................ 54
Slave Select (RA5/SS/AN4)........................................ 54
Synchronous Serial Port Enable (SSPEN Bit) ............ 53
SSP ..................................................................................... 51
Enable (SSPIE Bit)...................................................... 18
Flag (SSPIF Bit) .......................................................... 19
RA5/SS/AN4 Pin ....................................................... 7, 8
RC3/SCK/SCL Pin .................................................... 7, 9
RC4/SDI/SDA Pin ..................................................... 7, 9
RC5/SDO Pin............................................................ 7, 9
RCSTA Register ......................................................... 13
SPBRG Register ......................................................... 14
SSPADD Register....................................................... 14
SSPBUF Register ....................................................... 13
SSPCON Register ................................................ 13, 53
SSPSTAT Register ............................................... 14, 52
TMR2 Output for Clock Shift ................................. 43, 44
TXSTA Register .......................................................... 14
Write Collision Detect (WCOL Bit) .............................. 53
SSPCON Register............................................................... 53
CKP Bit ....................................................................... 53
SSPEN Bit................................................................... 53
SSPM3:SSPM0 Bits.................................................... 53
SSPOV Bit .................................................................. 53
WCOL Bit .................................................................... 53
SSPSTAT Register ............................................................. 52
BF Bit .......................................................................... 52
CKE Bit ....................................................................... 52
D/A Bit......................................................................... 52
P bit....................................................................... 52, 60
R/W Bit ...................................................... 52, 57, 58, 59
S Bit ...................................................................... 52, 60
SMP Bit ....................................................................... 52
UA Bit.......................................................................... 52
Stack ................................................................................... 23
STATUS Register.................................................... 13, 15, 91
C Bit ............................................................................ 15
DC Bit.......................................................................... 15
IRP Bit......................................................................... 15
PD Bit.................................................................... 15, 83
RP1:RP0 Bits .............................................................. 15
TO Bit .................................................................... 15, 83
Z Bit............................................................................. 15
T
T1CON Register............................................................ 13, 39
T1CKPS1:T1CKPS0 Bits ............................................ 39
T1OSCEN Bit.............................................................. 39
T1SYNC Bit................................................................. 39
DS30605A-page 144
TMR1CS Bit................................................................ 39
TMR1ON Bit ............................................................... 39
T2CON Register ........................................................... 13, 43
T2CKPS1:T2CKPS0 Bits............................................ 43
TMR2ON Bit ............................................................... 43
TOUTPS3:TOUTPS0 Bits .......................................... 43
Timer0................................................................................. 37
Block Diagram ............................................................ 37
Clock Source Edge Select (T0SE Bit) .................. 16, 37
Clock Source Select (T0CS Bit) ........................... 16, 37
Overflow Enable (T0IE Bit) ......................................... 17
Overflow Flag (T0IF Bit) ....................................... 17, 91
Overflow Interrupt ................................................. 38, 91
RA4/T0CKI Pin, External Clock ................................ 7, 8
Timing Diagram ........................................................ 111
TMR0 Register ........................................................... 13
Timer1................................................................................. 39
Block Diagram ............................................................ 40
Capacitor Selection .................................................... 41
Clock Source Select (TMR1CS Bit) ............................ 39
External Clock Input Sync (T1SYNC Bit).................... 39
Module On/Off (TMR1ON Bit) .................................... 39
Oscillator............................................................... 39, 41
Oscillator Enable (T1OSCEN Bit) ............................... 39
Overflow Enable (TMR1IE Bit) ................................... 18
Overflow Flag (TMR1IF Bit) ........................................ 19
Overflow Interrupt ................................................. 39, 41
RC0/T1OSO/T1CKI Pin ............................................ 7, 9
RC1/T1OSI/CCP2 Pin .............................................. 7, 9
Special Event Trigger (CCP) ................................ 41, 47
T1CON Register ................................................... 13, 39
Timing Diagram ........................................................ 111
TMR1H Register ................................................... 13, 39
TMR1L Register ................................................... 13, 39
Timer2
Block Diagram ............................................................ 44
PR2 Register .................................................. 14, 43, 48
SSP Clock Shift .................................................... 43, 44
T2CON Register ................................................... 13, 43
TMR2 Register ..................................................... 13, 43
TMR2 to PR2 Match Enable (TMR2IE Bit) ................. 18
TMR2 to PR2 Match Flag (TMR2IF Bit) ..................... 19
TMR2 to PR2 Match Interrupt......................... 43, 44, 48
Timing Diagrams
I2C Reception (7-bit Address)..................................... 58
Time-out Sequence on Power-up ......................... 88, 89
USART Asynchronous Master Transmission ............. 67
USART Asynchronous Reception .............................. 68
USART Synchronous Reception ................................ 72
USART Synchronous Transmission ........................... 71
Wake-up from SLEEP via Interrupt ............................ 94
Timing Diagrams and Specifications ................................ 108
A/D Conversion ........................................................ 122
Brown-out Reset (BOR)............................................ 110
Capture/Compare/PWM (CCP) ................................ 112
CLKOUT and I/O ...................................................... 109
External Clock .......................................................... 108
I2C Bus Data............................................................. 119
I2C Bus Start/Stop Bits ............................................. 118
Oscillator Start-up Timer (OST) ................................ 110
Parallel Slave Port (PSP) ......................................... 113
Power-up Timer (PWRT) .......................................... 110
Reset ........................................................................ 110
Timer0 and Timer1 ................................................... 111
USART Synchronous Receive
( Master/Slave) ......................................................... 120
USART SynchronousTransmission
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
( Master/Slave).......................................................... 120
Watchdog Timer (WDT) ............................................ 110
TRISE Register ............................................................. 14, 33
IBF Bit ......................................................................... 33
IBOV Bit ...................................................................... 33
OBF Bit ....................................................................... 33
PSPMODE Bit................................................. 31, 33, 35
TXSTA Register .................................................................. 61
BRGH Bit .............................................................. 61, 63
CSRC Bit..................................................................... 61
SYNC Bit..................................................................... 61
TRMT Bit..................................................................... 61
TX9 Bit ........................................................................ 61
TX9D Bit...................................................................... 61
TXEN Bit ..................................................................... 61
Timing Diagram .......................................................... 94
WDT Reset ................................................................. 87
Watchdog Timer (WDT)................................................ 81, 92
Block Diagram ............................................................ 92
Enable (WDTE Bit) ............................................... 81, 92
Programming Considerations ..................................... 92
RC Oscillator .............................................................. 92
Time-out Period .......................................................... 92
Timing Diagram ........................................................ 110
WDT Reset, Normal Operation....................... 83, 86, 87
WDT Reset, SLEEP ....................................... 83, 86, 87
WWW, On-Line Support ............................................... 4, 147
U
USART ................................................................................ 61
Asynchronous Mode ................................................... 66
Master Transmission .......................................... 67
Receive Block Diagram ...................................... 68
Reception............................................................ 68
Transmit Block Diagram ..................................... 66
Baud Rate Generator (BRG)....................................... 63
Baud Rate Error, Calculating .............................. 63
Baud Rate Formula............................................. 63
Baud Rates, Asynchronous Mode
(BRGH=0) ........................................................... 64
Baud Rates, Asynchronous Mode
(BRGH=1) ........................................................... 65
Baud Rates, Synchronous Mode ........................ 64
High Baud Rate Select (BRGH Bit) .............. 61, 63
Sampling............................................................. 63
Clock Source Select (CSRC Bit)................................. 61
Continuous Receive Enable (CREN Bit)..................... 62
Framing Error (FERR Bit) ........................................... 62
Mode Select (SYNC Bit) ............................................. 61
Overrun Error (OERR Bit) ........................................... 62
RC6/TX/CK Pin ......................................................... 7, 9
RC7/RX/DT Pin......................................................... 7, 9
RCREG Register......................................................... 13
RCSTA Register ......................................................... 62
Receive Data, 9th bit (RX9D Bit) ................................ 62
Receive Enable (RCIE Bit).......................................... 18
Receive Enable, 9-bit (RX9 Bit) .................................. 62
Receive Flag (RCIF Bit) .............................................. 19
Serial Port Enable (SPEN Bit)............................... 61, 62
Single Receive Enable (SREN Bit) ............................. 62
Synchronous Master Mode ......................................... 70
Reception............................................................ 72
Timing Diagram, Synchronous Receive ........... 120
Timing Diagram, Synchronous
Transmission .................................................... 120
Transmission ...................................................... 71
Synchronous Slave Mode ........................................... 73
Transmit Data, 9th Bit (TX9D)..................................... 61
Transmit Enable (TXEN Bit)........................................ 61
Transmit Enable (TXIE Bit) ......................................... 18
Transmit Enable, Nine-bit (TX9 Bit) ............................ 61
Transmit Flag (TXIE Bit) ............................................. 19
Transmit Shift Register Status (TRMT Bit).................. 61
TXREG Register ......................................................... 13
TXSTA Register .......................................................... 61
W
W Register .......................................................................... 91
Wake-up from SLEEP................................................... 81, 93
Interrupts............................................................... 86, 87
MCLR Reset ............................................................... 87
 1998 Microchip Technology Inc.
DS30605A-page 145
PIC16C63A/65B/73B/74B
NOTES:
DS30605A-page 146
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
Connecting to the Microchip Internet Web Site
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-602-786-7302 for the rest of the world.
980106
The Microchip web site is available by using your
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The file transfer site is available by using an FTP service to connect to:
ftp://ftp.futureone.com/pub/microchip
The web site and file transfer site provide a variety of
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 1998 Microchip Technology Inc.
Trademarks: The Microchip name, logo, PIC, PICSTART,
PICMASTER and PRO MATE are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries. PICmicro, FlexROM, MPLAB and fuzzyLAB are
trademarks and SQTP is a service mark of Microchip in
the U.S.A.
All other trademarks mentioned herein are the property of
their respective companies.
DS30605A-page 147
PIC16C63A/65B/73B/74B
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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Device: PIC16C63A/65B/73B/74B Literature Number: DS30605A
Questions:
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3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
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DS30605A-page 148
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
PIC16C63A/65B/73B/74B PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
-XX
Frequency Temperature
Range
Range
/XX
XXX
Package
Pattern
Examples:
a)
b)
Device
PIC16C6X(1), PIC16C6XT(2);VDD range 4.0V to
PIC16LC6X(1), PIC16LC6XT(2);VDD range 2.5V
PIC16C7X(1), PIC16C7XT(2);VDD range 4.0V to
PIC16LC7X(1), PIC16LC7XT(2);VDD range 2.5V
Frequency Range
04
20
= 4 MHz
= 20 MHz
Temperature Range
blank
I
E
=
0°C to
70°C
= -40°C to +85°C
= -40°C to +125°C
Package
JW
PQ
PT
SO
SP
P
L
SS
=
=
=
=
=
=
=
=
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
5.5V
to 5.5V
5.5V
to 5.5V
c)
PIC16C74B -04/P 301 = Commercial temp.,
PDIP package, 4 MHz, normal VDD limits, QTP
pattern #301.
PIC16LC63A - 04I/SO = Industrial temp., SOIC
package, 200 kHz, Extended VDD limits.
PIC16C65B - 20I/P = Industrial temp., PDIP
package, 20MHz, normal VDD limits.
Note 1:
2:
(Commercial)
(Industrial)
(Extended)
C
LC
T
= CMOS
= Low Power CMOS
= in tape and reel - SOIC, SSOP,
PLCC, QFP, TQ and FP
packages only.
Windowed CERDIP
MQFP (Metric PQFP)
TQFP (Thin Quad Flatpack)
SOIC
Skinny plastic dip
PDIP
PLCC
SSOP
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type (including LC devices).
 1998 Microchip Technology Inc.
DS30605A-page 149
PIC16C63A/65B/73B/74B
NOTES:
DS30605A-page 150
 1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
NOTES:
 1998 Microchip Technology Inc.
DS30605A-page 151
M
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
ASIA/PACIFIC (continued)
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New York
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San Jose
Microchip Technology Inc.
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Tel: 408-436-7950 Fax: 408-436-7955
All rights reserved. © 1998, Microchip Technology Incorporated, USA. 8/98
Arizona Microchip Technology SARL
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Italy
7/7/98
Microchip received ISO 9001 Quality
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Our field-programmable PICmicro™
8-bit MCUs, Serial EEPROMs,
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Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no
liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use
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trademarks mentioned herein are the property of their respective companies.
DS30605A-page 152
 1998 Microchip Technology Inc.