PIC17C4X
High-Performance 8-Bit CMOS EPROM/ROM Microcontroller
Devices included in this data sheet:
PIC17CR42
PIC17C42A
PIC17C43
PIC17CR43
PIC17C44
PIC17C42†
PDIP, CERDIP, Windowed CERDIP
Microcontroller Core Features:
✯
• Only 58 single word instructions to learn
• All single cycle instructions (121 ns) except for
program branches and table reads/writes which
are two-cycle
• Operating speed:
- DC - 33 MHz clock input
- DC - 121 ns instruction cycle
Program Memory
Device
Data Memory
EPROM
✯
ROM
PIC17CR42
2K
232
PIC17C42A
2K
232
PIC17C43
4K
454
PIC17CR43
4K
454
PIC17C44
8K
454
PIC17C42†
2K
232
• Hardware Multiplier
(Not available on the PIC17C42)
• Interrupt capability
• 16 levels deep hardware stack
• Direct, indirect and relative addressing modes
• Internal/External program memory execution
• 64K x 16 addressable program memory space
Peripheral Features:
• 33 I/O pins with individual direction control
• High current sink/source for direct LED drive
- RA2 and RA3 are open drain, high voltage
(12V), high current (60 mA), I/O
• Two capture inputs and two PWM outputs
- Captures are 16-bit, max resolution 160 ns
- PWM resolution is 1- to 10-bit
• TMR0: 16-bit timer/counter with 8-bit programmable prescaler
• TMR1: 8-bit timer/counter
VDD
RC0/AD0
RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
VSS
RB0/CAP1
RB1/CAP2
RB2/PWM1
RB3/PWM2
RB4/TCLK12
RB5/TCLK3
RB6
RB7
OSC1/CLKIN
OSC2/CLKOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC17C4X
•
•
•
•
•
•
Pin Diagram
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RD0/AD8
RD1/AD9
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
MCLR/VPP
VSS
RE0/ALE
RE1/OE
RE2/WR
TEST
RA0/INT
RA1/T0CKI
RA2
RA3
RA4/RX/DT
RA5/TX/CK
• TMR2: 8-bit timer/counter
• TMR3: 16-bit timer/counter
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
Special Microcontroller Features:
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Code-protection
• Power saving SLEEP mode
• Selectable oscillator options
CMOS Technology:
• Low-power, high-speed CMOS EPROM/ROM
technology
• Fully static design
• Wide operating voltage range (2.5V to 6.0V)
• Commercial and Industrial Temperature Range
• Low-power consumption
- < 5 mA @ 5V, 4 MHz
- 100 µA typical @ 4.5V, 32 kHz
- < 1 µA typical standby current @ 5V
†NOT recommended for new designs, use 17C42A.
1996 Microchip Technology Inc.
DS30412C-page 1
This document was created with FrameMaker 4 0 4
PIC17C4X
MQFP
TQFP
39
38
37
36
35
34
33
32
31
30
29
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
MCLR/VPP
VSS
VSS
RE0/ALE
RE1/OE
RE2/WR
TEST
28
27
26
25
24
23
22
21
20
19
18
TEST
RE2/WR
RE1/OE
RE0/ALE
VSS
VSS
MCLR/VPP
RD7/AD15
RD6/AD14
RD5/AD13
RD4/AD12
1
2
3
4
5
6
7
8
9
10
11
PIC17C4X
7
8
9
10
11
12
13
14
15
16
17
PIC17C4X
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
VSS
VSS
RB0/CAP1
RB1/CAP2
RB2/PWM1
RB3/PWM2
RB4/TCLK12
44
43
42
41
40
39
38
37
36
35
34
6
5
4
3
2
1
44
43
42
41
40
PLCC
RA0/INT
RA1/T0CKI
RA2
RA3
RA4/RX/DT
RA5/TX/CK
OSC2/CLKOUT
OSC1/CLKIN
RB7
RB6
RB5/TCLK3
RC3/AD3
RC2/AD2
RC1/AD1
RC0/AD0
NC
VDD
VDD
RD0/AD8
RD1/AD9
RD2/AD10
RD3/AD11
Pin Diagrams Cont.’d
33
32
31
30
29
28
27
26
25
24
23
RB4/TCLK12
RB3/PWM2
RB2/PWM1
RB1/CAP2
RB0/CAP1
VSS
VSS
RC7/AD7
RC6/AD6
RC5/AD5
RC4/AD4
22
21
20
19
18
17
16
15
14
13
12
RC3/AD3
RC2/AD2
RC1/AD1
RC0/AD0
NC
VDD
VDD
RD0/AD8
RD1/AD9
RD2/AD10
RD3/AD11
RA0/INT
RA1/T0CKI
RA2
RA3
RA4/RX/DT
RA5/TX/CK
OSC2/CLKOUT
OSC1/CLKIN
RB7
RB6
RB5/TCLK3
All devices are available in all package types, listed in Section 21.0, with the following exceptions:
• ROM devices are not available in Windowed CERDIP Packages
• TQFP is not available for the PIC17C42.
DS30412C-page 2
1996 Microchip Technology Inc.
PIC17C4X
Table of Contents
1.0
Overview .............................................................................................................................................................. 5
2.0
PIC17C4X Device Varieties ................................................................................................................................. 7
3.0
Architectural Overview ......................................................................................................................................... 9
4.0
Reset .................................................................................................................................................................. 15
5.0
Interrupts ............................................................................................................................................................ 21
6.0
Memory Organization ......................................................................................................................................... 29
7.0
Table Reads and Table Writes........................................................................................................................... 43
8.0
Hardware Multiplier ............................................................................................................................................ 49
9.0
I/O Ports ............................................................................................................................................................. 53
10.0 Overview of Timer Resources ............................................................................................................................ 65
11.0 Timer0 ................................................................................................................................................................ 67
12.0 Timer1, Timer2, Timer3, PWMs and Captures................................................................................................... 71
13.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Module................................................ 83
14.0 Special Features of the CPU.............................................................................................................................. 99
15.0 Instruction Set Summary .................................................................................................................................. 107
16.0 Development Support....................................................................................................................................... 143
17.0 PIC17C42 Electrical Characteristics ................................................................................................................ 147
18.0 PIC17C42 DC and AC Characteristics............................................................................................................. 163
19.0 PIC17CR42/42A/43/R43/44 Electrical Characteristics..................................................................................... 175
20.0 PIC17CR42/42A/43/R43/44 DC and AC Characteristics ................................................................................. 193
21.0 Packaging Information...................................................................................................................................... 205
Appendix A: Modifications .......................................................................................................................................... 211
Appendix B: Compatibility........................................................................................................................................... 211
Appendix C: What’s New ............................................................................................................................................ 212
Appendix D: What’s Changed..................................................................................................................................... 212
Appendix E: PIC16/17 Microcontrollers ...................................................................................................................... 213
Appendix F: Errata for PIC17C42 Silicon ................................................................................................................... 223
Index ............................................................................................................................................................................ 226
PIC17C4X Product Identification System .................................................................................................................... 237
For register and module descriptions in this data sheet, device legends show which devices apply to those sections.
For example, the legend below shows that some features of only the PIC17C43, PIC17CR43, PIC17C44 are described
in this section.
Applicable Devices
42 R42 42A 43 R43 44
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have
missed a few things. If you find any information that is missing or appears in error from the previous version of
the PIC17C4X Data Sheet (Literature Number DS30412B), please use the reader response form in the back
of this data sheet to inform us. We appreciate your assistance in making this a better document.
To assist you in the use of this document, Appendix C contains a list of new information in this data sheet,
while Appendix D contains information that has changed
1996 Microchip Technology Inc.
DS30412C-page 3
PIC17C4X
NOTES:
DS30412C-page 4
1996 Microchip Technology Inc.
PIC17C4X
1.0
OVERVIEW
This data sheet covers the PIC17C4X group of the
PIC17CXX family of microcontrollers. The following
devices are discussed in this data sheet:
•
•
•
•
•
•
PIC17C42
PIC17CR42
PIC17C42A
PIC17C43
PIC17CR43
PIC17C44
There are four configuration options for the device operational modes:
•
•
•
•
The
PIC17CR42,
PIC17C42A,
PIC17C43,
PIC17CR43, and PIC17C44 devices include architectural enhancements over the PIC17C42. These
enhancements will be discussed throughout this data
sheet.
The
PIC17C4X
devices
are
40/44-Pin,
EPROM/ROM-based members of the versatile
PIC17CXX family of low-cost, high-performance,
CMOS, fully-static, 8-bit microcontrollers.
All PIC16/17 microcontrollers employ an advanced
RISC architecture. The PIC17CXX has enhanced core
features, 16-level deep stack, and multiple internal and
external interrupt sources. The separate instruction and
data buses of the Harvard architecture allow a 16-bit
wide instruction word with a separate 8-bit wide data.
The two stage instruction pipeline allows all instructions
to execute in a single cycle, except for program
branches (which require two cycles). A total of 55
instructions (reduced instruction set) are available in
the PIC17C42 and 58 instructions in all the other
devices. Additionally, a large register set gives some of
the architectural innovations used to achieve a very
high performance. For mathematical intensive applications all devices, except the PIC17C42, have a single
cycle 8 x 8 Hardware Multiplier.
PIC17CXX microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
PIC17C4X devices have up to 454 bytes of RAM and
33 I/O pins. In addition, the PIC17C4X adds several
peripheral features useful in many high performance
applications including:
•
•
•
•
power saving. The user can wake-up the chip from
SLEEP through several external and internal interrupts
and device resets.
Four timer/counters
Two capture inputs
Two PWM outputs
A Universal Synchronous Asynchronous Receiver
Transmitter (USART)
These special features reduce external components,
thus reducing cost, enhancing system reliability and
reducing power consumption. There are four oscillator
options, of which the single pin RC oscillator provides a
low-cost solution, the LF oscillator is for low frequency
crystals and minimizes power consumption, XT is a
standard crystal, and the EC is for external clock input.
The SLEEP (power-down) mode offers additional
Microprocessor
Microcontroller
Extended microcontroller
Protected microcontroller
The microprocessor and extended microcontroller
modes allow up to 64K-words of external program
memory.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software malfunction.
Table 1-1 lists the features of the PIC17C4X devices.
A UV-erasable CERDIP-packaged version is ideal for
code development while the cost-effective One-Time
Programmable (OTP) version is suitable for production
in any volume.
The PIC17C4X fits perfectly in applications ranging
from precise motor control and industrial process control to automotive, instrumentation, and telecom applications. Other applications that require extremely fast
execution of complex software programs or the flexibility of programming the software code as one of the last
steps of the manufacturing process would also be well
suited. The EPROM technology makes customization
of application programs (with unique security codes,
combinations, model numbers, parameter storage,
etc.) fast and convenient. Small footprint package
options make the PIC17C4X ideal for applications with
space limitations that require high performance. High
speed execution, powerful peripheral features, flexible
I/O, and low power consumption all at low cost make
the PIC17C4X ideal for a wide range of embedded control applications.
1.1
Family and Upward Compatibility
Those users familiar with the PIC16C5X and
PIC16CXX families of microcontrollers will see the
architectural enhancements that have been implemented. These enhancements allow the device to be
more efficient in software and hardware requirements.
Please refer to Appendix A for a detailed list of
enhancements and modifications. Code written for
PIC16C5X or PIC16CXX can be easily ported to
PIC17CXX family of devices (Appendix B).
1.2
Development Support
The PIC17CXX family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a universal programmer, a “C” compiler, and
fuzzy logic support tools.
1996 Microchip Technology Inc.
DS30412C-page 5
This document was created with FrameMaker 4 0 4
PIC17C4X
TABLE 1-1:
PIC17CXX FAMILY OF DEVICES
Features
PIC17C42
PIC17CR42
PIC17C42A
PIC17C43
PIC17CR43
PIC17C44
Maximum Frequency of Operation
Operating Voltage Range
Program Memory x16
(EPROM)
(ROM)
Data Memory (bytes)
Hardware Multiplier (8 x 8)
Timer0 (16-bit + 8-bit postscaler)
Timer1 (8-bit)
Timer2 (8-bit)
Timer3 (16-bit)
Capture inputs (16-bit)
PWM outputs (up to 10-bit)
USART/SCI
Power-on Reset
Watchdog Timer
External Interrupts
Interrupt Sources
Program Memory Code Protect
I/O Pins
I/O High Current Capabil- Source
ity
Sink
25 MHz
4.5 - 5.5V
2K
232
Yes
Yes
Yes
Yes
2
2
Yes
Yes
Yes
Yes
11
Yes
33
25 mA
33 MHz
2.5 - 6.0V
2K
232
Yes
Yes
Yes
Yes
Yes
2
2
Yes
Yes
Yes
Yes
11
Yes
33
25 mA
33 MHz
2.5 - 6.0V
2K
232
Yes
Yes
Yes
Yes
Yes
2
2
Yes
Yes
Yes
Yes
11
Yes
33
25 mA
33 MHz
2.5 - 6.0V
4K
454
Yes
Yes
Yes
Yes
Yes
2
2
Yes
Yes
Yes
Yes
11
Yes
33
25 mA
33 MHz
2.5 - 6.0V
4K
454
Yes
Yes
Yes
Yes
Yes
2
2
Yes
Yes
Yes
Yes
11
Yes
33
25 mA
33 MHz
2.5 - 6.0V
8K
454
Yes
Yes
Yes
Yes
Yes
2
2
Yes
Yes
Yes
Yes
11
Yes
33
25 mA
25 mA(1)
40-pin DIP
44-pin PLCC
44-pin MQFP
25 mA(1)
40-pin DIP
44-pin PLCC
44-pin MQFP
44-pin TQFP
25 mA(1)
40-pin DIP
44-pin PLCC
44-pin MQFP
44-pin TQFP
25 mA(1)
40-pin DIP
44-pin PLCC
44-pin MQFP
44-pin TQFP
25 mA(1)
40-pin DIP
44-pin PLCC
44-pin MQFP
44-pin TQFP
25 mA(1)
40-pin DIP
44-pin PLCC
44-pin MQFP
44-pin TQFP
Package Types
Note 1:
Pins RA2 and RA3 can sink up to 60 mA.
DS30412C-page 6
1996 Microchip Technology Inc.
PIC17C4X
2.0
PIC17C4X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC17C4X Product Selection System section at the end of this data sheet. When
placing orders, please use the “PIC17C4X Product
Identification System” at the back of this data sheet to
specify the correct part number.
For the PIC17C4X family of devices, there are four
device “types” as indicated in the device number:
1.
2.
3.
4.
2.1
C, as in PIC17C42. These devices have
EPROM type memory and operate over the
standard voltage range.
LC, as in PIC17LC42. These devices have
EPROM type memory, operate over an
extended voltage range, and reduced frequency
range.
CR, as in PIC17CR42. These devices have
ROM type memory and operate over the standard voltage range.
LCR, as in PIC17LCR42. These devices have
ROM type memory, operate over an extended
voltage range, and reduced frequency range.
UV Erasable Devices
The UV erasable version, offered in CERDIP package,
is optimal for prototype development and pilot programs.
The UV erasable version can be erased and reprogrammed to any of the configuration modes.
Microchip's PRO MATE programmer supports programming of the PIC17C4X. Third party programmers
also are available; refer to the Third Party Guide for a
list of sources.
2.2
2.3
Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for factory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before production shipments are available. Please contact your local
Microchip Technology sales office for more details.
2.4
Serialized Quick-Turnaround
Production (SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
ROM devices do not allow serialization information in
the program memory space.
For information on submitting ROM code, please contact your regional sales office.
2.5
Read Only Memory (ROM) Devices
Microchip offers masked ROM versions of several of
the highest volume parts, thus giving customers a low
cost option for high volume, mature products.
For information on submitting ROM code, please contact your regional sales office.
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers expecting frequent code changes and
updates.
The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
1996 Microchip Technology Inc.
DS30412C-page 7
This document was created with FrameMaker 4 0 4
PIC17C4X
NOTES:
DS30412C-page 8
1996 Microchip Technology Inc.
PIC17C4X
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC17C4X can be attributed to a number of architectural features commonly
found in RISC microprocessors. To begin with, the
PIC17C4X uses a modified Harvard architecture. This
architecture has the program and data accessed from
separate memories. So the device has a program
memory bus and a data memory bus. This improves
bandwidth over traditional von Neumann architecture,
where program and data are fetched from the same
memory (accesses over the same bus). Separating
program and data memory further allows instructions to
be sized differently than the 8-bit wide data word.
PIC17C4X opcodes are 16-bits wide, enabling single
word instructions. The full 16-bit wide program memory
bus fetches a 16-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions. Consequently, all instructions execute in a single
cycle (121 ns @ 33 MHz), except for program branches
and two special instructions that transfer data between
program and data memory.
The PIC17C4X can address up to 64K x 16 of program
memory space.
The PIC17C42 and PIC17C42A integrate 2K x 16 of
EPROM program memory on-chip, while the
PIC17CR42 has 2K x 16 of ROM program memory onchip.
The PIC17C43 integrates 4K x 16 of EPROM program
memory, while the PIC17CR43 has 4K x 16 of ROM
program memory.
The PIC17C44 integrates 8K x 16 EPROM program
memory.
Program execution can be internal only (microcontroller or protected microcontroller mode), external only
(microprocessor mode) or both (extended microcontroller mode). Extended microcontroller mode does not
allow code protection.
The PIC17CXX can directly or indirectly address its
register files or data memory. All special function registers, including the Program Counter (PC) and Working
Register (WREG), are mapped in the data memory.
The PIC17CXX has an orthogonal (symmetrical)
instruction set that makes it possible to carry out any
operation on any register using any addressing mode.
This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC17CXX simple
yet efficient. In addition, the learning curve is reduced
significantly.
One of the PIC17CXX family architectural enhancements from the PIC16CXX family allows two file registers to be used in some two operand instructions. This
allows data to be moved directly between two registers
without going through the WREG register. This
increases performance and decreases program memory usage.
The PIC17CXX devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic
unit. It performs arithmetic and Boolean functions
between data in the working register and any register
file.
The ALU is 8-bits wide and capable of addition, subtraction, shift, and logical operations. Unless otherwise
mentioned, arithmetic operations are two's complement in nature.
The WREG register is an 8-bit working register used for
ALU operations.
All PIC17C4X devices (except the PIC17C42) have an
8 x 8 hardware multiplier. This multiplier generates a
16-bit result in a single cycle.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
Although the ALU does not perform signed arithmetic,
the Overflow bit (OV) can be used to implement signed
math. Signed arithmetic is comprised of a magnitude
and a sign bit. The overflow bit indicates if the magnitude overflows and causes the sign bit to change state.
Signed math can have greater than 7-bit values (magnitude), if more than one byte is used. The use of the
overflow bit only operates on bit6 (MSb of magnitude)
and bit7 (sign bit) of the value in the ALU. That is, the
overflow bit is not useful if trying to implement signed
math where the magnitude, for example, is 11-bits. If
the signed math values are greater than 7-bits (15-, 24or 31-bit), the algorithm must ensure that the low order
bytes ignore the overflow status bit.
Care should be taken when adding and subtracting
signed numbers to ensure that the correct operation is
executed. Example 3-1 shows an item that must be
taken into account when doing signed arithmetic on an
ALU which operates as an unsigned machine.
EXAMPLE 3-1:
SIGNED MATH
Hex Value
Signed Value
Math
Unsigned Value
Math
FFh
+ 01h
= ?
-127
+
1
= -126 (FEh)
255
+
1
=
0 (00h);
Carry bit = 1
Signed math requires the result in REG to
be FEh (-126). This would be accomplished
by subtracting one as opposed to adding
one.
Simplified block diagrams are shown in Figure 3-1 and
Figure 3-2. The descriptions of the device pins are
listed in Table 3-1.
1996 Microchip Technology Inc.
DS30412C-page 9
This document was created with FrameMaker 4 0 4
DS30412C-page 10
RA0/INT
RA1/T0CKI
RA2
RA3
RA4/RX/DT
RA5/TX/CK
PORTA
RB0/CAP1
RB1/CAP2
RB2/PWM1
RB2/PWM2
RB4/TCLK12
RB5/TCLK3
RB6
RB7
PORTB
6
8
SHIFTER
ALU
2
6
8
6
RA1/
T0CKI
BITOP
DATA BUS <8>
RDF
RA0/INT
RA1/T0CKI
PERIPHERALS
Timer0 MODULE
SERIAL PORT
DIGITAL I/O
PORTS A, B
Timer1, Timer2, Timer3
CAPTURE
PWM
WREG <8>
WRF
READ/WRITE
DECODE
FOR REGISTERS
MAPPED
IN DATA
SPACE
IR <7>
BSR
4
DATA LATCH
DATA RAM
232x8
IR <2:0>
3
IR BUS <7:0>
RAM ADDR BUFFER
8
INTERRUPT
MODULE
PCH
CONTROL OUTPUTS
16
STACK
16 x 16
CONTROL
SIGNALS
TO CPU
PCL
PROGRAM
MEMORY
(EPROM/ROM)
2K x 16
16
11
FSR0
8
FSR1
AD <15:0>
PORTC and
PORTD
TEST
MCLR/VPP
VDD, VSS
OSC1, OSC2
ALE, WR, OE
PORTE
DECODE
SYSTEM
BUS
INTERFACE
CLOCK GENERATOR
POWER ON RESET
WATCHDOG TIMER
OSC STARTUP TIMER
TEST MODE SELECT
ADDRESS LATCH
CHIP_RESET
AND OTHER
CONTROL
SIGNALS
Q1, Q2, Q3, Q4
16
8
DATA LATCH
ROM LATCH <16>
8
IR LATCH <16>
TABLE PTR<16>
TABLE LATCH <16>
PCLATH<8>
LITERAL
INSTRUCTION
DECODER
IR BUS <16>
FIGURE 3-1:
DATA BUS <8>
IR BUS <16>
PIC17C4X
PIC17C42 BLOCK DIAGRAM
1996 Microchip Technology Inc.
1996 Microchip Technology Inc.
RA0/INT
RA1/T0CKI
RA2
RA3
RA4/RX/DT
RA5/TX/CK
PORTA
RB0/CAP1
RB1/CAP2
RB2/PWM1
RB2/PWM2
RB4/TCLK12
RB5/TCLK3
RB6
RB7
PORTB
6
8
SHIFTER
ALU
BITOP
RA1/
T0CKI
2
6
8
6
PRODH
DATA BUS <8>
RDF
RA0/INT
RA1/T0CKI
PERIPHERALS
Timer0 MODULE
SERIAL PORT
DIGITAL I/O
PORTS A, B
WRF
READ/WRITE
DECODE
FOR REGISTERS
MAPPED
IN DATA
SPACE
Timer1, Timer2, Timer3
CAPTURE
PWM
PRODL
8 x 8 mult
WREG <8>
IR <7>
BSR
4
DATA LATCH
IR <2:0>
232 x 8 PIC17CR42
232 x 8 PIC17C42A
454 x 8 PIC17C43
454 x 8 PIC17CR43
454 x 8 PIC17C44
DATA RAM
3
BSR<7:4>
IR BUS<7:0>
RAM ADDR BUFFER
12
INTERRUPT
MODULE
PCH
CONTROL OUTPUTS
16
STACK
16 x 16
CONTROL
SIGNALS
TO CPU
PCL
PROGRAM
MEMORY
(EPROM/ROM)
16
13
FSR0
8
FSR1
TEST
MCLR/VPP
VDD, VSS
OSC1, OSC2
ALE, WR, OE
PORTE
AD <15:0>
PORTC and
PORTD
DECODE
SYSTEM
BUS
INTERFACE
CLOCK GENERATOR
POWER ON RESET
WATCHDOG TIMER
OSC STARTUP TIMER
TEST MODE SELECT
ADDRESS LATCH
2K x 16 - PIC17CR42
2K x 16 - PIC17C42A
4K x 16 - PIC17C43
4K x 16 - PIC17CR43
8K x 16 - PIC17C44
CHIP_RESET
AND OTHER
CONTROL
SIGNALS
Q1, Q2, Q3, Q4
16
8
DATA LATCH
ROM LATCH <16>
8
IR LATCH <16>
TABLE PTR<16>
TABLE LATCH <16>
PCLATH<8>
LITERAL
INSTRUCTION
DECODER
IR BUS <16>
FIGURE 3-2:
DATA BUS <8>
IR BUS <16>
PIC17C4X
PIC17CR42/42A/43/R43/44 BLOCK DIAGRAM
DS30412C-page 11
PIC17C4X
TABLE 3-1:
PINOUT DESCRIPTIONS
DIP
No.
PLCC
No.
QFP
No.
OSC1/CLKIN
19
21
37
I
ST
OSC2/CLKOUT
20
22
38
O
—
MCLR/VPP
32
35
7
I/P
ST
RA0/INT
26
28
44
I
ST
RA1/T0CKI
25
27
43
I
ST
RA2
24
26
42
I/O
ST
RA3
23
25
41
I/O
ST
RA4/RX/DT
22
24
40
I/O
ST
RA5/TX/CK
21
23
39
I/O
ST
RB0/CAP1
RB1/CAP2
RB2/PWM1
RB3/PWM2
RB4/TCLK12
11
12
13
14
15
13
14
15
16
17
29
30
31
32
33
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
RB5/TCLK3
16
18
34
I/O
ST
RB6
RB7
17
18
19
20
35
36
I/O
I/O
ST
ST
Name
I/O/P Buffer
Description
Type Type
Oscillator input in crystal/resonator or RC oscillator mode.
External clock input in external clock mode.
Oscillator output. Connects to crystal or resonator in crystal
oscillator mode. In RC oscillator or external clock modes
OSC2 pin outputs CLKOUT which has one fourth the frequency of OSC1 and denotes the instruction cycle rate.
Master clear (reset) input/Programming Voltage (VPP) input.
This is the active low reset input to the chip.
PORTA is a bi-directional I/O Port except for RA0 and RA1
which are input only.
RA0/INT can also be selected as an external interrupt
input. Interrupt can be configured to be on positive or
negative edge.
RA1/T0CKI can also be selected as an external interrupt
input, and the interrupt can be configured to be on positive or negative edge. RA1/T0CKI can also be selected
to be the clock input to the Timer0 timer/counter.
High voltage, high current, open drain input/output port
pins.
High voltage, high current, open drain input/output port
pins.
RA4/RX/DT can also be selected as the USART (SCI)
Asynchronous Receive or USART (SCI) Synchronous
Data.
RA5/TX/CK can also be selected as the USART (SCI)
Asynchronous Transmit or USART (SCI) Synchronous
Clock.
PORTB is a bi-directional I/O Port with software configurable
weak pull-ups.
RB0/CAP1 can also be the CAP1 input pin.
RB1/CAP2 can also be the CAP2 input pin.
RB2/PWM1 can also be the PWM1 output pin.
RB3/PWM2 can also be the PWM2 output pin.
RB4/TCLK12 can also be the external clock input to
Timer1 and Timer2.
RB5/TCLK3 can also be the external clock input to
Timer3.
PORTC is a bi-directional I/O Port.
RC0/AD0
2
3
19
I/O
TTL
This is also the lower half of the 16-bit wide system bus
in microprocessor mode or extended microcontroller
RC1/AD1
3
4
20
I/O
TTL
mode. In multiplexed system bus configuration, these
RC2/AD2
4
5
21
I/O
TTL
pins are address output as well as data input or output.
RC3/AD3
5
6
22
I/O
TTL
RC4/AD4
6
7
23
I/O
TTL
RC5/AD5
7
8
24
I/O
TTL
RC6/AD6
8
9
25
I/O
TTL
RC7/AD7
9
10
26
I/O
TTL
Legend: I = Input only; O = Output only; I/O = Input/Output; P = Power; — = Not Used; TTL = TTL input;
ST = Schmitt Trigger input.
DS30412C-page 12
1996 Microchip Technology Inc.
PIC17C4X
TABLE 3-1:
PINOUT DESCRIPTIONS
Name
DIP
No.
PLCC
No.
QFP
No.
I/O/P Buffer
Description
Type Type
RD0/AD8
RD1/AD9
RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
40
39
38
37
36
35
34
33
43
42
41
40
39
38
37
36
15
14
13
12
11
10
9
8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
RE0/ALE
30
32
4
I/O
TTL
RE1/OE
29
31
3
I/O
TTL
RE2/WR
28
30
2
I/O
TTL
TEST
27
29
1
I
ST
VSS
10,
31
PORTD is a bi-directional I/O Port.
This is also the upper byte of the 16-bit system bus in
microprocessor mode or extended microprocessor mode
or extended microcontroller mode. In multiplexed system
bus configuration these pins are address output as well
as data input or output.
PORTE is a bi-directional I/O Port.
In microprocessor mode or extended microcontroller
mode, it is the Address Latch Enable (ALE) output.
Address should be latched on the falling edge of ALE
output.
In microprocessor or extended microcontroller mode, it is
the Output Enable (OE) control output (active low).
In microprocessor or extended microcontroller mode, it is
the Write Enable (WR) control output (active low).
Test mode selection control input. Always tie to VSS for normal operation.
Ground reference for logic and I/O pins.
11,
5, 6,
P
12, 27, 28
33, 34
VDD
1
1, 44 16, 17
P
Positive supply for logic and I/O pins.
Legend: I = Input only; O = Output only; I/O = Input/Output; P = Power; — = Not Used; TTL = TTL input;
ST = Schmitt Trigger input.
1996 Microchip Technology Inc.
DS30412C-page 13
PIC17C4X
Clocking Scheme/Instruction Cycle
3.1
3.2
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3, and Q4. Internally, the program counter (PC) is incremented every Q1, and the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 3-3.
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3, and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO) then
two cycles are required to complete the instruction
(Example 3-2).
A fetch cycle begins with the program counter incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-3:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
EXAMPLE 3-2:
1. MOVLW 55h
PC
Fetch INST (PC)
Execute INST (PC-1)
PC+2
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
Tcy0
Tcy1
Fetch 1
Execute 1
2. MOVWF PORTB
3. CALL SUB_1
4. BSF
PC+1
PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
Fetch 2
Tcy2
Tcy3
Tcy4
Tcy5
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS30412C-page 14
1996 Microchip Technology Inc.
PIC17C4X
4.0
RESET
4.1
Power-on Reset (POR), Power-up
Timer (PWRT), and Oscillator Start-up
Timer (OST)
4.1.1
POWER-ON RESET (POR)
The PIC17CXX differentiates between various kinds of
reset:
• Power-on Reset (POR)
• MCLR reset during normal operation
• WDT Reset (normal operation)
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are forced to a “reset
state” on Power-on Reset (POR), on MCLR or WDT
Reset and on MCLR reset during SLEEP. They are not
affected by a WDT Reset during SLEEP, since this reset
is viewed as the resumption of normal operation. The
TO and PD bits are set or cleared differently in different
reset situations as indicated in Table 4-3. These bits are
used in software to determine the nature of reset. See
Table 4-4 for a full description of reset states of all registers.
Note:
While the device is in a reset state, the
internal phase clock is held in the Q1 state.
Any processor mode that allows external
execution will force the RE0/ALE pin as a
low output and the RE1/OE and RE2/WR
pins as high outputs.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 4-1.
FIGURE 4-1:
The Power-on Reset circuit holds the device in reset
until VDD is above the trip point (in the range of 1.4V 2.3V). The PIC17C42 does not produce an internal
reset when VDD declines. All other devices will produce
an internal reset for both rising and falling VDD. To take
advantage of the POR, just tie the MCLR/VPP pin
directly (or through a resistor) to VDD. This will eliminate
external RC components usually needed to create
Power-on Reset. A minimum rise time for VDD is
required. See Electrical Specifications for details.
4.1.2
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 96 ms time-out
(nominal) on power-up. This occurs from rising edge of
the POR signal and after the first rising edge of MCLR
(detected high). The Power-up Timer operates on an
internal RC oscillator. The chip is kept in RESET as
long as the PWRT is active. In most cases the PWRT
delay allows the VDD to rise to an acceptable level.
The power-up time delay will vary from chip to chip and
to VDD and temperature. See DC parameters for
details.
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
WDT
Module
WDT
Time_Out
Reset
VDD rise
detect
S
Power_On_Reset
VDD
OST/PWRT
Chip_Reset
R
OST
Q
10-bit Ripple counter
OSC1
PWRT
† This RC oscillator is shared with the WDT
when not in a power-up sequence.
Enable PWRT
10-bit Ripple counter
Enable OST
On-chip
RC OSC†
Power_Up
(Enable the PWRT timer
only during Power_Up)
(Power_Up + Wake_Up) (XT + LF)
(Enable the OST if it is Power_Up or Wake_Up
from SLEEP and OSC type is XT or LF)
1996 Microchip Technology Inc.
DS30412C-page 15
This document was created with FrameMaker 4 0 4
PIC17C4X
4.1.3
OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (1024TOSC) delay after MCLR is
detected high or a wake-up from SLEEP event occurs.
TABLE 4-1:
Oscillator
Configuration
Power-up
Wake up
from
SLEEP
MCLR
Reset
XT, LF
Greater of:
96 ms or
1024TOSC
1024TOSC
—
EC, RC
Greater of:
96 ms or
1024TOSC
—
—
The OST time-out is invoked only for XT and LF oscillator modes on a Power-on Reset or a Wake-up from
SLEEP.
The OST counts the oscillator pulses on the
OSC1/CLKIN pin. The counter only starts incrementing
after the amplitude of the signal reaches the oscillator
input thresholds. This delay allows the crystal oscillator
or resonator to stabilize before the device exits reset.
The length of time-out is a function of the crystal/resonator frequency.
4.1.4
TIME-OUT SEQUENCE
On power-up the time-out sequence is as follows: First
the internal POR signal goes high when the POR trip
point is reached. If MCLR is high, then both the OST
and PWRT timers start. In general the PWRT time-out
is longer, except with low frequency crystals/resonators. The total time-out also varies based on oscillator
configuration. Table 4-1 shows the times that are associated with the oscillator configuration. Figure 4-2 and
Figure 4-3 display these time-out sequences.
If the device voltage is not within electrical specification
at the end of a time-out, the MCLR/VPP pin must be
held low until the voltage is within the device specification. The use of an external RC delay is sufficient for
many of these applications.
TIME-OUT IN VARIOUS
SITUATIONS
The time-out sequence begins from the first rising edge
of MCLR.
Table 4-3 shows the reset conditions for some special
registers, while Table 4-4 shows the initialization conditions for all the registers. The shaded registers (in
Table 4-4) are for all devices except the PIC17C42. In
the PIC17C42, the PRODH and PRODL registers are
general purpose RAM.
TABLE 4-2:
STATUS BITS AND THEIR
SIGNIFICANCE
Event
TO
PD
1
1
Power-on Reset, MCLR Reset during normal
operation, or CLRWDT instruction executed
1
0
MCLR Reset during SLEEP or interrupt wake-up
from SLEEP
0
1
WDT Reset during normal operation
0
0
WDT Reset during SLEEP
In Figure 4-2, Figure 4-3 and Figure 4-4, TPWRT >
TOST, as would be the case in higher frequency crystals. For lower frequency crystals, (i.e., 32 kHz) TOST
would be greater.
TABLE 4-3:
RESET CONDITION FOR THE PROGRAM COUNTER AND THE CPUSTA REGISTER
Event
Power-on Reset
PCH:PCL
CPUSTA
OST Active
0000h
--11 11--
Yes
MCLR Reset during normal operation
0000h
--11 11--
No
MCLR Reset during SLEEP
0000h
--11 10--
Yes (2)
WDT Reset during normal operation
0000h
--11 01--
No
0000h
--11 00--
Yes (2)
PC + 1
--11 10--
Yes (2)
PC + 1 (1)
--10 10--
Yes (2)
WDT Reset during
SLEEP (3)
Interrupt wake-up from SLEEP
GLINTD is set
GLINTD is clear
Legend: u = unchanged, x = unknown, - = unimplemented read as '0'.
Note 1: On wake-up, this instruction is executed. The instruction at the appropriate interrupt vector is fetched and
then executed.
2: The OST is only active when the Oscillator is configured for XT or LF modes.
3: The Program Counter = 0, that is the device branches to the reset vector. This is different from the
mid-range devices.
DS30412C-page 16
1996 Microchip Technology Inc.
PIC17C4X
FIGURE 4-2:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-4:
SLOW RISE TIME (MCLR TIED TO VDD)
5V
VDD
1V
0V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
1996 Microchip Technology Inc.
DS30412C-page 17
PIC17C4X
FIGURE 4-5:
OSCILLATOR START-UPTIME
FIGURE 4-8:
PIC17C42 EXTERNAL
POWER-ON RESET CIRCUIT
(FOR SLOW VDD
POWER-UP)
VDD
VDD
VDD
MCLR
D
R
OSC2
R1
MCLR
TOSC1
PIC17C42
C
TOST
OST TIME_OUT
PWRT TIME_OUT
TPWRT
INTERNAL RESET
This figure shows in greater detail the timings involved
with the oscillator start-up timer. In this example the
low frequency crystal start-up time is larger than
power-up time (TPWRT).
Tosc1 = time for the crystal oscillator to react to an
oscillation level detectable by the Oscillator Start-up
Timer (ost).
TOST = 1024TOSC.
FIGURE 4-6:
USING ON-CHIP POR
VDD
VDD
MCLR
Note 1: An external Power-on Reset circuit is
required only if VDD power-up time is too
slow. The diode D helps discharge the
capacitor quickly when VDD powers
down.
2: R < 40 kΩ is recommended to ensure
that the voltage drop across R does not
exceed 0.2V (max. leakage current spec.
on the MCLR/VPP pin is 5 µA). A larger
voltage drop will degrade VIH level on the
MCLR/VPP pin.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor C in the event of MCLR/VPP pin
breakdown due to Electrostatic Discharge (ESD) or (Electrical Overstress)
EOS.
PIC17CXX
FIGURE 4-9:
FIGURE 4-7:
BROWN-OUT PROTECTION
CIRCUIT 1
BROWN-OUT PROTECTION
CIRCUIT 2
VDD
VDD
R1
VDD
Q1
VDD
33k
10k
40 kΩ
PIC17CXX
MCLR
40 kΩ
PIC17CXX
This circuit will activate reset when VDD goes below
(Vz + 0.7V) where Vz = Zener voltage.
DS30412C-page 18
MCLR
R2
This brown-out circuit is less expensive, albeit less
accurate. Transistor Q1 turns off when VDD is below a
certain level such that:
VDD •
R1
R1 + R2
= 0.7V
1996 Microchip Technology Inc.
PIC17C4X
TABLE 4-4:
INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS
MCLR Reset
WDT Reset
Wake-up from SLEEP
through interrupt
Register
Address
Power-on Reset
Unbanked
INDF0
FSR0
PCL
00h
01h
02h
0000 0000
xxxx xxxx
0000h
0000 0000
uuuu uuuu
0000h
03h
04h
05h
06h
0000
1111
0000
--11
0000
1111
0000
--11
07h
0000 0000
0000 0000
08h
09h
0Ah
0Bh
0Ch
0Dh
0000
xxxx
xxxx
xxxx
xxxx
xxxx
0000
uuuu
uuuu
uuuu
uuuu
uuuu
TBLPTRH (4)
0Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
(5)
0Dh
0000 0000
0000 0000
uuuu uuuu
TBLPTRH (5)
BSR
0Eh
0000 0000
0000 0000
uuuu uuuu
PCLATH
ALUSTA
T0STA
CPUSTA(3)
INTSTA
INDF1
FSR1
WREG
TMR0L
TMR0H
TBLPTRL (4)
TBLPTRL
0000
xxxx
00011-0000
xxxx
xxxx
xxxx
xxxx
xxxx
0000
uuuu
000qq-0000
uuuu
uuuu
uuuu
uuuu
uuuu
0000 0000
uuuu uuuu
PC + 1(2)
uuuu uuuu
1111 uuuu
0000 000--uu qq-uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu(1)
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
0Fh
0000 0000
0000 0000
uuuu uuuu
Bank 0
PORTA
DDRB
PORTB
RCSTA
RCREG
TXSTA
TXREG
SPBRG
10h
11h
12h
13h
14h
15h
16h
17h
0-xx
1111
xxxx
0000
xxxx
0000
xxxx
xxxx
xxxx
1111
xxxx
-00x
xxxx
--1x
xxxx
xxxx
0-uu
1111
uuuu
0000
uuuu
0000
uuuu
uuuu
uuuu
1111
uuuu
-00u
uuuu
--1u
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
-uuu
uuuu
--uu
uuuu
uuuu
Bank 1
DDRC
PORTC
DDRD
PORTD
DDRE
PORTE
PIR
10h
11h
12h
13h
14h
15h
16h
1111
xxxx
1111
xxxx
------0000
1111
xxxx
1111
xxxx
-111
-xxx
0010
1111
uuuu
1111
uuuu
------0000
1111
uuuu
1111
uuuu
-111
-uuu
0010
uuuu
uuuu
uuuu
uuuu
-------
uuuu
uuuu
uuuu
uuuu
-uuu
-uuu
PIE
Legend:
Note 1:
2:
3:
4:
5:
uuuu uuuu(1)
17h
0000 0000
0000 0000
uuuu uuuu
u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition.
One or more bits in INTSTA, PIR will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
See Table 4-3 for reset value of specific condition.
Only applies to the PIC17C42.
Does not apply to the PIC17C42.
1996 Microchip Technology Inc.
DS30412C-page 19
PIC17C4X
TABLE 4-4:
INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS
Power-on Reset
MCLR Reset
WDT Reset
(Cont.’d)
Wake-up from SLEEP
through interrupt
Register
Address
Bank 2
TMR1
TMR2
TMR3L
TMR3H
PR1
PR2
PR3/CA1L
PR3/CA1H
10h
11h
12h
13h
14h
15h
16h
17h
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
Bank 3
PW1DCL
PW2DCL
PW1DCH
PW2DCH
CA2L
CA2H
TCON1
TCON2
10h
11h
12h
13h
14h
15h
16h
17h
xx-xx-xxxx
xxxx
xxxx
xxxx
0000
0000
------xxxx
xxxx
xxxx
xxxx
0000
0000
uu-uu-uuuu
uuuu
uuuu
uuuu
0000
0000
------uuuu
uuuu
uuuu
uuuu
0000
0000
uu-uu-uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
------uuuu
uuuu
uuuu
uuuu
uuuu
uuuu
18h
xxxx xxxx
Unbanked
PRODL (5)
uuuu uuuu
uuuu uuuu
19h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODH (5)
Legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition.
Note 1: One or more bits in INTSTA, PIR will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 4-3 for reset value of specific condition.
4: Only applies to the PIC17C42.
5: Does not apply to the PIC17C42.
DS30412C-page 20
1996 Microchip Technology Inc.
PIC17C4X
5.0
INTERRUPTS
The PIC17C4X devices have 11 sources of interrupt:
•
•
•
•
•
•
•
•
•
•
•
External interrupt from the RA0/INT pin
Change on RB7:RB0 pins
TMR0 Overflow
TMR1 Overflow
TMR2 Overflow
TMR3 Overflow
USART Transmit buffer empty
USART Receive buffer full
Capture1
Capture2
T0CKI edge occurred
There are four registers used in the control and status
of interrupts. These are:
•
•
•
•
CPUSTA
INTSTA
PIE
PIR
The CPUSTA register contains the GLINTD bit. This is
the Global Interrupt Disable bit. When this bit is set, all
interrupts are disabled. This bit is part of the controller
core functionality and is described in the Memory Organization section.
When an interrupt is responded to, the GLINTD bit is
automatically set to disable any further interrupt, the
return address is pushed onto the stack and the PC is
loaded with the interrupt vector address. There are four
interrupt vectors. Each vector address is for a specific
interrupt source (except the peripheral interrupts which
have the same vector address). These sources are:
•
•
•
•
External interrupt from the RA0/INT pin
TMR0 Overflow
T0CKI edge occurred
Any peripheral interrupt
When program execution vectors to one of these interrupt vector addresses (except for the peripheral interrupt address), the interrupt flag bit is automatically
cleared. Vectoring to the peripheral interrupt vector
address does not automatically clear the source of the
interrupt. In the peripheral interrupt service routine, the
source(s) of the interrupt can be determined by testing
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid infinite interrupt requests.
All of the individual interrupt flag bits will be set regardless of the status of their corresponding mask bit or the
GLINTD bit.
For external interrupt events, there will be an interrupt
latency. For two cycle instructions, the latency could be
one instruction cycle longer.
The “return from interrupt” instruction, RETFIE, can be
used to mark the end of the interrupt service routine.
When this instruction is executed, the stack is
“POPed”, and the GLINTD bit is cleared (to re-enable
interrupts).
FIGURE 5-1:
INTERRUPT LOGIC
TMR1IF
TMR1IE
TMR2IF
TMR2IE
T0IF
T0IE
TMR3IF
TMR3IE
INTF
INTE
CA1IF
CA1IE
CA2IF
CA2IE
TXIF
TXIE
Wake-up (If in SLEEP mode)
or terminate long write
Interrupt to CPU
T0CKIF
T0CKIE
PEIF
PEIE
GLINTD
RCIF
RCIE
RBIF
RBIE
1996 Microchip Technology Inc.
DS30412C-page 21
This document was created with FrameMaker 4 0 4
PIC17C4X
5.1
Interrupt Status Register (INTSTA)
The Interrupt Status/Control register (INTSTA) records
the individual interrupt requests in flag bits, and contains the individual interrupt enable bits (not for the
peripherals).
The PEIF bit is a read only, bit wise OR of all the peripheral flag bits in the PIR register (Figure 5-4).
Note:
T0IF, INTF, T0CKIF, or PEIF will be set by
the specified condition, even if the corresponding interrupt enable bit is clear (interrupt disabled) or the GLINTD bit is set (all
interrupts disabled).
Care should be taken when clearing any of the INTSTA
register enable bits when interrupts are enabled
(GLINTD is clear). If any of the INTSTA flag bits (T0IF,
INTF, T0CKIF, or PEIF) are set in the same instruction
cycle as the corresponding interrupt enable bit is
cleared, the device will vector to the reset address
(0x00).
When disabling any of the INTSTA enable bits, the
GLINTD bit should be set (disabled).
FIGURE 5-2: INTSTA REGISTER (ADDRESS: 07h, UNBANKED)
R-0
PEIF
bit7
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
T0CKIF T0IF
INTF
PEIE T0CKIE
T0IE
INTE
bit0
R = Readable bit
W = Writable bit
- n = Value at POR reset
bit 7:
PEIF: Peripheral Interrupt Flag bit
This bit is the OR of all peripheral interrupt flag bits AND’ed with their corresponding enable bits.
1 = A peripheral interrupt is pending
0 = No peripheral interrupt is pending
bit 6:
T0CKIF: External Interrupt on T0CKI Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to vector (18h).
1 = The software specified edge occurred on the RA1/T0CKI pin
0 = The software specified edge did not occur on the RA1/T0CKI pin
bit 5:
T0IF: TMR0 Overflow Interrupt Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to vector (10h).
1 = TMR0 overflowed
0 = TMR0 did not overflow
bit 4:
INTF: External Interrupt on INT Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to vector (08h).
1 = The software specified edge occurred on the RA0/INT pin
0 = The software specified edge did not occur on the RA0/INT pin
bit 3:
PEIE: Peripheral Interrupt Enable bit
This bit enables all peripheral interrupts that have their corresponding enable bits set.
1 = Enable peripheral interrupts
0 = Disable peripheral interrupts
bit 2:
T0CKIE: External Interrupt on T0CKI Pin Enable bit
1 = Enable software specified edge interrupt on the RA1/T0CKI pin
0 = Disable interrupt on the RA1/T0CKI pin
bit 1:
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enable TMR0 overflow interrupt
0 = Disable TMR0 overflow interrupt
bit 0:
INTE: External Interrupt on RA0/INT Pin Enable bit
1 = Enable software specified edge interrupt on the RA0/INT pin
0 = Disable software specified edge interrupt on the RA0/INT pin
DS30412C-page 22
1996 Microchip Technology Inc.
PIC17C4X
5.2
Peripheral Interrupt Enable Register
(PIE)
This register contains the individual flag bits for the
Peripheral interrupts.
FIGURE 5-3: PIE REGISTER (ADDRESS: 17h, BANK 1)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TXIE
RCIE
bit7
bit0
bit 7:
RBIE: PORTB Interrupt on Change Enable bit
1 = Enable PORTB interrupt on change
0 = Disable PORTB interrupt on change
bit 6:
TMR3IE: Timer3 Interrupt Enable bit
1 = Enable Timer3 interrupt
0 = Disable Timer3 interrupt
bit 5:
TMR2IE: Timer2 Interrupt Enable bit
1 = Enable Timer2 interrupt
0 = Disable Timer2 interrupt
bit 4:
TMR1IE: Timer1 Interrupt Enable bit
1 = Enable Timer1 interrupt
0 = Disable Timer1 interrupt
bit 3:
CA2IE: Capture2 Interrupt Enable bit
1 = Enable Capture interrupt on RB1/CAP2 pin
0 = Disable Capture interrupt on RB1/CAP2 pin
bit 2:
CA1IE: Capture1 Interrupt Enable bit
1 = Enable Capture interrupt on RB2/CAP1 pin
0 = Disable Capture interrupt on RB2/CAP1 pin
bit 1:
TXIE: USART Transmit Interrupt Enable bit
1 = Enable Transmit buffer empty interrupt
0 = Disable Transmit buffer empty interrupt
bit 0:
RCIE: USART Receive Interrupt Enable bit
1 = Enable Receive buffer full interrupt
0 = Disable Receive buffer full interrupt
1996 Microchip Technology Inc.
R = Readable bit
W = Writable bit
-n = Value at POR reset
DS30412C-page 23
PIC17C4X
5.3
Peripheral Interrupt Request Register
(PIR)
Note:
This register contains the individual flag bits for the
peripheral interrupts.
These bits will be set by the specified condition, even if the corresponding interrupt
enable bit is cleared (interrupt disabled), or
the GLINTD bit is set (all interrupts disabled). Before enabling an interrupt, the
user may wish to clear the interrupt flag to
ensure that the program does not immediately branch to the peripheral interrupt service routine.
FIGURE 5-4: PIR REGISTER (ADDRESS: 16h, BANK 1)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
RBIF TMR3IF TMR2IF TMR1IF CA2IF
CA1IF
bit7
R-1
TXIF
R-0
RCIF
bit0
R = Readable bit
W = Writable bit
-n = Value at POR reset
bit 7:
RBIF: PORTB Interrupt on Change Flag bit
1 = One of the PORTB inputs changed (Software must end the mismatch condition)
0 = None of the PORTB inputs have changed
bit 6:
TMR3IF: Timer3 Interrupt Flag bit
If Capture1 is enabled (CA1/PR3 = 1)
1 = Timer3 overflowed
0 = Timer3 did not overflow
If Capture1 is disabled (CA1/PR3 = 0)
1 = Timer3 value has rolled over to 0000h from equalling the period register (PR3H:PR3L) value
0 = Timer3 value has not rolled over to 0000h from equalling the period register (PR3H:PR3L) value
bit 5:
TMR2IF: Timer2 Interrupt Flag bit
1 = Timer2 value has rolled over to 0000h from equalling the period register (PR2) value
0 = Timer2 value has not rolled over to 0000h from equalling the period register (PR2) value
bit 4:
TMR1IF: Timer1 Interrupt Flag bit
If Timer1 is in 8-bit mode (T16 = 0)
1 = Timer1 value has rolled over to 0000h from equalling the period register (PR) value
0 = Timer1 value has not rolled over to 0000h from equalling the period register (PR2) value
If Timer1 is in 16-bit mode (T16 = 1)
1 = TMR1:TMR2 value has rolled over to 0000h from equalling the period register (PR1:PR2) value
0 = TMR1:TMR2 value has not rolled over to 0000h from equalling the period register (PR1:PR2) value
bit 3:
CA2IF: Capture2 Interrupt Flag bit
1 = Capture event occurred on RB1/CAP2 pin
0 = Capture event did not occur on RB1/CAP2 pin
bit 2:
CA1IF: Capture1 Interrupt Flag bit
1 = Capture event occurred on RB0/CAP1 pin
0 = Capture event did not occur on RB0/CAP1 pin
bit 1:
TXIF: USART Transmit Interrupt Flag bit
1 = Transmit buffer is empty
0 = Transmit buffer is full
bit 0:
RCIF: USART Receive Interrupt Flag bit
1 = Receive buffer is full
0 = Receive buffer is empty
DS30412C-page 24
1996 Microchip Technology Inc.
PIC17C4X
5.4
Interrupt Operation
Global Interrupt Disable bit, GLINTD (CPUSTA<4>),
enables all unmasked interrupts (if clear) or disables all
interrupts (if set). Individual interrupts can be disabled
through their corresponding enable bits in the INTSTA
register. Peripheral interrupts need either the global
peripheral enable PEIE bit disabled, or the specific
peripheral enable bit disabled. Disabling the peripherals via the global peripheral enable bit, disables all
peripheral interrupts. GLINTD is set on reset (interrupts
disabled).
The RETFIE instruction allows returning from interrupt
and re-enable interrupts at the same time.
Note 1: Individual interrupt flag bits are set regardless of the status of their corresponding
mask bit or the GLINTD bit.
Note 2: When disabling any of the INTSTA enable
bits, the GLINTD bit should be set
(disabled).
Note 3: For the PIC17C42 only:
If an interrupt occurs while the Global Interrupt Disable (GLINTD) bit is being set, the
GLINTD bit may unintentionally be reenabled by the user’s Interrupt Service
Routine (the RETFIE instruction). The
events that would cause this to occur are:
When an interrupt is responded to, the GLINTD bit is
automatically set to disable any further interrupt, the
return address is pushed onto the stack and the PC is
loaded with interrupt vector. There are four interrupt
vectors to reduce interrupt latency.
The peripheral interrupt vector has multiple interrupt
sources. Once in the peripheral interrupt service routine, the source(s) of the interrupt can be determined by
polling the interrupt flag bits. The peripheral interrupt
flag bit(s) must be cleared in software before reenabling interrupts to avoid continuous interrupts.
The PIC17C4X devices have four interrupt vectors.
These vectors and their hardware priority are shown in
Table 5-1. If two enabled interrupts occur “at the same
time”, the interrupt of the highest priority will be serviced first. This means that the vector address of that
interrupt will be loaded into the program counter (PC).
TABLE 5-1:
Address
0008h
0010h
0018h
0020h
INTERRUPT VECTORS/
PRIORITIES
Vector
External Interrupt on RA0/
INT pin (INTF)
TMR0 overflow interrupt
(T0IF)
External Interrupt on T0CKI
(T0CKIF)
Peripherals (PEIF)
1996 Microchip Technology Inc.
1 (Highest)
2
An interrupt occurs simultaneously
with an instruction that sets the
GLINTD bit.
2.
The program branches to the Interrupt
vector and executes the Interrupt Service Routine.
3.
The Interrupt Service Routine completes with the execution of the RETFIE instruction. This causes the
GLINTD bit to be cleared (enables
interrupts), and the program returns to
the instruction after the one which was
meant to disable interrupts.
The method to ensure that interrupts are
globally disabled is:
1.
LOOP
Priority
1.
BSF
BTFSS
GOTO
Ensure that the GLINTD bit was set by
the instruction, as shown in the following code:
CPUSTA, GLINTD ;
;
CPUSTA, GLINTD ;
;
LOOP
;
;
;
;
Disable Global
Interrupt
Global Interrupt
Disabled?
NO, try again
YES, continue
with program
low
3
4 (Lowest)
DS30412C-page 25
PIC17C4X
5.5
RA0/INT Interrupt
5.7
The external interrupt on the RA0/INT pin is edge triggered. Either the rising edge, if INTEDG bit
(T0STA<7>) is set, or the falling edge, if INTEDG bit is
clear. When a valid edge appears on the RA0/INT pin,
the INTF bit (INTSTA<4>) is set. This interrupt can be
disabled by clearing the INTE control bit (INTSTA<0>).
The INT interrupt can wake the processor from SLEEP.
See Section 14.4 for details on SLEEP operation.
5.6
The external interrupt on the RA1/T0CKI pin is edge
triggered. Either the rising edge, if the T0SE bit
(T0STA<6>) is set, or the falling edge, if the T0SE bit is
clear. When a valid edge appears on the RA1/T0CKI
pin, the T0CKIF bit (INTSTA<6>) is set. This interrupt
can be disabled by clearing the T0CKIE control bit
(INTSTA<2>). The T0CKI interrupt can wake up the
processor from SLEEP. See Section 14.4 for details on
SLEEP operation.
TMR0 Interrupt
5.8
An overflow (FFFFh → 0000h) in TMR0 will set the
T0IF (INTSTA<5>) bit. The interrupt can be enabled/
disabled by setting/clearing the T0IE control bit
(INTSTA<1>). For operation of the Timer0 module, see
Section 11.0.
FIGURE 5-5:
T0CKI Interrupt
Peripheral Interrupt
The peripheral interrupt flag indicates that at least one
of the peripheral interrupts occurred (PEIF is set). The
PEIF bit is a read only bit, and is a bit wise OR of all the
flag bits in the PIR register AND’ed with the corresponding enable bits in the PIE register. Some of the
peripheral interrupts can wake the processor from
SLEEP. See Section 14.4 for details on SLEEP operation.
INT PIN / T0CKI PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
OSC2
RA0/INT or
RA1/T0CKI
INTF or
T0CKIF
GLINTD
PC
System Bus
Instruction
Fetched
PC
PC
Instruction
executed
DS30412C-page 26
PC + 1
Inst (PC)
Addr
Inst (PC+1)
Inst (PC)
YY
Addr (Vector)
Addr
Inst (PC+1)
Dummy
Addr
Inst (Vector)
Dummy
Addr
RETFIE
YY + 1
Addr
PC + 1
Inst (YY + 1)
RETFIE
Dummy
1996 Microchip Technology Inc.
PIC17C4X
5.9
Context Saving During Interrupts
During an interrupt, only the returned PC value is saved
on the stack. Typically, users may wish to save key registers during an interrupt; e.g. WREG, ALUSTA and the
BSR registers. This requires implementation in software.
EXAMPLE 5-1:
Example 5-1 shows the saving and restoring of information for an interrupt service routine. The PUSH and
POP routines could either be in each interrupt service
routine or could be subroutines that were called.
Depending on the application, other registers may also
need to be saved, such as PCLATH.
SAVING STATUS AND WREG IN RAM
;
; The addresses that are used to store the CPUSTA and WREG values
; must be in the data memory address range of 18h - 1Fh. Up to
; 8 locations can be saved and restored using
; the MOVFP instruction. This instruction neither affects the status
; bits, nor corrupts the WREG register.
;
;
PUSH
MOVFP
WREG, TEMP_W
; Save WREG
MOVFP
ALUSTA, TEMP_STATUS ; Save ALUSTA
MOVFP
BSR, TEMP_BSR
; Save BSR
ISR
POP
:
:
MOVFP
MOVFP
MOVFP
RETFIE
; This is the interrupt service routine
TEMP_W, WREG
TEMP_STATUS, ALUSTA
TEMP_BSR, BSR
1996 Microchip Technology Inc.
;
;
;
;
Restore WREG
Restore ALUSTA
Restore BSR
Return from Interrupts enabled
DS30412C-page 27
PIC17C4X
NOTES:
DS30412C-page 28
1996 Microchip Technology Inc.
PIC17C4X
6.0
MEMORY ORGANIZATION
There are two memory blocks in the PIC17C4X; program memory and data memory. Each block has its
own bus, so that access to each block can occur during
the same oscillator cycle.
The data memory can further be broken down into General Purpose RAM and the Special Function Registers
(SFRs). The operation of the SFRs that control the
“core” are described here. The SFRs used to control
the peripheral modules are described in the section discussing each individual peripheral module.
FIGURE 6-1:
PROGRAM MEMORY MAP
AND STACK
PC<15:0>
16
CALL, RETURN
RETFIE, RETLW
Stack Level 1
•
•
•
Stack Level 16
Reset Vector
0000h
INT Pin Interrupt Vector
0008h
Program Memory Organization
Timer0 Interrupt Vector
0010h
PIC17C4X devices have a 16-bit program counter
capable of addressing a 64K x 16 program memory
space. The reset vector is at 0000h and the interrupt
vectors are at 0008h, 0010h, 0018h, and 0020h
(Figure 6-1).
T0CKI Pin Interrupt Vector
0018h
Peripheral Interrupt Vector
0020h
0021h
6.1.1
PROGRAM MEMORY OPERATION
The PIC17C4X can operate in one of four possible program memory configurations. The configuration is
selected by two configuration bits. The possible modes
are:
FFFh
(PIC17C43
PIC17CR43)
Microprocessor
Microcontroller
Extended Microcontroller
Protected Microcontroller
1FFFh
(PIC17C44)
The microcontroller and protected microcontroller
modes only allow internal execution. Any access
beyond the program memory reads unknown data.
The protected microcontroller mode also enables the
code protection feature.
The extended microcontroller mode accesses both the
internal program memory as well as external program
memory. Execution automatically switches between
internal and external memory. The 16-bits of address
allow a program memory range of 64K-words.
Configuration Memory
Space
•
•
•
•
7FFh
(PIC17C42,
PIC17CR42,
PIC17C42A)
User Memory
Space (1)
6.1
The microprocessor mode only accesses the external
program memory. The on-chip program memory is
ignored. The 16-bits of address allow a program memory range of 64K-words. Microprocessor mode is the
default mode of an unprogrammed device.
The different modes allow different access to the configuration bits, test memory, and boot ROM. Table 6-1
lists which modes can access which areas in memory.
Test Memory and Boot Memory are not required for
normal operation of the device. Care should be taken to
ensure that no unintended branches occur to these
areas.
FOSC0
FOSC1
WDTPS0
WDTPS1
PM0
Reserved
PM1
Reserved
Reserved
PM2(2)
Test EPROM
FDFFh
FE00h
FE01h
FE02h
FE03h
FE04h
FE05h
FE06h
FE07h
FE08h
FE0Eh
FE0Fh
FE10h
FF5Fh
FF60h
Boot ROM
FFFFh
Note 1:
User memory space may be internal, external, or
both. The memory configuration depends on the
processor mode.
2: This location is reserved on the PIC17C42.
1996 Microchip Technology Inc.
DS30412C-page 29
This document was created with FrameMaker 4 0 4
PIC17C4X
MODE MEMORY ACCESS
Internal
Program
Memory
Configuration Bits,
Test Memory,
Boot ROM
Microprocessor
No Access
No Access
Microcontroller
Access
Access
Extended
Microcontroller
Access
No Access
Protected
Microcontroller
Access
Access
MEMORY MAP IN DIFFERENT MODES
PIC17C42,
PIC17CR42,
PIC17C42A
Extended
Microcontroller
Mode
Microcontroller
Modes
0000h
0000h
0000h
07FFh
On-chip
Program
Memory
07FFh
0800h
On-chip
Program
Memory
PROGRAM SPACE
Microprocessor
Mode
0800h
External
Program
Memory
External
Program
Memory
FE00h Config. Bits
Test Memory
FFFFh Boot ROM
FFFFh
FFFFh
OFF-CHIP
ON-CHIP
OFF-CHIP
ON-CHIP
00h
PIC17C43,
PIC17CR43,
PIC17C44
ON-CHIP
00h
FFh
OFF-CHIP
OFF-CHIP
00h
FFh
ON-CHIP
OFF-CHIP
ON-CHIP
FFh
OFF-CHIP
0000h
0000h
0FFFh/1FFFh
ON-CHIP
0000h
On-chip
Program
Memory
0FFFh/1FFFh
1000h/2000h
On-chip
Program
Memory
1000h/
2000h
External
Program
Memory
External
Program
Memory
FE00h Config. Bits
Test Memory
FFFFh Boot ROM
FFFFh
FFFFh
OFF-CHIP
ON-CHIP
OFF-CHIP
00h
FFh
OFF-CHIP
DS30412C-page 30
ON-CHIP
OFF-CHIP
00h
120h
ON-CHIP
ON-CHIP
00h
120h
1FFh
FFh
OFF-CHIP
DATA SPACE
FIGURE 6-2:
Regardless of the processor mode, data memory is
always on-chip.
PROGRAM SPACE
Operating
Mode
The PIC17C4X can operate in modes where the program memory is off-chip. They are the microprocessor
and extended microcontroller modes. The microprocessor mode is the default for an unprogrammed
device.
120h
1FFh
ON-CHIP
FFh
OFF-CHIP
1FFh
ON-CHIP
DATA SPACE
TABLE 6-1:
1996 Microchip Technology Inc.
PIC17C4X
6.1.2
EXTERNAL MEMORY INTERFACE
In extended microcontroller mode, when the device is
executing out of internal memory, the control signals
will continue to be active. That is, they indicate the
action that is occurring in the internal memory. The
external memory access is ignored.
When either microprocessor or extended microcontroller mode is selected, PORTC, PORTD and PORTE are
configured as the system bus. PORTC and PORTD are
the multiplexed address/data bus and PORTE is for the
control signals. External components are needed to
demultiplex the address and data. This can be done as
shown in Figure 6-4. The waveforms of address and
data are shown in Figure 6-3. For complete timings,
please refer to the electrical specification section.
FIGURE 6-3:
Q1
AD
<15:0>
Q2
This following selection is for use with Microchip
EPROMs. For interfacing to other manufacturers memory, please refer to the electrical specifications of the
desired PIC17C4X device, as well as the desired memory device to ensure compatibility.
TABLE 6-2:
EXTERNAL PROGRAM
MEMORY ACCESS
WAVEFORMS
Q4
Q3
Address out Data in
Q1
Q2
Q3
Address out
EPROM Suffix
Q1
Q4
EPROM MEMORY ACCESS
TIME ORDERING SUFFIX
PIC17C4X Instruction
Oscillator
Cycle
Frequency Time (TCY)
Data out
PIC17C42
PIC17C43
PIC17C44
ALE
OE
'1'
WR
Read cycle
Write cycle
The system bus requires that there is no bus conflict
(minimal leakage), so the output value (address) will be
capacitively held at the desired value.
As the speed of the processor increases, external
EPROM memory with faster access time must be used.
Table 6-2 lists external memory speed requirements for
a given PIC17C4X device frequency.
8 MHz
500 ns
-25
-25
16 MHz
250 ns
-12
-15
20 MHz
200 ns
-90
-10
25 MHz
160 ns
N.A.
-70
33 MHz
121 ns
N.A.
(1)
Note 1: The access times for this requires the use of
fast SRAMS.
Note:
FIGURE 6-4:
The external memory interface is not supported for the LC devices.
TYPICAL EXTERNAL PROGRAM MEMORY CONNECTION DIAGRAM
AD15-AD0
Memory
(MSB)
A15-A0
AD7-AD0
373
PIC17C4X
Memory
(LSB)
Ax-A0
Ax-A0
D7-D0
D7-D0
CE
CE
OE WR (2)
OE
WR(2)
AD15-AD8
373
ALE
138(1)
(1)
I/O
OE
WR
Note 1: Use of I/O pins is only required for paged memory.
2: This signal is unused for ROM and EPROM devices.
1996 Microchip Technology Inc.
DS30412C-page 31
PIC17C4X
6.2
Data Memory Organization
6.2.1
GENERAL PURPOSE REGISTER (GPR)
Data memory is partitioned into two areas. The first is
the General Purpose Registers (GPR) area, while the
second is the Special Function Registers (SFR) area.
The SFRs control the operation of the device.
All devices have some amount of GPR area. The GPRs
are 8-bits wide. When the GPR area is greater than
232, it must be banked to allow access to the additional
memory space.
Portions of data memory are banked, this is for both
areas. The GPR area is banked to allow greater than
232 bytes of general purpose RAM. SFRs are for the
registers that control the peripheral functions. Banking
requires the use of control bits for bank selection.
These control bits are located in the Bank Select Register (BSR). If an access is made to a location outside
this banked region, the BSR bits are ignored.
Figure 6-5 shows the data memory map organization
for the PIC17C42 and Figure 6-6 for all of the other
PIC17C4X devices.
Only the PIC17C43 and PIC17C44 devices have
banked memory in the GPR area. To facilitate switching
between these banks, the MOVLR bank instruction has
been added to the instruction set. GPRs are not initialized by a Power-on Reset and are unchanged on all
other resets.
Instructions MOVPF and MOVFP provide the means to
move values from the peripheral area (“P”) to any location in the register file (“F”), and vice-versa. The definition of the “P” range is from 0h to 1Fh, while the “F”
range is 0h to FFh. The “P” range has six more locations than peripheral registers (eight locations for the
PIC17C42 device) which can be used as General Purpose Registers. This can be useful in some applications
where variables need to be copied to other locations in
the general purpose RAM (such as saving status information during an interrupt).
The SFRs can be classified into two sets, those associated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described here, while those related to a
peripheral feature are described in the section for each
peripheral feature.
6.2.2
SPECIAL FUNCTION REGISTERS (SFR)
The SFRs are used by the CPU and peripheral functions to control the operation of the device (Figure 6-5
and Figure 6-6). These registers are static RAM.
The peripheral registers are in the banked portion of
memory, while the core registers are in the unbanked
region. To facilitate switching between the peripheral
banks, the MOVLB bank instruction has been provided.
The entire data memory can be accessed either directly
or indirectly through file select registers FSR0 and
FSR1 (Section 6.4). Indirect addressing uses the
appropriate control bits of the BSR for accesses into the
banked areas of data memory. The BSR is explained in
greater detail in Section 6.8.
DS30412C-page 32
1996 Microchip Technology Inc.
PIC17C4X
FIGURE 6-5:
PIC17C42 REGISTER FILE
MAP
FIGURE 6-6:
PIC17CR42/42A/43/R43/44
REGISTER FILE MAP
Addr Unbanked
Addr Unbanked
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
INDF0
FSR0
PCL
PCLATH
ALUSTA
T0STA
CPUSTA
INTSTA
INDF1
FSR1
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
Bank 0
10h
11h
12h
13h
14h
15h
16h
17h
18h
1Fh
20h
Bank 1
(1)
Bank 2
(1)
Bank 3
(1)
PORTA
DDRC
TMR1
PW1DCL
DDRB
PORTC
TMR2
PW2DCL
PORTB
DDRD
TMR3L
PW1DCH
RCSTA
PORTD
TMR3H
PW2DCH
RCREG
DDRE
PR1
CA2L
TXSTA
PORTE
PR2
CA2H
TXREG
PIR
PR3L/CA1L
TCON1
SPBRG
PIE
PR3H/CA1H
TCON2
General
Purpose
RAM
FFh
Note 1: SFR file locations 10h - 17h are banked. All
other SFRs ignore the Bank Select Register
(BSR) bits.
1996 Microchip Technology Inc.
INDF0
FSR0
PCL
PCLATH
ALUSTA
T0STA
CPUSTA
INTSTA
INDF1
FSR1
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
Bank 0
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Fh
20h
Bank 1 (1)
Bank 2 (1) Bank 3 (1)
PORTA
DDRC
TMR1
DDRB
PORTC
TMR2
PW1DCL
PW2DCL
PORTB
DDRD
TMR3L
PW1DCH
RCSTA
PORTD
TMR3H
PW2DCH
RCREG
DDRE
PR1
CA2L
TXSTA
PORTE
PR2
CA2H
TXREG
PIR
PR3L/CA1L
TCON1
SPBRG
PIE
PR3H/CA1H
TCON2
PRODL
PRODH
General
Purpose
RAM (2)
General
Purpose
RAM (2)
FFh
Note 1: SFR file locations 10h - 17h are banked. All
other SFRs ignore the Bank Select Register
(BSR) bits.
2: General Purpose Registers (GPR) locations
20h - FFh and 120h - 1FFh are banked. All
other GPRs ignore the Bank Select Register
(BSR) bits.
DS30412C-page 33
PIC17C4X
TABLE 6-3:
Address
Name
SPECIAL FUNCTION REGISTERS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other
resets (3)
---- ----
Unbanked
00h
INDF0
Uses contents of FSR0 to address data memory (not a physical register)
---- ----
01h
FSR0
Indirect data memory address pointer 0
xxxx xxxx
uuuu uuuu
02h
PCL
Low order 8-bits of PC
0000 0000
0000 0000
03h(1)
PCLATH
Holding register for upper 8-bits of PC
04h
ALUSTA
05h
T0STA
0000 0000
uuuu uuuu
FS3
FS2
FS1
FS0
OV
Z
DC
C
1111 xxxx
1111 uuuu
INTEDG
T0SE
T0CS
PS3
PS2
PS1
PS0
—
0000 000-
0000 000-
06h
CPUSTA
—
—
STKAV
GLINTD
TO
PD
—
—
--11 11--
--11 qq--
07h
INTSTA
PEIF
T0CKIF
T0IF
INTF
PEIE
T0CKIE
T0IE
INTE
0000 0000
0000 0000
08h
INDF1
Uses contents of FSR1 to address data memory (not a physical register)
---- ----
---- ----
09h
FSR1
Indirect data memory address pointer 1
xxxx xxxx
uuuu uuuu
0Ah
WREG
Working register
xxxx xxxx
uuuu uuuu
0Bh
TMR0L
TMR0 register; low byte
xxxx xxxx
uuuu uuuu
0Ch
TMR0H
TMR0 register; high byte
xxxx xxxx
uuuu uuuu
0Dh
TBLPTRL
Low byte of program memory table pointer
(4)
(4)
0Eh
TBLPTRH
High byte of program memory table pointer
(4)
(4)
0Fh
BSR
Bank select register
0000 0000
0000 0000
(2)
Bank 0
10h
PORTA
0-xx xxxx
0-uu uuuu
11h
DDRB
Data direction register for PORTB
1111 1111
1111 1111
12h
PORTB
PORTB data latch
xxxx xxxx
uuuu uuuu
13h
RCSTA
0000 -00x
0000 -00u
14h
RCREG
15h
TXSTA
16h
TXREG
17h
SPBRG
DDRC
Data direction register for PORTC
RBPU
SPEN
—
RX9
RA5
SREN
RA4
CREN
RA3
—
RA2
FERR
RA1/T0CKI
OERR
RA0/INT
RX9D
Serial port receive register
xxxx xxxx
uuuu uuuu
0000 --1x
0000 --1u
Serial port transmit register
xxxx xxxx
uuuu uuuu
Baud rate generator register
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
xxxx xxxx
uuuu uuuu
CSRC
TX9
TXEN
SYNC
—
—
TRMT
TX9D
Bank 1
10h
11h
PORTC
12h
DDRD
13h
PORTD
RC7/
AD7
RC6/
AD6
RC5/
AD5
RC4/
AD4
RC3/
AD3
RC2/
AD2
RC1/
AD1
RC0/
AD0
1111 1111
1111 1111
RD4/
AD12
RD3/
AD11
RD2/
AD10
RD1/
AD9
RD0/
AD8
xxxx xxxx
uuuu uuuu
---- -111
---- -111
—
—
RE2/WR
RE1/OE
RE0/ALE
---- -xxx
---- -uuu
Data direction register for PORTD
RD7/
AD15
RD6/
AD14
RD5/
AD13
14h
DDRE
15h
PORTE
16h
PIR
RBIF
TMR3IF
TMR2IF
TMR1IF
CA2IF
CA1IF
TXIF
RCIF
0000 0010
0000 0010
17h
PIE
RBIE
TMR3IE
TMR2IE
TMR1IE
CA2IE
CA1IE
TXIE
RCIE
0000 0000
0000 0000
Legend:
Note 1:
2:
3:
4:
5:
Data direction register for PORTE
—
—
—
x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. Shaded cells are unimplemented, read as '0'.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose contents are updated
from or transferred to the upper byte of the program counter.
The TO and PD status bits in CPUSTA are not affected by a MCLR reset.
Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
The following values are for both TBLPTRL and TBLPTRH:
All PIC17C4X devices (Power-on Reset 0000 0000) and (All other resets 0000 0000)
except the PIC17C42 (Power-on Reset xxxx xxxx) and (All other resets uuuu uuuu)
The PRODL and PRODH registers are not implemented on the PIC17C42.
DS30412C-page 34
1996 Microchip Technology Inc.
PIC17C4X
TABLE 6-3:
Address
SPECIAL FUNCTION REGISTERS (Cont.’d)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other
resets (3)
Bank 2
10h
TMR1
Timer1
xxxx xxxx
uuuu uuuu
11h
TMR2
Timer2
xxxx xxxx
uuuu uuuu
12h
TMR3L
TMR3 register; low byte
xxxx xxxx
uuuu uuuu
13h
TMR3H
TMR3 register; high byte
xxxx xxxx
uuuu uuuu
14h
PR1
Timer1 period register
xxxx xxxx
uuuu uuuu
15h
PR2
Timer2 period register
xxxx xxxx
uuuu uuuu
16h
PR3L/CA1L
Timer3 period register, low byte/capture1 register; low byte
xxxx xxxx
uuuu uuuu
17h
PR3H/CA1H
Timer3 period register, high byte/capture1 register; high byte
xxxx xxxx
uuuu uuuu
Bank 3
10h
PW1DCL
DC1
DC0
—
—
—
—
—
—
xx-- ----
uu-- ----
11h
PW2DCL
DC1
DC0
TM2PW2
—
—
—
—
—
xx0- ----
uu0- ----
12h
PW1DCH
DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx
uuuu uuuu
13h
PW2DCH
DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx
uuuu uuuu
14h
CA2L
Capture2 low byte
xxxx xxxx
uuuu uuuu
15h
CA2H
Capture2 high byte
xxxx xxxx
uuuu uuuu
16h
TCON1
CA2ED1 CA2ED0
TMR3CS
TMR2CS
TMR1CS
0000 0000
0000 0000
17h
TCON2
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON
TMR2ON
TMR1ON
0000 0000
0000 0000
CA1ED1
CA1ED0
T16
Unbanked
18h (5)
PRODL
Low Byte of 16-bit Product (8 x 8 Hardware Multiply)
xxxx xxxx
uuuu uuuu
(5)
PRODH
High Byte of 16-bit Product (8 x 8 Hardware Multiply)
xxxx xxxx
uuuu uuuu
19h
Legend:
Note 1:
2:
3:
4:
5:
x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. Shaded cells are unimplemented, read as '0'.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose contents are updated
from or transferred to the upper byte of the program counter.
The TO and PD status bits in CPUSTA are not affected by a MCLR reset.
Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
The following values are for both TBLPTRL and TBLPTRH:
All PIC17C4X devices (Power-on Reset 0000 0000) and (All other resets 0000 0000)
except the PIC17C42 (Power-on Reset xxxx xxxx) and (All other resets uuuu uuuu)
The PRODL and PRODH registers are not implemented on the PIC17C42.
1996 Microchip Technology Inc.
DS30412C-page 35
PIC17C4X
6.2.2.1
ALU STATUS REGISTER (ALUSTA)
The ALUSTA register contains the status bits of the
Arithmetic and Logic Unit and the mode control bits for
the indirect addressing register.
As with all the other registers, the ALUSTA register can
be the destination for any instruction. If the ALUSTA
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Therefore, the result of an instruction with
the ALUSTA register as destination may be different
than intended.
For example, CLRF ALUSTA will clear the upper four bits
and set the Z bit. This leaves the ALUSTA register as
0000u1uu (where u = unchanged).
FIGURE 6-7:
It is recommended, therefore, that only BCF, BSF, SWAPF
and MOVWF instructions be used to alter the ALUSTA
register because these instructions do not affect any
status bit. To see how other instructions affect the status bits, see the “Instruction Set Summary.”
Note 1: The C and DC bits operate as a borrow
out bit in subtraction. See the SUBLW and
SUBWF instructions for examples.
Note 2: The overflow bit will be set if the 2’s complement result exceeds +127 or is less
than -128.
Arithmetic and Logic Unit (ALU) is capable of carrying
out arithmetic or logical operations on two operands or
a single operand. All single operand instructions operate either on the WREG register or a file register. For
two operand instructions, one of the operands is the
WREG register and the other one is either a file register
or an 8-bit immediate constant.
ALUSTA REGISTER (ADDRESS: 04h, UNBANKED)
R/W - 1 R/W - 1 R/W - 1 R/W - 1
FS3
FS2
FS1
FS0
bit7
R/W - x
OV
R/W - x
Z
R/W - x
DC
R/W - x
C
bit0
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
bit 7-6: FS3:FS2: FSR1 Mode Select bits
00 = Post auto-decrement FSR1 value
01 = Post auto-increment FSR1 value
1x = FSR1 value does not change
bit 5-4: FS1:FS0: FSR0 Mode Select bits
00 = Post auto-decrement FSR0 value
01 = Post auto-increment FSR0 value
1x = FSR0 value does not change
bit 3:
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude,
which causes the sign bit (bit7) to change state.
1 = Overflow occurred for signed arithmetic, (in this arithmetic operation)
0 = No overflow occurred
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The results of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit
For ADDWF and ADDLW instructions.
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
Note: For borrow the polarity is reversed.
bit 0:
C: carry/borrow bit
For ADDWF and ADDLW instructions.
1 = A carry-out from the most significant bit of the result occurred
Note that a subtraction is executed by adding the two’s complement of the second operand. For rotate
(RRCF, RLCF) instructions, this bit is loaded with either the high or low order bit of the source register.
0 = No carry-out from the most significant bit of the result
Note: For borrow the polarity is reversed.
DS30412C-page 36
1996 Microchip Technology Inc.
PIC17C4X
6.2.2.2
CPU STATUS REGISTER (CPUSTA)
The CPUSTA register contains the status and control
bits for the CPU. This register is used to globally
enable/disable interrupts. If only a specific interrupt is
desired to be enabled/disabled, please refer to the
INTerrupt STAtus (INTSTA) register and the Peripheral
Interrupt Enable (PIE) register. This register also indicates if the stack is available and contains the
Power-down (PD) and Time-out (TO) bits. The TO, PD,
and STKAV bits are not writable. These bits are set and
cleared according to device logic. Therefore, the result
of an instruction with the CPUSTA register as destination may be different than intended.
FIGURE 6-8:
U-0
—
bit7
CPUSTA REGISTER (ADDRESS: 06h, UNBANKED)
U-0
—
R-1
R/W - 1
STKAV GLINTD
R-1
TO
R-1
PD
U-0
—
U-0
—
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
Read as ‘0’
- n = Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5:
STKAV: Stack Available bit
This bit indicates that the 4-bit stack pointer value is Fh, or has rolled over from Fh → 0h (stack overflow).
1 = Stack is available
0 = Stack is full, or a stack overflow may have occurred (Once this bit has been cleared by a
stack overflow, only a device reset will set this bit)
bit 4:
GLINTD: Global Interrupt Disable bit
This bit disables all interrupts. When enabling interrupts, only the sources with their enable bits set can
cause an interrupt.
1 = Disable all interrupts
0 = Enables all un-masked interrupts
bit 3:
TO: WDT Time-out Status bit
1 = After power-up or by a CLRWDT instruction
0 = A Watchdog Timer time-out occurred
bit 2:
PD: Power-down Status bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 1-0: Unimplemented: Read as '0'
1996 Microchip Technology Inc.
DS30412C-page 37
PIC17C4X
6.2.2.3
TMR0 STATUS/CONTROL REGISTER
(T0STA)
This register contains various control bits. Bit7
(INTEDG) is used to control the edge upon which a signal on the RA0/INT pin will set the RB0/INT interrupt
flag. The other bits configure the Timer0 prescaler and
clock source. (Figure 11-1).
FIGURE 6-9:
R/W - 0
INTEDG
bit7
T0STA REGISTER (ADDRESS: 05h, UNBANKED)
R/W - 0
T0SE
R/W - 0
T0CS
R/W - 0
PS3
R/W - 0
PS2
R/W - 0
PS1
R/W - 0
PS0
U-0
—
bit0
R = Readable bit
W = Writable bit
U = Unimplemented,
reads as ‘0’
-n = Value at POR reset
bit 7:
INTEDG: RA0/INT Pin Interrupt Edge Select bit
This bit selects the edge upon which the interrupt is detected.
1 = Rising edge of RA0/INT pin generates interrupt
0 = Falling edge of RA0/INT pin generates interrupt
bit 6:
T0SE: Timer0 Clock Input Edge Select bit
This bit selects the edge upon which TMR0 will increment.
When T0CS = 0
1 = Rising edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt
0 = Falling edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt
When T0CS = 1
Don’t care
bit 5:
T0CS: Timer0 Clock Source Select bit
This bit selects the clock source for Timer0.
1 = Internal instruction clock cycle (TCY)
0 = T0CKI pin
bit 4-1: PS3:PS0: Timer0 Prescale Selection bits
These bits select the prescale value for Timer0.
PS3:PS0
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
bit 0:
Prescale Value
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Unimplemented: Read as '0'
DS30412C-page 38
1996 Microchip Technology Inc.
PIC17C4X
6.3
Stack Operation
6.4
Indirect Addressing
The PIC17C4X devices have a 16 x 16-bit wide hardware stack (Figure 6-1). The stack is not part of either
the program or data memory space, and the stack
pointer is neither readable nor writable. The PC is
“PUSHed” onto the stack when a CALL instruction is
executed or an interrupt is acknowledged. The stack is
“POPed” in the event of a RETURN, RETLW, or a RETFIE
instruction execution. PCLATH is not affected by a
“PUSH” or a “POP” operation.
Indirect addressing is a mode of addressing data
memory where the data memory address in the
instruction is not fixed. That is, the register that is to be
read or written can be modified by the program. This
can be useful for data tables in the data memory.
Figure 6-10 shows the operation of indirect addressing. This shows the moving of the value to the data
memory address specified by the value of the FSR
register.
The stack operates as a circular buffer, with the stack
pointer initialized to '0' after all resets. There is a stack
available bit (STKAV) to allow software to ensure that
the stack has not overflowed. The STKAV bit is set after
a device reset. When the stack pointer equals Fh,
STKAV is cleared. When the stack pointer rolls over
from Fh to 0h, the STKAV bit will be held clear until a
device reset.
Example 6-1 shows the use of indirect addressing to
clear RAM in a minimum number of instructions. A
similar concept could be used to move a defined number of bytes (block) of data to the USART transmit register (TXREG). The starting address of the block of
data to be transmitted could easily be modified by the
program.
FIGURE 6-10: INDIRECT ADDRESSING
Note 1: There is not a status bit for stack underflow. The STKAV bit can be used to detect
the underflow which results in the stack
pointer being at the top of stack.
Note 2: There are no instruction mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt vector.
Note 3: After a reset, if a “POP” operation occurs
before a “PUSH” operation, the STKAV bit
will be cleared. This will appear as if the
stack is full (underflow has occurred). If a
“PUSH” operation occurs next (before
another “POP”), the STKAV bit will be
locked clear. Only a device reset will
cause this bit to set.
RAM
Instruction
Executed
Opcode
Address
File = INDFx
Instruction
Fetched
Opcode
File
FSR
After the device is “PUSHed” sixteen times (without a
“POP”), the seventeenth push overwrites the value
from the first push. The eighteenth push overwrites the
second push (and so on).
1996 Microchip Technology Inc.
DS30412C-page 39
PIC17C4X
6.4.1
INDIRECT ADDRESSING REGISTERS
The PIC17C4X has four registers for indirect addressing. These registers are:
A simple program to clear RAM from 20h - FFh is
shown in Example 6-1.
EXAMPLE 6-1:
• INDF0 and FSR0
• INDF1 and FSR1
Registers INDF0 and INDF1 are not physically implemented. Reading or writing to these registers activates
indirect addressing, with the value in the corresponding FSR register being the address of the data. The
FSR is an 8-bit register and allows addressing anywhere in the 256-byte data memory address range.
For banked memory, the bank of memory accessed is
specified by the value in the BSR.
If file INDF0 (or INDF1) itself is read indirectly via an
FSR, all '0's are read (Zero bit is set). Similarly, if
INDF0 (or INDF1) is written to indirectly, the operation
will be equivalent to a NOP, and the status bits are not
affected.
6.4.2
INDIRECT ADDRESSING OPERATION
The indirect addressing capability has been enhanced
over that of the PIC16CXX family. There are two control bits associated with each FSR register. These two
bits configure the FSR register to:
• Auto-decrement the value (address) in the FSR
after an indirect access
• Auto-increment the value (address) in the FSR
after an indirect access
• No change to the value (address) in the FSR after
an indirect access
These control bits are located in the ALUSTA register.
The FSR1 register is controlled by the FS3:FS2 bits
and FSR0 is controlled by the FS1:FS0 bits.
When using the auto-increment or auto-decrement
features, the effect on the FSR is not reflected in the
ALUSTA register. For example, if the indirect address
causes the FSR to equal '0', the Z bit will not be set.
LP
6.5
MOVLW
MOVWF
BCF
BSF
BCF
MOVLW
CLRF
CPFSEQ
GOTO
:
:
INDIRECT ADDRESSING
0x20
FSR0
ALUSTA,
ALUSTA,
ALUSTA,
END_RAM
INDF0
FSR0
LP
FS1
FS0
C
+ 1
;
;
;
;
;
;
;
;
;
;
;
FSR0 = 20h
Increment FSR
after access
C = 0
Addr(FSR) = 0
FSR0 = END_RAM+1?
NO, clear next
YES, All RAM is
cleared
Table Pointer (TBLPTRL and
TBLPTRH)
File registers TBLPTRL and TBLPTRH form a 16-bit
pointer to address the 64K program memory space.
The table pointer is used by instructions TABLWT and
TABLRD.
The TABLRD and the TABLWT instructions allow transfer of data between program and data space. The table
pointer serves as the 16-bit address of the data word
within the program memory. For a more complete
description of these registers and the operation of Table
Reads and Table Writes, see Section 7.0.
6.6
Table Latch (TBLATH, TBLATL)
The table latch (TBLAT) is a 16-bit register, with
TBLATH and TBLATL referring to the high and low
bytes of the register. It is not mapped into data or program memory. The table latch is used as a temporary
holding latch during data transfer between program and
data memory (see descriptions of instructions TABLRD,
TABLWT, TLRD and TLWT). For a more complete
description of these registers and the operation of Table
Reads and Table Writes, see Section 7.0.
If the FSR register contains a value of 0h, an indirect
read will read 0h (Zero bit is set) while an indirect write
will be equivalent to a NOP (status bits are not
affected).
Indirect addressing allows single cycle data transfers
within the entire data space. This is possible with the
use of the MOVPF and MOVFP instructions, where either
'p' or 'f' is specified as INDF0 (or INDF1).
If the source or destination of the indirect address is in
banked memory, the location accessed will be determined by the value in the BSR.
DS30412C-page 40
1996 Microchip Technology Inc.
PIC17C4X
6.7
Program Counter Module
Using Figure 6-11, the operations of the PC and
PCLATH for different instructions are as follows:
The Program Counter (PC) is a 16-bit register. PCL, the
low byte of the PC, is mapped in the data memory. PCL
is readable and writable just as is any other register.
PCH is the high byte of the PC and is not directly
addressable. Since PCH is not mapped in data or program memory, an 8-bit register PCLATH (PC high latch)
is used as a holding latch for the high byte of the PC.
PCLATH is mapped into data memory. The user can
read or write PCH through PCLATH.
The 16-bit wide PC is incremented after each instruction fetch during Q1 unless:
• Modified by GOTO, CALL, LCALL, RETURN, RETLW,
or RETFIE instruction
• Modified by an interrupt response
• Due to destination write to PCL by an instruction
“Skips” are equivalent to a forced NOP cycle at the
skipped address.
a)
b)
c)
d)
Figure 6-11 and Figure 6-12 show the operation of the
program counter for various situations.
FIGURE 6-11: PROGRAM COUNTER
OPERATION
e)
Internal data bus <8>
Using Figure 6-12, the operation of the PC and
PCLATH for GOTO and CALL instructions is a follows:
8
CALL, GOTO instructions:
A 13-bit destination address is provided in the
instruction (opcode).
Opcode<12:0> → PC <12:0>
PC<15:13> → PCLATH<7:5>
Opcode<12:8> → PCLATH <4:0>
8
PCLATH
8
PCH
PCL
FIGURE 6-12: PROGRAM COUNTER USING
THE CALL AND GOTO
INSTRUCTIONS
15
13 12
Last write
to PCLATH
8 7
Opcode
0
5
3
7
54
0
PCLATH
8
0
8 7
PCH
1996 Microchip Technology Inc.
The read-modify-write only affects the PCL with the
result. PCH is loaded with the value in the PCLATH.
For example, ADDWF PCL will result in a jump within the
current page. If PC = 03F0h, WREG = 30h and
PCLATH = 03h before instruction, PC = 0320h after the
instruction. To accomplish a true 16-bit computed jump,
the user needs to compute the 16-bit destination
address, write the high byte to PCLATH and then write
the low value to PCL.
The following PC related operations do not change
PCLATH:
8
15
LCALL instructions:
An 8-bit destination address is provided in the
instruction (opcode). PCLATH is unchanged.
PCLATH → PCH
Opcode<7:0> → PCL
Read instructions on PCL:
Any instruction that reads PCL.
PCL → data bus → ALU or destination
PCH → PCLATH
Write instructions on PCL:
Any instruction that writes to PCL.
8-bit data → data bus → PCL
PCLATH → PCH
Read-Modify-Write instructions on PCL:
Any instruction that does a read-write-modify
operation on PCL, such as ADDWF PCL.
Read: PCL → data bus → ALU
Write: 8-bit result → data bus → PCL
PCLATH → PCH
RETURN instruction:
PCH → PCLATH
Stack<MRU> → PC<15:0>
PCL
a)
b)
c)
LCALL, RETLW, and RETFIE instructions.
Interrupt vector is forced onto the PC.
Read-modify-write instructions on PCL (e.g. BSF
PCL).
DS30412C-page 41
PIC17C4X
6.8
Bank Select Register (BSR)
For the PIC17C43, PIC17CR43, and PIC17C44
devices, the need for a large general purpose memory
space dictated a general purpose RAM banking
scheme. The upper nibble of the BSR selects the currently active general purpose RAM bank. To assist this,
a MOVLR bank instruction has been provided in the
instruction set.
The BSR is used to switch between banks in the data
memory area (Figure 6-13). In the PIC17C42,
PIC17CR42, and PIC17C42A only the lower nibble is
implemented. While in the PIC17C43, PIC17CR43,
and PIC17C44 devices, the entire byte is implemented.
The lower nibble is used to select the peripheral register bank. The upper nibble is used to select the general
purpose memory bank.
If the currently selected bank is not implemented (such
as Bank 13), any read will read all '0's. Any write is completed to the bit bucket and the ALU status bits will be
set/cleared as appropriate.
All the Special Function Registers (SFRs) are mapped
into the data memory space. In order to accommodate
the large number of registers, a banking scheme has
been used. A segment of the SFRs, from address 10h
to address 17h, is banked. The lower nibble of the bank
select register (BSR) selects the currently active
“peripheral bank.” Effort has been made to group the
peripheral registers of related functionality in one bank.
However, it will still be necessary to switch from bank
to bank in order to address all peripherals related to a
single task. To assist this, a MOVLB bank instruction is
in the instruction set.
Note:
Registers in Bank 15 in the Special Function Register area, are reserved for
Microchip use. Reading of registers in this
bank may cause random values to be read.
FIGURE 6-13: BSR OPERATION (PIC17C43/R43/44)
BSR
7
4 3
(2)
Address
Range
0
(1)
0
1
2
3
4
10h
15
SFR
Banks
•••
17h
Bank 0
Bank 1
Bank 2
0
1
2
20h
Bank 3
Bank 4
Bank 15
15
•••
GPR
Banks
•••
FFh
Bank 0
Bank 1
Bank 2
Bank 15
Note 1:
Only Banks 0 through Bank 3 are implemented. Selection of an unimplemented bank is not recommended.
Bank 15 is reserved for Microchip use, reading of registers in this bank may cause random values to be read.
2: Only Banks 0 and Bank 1 are implemented. Selection of an unimplemented bank is not recommended.
DS30412C-page 42
1996 Microchip Technology Inc.
PIC17C4X
7.0
TABLE READS AND TABLE
WRITES
FIGURE 7-2:
The PIC17C4X has four instructions that allow the processor to move data from the data memory space to
the program memory space, and vice versa. Since the
program memory space is 16-bits wide and the data
memory space is 8-bits wide, two operations are
required to move 16-bit values to/from the data memory.
The TLWT t,f and TABLWT t,i,f instructions are
used to write data from the data memory space to the
program memory space. The TLRD t,f and TABLRD
t,i,f instructions are used to write data from the program memory space to the data memory space.
The program memory can be internal or external. For
the program memory access to be external, the device
needs to be operating in extended microcontroller or
microprocessor mode.
Figure 7-1 through Figure 7-4 show the operation of
these four instructions.
FIGURE 7-1:
TABLWT INSTRUCTION
OPERATION
TABLE POINTER
TBLPTRH
TBLPTRL
TABLE LATCH (16-bit)
TABLATH
TABLATL
3
3
TABLWT
1,i,f
TABLWT
DATA
MEMORY
f
0,i,f
PROGRAM MEMORY
1
Prog-Mem
(TBLPTR)
TLWT INSTRUCTION
OPERATION
2
TABLE POINTER
TBLPTRH
TBLPTRL
TABLE LATCH (16-bit)
TABLATH
TLWT
TABLATL
1,f
DATA
MEMORY
TLWT
0,f
PROGRAM MEMORY
Note 1: 8-bit value, from register 'f', loaded into
the high or low byte in TABLAT (16-bit).
2: 16-bit TABLAT value written to address
Program Memory (TBLPTR).
3: If “i” = 1, then TBLPTR = TBLPTR + 1,
If “i” = 0, then TBLPTR is unchanged.
f
1
Note 1: 8-bit value, from register 'f', loaded into the
high or low byte in TABLAT (16-bit).
1996 Microchip Technology Inc.
DS30412C-page 43
This document was created with FrameMaker 4 0 4
PIC17C4X
FIGURE 7-3:
TLRD INSTRUCTION
OPERATION
FIGURE 7-4:
TABLE POINTER
TABLE POINTER
TBLPTRH
TBLPTRH
TBLPTRL
TLRD
1,f
TBLPTRL
TABLE LATCH (16-bit)
TABLE LATCH (16-bit)
TABLATH
TABLRD INSTRUCTION
OPERATION
TABLATH
TABLATL
TLRD
TABLATL
0,f
3
3
DATA
MEMORY
TABLRD
TABLRD
1,i,f
DATA
MEMORY
f
0,i,f
PROGRAM MEMORY
PROGRAM MEMORY
1
f
1
Prog-Mem
(TBLPTR)
2
Note 1: 8-bit value, from TABLAT (16-bit) high or
low byte, loaded into register 'f'.
DS30412C-page 44
Note 1: 8-bit value, from TABLAT (16-bit) high or
low byte, loaded into register 'f'.
2: 16-bit value at Program Memory (TBLPTR)
loaded into TABLAT register.
3: If “i” = 1, then TBLPTR = TBLPTR + 1,
If “i” = 0, then TBLPTR is unchanged.
1996 Microchip Technology Inc.
PIC17C4X
Table Writes to Internal Memory
7.1
7.1.1
An interrupt source or reset are the only events that
terminate a long write operation. Terminating the long
write from an interrupt source requires that the interrupt enable and flag bits are set. The GLINTD bit only
enables the vectoring to the interrupt address.
A table write operation to internal memory causes a
long write operation. The long write is necessary for
programming the internal EPROM. Instruction execution is halted while in a long write cycle. The long write
will be terminated by any enabled interrupt. To ensure
that the EPROM location has been well programmed,
a minimum programming time is required (see specification #D114 ). Having only one interrupt enabled to
terminate the long write ensures that no unintentional
interrupts will prematurely terminate the long write.
If the T0CKI, RA0/INT, or TMR0 interrupt source is
used to terminate the long write; the interrupt flag, of
the highest priority enabled interrupt, will terminate the
long write and automatically be cleared.
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
Note 1: If an interrupt is pending, the TABLWT is
aborted (an NOP is executed). The
highest priority pending interrupt, from
the T0CKI, RA0/INT, or TMR0 sources
that is enabled, has its flag cleared.
Disable all interrupt sources, except the source
to terminate EPROM program write.
Raise MCLR/VPP pin to the programming voltage.
Clear the WDT.
Do the table write. The interrupt will terminate
the long write.
Verify the memory location (table read).
Note:
TERMINATING LONG WRITES
Note 2: If the interrupt is not being used for the
program write timing, the interrupt
should be disabled. This will ensure that
the interrupt is not lost, nor will it terminate the long write prematurely.
If a peripheral interrupt source is used to terminate the
long write, the interrupt enable and flag bits must be
set. The interrupt flag will not be automatically cleared
upon the vectoring to the interrupt vector address.
Programming requirements must be met.
See timing specification in electrical specifications for the desired device. Violating
these specifications (including temperature) may result in EPROM locations that
are not fully programmed and may lose
their state over time.
If the GLINTD bit is cleared prior to the long write,
when the long write is terminated, the program will
branch to the interrupt vector.
If the GLINTD bit is set prior to the long write, when
the long write is terminated, the program will not vector
to the interrupt address.
TABLE 7-1:
Interrupt
Source
RA0/INT, TMR0,
T0CKI
Peripheral
INTERRUPT - TABLE WRITE INTERACTION
GLINTD
Enable
Bit
Flag
Bit
0
1
1
0
1
1
1
0
1
0
x
1
0
0
1
1
1
1
0
1
1
0
x
1
1996 Microchip Technology Inc.
Action
Terminate long table write (to internal program
memory), branch to interrupt vector (branch clears
flag bit).
None
None
Terminate table write, do not branch to interrupt
vector (flag is automatically cleared).
Terminate table write, branch to interrupt vector.
None
None
Terminate table write, do not branch to interrupt
vector (flag is set).
DS30412C-page 45
PIC17C4X
7.2
Table Writes to External Memory
7.2.2
Table writes to external memory are always two-cycle
instructions. The second cycle writes the data to the
external memory location. The sequence of events for
an external memory write are the same for an internal
write.
TABLE WRITE CODE
The “i” operand of the TABLWT instruction can specify
that the value in the 16-bit TBLPTR register is automatically incremented for the next write. In
Example 7-1, the TBLPTR register is not automatically
incremented.
EXAMPLE 7-1:
Note:
If an interrupt is pending or occurs during
the TABLWT, the two cycle table write
completes. The RA0/INT, TMR0, or T0CKI
interrupt flag is automatically cleared or
the pending peripheral interrupt is
acknowledged.
FIGURE 7-5:
CLRWDT
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
TLWT
MOVLW
TABLWT
TABLE WRITE
HIGH (TBL_ADDR)
TBLPTRH
LOW (TBL_ADDR)
TBLPTRL
HIGH (DATA)
1, WREG
LOW (DATA)
0,0,WREG
;
;
;
;
;
;
;
;
;
;
;
;
Clear WDT
Load the Table
address
Load HI byte
in TABLATCH
Load LO byte
in TABLATCH
and write to
program memory
(Ext. SRAM)
TABLWT WRITE TIMING (EXTERNAL MEMORY)
Q1 Q2 Q3 Q4
AD15:AD0
PC
Instruction
fetched
TABLWT
Instruction
executed
INST (PC-1)
Q1 Q2 Q3 Q4
PC+1
Q1 Q2 Q3 Q4
TBL
Data out
INST (PC+1)
TABLWT cycle1
Q1 Q2 Q3 Q4
PC+2
INST (PC+2)
TABLWT cycle2
INST (PC+1)
Data write cycle
ALE
OE
'1'
WR
Note:
If external write GLINTD = '1', Enable bit = '1', '1' → Flag bit, Do table write. The highest pending interrupt is cleared.
DS30412C-page 46
1996 Microchip Technology Inc.
PIC17C4X
FIGURE 7-6:
CONSECUTIVE TABLWT WRITE TIMING (EXTERNAL MEMORY)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
PC
Instruction
fetched
TABLWT1
Instruction
executed
INST (PC-1)
PC+1
TBL1
Data out 1
TABLWT2
PC+2
TBL2
Data out 2
INST (PC+2)
INST (PC+3)
TABLWT1 cycle1 TABLWT1 cycle2 TABLWT2 cycle1 TABLWT2 cycle2
Data write cycle
PC+3
INST (PC+2)
Data write cycle
ALE
OE
WR
1996 Microchip Technology Inc.
DS30412C-page 47
PIC17C4X
7.3
Table Reads
EXAMPLE 7-2:
The table read allows the program memory to be read.
This allows constant data to be stored in the program
memory space, and retrieved into data memory when
needed. Example 7-2 reads the 16-bit value at program memory address TBLPTR. After the dummy byte
has been read from the TABLATH, the TABLATH is
loaded with the 16-bit data from program memory
address TBLPTR + 1. The first read loads the data into
the latch, and can be considered a dummy read
(unknown data loaded into 'f'). INDF0 should be configured for either auto-increment or auto-decrement.
FIGURE 7-7:
TABLE READ
MOVLW
MOVWF
MOVLW
MOVWF
TABLRD
HIGH (TBL_ADDR)
TBLPTRH
LOW (TBL_ADDR)
TBLPTRL
0,0,DUMMY
TLRD
1, INDF0
TABLRD
0,1,INDF0
;
;
;
;
;
;
;
;
;
;
;
Load the Table
address
Dummy read,
Updates TABLATCH
Read HI byte
of TABLATCH
Read LO byte
of TABLATCH and
Update TABLATCH
TABLRD TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
PC
Instruction
fetched
TABLRD
Instruction
executed
INST (PC-1)
PC+1
TBL
Data in
INST (PC+2)
INST (PC+1)
TABLRD cycle1
PC+2
TABLRD cycle2
INST (PC+1)
Data read cycle
ALE
OE
WR
FIGURE 7-8:
'1'
TABLRD TIMING (CONSECUTIVE TABLRD INSTRUCTIONS)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
PC
Instruction
fetched
TABLRD1
Instruction
executed
INST (PC-1)
PC+1
TBL1 Data in 1
PC+2
TBL2
Data in 2
INST (PC+2)
TABLRD2
INST (PC+3)
TABLRD1 cycle1 TABLRD1 cycle2 TABLRD2 cycle1 TABLRD2 cycle2
Data read cycle
PC+3
INST (PC+2)
Data read cycle
ALE
OE
'1'
WR
DS30412C-page 48
1996 Microchip Technology Inc.
PIC17C4X
8.0
HARDWARE MULTIPLIER
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s most significant bit (MSb) is tested
and the appropriate subtractions are done.
All PIC17C4X devices except the PIC17C42, have an
8 x 8 hardware multiplier included in the ALU of the
device. By making the multiply a hardware operation, it
completes in a single instruction cycle. This is an
unsigned multiply that gives a 16-bit result. The result
is stored into the 16-bit PRODuct register
(PRODH:PRODL). The multiplier does not affect any
flags in the ALUSTA register.
EXAMPLE 8-1:
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
EXAMPLE 8-2:
MOVFP
MULWF
8 x 8 MULTIPLY ROUTINE
ARG1, WREG
ARG2
; ARG1 * ARG2 ->
;
PRODH:PRODL
8 x 8 SIGNED MULTIPLY
ROUTINE
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
MOVFP
MULWF
ARG1, WREG
ARG2
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
BTFSC
SUBWF
ARG2, SB
PRODH, F
Table 8-1 shows a performance comparison between
the PIC17C42 and all other PIC17CXX devices, which
have the single cycle hardware multiply.
MOVFP
BTFSC
SUBWF
ARG2, WREG
ARG1, SB
PRODH, F
; ARG1 * ARG2 ->
;
PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
;
- ARG1
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
TABLE 8-1:
PERFORMANCE COMPARISON
Routine
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
Device
PIC17C42
All other PIC17CXX devices
PIC17C42
All other PIC17CXX devices
PIC17C42
All other PIC17CXX devices
PIC17C42
All other PIC17CXX devices
Time
Program Memory
(Words)
Cycles (Max)
13
1
—
6
21
24
52
36
69
1
—
6
242
24
254
36
1996 Microchip Technology Inc.
@ 25 MHz
@ 33 MHz
11.04 µs
160 ns
—
960 ns
38.72 µs
3.84 µs
40.64 µs
5.76 µs
N/A
121 ns
N/A
727 ns
N/A
2.91 µs
N/A
4.36 µs
DS30412C-page 49
This document was created with FrameMaker 4 0 4
PIC17C4X
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 8-1 shows the algorithm
that is used. The 32-bit result is stored in 4 registers
RES3:RES0.
EQUATION 8-1:
RES3:RES0
MOVFP
MULWF
MOVPF
MOVPF
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
16 x 16 MULTIPLY ROUTINE
ARG1L, WREG
ARG2L
; ARG1L * ARG2L ->
;
PRODH:PRODL
PRODH, RES1 ;
PRODL, RES0 ;
;
MOVFP
MULWF
=
ARG1H:ARG1L * ARG2H:ARG2L
=
(ARG1H * ARG2H * 216) +
(ARG1H * ARG2L * 28)
+
28)
+
(ARG1L * ARG2H *
EXAMPLE 8-3:
MOVPF
MOVPF
ARG1H, WREG
ARG2H
; ARG1H * ARG2H ->
;
PRODH:PRODL
PRODH, RES3 ;
PRODL, RES2 ;
;
MOVFP
MULWF
(ARG1L * ARG2L)
MOVFP
ADDWF
MOVFP
ADDWFC
CLRF
ADDWFC
ARG1L, WREG
ARG2H
; ARG1L * ARG2H ->
;
PRODH:PRODL
PRODL, WREG ;
RES1, F
; Add cross
PRODH, WREG ;
products
RES2, F
;
WREG, F
;
RES3, F
;
;
DS30412C-page 50
MOVFP
MULWF
ARG1H, WREG ;
ARG2L
; ARG1H * ARG2L ->
;
PRODH:PRODL
MOVFP
ADDWF
MOVFP
ADDWFC
CLRF
ADDWFC
PRODL, WREG
RES1, F
PRODH, WREG
RES2, F
WREG, F
RES3, F
;
; Add cross
;
products
;
;
;
1996 Microchip Technology Inc.
PIC17C4X
Example 8-4 shows the sequence to do an 16 x 16
signed multiply. Equation 8-2 shows the algorithm that
used. The 32-bit result is stored in four registers
RES3:RES0. To account for the sign bits of the arguments, each argument pairs most significant bit (MSb)
is tested and the appropriate subtractions are done.
EXAMPLE 8-4:
EQUATION 8-2:
;
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
MOVFP
MULWF
MOVPF
MOVPF
MOVFP
MULWF
MOVPF
MOVPF
RES3:RES0
= (ARG1H * ARG2H * 2 )
+
(ARG1H * ARG2L * 28)
+
28)
+
(ARG1L * ARG2H *
(ARG1L * ARG2L)
ARG1L, WREG
ARG2L
; ARG1L * ARG2L ->
;
PRODH:PRODL
PRODH, RES1 ;
PRODL, RES0 ;
ARG1H, WREG
ARG2H
; ARG1H * ARG2H ->
;
PRODH:PRODL
PRODH, RES3 ;
PRODL, RES2 ;
;
= ARG1H:ARG1L * ARG2H:ARG2L
16
16 x 16 SIGNED MULTIPLY
ROUTINE
MOVFP
MULWF
MOVFP
ADDWF
MOVFP
ADDWFC
CLRF
ADDWFC
+
(-1 * ARG2H<7> * ARG1H:ARG1L * 216) +
(-1 * ARG1H<7> * ARG2H:ARG2L * 216)
ARG1L, WREG
ARG2H
; ARG1L * ARG2H ->
;
PRODH:PRODL
PRODL, WREG ;
RES1, F
; Add cross
PRODH, WREG ;
products
RES2, F
;
WREG, F
;
RES3, F
;
;
MOVFP
MULWF
ARG1H, WREG ;
ARG2L
; ARG1H * ARG2L ->
;
PRODH:PRODL
MOVFP
ADDWF
MOVFP
ADDWFC
CLRF
ADDWFC
PRODL, WREG
RES1, F
PRODH, WREG
RES2, F
WREG, F
RES3, F
;
; Add cross
;
products
;
;
;
BTFSS
GOTO
MOVFP
SUBWF
MOVFP
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, WREG
RES2
ARG1H, WREG
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
ARG1H, 7
CONT_CODE
ARG2L, WREG
RES2
ARG2H, WREG
RES3
; ARG1H:ARG1L neg?
; no, done
;
;
;
;
;
SIGN_ARG1
BTFSS
GOTO
MOVFP
SUBWF
MOVFP
SUBWFB
;
CONT_CODE
:
1996 Microchip Technology Inc.
DS30412C-page 51
PIC17C4X
NOTES:
DS30412C-page 52
1996 Microchip Technology Inc.
PIC17C4X
9.0
I/O PORTS
The PIC17C4X devices have five I/O ports, PORTA
through PORTE. PORTB through PORTE have a corresponding Data Direction Register (DDR), which is used
to configure the port pins as inputs or outputs. These
five ports are made up of 33 I/O pins. Some of these
ports pins are multiplexed with alternate functions.
PORTC, PORTD, and PORTE are multiplexed with the
system bus. These pins are configured as the system
bus when the device’s configuration bits are selected to
Microprocessor or Extended Microcontroller modes. In
the two other microcontroller modes, these pins are
general purpose I/O.
PORTA and PORTB are multiplexed with the peripheral
features of the device. These peripheral features are:
•
•
•
•
•
Timer modules
Capture module
PWM module
USART/SCI module
External Interrupt pin
PORTA is a 6-bit wide latch. PORTA does not have a
corresponding Data Direction Register (DDR).
Reading PORTA reads the status of the pins.
The RA1 pin is multiplexed with TMR0 clock input, and
RA4 and RA5 are multiplexed with the USART functions. The control of RA4 and RA5 as outputs is automatically configured by the USART module.
9.1.1
• PWM module
• USART/SCI module
When a pin is automatically configured as an output by
a peripheral module, the pins data direction (DDR) bit
is unknown. After disabling the peripheral module, the
user should re-initialize the DDR bit to the desired configuration.
The other peripheral modules (which require an input)
must have their data direction bit configured appropriately.
USING RA2, RA3 AS OUTPUTS
The RA2 and RA3 pins are open drain outputs. To use
the RA2 or the RA3 pin(s) as output(s), simply write to
the PORTA register the desired value. A '0' will cause
the pin to drive low, while a '1' will cause the pin to float
(hi-impedance). An external pull-up resistor should be
used to pull the pin high. Writes to PORTA will not affect
the other pins.
Note:
When some of these peripheral modules are turned on,
the port pin will automatically configure to the alternate
function. The modules that do this are:
Note:
PORTA Register
9.1
When using the RA2 or RA3 pin(s) as output(s), read-modify-write instructions (such
as BCF, BSF, BTG) on PORTA are not recommended.
Such operations read the port pins, do the
desired operation, and then write this value
to the data latch. This may inadvertently
cause the RA2 or RA3 pins to switch from
input to output (or vice-versa).
It is recommended to use a shadow register for PORTA. Do the bit operations on this
shadow register and then move it to
PORTA.
FIGURE 9-1:
RA0 AND RA1 BLOCK
DIAGRAM
A pin that is a peripheral input, can be configured as an output (DDRx<y> is cleared).
The peripheral events will be determined
by the action output on the port pin.
DATA BUS
RD_PORTA
(Q2)
Note: I/O pins have protection diodes to VDD and VSS.
1996 Microchip Technology Inc.
DS30412C-page 53
This document was created with FrameMaker 4 0 4
PIC17C4X
FIGURE 9-2:
RA2 AND RA3 BLOCK
DIAGRAM
FIGURE 9-3:
RA4 AND RA5 BLOCK
DIAGRAM
Data Bus
Serial port input signal
Data Bus
Q
Q
D
RD_PORTA
(Q2)
RD_PORTA
(Q2)
CK
Serial port output signals
WR_PORTA
(Q4)
OE = SPEN,SYNC,TXEN, CREN, SREN for RA4
Note: I/O pins have protection diodes to VSS.
OE = SPEN (SYNC+SYNC,CSRC) for RA5
Note: I/O pins have protection diodes to VDD and VSS.
TABLE 9-1:
Name
PORTA FUNCTIONS
Bit0
Buffer Type
Function
RA0/INT
bit0
ST
RA1/T0CKI
bit1
ST
RA2
bit2
ST
RA3
bit3
ST
RA4/RX/DT
bit4
ST
RA5/TX/CK
bit5
ST
RBPU
bit7
—
Legend: ST = Schmitt Trigger input.
TABLE 9-2:
Address
Input or external interrupt input.
Input or clock input to the TMR0 timer/counter, and/or an external interrupt input.
Input/Output. Output is open drain type.
Input/Output. Output is open drain type.
Input or USART Asynchronous Receive or USART Synchronous Data.
Input or USART Asynchronous Transmit or USART Synchronous Clock.
Control bit for PORTB weak pull-ups.
REGISTERS/BITS ASSOCIATED WITH PORTA
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note1)
10h, Bank 0
PORTA
RBPU
—
RA5
RA4
RA3
RA2
RA1/T0CKI
RA0/INT
0-xx xxxx
0-uu uuuu
05h, Unbanked
T0STA
INTEDG
T0SE
T0CS
PS3
PS2
PS1
PS0
—
0000 000-
0000 000-
13h, Bank 0
RCSTA
SPEN
RC9
SREN
CREN
—
FERR
OERR
RC9D
0000 -00x
0000 -00u
15h, Bank 0
TXSTA
CSRC
TX9
TXEN
SYNC
—
—
TRMT
TX9D
0000 --1x
0000 --1u
Legend: x = unknown, u = unchanged, - = unimplemented reads as '0'. Shaded cells are not used by PORTA.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
DS30412C-page 54
1996 Microchip Technology Inc.
PIC17C4X
9.2
PORTB and DDRB Registers
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the interrupt by:
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is DDRB. A '1' in DDRB
configures the corresponding port pin as an input. A '0'
in the DDRB register configures the corresponding port
pin as an output. Reading PORTB reads the status of
the pins, whereas writing to it will write to the port latch.
a)
b)
A mismatch condition will continue to set the RBIF bit.
Reading then writing PORTB will end the mismatch
condition, and allow the RBIF bit to be cleared.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
done by clearing the RBPU (PORTA<7>) bit. The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are enabled on
any reset.
This interrupt on mismatch feature, together with software configurable pull-ups on this port, allows easy
interface to a key pad and make it possible for wake-up
on key-depression. For an example, refer to AN552 in
the Embedded Control Handbook.
PORTB also has an interrupt on change feature. Only
pins configured as inputs can cause this interrupt to
occur (i.e. any RB7:RB0 pin configured as an output is
excluded from the interrupt on change comparison).
The input pins (of RB7:RB0) are compared with the
value in the PORTB data latch. The “mismatch” outputs
of RB7:RB0 are OR’ed together to generate the
PORTB Interrupt Flag RBIF (PIR<7>).
FIGURE 9-4:
Read-Write PORTB (such as; MOVPF PORTB,
PORTB). This will end mismatch condition.
Then, clear the RBIF bit.
The interrupt on change feature is recommended for
wake-up on operations where PORTB is only used for
the interrupt on change feature and key depression
operation.
BLOCK DIAGRAM OF RB<7:4> AND RB<1:0> PORT PINS
Peripheral Data in
RBPU (PORTA<7>)
Weak
Pull-Up
Match Signal
from other
port pins
RBIF
Port
Input Latch
Data Bus
RD_DDRB (Q2)
RD_PORTB (Q2)
D
OE
Q
WR_DDRB (Q4)
CK
D
Port
Data
Q
CK
WR_PORTB (Q4)
Note: I/O pins have protection diodes to VDD and VSS.
1996 Microchip Technology Inc.
DS30412C-page 55
PIC17C4X
FIGURE 9-5:
BLOCK DIAGRAM OF RB3 AND RB2 PORT PINS
Peripheral Data in
RBPU (PORTA<7>)
Weak
Pull-Up
Match Signal
from other
port pins
RBIF
Port
Input Latch
Data Bus
RD_DDRB (Q2)
RD_PORTB (Q2)
D
OE
Q
WR_DDRB (Q4)
CK
D
Port
Data
Q
CK
R
WR_PORTB (Q4)
PWM_output
PWM_select
Note: I/O pins have protection diodes to VDD and Vss.
DS30412C-page 56
1996 Microchip Technology Inc.
PIC17C4X
Example 9-1 shows the instruction sequence to initialize PORTB. The Bank Select Register (BSR) must be
selected to Bank 0 for the port to be initialized.
EXAMPLE 9-1:
MOVLB 0
CLRF
INITIALIZING PORTB
; Select Bank 0
PORTB
; Initialize PORTB by clearing
;
MOVLW 0xCF
MOVWF DDRB
TABLE 9-3:
output data latches
; Value used to initialize
;
data direction
;
Set RB<3:0> as inputs
;
RB<5:4> as outputs
;
RB<7:6> as inputs
PORTB FUNCTIONS
Name
Bit
Buffer Type
Function
RB0/CAP1
bit0
ST
RB1/CAP2
bit1
ST
RB2/PWM1
bit2
ST
RB3/PWM2
bit3
ST
RB4/TCLK12
bit4
ST
RB5/TCLK3
bit5
ST
RB6
bit6
ST
RB7
bit7
ST
Input/Output or the RB0/CAP1 input pin. Software programmable weak pullup and interrupt on change features.
Input/Output or the RB1/CAP2 input pin. Software programmable weak pullup and interrupt on change features.
Input/Output or the RB2/PWM1 output pin. Software programmable weak
pull-up and interrupt on change features.
Input/Output or the RB3/PWM2 output pin. Software programmable weak
pull-up and interrupt on change features.
Input/Output or the external clock input to Timer1 and Timer2. Software programmable weak pull-up and interrupt on change features.
Input/Output or the external clock input to Timer3. Software programmable
weak pull-up and interrupt on change features.
Input/Output pin. Software programmable weak pull-up and interrupt on
change features.
Input/Output pin. Software programmable weak pull-up and interrupt on
change features.
Legend: ST = Schmitt Trigger input.
TABLE 9-4:
REGISTERS/BITS ASSOCIATED WITH PORTB
Address
Name
Bit 7
Bit 6
Bit 5
12h, Bank 0
PORTB
PORTB data latch
11h, Bank 0
DDRB
Data direction register for PORTB
10h, Bank 0
PORTA
06h, Unbanked
CPUSTA
07h, Unbanked
INTSTA
16h, Bank 1
PIR
Bit 4
Bit 3
Bit 2
Bit 1
Value on all
other
resets
(Note1)
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
—
RA5
RA4
—
—
STKAV
GLINTD
TO
PD
PEIF
T0CKIF
T0IF
INTF
PEIE
T0CKIE
RBIF
TMR3IF
TMR2IF
TMR1IF
CA2IF
CA1IF
TXIF
RBIE
RBPU
Value on
Power-on
Reset
Bit 0
RA3
RA2
RA1/T0CKI
RA0/INT
0-xx xxxx 0-uu uuuu
—
—
--11 11-- --11 qq--
T0IE
INTE
0000 0000 0000 0000
RCIF
0000 0010 0000 0010
RCIE
0000 0000 0000 0000
17h, Bank 1
PIE
TMR3IE
TMR2IE
TMR1IE
CA2IE
CA1IE
TXIE
16h, Bank 3
TCON1
CA2ED1 CA2ED0
CA1ED1
CA1ED0
T16
TMR3CS
TMR2CS
TMR1CS 0000 0000 0000 0000
17h, Bank 3
TCON2
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON
TMR2ON
TMR1ON 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = Value depends on condition.
Shaded cells are not used by PORTB.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
1996 Microchip Technology Inc.
DS30412C-page 57
PIC17C4X
9.3
PORTC and DDRC Registers
Example 9-2 shows the instruction sequence to initialize PORTC. The Bank Select Register (BSR) must be
selected to Bank 1 for the port to be initialized.
PORTC is an 8-bit bi-directional port. The corresponding data direction register is DDRC. A '1' in DDRC configures the corresponding port pin as an input. A '0' in
the DDRC register configures the corresponding port
pin as an output. Reading PORTC reads the status of
the pins, whereas writing to it will write to the port latch.
PORTC is multiplexed with the system bus. When
operating as the system bus, PORTC is the low order
byte of the address/data bus (AD7:AD0). The timing for
the system bus is shown in the Electrical Characteristics section.
Note:
EXAMPLE 9-2:
MOVLB 1
CLRF
PORTC
MOVLW 0xCF
MOVWF DDRC
This port is configured as the system bus
when the device’s configuration bits are
selected to Microprocessor or Extended
Microcontroller modes. In the two other
microcontroller modes, this port is a general purpose I/O.
FIGURE 9-6:
INITIALIZING PORTC
;
;
;
;
;
;
;
;
;
;
Select Bank 1
Initialize PORTC data
latches before setting
the data direction
register
Value used to initialize
data direction
Set RC<3:0> as inputs
RC<5:4> as outputs
RC<7:6> as inputs
BLOCK DIAGRAM OF RC<7:0> PORT PINS
to D_Bus → IR
INSTRUCTION READ
Data Bus
TTL
Input
Buffer
RD_PORTC
0
1
Port
Data
D
Q
WR_PORTC
CK
D
Q
R
CK
S
RD_DDRC
WR_DDRC
EX_EN
DATA/ADDR_OUT
DRV_SYS
SYS BUS
Control
Note: I/O pins have protection diodes to VDD and Vss.
DS30412C-page 58
1996 Microchip Technology Inc.
PIC17C4X
TABLE 9-5:
PORTC FUNCTIONS
Name
Bit
Buffer Type
Function
RC0/AD0
bit0
TTL
Input/Output or system bus address/data pin.
RC1/AD1
bit1
TTL
Input/Output or system bus address/data pin.
RC2/AD2
bit2
TTL
Input/Output or system bus address/data pin.
RC3/AD3
bit3
TTL
Input/Output or system bus address/data pin.
RC4/AD4
bit4
TTL
Input/Output or system bus address/data pin.
RC5/AD5
bit5
TTL
Input/Output or system bus address/data pin.
RC6/AD6
bit6
TTL
Input/Output or system bus address/data pin.
RC7/AD7
bit7
TTL
Input/Output or system bus address/data pin.
Legend: TTL = TTL input.
TABLE 9-6:
REGISTERS/BITS ASSOCIATED WITH PORTC
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note1)
11h, Bank 1
PORTC
RC7/
AD7
RC6/
AD6
RC5/
AD5
RC4/
AD4
RC3/
AD3
RC2/
AD2
RC1/
AD1
RC0/
AD0
xxxx xxxx
uuuu uuuu
10h, Bank 1
DDRC
1111 1111
1111 1111
Data direction register for PORTC
Legend: x = unknown, u = unchanged.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
1996 Microchip Technology Inc.
DS30412C-page 59
PIC17C4X
9.4
PORTD and DDRD Registers
Example 9-3 shows the instruction sequence to initialize PORTD. The Bank Select Register (BSR) must be
selected to Bank 1 for the port to be initialized.
PORTD is an 8-bit bi-directional port. The corresponding data direction register is DDRD. A '1' in DDRD configures the corresponding port pin as an input. A '0' in
the DDRC register configures the corresponding port
pin as an output. Reading PORTD reads the status of
the pins, whereas writing to it will write to the port latch.
PORTD is multiplexed with the system bus. When
operating as the system bus, PORTD is the high order
byte of the address/data bus (AD15:AD8). The timing
for the system bus is shown in the Electrical Characteristics section.
Note:
EXAMPLE 9-3:
MOVLB 1
CLRF
PORTD
MOVLW 0xCF
MOVWF DDRD
This port is configured as the system bus
when the device’s configuration bits are
selected to Microprocessor or Extended
Microcontroller modes. In the two other
microcontroller modes, this port is a general purpose I/O.
FIGURE 9-7:
INITIALIZING PORTD
;
;
;
;
;
;
;
;
;
;
Select Bank 1
Initialize PORTD data
latches before setting
the data direction
register
Value used to initialize
data direction
Set RD<3:0> as inputs
RD<5:4> as outputs
RD<7:6> as inputs
PORTD BLOCK DIAGRAM (IN I/O PORT MODE)
to D_Bus → IR
INSTRUCTION READ
Data Bus
TTL
Input
Buffer
RD_PORTD
0
1
Port
Data
D
Q
WR_PORTD
CK
D
Q
R
CK
S
RD_DDRD
WR_DDRD
EX_EN
DATA/ADDR_OUT
DRV_SYS
SYS BUS
Control
Note: I/O pins have protection diodes to VDD and Vss.
DS30412C-page 60
1996 Microchip Technology Inc.
PIC17C4X
TABLE 9-7:
Name
PORTD FUNCTIONS
Bit
Buffer Type
RD0/AD8
bit0
RD1/AD9
bit1
RD2/AD10
bit2
RD3/AD11
bit3
RD4/AD12
bit4
RD5/AD13
bit5
RD6/AD14
bit6
RD7/AD15
bit7
Legend: TTL = TTL input.
TABLE 9-8:
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Function
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
Input/Output or system bus address/data pin.
REGISTERS/BITS ASSOCIATED WITH PORTD
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note1)
13h, Bank 1
PORTD
RD7/
AD15
RD6/
AD14
RD5/
AD13
RD4/
AD12
RD3/
AD11
RD2/
AD10
RD1/
AD9
RD0/
AD8
xxxx xxxx
uuuu uuuu
12h, Bank 1
DDRD
1111 1111
1111 1111
Data direction register for PORTD
Legend: x = unknown, u = unchanged.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
1996 Microchip Technology Inc.
DS30412C-page 61
PIC17C4X
9.4.1
PORTE AND DDRE REGISTER
Example 9-4 shows the instruction sequence to initialize PORTE. The Bank Select Register (BSR) must be
selected to Bank 1 for the port to be initialized.
PORTE is a 3-bit bi-directional port. The corresponding
data direction register is DDRE. A '1' in DDRE configures the corresponding port pin as an input. A '0' in the
DDRE register configures the corresponding port pin
as an output. Reading PORTE reads the status of the
pins, whereas writing to it will write to the port latch.
PORTE is multiplexed with the system bus. When
operating as the system bus, PORTE contains the control signals for the address/data bus (AD15:AD0).
These control signals are Address Latch Enable (ALE),
Output Enable (OE), and Write (WR). The control signals OE and WR are active low signals. The timing for
the system bus is shown in the Electrical Characteristics section.
Note:
EXAMPLE 9-4:
MOVLB 1
CLRF
PORTE
MOVLW 0x03
MOVWF DDRE
INITIALIZING PORTE
;
;
;
;
;
;
;
;
;
;
;
Select Bank 1
Initialize PORTE data
latches before setting
the data direction
register
Value used to initialize
data direction
Set RE<1:0> as inputs
RE<2> as outputs
RE<7:3> are always
read as '0'
This port is configured as the system bus
when the device’s configuration bits are
selected to Microprocessor or Extended
Microcontroller modes. In the two other
microcontroller modes, this port is a general purpose I/O.
FIGURE 9-8:
PORTE BLOCK DIAGRAM (IN I/O PORT MODE)
Data Bus
TTL
Input
Buffer
RD_PORTE
Port
0
Data
1
D
Q
WR_PORTE
CK
D
Q
R
CK
S
RD_DDRE
WR_DDRE
EX_EN
CNTL
DRV_SYS
SYS BUS
Control
Note: I/O pins have protection diodes to VDD and Vss.
DS30412C-page 62
1996 Microchip Technology Inc.
PIC17C4X
TABLE 9-9:
PORTE FUNCTIONS
Name
Bit
Buffer Type
RE0/ALE
bit0
RE1/OE
bit1
RE2/WR
bit2
Legend: TTL = TTL input.
TABLE 9-10:
Address
TTL
TTL
TTL
Function
Input/Output or system bus Address Latch Enable (ALE) control pin.
Input/Output or system bus Output Enable (OE) control pin.
Input/Output or system bus Write (WR) control pin.
REGISTERS/BITS ASSOCIATED WITH PORTE
Name
15h, Bank 1
PORTE
14h, Bank 1
DDRE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note1)
—
—
—
—
—
RE2/WR
RE1/OE
RE0/ALE
---- -xxx
---- -uuu
---- -111
---- -111
Data direction register for PORTE
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
1996 Microchip Technology Inc.
DS30412C-page 63
PIC17C4X
9.5
I/O Programming Considerations
9.5.1
BI-DIRECTIONAL I/O PORTS
EXAMPLE 9-5:
Any instruction which writes, operates internally as a
read followed by a write operation. For example, the
BCF and BSF instructions read the register into the
CPU, execute the bit operation, and write the result
back to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(e.g. bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and re-written to the data latch of this particular pin, overwriting the previous content. As long as the
pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the
content of the data latch may now be unknown.
; Initial PORT settings: PORTB<7:4> Inputs
;
PORTB<3:0> Outputs
; PORTB<7:6> have pull-ups and are
; not connected to other circuitry
;
;
PORT latch PORT pins
;
---------- --------;
BCF
PORTB, 7
01pp pppp
11pp pppp
BCF
PORTB, 6
10pp pppp
11pp pppp
;
BCF
DDRB, 7
10pp pppp
11pp pppp
BCF
DDRB, 6
10pp pppp
10pp pppp
;
; Note that the user may have expected the
; pin values to be 00pp pppp. The 2nd BCF
; caused RB7 to be latched as the pin value
; (High).
Note:
Reading a port reads the values of the port pins. Writing
to the port register writes the value to the port latch.
When using read-modify-write instructions (BCF, BSF,
BTG, etc.) on a port, the value of the port pins is read,
the desired operation is performed with this value, and
the value is then written to the port latch.
9.5.2
Example 9-5 shows the effect of two sequential
read-modify-write instructions on an I/O port.
FIGURE 9-9:
A pin actively outputting a Low or High
should not be driven from external devices
in order to change the level on this pin (i.e.
“wired-or”, “wired-and”). The resulting high
output currents may damage the device.
SUCCESSIVE OPERATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle (Figure 99). Therefore, care must be exercised if a write followed
by a read operation is carried out on the same I/O port.
The sequence of instructions should be such to allow
the pin voltage to stabilize (load dependent) before
executing the instruction that reads the values on that
I/O port. Otherwise, the previous state of that pin may
be read into the CPU rather than the “new” state. When
in doubt, it is better to separate these instructions with
a NOP or another instruction not accessing this I/O port.
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Instruction
fetched
READ MODIFY WRITE
INSTRUCTIONS ON AN
I/O PORT
PC + 1
MOVWF PORTB MOVF PORTB,W
write to
PORTB
PC + 2
PC + 3
NOP
NOP
RB7:RB0
Note:
This example shows a write to PORTB
followed by a read from PORTB.
Note that:
data setup time = (0.25 TCY - TPD)
where TCY = instruction cycle.
TPD = propagation delay
Therefore, at higher clock
frequencies, a write followed by a
read may be problematic.
Port pin
sampled here
Instruction
executed
DS30412C-page 64
MOVWF PORTB
write to
PORTB
MOVF PORTB,W
NOP
1996 Microchip Technology Inc.
PIC17C4X
10.0
OVERVIEW OF TIMER
RESOURCES
The PIC17C4X has four timer modules. Each module
can generate an interrupt to indicate that an event has
occurred. These timers are called:
• Timer0 - 16-bit timer with programmable 8-bit
prescaler
• Timer1 - 8-bit timer
• Timer2 - 8-bit timer
• Timer3 - 16-bit timer
For enhanced time-base functionality, two input Captures and two Pulse Width Modulation (PWM) outputs
are possible. The PWMs use the TMR1 and TMR2
resources and the input Captures use the TMR3
resource.
10.1
The Timer0 module also has a programmable prescaler option. The PS3:PS0 bits (T0STA<4:1>) determine the prescaler value. TMR0 can increment at the
following rates: 1:1, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64,
1:128, 1:256.
When TImer0’s clock source is an external clock, the
Timer0 module can be selected to increment on either
the rising or falling edge.
Synchronization of the external clock occurs after the
prescaler. When the prescaler is used, the external
clock frequency may be higher then the device’s frequency. The maximum frequency is 50 MHz, given the
high and low time requirements of the clock.
Timer2 Overview
The TMR2 module is an 8-bit timer/counter with an 8bit period register (PR2). When the TMR2 value rolls
over from the period match value to 0h, the TMR2IF
flag is set, and an interrupt will be generated when
enabled. In counter mode, the clock comes from the
RB4/TCLK12 pin, which can also be selected to be the
clock for the TMR1 module.
TMR1 can be concatenated to TMR2 to form a 16-bit
timer. The TMR2 register is the MSB and TMR1 is the
LSB. When in the 16-bit timer mode, there is a corresponding 16-bit period register (PR2:PR1). When the
TMR2:TMR1 value rolls over from the period match
value to 0h, the TMR1IF flag is set, and an interrupt
will be generated when enabled.
10.4
Timer0 Overview
The Timer0 module is a simple 16-bit overflow counter.
The clock source can be either the internal system
clock (Fosc/4) or an external clock.
10.2
10.3
Timer3 Overview
The TImer3 module is a 16-bit timer/counter with a 16bit period register. When the TMR3H:TMR3L value
rolls over to 0h, the TMR3IF bit is set and an interrupt
will be generated when enabled. In counter mode, the
clock comes from the RB5/TCLK3 pin.
When operating in the dual capture mode, the period
registers become the second 16-bit capture register.
10.5
Role of the Timer/Counters
The timer modules are general purpose, but have dedicated resources associated with them. TImer1 and
Timer2 are the time-bases for the two Pulse Width
Modulation (PWM) outputs, while Timer3 is the timebase for the two input captures.
Timer1 Overview
The TImer0 module is an 8-bit timer/counter with an 8bit period register (PR1). When the TMR1 value rolls
over from the period match value to 0h, the TMR1IF
flag is set, and an interrupt will be generated when
enabled. In counter mode, the clock comes from the
RB4/TCLK12 pin, which can also be selected to be the
clock for the Timer2 module.
TMR1 can be concatenated to TMR2 to form a 16-bit
timer. The TMR1 register is the LSB and TMR2 is the
MSB. When in the 16-bit timer mode, there is a corresponding 16-bit period register (PR2:PR1). When the
TMR2:TMR1 value rolls over from the period match
value to 0h, the TMR1IF flag is set, and an interrupt
will be generated when enabled.
1996 Microchip Technology Inc.
DS30412C-page 65
This document was created with FrameMaker 4 0 4
PIC17C4X
NOTES:
DS30412C-page 66
1996 Microchip Technology Inc.
PIC17C4X
11.0
TIMER0
The Timer0 module consists of a 16-bit timer/counter,
TMR0. The high byte is TMR0H and the low byte is
TMR0L. A software programmable 8-bit prescaler
makes an effective 24-bit overflow timer. The clock
source is also software programmable as either the
internal instruction clock or the RA1/T0CKI pin. The
control bits for this module are in register T0STA
(Figure 11-1).
FIGURE 11-1: T0STA REGISTER (ADDRESS: 05h, UNBANKED)
R/W - 0
INTEDG
bit7
R/W - 0
T0SE
R/W - 0
T0CS
R/W - 0
PS3
R/W - 0
PS2
R/W - 0
PS1
R/W - 0
PS0
U-0
—
bit0
R = Readable bit
W = Writable bit
U = Unimplemented,
Read as '0'
-n = Value at POR reset
bit 7:
INTEDG: RA0/INT Pin Interrupt Edge Select bit
This bit selects the edge upon which the interrupt is detected
1 = Rising edge of RA0/INT pin generates interrupt
0 = Falling edge of RA0/INT pin generates interrupt
bit 6:
T0SE: Timer0 Clock Input Edge Select bit
This bit selects the edge upon which TMR0 will increment
When T0CS = 0
1 = Rising edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt
0 = Falling edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt
When T0CS = 1
Don’t care
bit 5:
T0CS: Timer0 Clock Source Select bit
This bit selects the clock source for TMR0.
1 = Internal instruction clock cycle (TCY)
0 = T0CKI pin
bit 4-1: PS3:PS0: Timer0 Prescale Selection bits
These bits select the prescale value for TMR0.
PS3:PS0
Prescale Value
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
bit 0:
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Unimplemented: Read as '0'
1996 Microchip Technology Inc.
DS30412C-page 67
This document was created with FrameMaker 4 0 4
PIC17C4X
11.1
Timer0 Operation
11.2
When the T0CS (T0STA<5>) bit is set, TMR0 increments on the internal clock. When T0CS is clear, TMR0
increments on the external clock (RA1/T0CKI pin). The
external clock edge can be configured in software.
When the T0SE (T0STA<6>) bit is set, the timer will
increment on the rising edge of the RA1/T0CKI pin.
When T0SE is clear, the timer will increment on the falling edge of the RA1/T0CKI pin. The prescaler can be
programmed to introduce a prescale of 1:1 to 1:256.
The timer increments from 0000h to FFFFh and rolls
over to 0000h. On overflow, the TMR0 Interrupt Flag bit
(T0IF) is set. The TMR0 interrupt can be masked by
clearing the corresponding TMR0 Interrupt Enable bit
(T0IE). The TMR0 Interrupt Flag bit (T0IF) is automatically cleared when vectoring to the TMR0 interrupt vector.
Using Timer0 with External Clock
When the external clock input is used for Timer0, it is
synchronized with the internal phase clocks.
Figure 11-3 shows the synchronization of the external
clock. This synchronization is done after the prescaler.
The output of the prescaler (PSOUT) is sampled twice
in every instruction cycle to detect a rising or a falling
edge. The timing requirements for the external clock
are detailed in the electrical specification section for the
desired device.
11.2.1
DELAY FROM EXTERNAL CLOCK EDGE
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time TMR0 is actually
incremented. Figure 11-3 shows that this delay is
between 3TOSC and 7TOSC. Thus, for example, measuring the interval between two edges (e.g. period) will
be accurate within ±4TOSC (±121 ns @ 33 MHz).
FIGURE 11-2: TIMER0 MODULE BLOCK DIAGRAM
0
RA1/T0CKI
Fosc/4
1
Prescaler
(8 stage
async ripple
counter)
T0SE
(T0STA<6>)
Interrupt on overflow
sets T0IF
(INTSTA<5>)
Synchronization
TMR0H<8> TMR0L<8>
PSOUT
4
T0CS
(T0STA<5>)
PS3:PS0
(T0STA<4:1>)
Q2
Q4
FIGURE 11-3: TMR0 TIMING WITH EXTERNAL CLOCK (INCREMENT ON FALLING EDGE)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Prescaler
output
(PSOUT)
(note 3)
Sampled
Prescaler
output
(note 2)
(note 1)
Increment
TMR0
TMR0
T0
T0 + 1
T0 + 2
Note 1: The delay from the T0CKI edge to the TMR0 increment is 3Tosc to 7Tosc.
2: ↑ = PSOUT is sampled here.
3: The PSOUT high time is too short and is missed by the sampling circuit.
DS30412C-page 68
1996 Microchip Technology Inc.
PIC17C4X
Read/Write Consideration for TMR0
11.3
11.3.2
Since writing to either TMR0L or TMR0H will effectively
inhibit increment of that half of the TMR0 in the next
cycle (following write), but not inhibit increment of the
other half, the user must write to TMR0L first and
TMR0H next in two consecutive instructions, as shown
in Example 11-2. The interrupt must be disabled. Any
write to either TMR0L or TMR0H clears the prescaler.
Although TMR0 is a 16-bit timer/counter, only 8-bits at
a time can be read or written during a single instruction
cycle. Care must be taken during any read or write.
11.3.1
READING 16-BIT VALUE
The problem in reading the entire 16-bit value is that
after reading the low (or high) byte, its value may
change from FFh to 00h.
EXAMPLE 11-2: 16-BIT WRITE
Example 11-1 shows a 16-bit read. To ensure a proper
read, interrupts must be disabled during this routine.
BSF
MOVFP
MOVFP
BCF
EXAMPLE 11-1: 16-BIT READ
MOVPF
MOVPF
MOVFP
CPFSLT
RETURN
MOVPF
MOVPF
RETURN
TMR0L, TMPLO
TMR0H, TMPHI
TMPLO, WREG
TMR0L
TMR0L, TMPLO
TMR0H, TMPHI
WRITING A 16-BIT VALUE TO TMR0
;read low tmr0
;read high tmr0
;tmplo −> wreg
;tmr0l < wreg?
;no then return
;read low tmr0
;read high tmr0
;return
CPUSTA, GLINTD
RAM_L, TMR0L
RAM_H, TMR0H
CPUSTA, GLINTD
11.4
; Disable interrupt
;
;
; Done, enable interrupt
Prescaler Assignments
Timer0 has an 8-bit prescaler. The prescaler assignment is fully under software control; i.e., it can be
changed “on the fly” during program execution. When
changing the prescaler assignment, clearing the prescaler is recommended before changing assignment.
The value of the prescaler is “unknown,” and assigning
a value that is less then the present value makes it difficult to take this unknown time into account.
FIGURE 11-4: TMR0 TIMING: WRITE HIGH OR LOW BYTE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
PC
PC+1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC+2
PC+3
PC+4
ALE
TMR0L
T0
T0+1
New T0 (NT0)
New T0+1
Fetch
Instruction
executed
MOVFP W,TMR0L MOVFP TMR0L,W MOVFP TMR0L,W MOVFP TMR0L,W
Write to TMR0L
Read TMR0L
Read TMR0L
Read TMR0L
(Value = NT0)
(Value = NT0)
(Value = NT0 +1)
TMR0H
1996 Microchip Technology Inc.
DS30412C-page 69
PIC17C4X
FIGURE 11-5: TMR0 READ/WRITE IN TIMER MODE
Q1
Q2 Q3
Q4
Q1
Q2 Q3
Q4
Q1
Q2 Q3
Q4
Q1
Q2 Q3
Q4
Q1
Q2 Q3
Q4
Q1
Q2 Q3
Q4
AD15:AD0
ALE
WR_TRM0L
WR_TMR0H
RD_TMR0L
TMR0L
Instruction
fetched
Instruction
executed
12
12
TMR0H
FE
56
FF
MOVFP
MOVFP
DATAL,TMR0L DATAH,TMR0H
Write TMR0L Write TMR0H
Previously
Fetched
Instruction
AB
13
57
MOVPF
TMR0L,W
Read TMR0L
MOVFP
MOVFP
DATAL,TMR0L DATAH,TMR0H
Write TMR0L Write TMR0H
MOVPF
TMR0L,W
Read TMR0L
MOVPF
TMR0L,W
Read TMR0L
58
MOVPF
TMR0L,W
Read TMR0L
MOVPF
TMR0L,W
Read TMR0L
MOVPF
TMR0L,W
Read TMR0L
MOVPF
TMR0L,W
Read TMR0L
In this example, old TMR0 value is 12FEh, new value of AB56h is written.
TABLE 11-1:
REGISTERS/BITS ASSOCIATED WITH TIMER0
Address
Name
Bit 7
Bit 6
05h, Unbanked
T0STA
INTEDG
T0SE
06h, Unbanked
CPUSTA
—
—
07h, Unbanked
INTSTA
PEIF
T0CKIF
T0IF
0Bh, Unbanked
TMR0L
TMR0 register; low byte
0Ch, Unbanked
TMR0H
TMR0 register; high byte
Legend:
Note 1:
Bit 5
Value on
Power-on
Reset
Value on all
other resets
(Note1)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T0CS
PS3
PS2
PS1
PS0
—
0000 000-
0000 000-
STKAV
GLINTD
TO
PD
—
—
--11 11--
--11 qq--
INTF
PEIE
T0CKIE
T0IE
INTE
0000 0000
0000 0000
xxxx xxxx
uuuu uuuu
xxxx xxxx
uuuu uuuu
x = unknown, u = unchanged, - = unimplemented read as a '0', q - value depends on condition, Shaded cells are not used by Timer0.
Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
DS30412C-page 70
1996 Microchip Technology Inc.
PIC17C4X
12.0
TIMER1, TIMER2, TIMER3,
PWMS AND CAPTURES
The PIC17C4X has a wealth of timers and time-based
functions to ease the implementation of control applications. These time-base functions include two PWM outputs and two Capture inputs.
Timer1 and Timer2 are two 8-bit incrementing timers,
each with a period register (PR1 and PR2 respectively)
and separate overflow interrupt flags. Timer1 and
Timer2 can operate either as timers (increment on
internal Fosc/4 clock) or as counters (increment on falling edge of external clock on pin RB4/TCLK12). They
are also software configurable to operate as a single
16-bit timer. These timers are also used as the
time-base for the PWM (pulse width modulation) module.
Timer3 is a 16-bit timer/counter consisting of the
TMR3H and TMR3L registers. This timer has four other
associated registers. Two registers are used as a 16-bit
period register or a 16-bit Capture1 register
(PR3H/CA1H:PR3L/CA1L). The other two registers are
strictly the Capture2 registers (CA2H:CA2L). Timer3 is
the time-base for the two 16-bit captures.
TMR3 can be software configured to increment from
the internal system clock or from an external signal on
the RB5/TCLK3 pin.
Figure 12-1 and Figure 12-2 are the control registers
for the operation of Timer1, Timer2, and Timer3, as well
as PWM1, PWM2, Capture1, and Capture2.
FIGURE 12-1: TCON1 REGISTER (ADDRESS: 16h, BANK 3)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
CA2ED1 CA2ED0 CA1ED1 CA1ED0
T16
TMR3CS TMR2CS TMR1CS
bit7
bit0
R = Readable bit
W = Writable bit
-n = Value at POR reset
bit 7-6: CA2ED1:CA2ED0: Capture2 Mode Select bits
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
bit 5-4: CA1ED1:CA1ED0: Capture1 Mode Select bits
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
bit 3:
T16: Timer1:Timer2 Mode Select bit
1 = Timer1 and Timer2 form a 16-bit timer
0 = Timer1 and Timer2 are two 8-bit timers
bit 2:
TMR3CS: Timer3 Clock Source Select bit
1 = TMR3 increments off the falling edge of the RB5/TCLK3 pin
0 = TMR3 increments off the internal clock
bit 1:
TMR2CS: Timer2 Clock Source Select bit
1 = TMR2 increments off the falling edge of the RB4/TCLK12 pin
0 = TMR2 increments off the internal clock
bit 0:
TMR1CS: Timer1 Clock Source Select bit
1 = TMR1 increments off the falling edge of the RB4/TCLK12 pin
0 = TMR1 increments off the internal clock
1996 Microchip Technology Inc.
DS30412C-page 71
This document was created with FrameMaker 4 0 4
PIC17C4X
FIGURE 12-2: TCON2 REGISTER (ADDRESS: 17h, BANK 3)
R-0
R-0
R/W - 0
R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON
bit7
bit0
R = Readable bit
W = Writable bit
-n = Value at POR reset
bit 7:
CA2OVF: Capture2 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair (CA2H:CA2L)
before the next capture event occurred. The capture register retains the oldest unread capture value (last
capture before overflow). Subsequent capture events will not update the capture register with the Timer3
value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture2 register
0 = No overflow occurred on Capture2 register
bit 6:
CA1OVF: Capture1 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair
(PR3H/CA2H:PR3L/CA2L) before the next capture event occurred. The capture register retains the oldest unread capture value (last capture before overflow). Subsequent capture events will not update the
capture register with the TMR3 value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture1 register
0 = No overflow occurred on Capture1 register
bit 5:
PWM2ON: PWM2 On bit
1 = PWM2 is enabled (The RB3/PWM2 pin ignores the state of the DDRB<3> bit)
0 = PWM2 is disabled (The RB3/PWM2 pin uses the state of the DDRB<3> bit for data direction)
bit 4:
PWM1ON: PWM1 On bit
1 = PWM1 is enabled (The RB2/PWM1 pin ignores the state of the DDRB<2> bit)
0 = PWM1 is disabled (The RB2/PWM1 pin uses the state of the DDRB<2> bit for data direction)
bit 3:
CA1/PR3: CA1/PR3 Register Mode Select bit
1 = Enables Capture1 (PR3H/CA1H:PR3L/CA1L is the Capture1 register. Timer3 runs without
a period register)
0 = Enables the Period register (PR3H/CA1H:PR3L/CA1L is the Period register for Timer3)
bit 2:
TMR3ON: Timer3 On bit
1 = Starts Timer3
0 = Stops Timer3
bit 1:
TMR2ON: Timer2 On bit
This bit controls the incrementing of the Timer2 register. When Timer2:Timer1 form the 16-bit timer (T16
is set), TMR2ON must be set. This allows the MSB of the timer to increment.
1 = Starts Timer2 (Must be enabled if the T16 bit (TCON1<3>) is set)
0 = Stops Timer2
bit 0:
TMR1ON: Timer1 On bit
When T16 is set (in 16-bit Timer Mode)
1 = Starts 16-bit Timer2:Timer1
0 = Stops 16-bit Timer2:Timer1
When T16 is clear (in 8-bit Timer Mode)
1 = Starts 8-bit Timer1
0 = Stops 8-bit Timer1
DS30412C-page 72
1996 Microchip Technology Inc.
PIC17C4X
12.1
Timer1 and Timer2
12.1.1
TIMER1, TIMER2 IN 8-BIT MODE
12.1.1.1
Both Timer1 and Timer2 will operate in 8-bit mode
when the T16 bit is clear. These two timers can be independently configured to increment from the internal
instruction cycle clock or from an external clock source
on the RB4/TCLK12 pin. The timer clock source is configured by the TMRxCS bit (x = 1 for Timer1 or = 2 for
Timer2). When TMRxCS is clear, the clock source is
internal and increments once every instruction cycle
(Fosc/4). When TMRxCS is set, the clock source is the
RB4/TCLK12 pin, and the timer will increment on every
falling edge of the RB4/TCLK12 pin.
EXTERNAL CLOCK INPUT FOR TIMER1
OR TIMER2
When TMRxCS is set, the clock source is the
RB4/TCLK12 pin, and the timer will increment on every
falling edge on the RB4/TCLK12 pin. The TCLK12 input
is synchronized with internal phase clocks. This causes
a delay from the time a falling edge appears on TCLK12
to the time TMR1 or TMR2 is actually incremented. For
the external clock input timing requirements, see the
Electrical Specification section.
The timer increments from 00h until it equals the Period
register (PRx). It then resets to 00h at the next increment cycle. The timer interrupt flag is set when the timer
is reset. TMR1 and TMR2 have individual interrupt flag
bits. The TMR1 interrupt flag bit is latched into TMR1IF,
and the TMR2 interrupt flag bit is latched into TMR2IF.
Each timer also has a corresponding interrupt enable
bit (TMRxIE). The timer interrupt can be enabled by setting this bit and disabled by clearing this bit. For peripheral interrupts to be enabled, the Peripheral Interrupt
Enable bit must be enabled (PEIE is set) and global
interrupts must be enabled (GLINTD is cleared).
The timers can be turned on and off under software
control. When the Timerx On control bit (TMRxON) is
set, the timer increments from the clock source. When
TMRxON is cleared, the timer is turned off and cannot
cause the timer interrupt flag to be set.
FIGURE 12-3: TIMER1 AND TIMER2 IN TWO 8-BIT TIMER/COUNTER MODE
Fosc/4
0
TMR1
Reset
Set TMR1IF
(PIR<4>)
1
TMR1ON
(TCON2<0>)
TMR1CS
(TCON1<0>)
Comparator<8>
Comparator x8
Equal
PR1
RB4/TCLK12
1
TMR2
Fosc/4
TMR2ON
(TCON2<1>)
TMR2CS
(TCON1<1>)
1996 Microchip Technology Inc.
Reset
Set TMR2IF
(PIR<5>)
0
Comparator<8>
Comparator x8
Equal
PR2
DS30412C-page 73
PIC17C4X
12.1.2
12.1.2.1
TIMER1 & TIMER2 IN 16-BIT MODE
To select 16-bit mode, the T16 bit must be set. In this
mode TMR1 and TMR2 are concatenated to form a
16-bit timer (TMR2:TMR1). The 16-bit timer increments until it matches the 16-bit period register
(PR2:PR1). On the following timer clock, the timer
value is reset to 0h, and the TMR1IF bit is set.
EXTERNAL CLOCK INPUT FOR
TMR1:TMR2
When TMR1CS is set, the 16-bit TMR2:TMR1 increments on the falling edge of clock input TCLK12. The
input on the RB4/TCLK12 pin is sampled and synchronized by the internal phase clocks twice every instruction cycle. This causes a delay from the time a falling
edge appears on RB4/TCLK12 to the time
TMR2:TMR1 is actually incremented. For the external
clock input timing requirements, see the Electrical
Specification section.
When selecting the clock source for the16-bit timer, the
TMR1CS bit controls the entire 16-bit timer and
TMR2CS is a “don’t care.” When TMR1CS is clear, the
timer increments once every instruction cycle (Fosc/4).
When TMR1CS is set, the timer increments on every
falling edge of the RB4/TCLK12 pin. For the 16-bit timer
to increment, both TMR1ON and TMR2ON bits must be
set (Table 12-1).
TABLE 12-1:
TURNING ON 16-BIT TIMER
TMR2ON
TMR1ON
Result
1
1
16-bit timer
(TMR2:TMR1) ON
0
1
Only TMR1 increments
x
0
16-bit timer OFF
FIGURE 12-4: TMR1 AND TMR2 IN 16-BIT TIMER/COUNTER MODE
1
RB4/TCLK12
TMR2 x 8
Fosc/4
TMR1ON
(TCON2<0>)
Address
Set Interrupt TMR1IF
(PIR<4>)
Comparator<8>
Comparator
x16
TMR1CS
(TCON1<0>)
TABLE 12-2:
Reset
TMR1 x 8
0
PR2 x 8
Equal
PR1 x 8
SUMMARY OF TIMER1 AND TIMER2 REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CA2ED0
CA1ED1
CA1ED0
T16
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note1)
16h, Bank 3
TCON1
CA2ED1
TMR3CS TMR2CS TMR1CS 0000 0000
0000 0000
17h, Bank 3
TCON2
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000
0000 0000
10h, Bank 2
TMR1
Timer1 register
xxxx xxxx
uuuu uuuu
11h, Bank 2
TMR2
Timer2 register
xxxx xxxx
uuuu uuuu
0000 0010
16h, Bank 1
PIR
RBIF
TMR3IF
TMR2IF
TMR1IF
CA2IF
CA1IF
TXIF
RCIF
0000 0010
17h, Bank 1
PIE
RBIE
TMR3IE
TMR2IE
TMR1IE
CA2IE
CA1IE
TXIE
RCIE
0000 0000
0000 0000
PEIF
T0CKIF
T0IF
INTF
PEIE
T0CKIE
T0IE
INTE
0000 0000
0000 0000
—
—
STKAV
GLINTD
TO
PD
—
—
07h, Unbanked INTSTA
06h, Unbanked CPUSTA
--11 11--
--11 qq--
14h, Bank 2
PR1
Timer1 period register
xxxx xxxx
uuuu uuuu
15h, Bank 2
PR2
Timer2 period register
xxxx xxxx
uuuu uuuu
10h, Bank 3
PW1DCL
DC1
DC0
—
—
—
—
—
—
xx-- ----
uu-- ----
11h, Bank 3
PW2DCL
DC1
DC0
TM2PW2
—
—
—
—
—
xx0- ----
uu0- ----
12h, Bank 3
PW1DCH
DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx
uuuu uuuu
13h, Bank 3
PW2DCH
DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx
uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', q - value depends on condition,
shaded cells are not used by Timer1 or Timer2.
Note 1: Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset.
DS30412C-page 74
1996 Microchip Technology Inc.
PIC17C4X
12.1.3
FIGURE 12-5: SIMPLIFIED PWM BLOCK
DIAGRAM
USING PULSE WIDTH MODULATION
(PWM) OUTPUTS WITH TMR1 AND TMR2
Two high speed pulse width modulation (PWM) outputs
are provided. The PWM1 output uses Timer1 as its
time-base, while PWM2 may be software configured to
use either Timer1 or Timer2 as the time-base. The
PWM outputs are on the RB2/PWM1 and RB3/PWM2
pins.
(Slave)
Read
RCy/PWMx
Comparator
Each PWM output has a maximum resolution of
10-bits. At 10-bit resolution, the PWM output frequency
is 24.4 kHz (@ 25 MHz clock) and at 8-bit resolution the
PWM output frequency is 97.7 kHz. The duty cycle of
the output can vary from 0% to 100%.
Figure 12-5 shows a simplified block diagram of the
PWM module. The duty cycle register is double buffered for glitch free operation. Figure 12-6 shows how a
glitch could occur if the duty cycle registers were not
double buffered.
PWxDCH
PWxDCL<7:6>
Write
Duty Cycle registers
TMR2
R
(Note 1)
Comparator
PRy
S
Q
PWMxON
Clear Timer,
PWMx pin and
Latch D.C.
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
The user needs to set the PWM1ON bit (TCON2<4>)
to enable the PWM1 output. When the PWM1ON bit is
set, the RB2/PWM1 pin is configured as PWM1 output
and forced as an output irrespective of the data direction bit (DDRB<2>). When the PWM1ON bit is clear,
the pin behaves as a port pin and its direction is controlled by its data direction bit (DDRB<2>). Similarly,
the PWM2ON (TCON2<5>) bit controls the configuration of the RB3/PWM2 pin.
FIGURE 12-6: PWM OUTPUT
0
10
20
30
40
0
PWM
output
Timer
interrupt
Note
Write new
PWM value
Timer interrupt
new PWM value
transferred to slave
The dotted line shows PWM output if duty cycle registers were not double buffered.
If the new duty cycle is written after the timer has passed that value, then the PWM does
not reset at all during the current cycle causing a “glitch”.
In this example, PWM period = 50. Old duty cycle is 30. New duty cycle value is 10.
1996 Microchip Technology Inc.
DS30412C-page 75
PIC17C4X
12.1.3.1
PWM PERIODS
The period of the PWM1 output is determined by
Timer1 and its period register (PR1). The period of the
PWM2 output can be software configured to use either
Timer1 or Timer2 as the time-base. When TM2PW2 bit
(PW2DCL<5>) is clear, the time-base is determined by
TMR1 and PR1. When TM2PW2 is set, the time-base
is determined by Timer2 and PR2.
Running two different PWM outputs on two different
timers allows different PWM periods. Running both
PWMs from Timer1 allows the best use of resources by
freeing Timer2 to operate as an 8-bit timer. Timer1 and
Timer2 can not be used as a 16-bit timer if either PWM
is being used.
The PWM periods can be calculated as follows:
period of PWM1 =[(PR1) + 1] x 4TOSC
The duty cycle of PWMx is determined by the 10-bit
value DCx<9:0>. The upper 8-bits are from register
PWxDCH and the lower 2-bits are from PWxDCL<7:6>
(PWxDCH:PWxDCL<7:6>). Table 12-3 shows the
maximum PWM frequency (FPWM) given the value in
the period register.
The number of bits of resolution that the PWM can
achieve depends on the operation frequency of the
device as well as the PWM frequency (FPWM).
Maximum PWM resolution (bits) for a given PWM frequency:
=
OSC
)
( FFPWM
bits
log (2)
The PWMx duty cycle is as follows:
PWMx Duty Cycle =
where DCx represents
PWxDCH:PWxDCL.
(DCx) x TOSC
the
10-bit
value
TABLE 12-3:
PWM
Frequency
PRx Value
High
Resolution
Standard
Resolution
12.1.3.2
period of PWM2 =[(PR1) + 1] x 4TOSC or
[(PR2) + 1] x 4TOSC
log
The user should also avoid any "read-modify-write"
operations on the duty cycle registers, such as: ADDWF
PW1DCH. This may cause duty cycle outputs that are
unpredictable.
from
If DCx = 0, then the duty cycle is zero. If PRx =
PWxDCH, then the PWM output will be low for one to
four Q-clock (depending on the state of the
PWxDCL<7:6> bits). For a Duty Cycle to be 100%, the
PWxDCH value must be greater then the PRx value.
PWM FREQUENCY vs.
RESOLUTION AT 25 MHz
Frequency (kHz)
24.4
48.8
65.104
97.66
390.6
0xFF
10-bit
0x7F 0x5F
9-bit 8.5-bit
0x3F
8-bit
0x0F
6-bit
8-bit
7-bit
6-bit
4-bit
6.5-bit
PWM INTERRUPTS
The PWM module makes use of TMR1 or TMR2 interrupts. A timer interrupt is generated when TMR1 or
TMR2 equals its period register and is cleared to zero.
This interrupt also marks the beginning of a PWM
cycle. The user can write new duty cycle values before
the timer roll-over. The TMR1 interrupt is latched into
the TMR1IF bit and the TMR2 interrupt is latched into
the TMR2IF bit. These flags must be cleared in software.
12.1.3.3
EXTERNAL CLOCK SOURCE
The PWMs will operate regardless of the clock source
of the timer. The use of an external clock has ramifications that must be understood. Because the external
TCLK12 input is synchronized internally (sampled once
per instruction cycle), the time TCLK12 changes to the
time the timer increments will vary by as much as TCY
(one instruction cycle). This will cause jitter in the duty
cycle as well as the period of the PWM output.
This jitter will be ±TCY, unless the external clock is synchronized with the processor clock. Use of one of the
PWM outputs as the clock source to the TCLKx input,
will supply a synchronized clock.
In general, when using an external clock source for
PWM, its frequency should be much less than the
device frequency (Fosc).
The duty cycle registers for both PWM outputs are double buffered. When the user writes to these registers,
they are stored in master latches. When TMR1 (or
TMR2) overflows and a new PWM period begins, the
master latch values are transferred to the slave latches
and the PWMx pin is forced high.
Note:
For PW1DCH, PW1DCL, PW2DCH and
PW2DCL registers, a write operation
writes to the "master latches" while a read
operation reads the "slave latches". As a
result, the user may not read back what
was just written to the duty cycle registers.
DS30412C-page 76
1996 Microchip Technology Inc.
PIC17C4X
12.1.3.3.1 MAX RESOLUTION/FREQUENCY FOR
EXTERNAL CLOCK INPUT
Timer3 has two modes of operation, depending on the
CA1/PR3 bit (TCON2<3>). These modes are:
The use of an external clock for the PWM time-base
(Timer1 or Timer2) limits the PWM output to a maximum resolution of 8-bits. The PWxDCL<7:6> bits must
be kept cleared. Use of any other value will distort the
PWM output. All resolutions are supported when internal clock mode is selected. The maximum attainable
frequency is also lower. This is a result of the timing
requirements of an external clock input for a timer (see
the Electrical Specification section). The maximum
PWM frequency, when the timers clock source is the
RB4/TCLK12 pin, is shown in Table 12-3 (standard resolution mode).
• One capture and one period register mode
• Dual capture register mode
12.2
Each 16-bit capture register has an interrupt flag associated with it. The flag is set when a capture is made.
The capture module is truly part of the Timer3 block.
Figure 12-7 and Figure 12-8 show the block diagrams
for the two modes of operation.
The PIC17C4X has up to two 16-bit capture registers
that capture the 16-bit value of TMR3 when events are
detected on capture pins. There are two capture pins
(RB0/CAP1 and RB1/CAP2), one for each capture register. The capture pins are multiplexed with PORTB
pins. An event can be:
•
•
•
•
Timer3
Timer3 is a 16-bit timer consisting of the TMR3H and
TMR3L registers. TMR3H is the high byte of the timer
and TMR3L is the low byte. This timer has an associated 16-bit period register (PR3H/CA1H:PR3L/CA1L).
This period register can be software configured to be a
second 16-bit capture register.
a rising edge
a falling edge
every 4th rising edge
every 16th rising edge
When the TMR3CS bit (TCON1<2>) is clear, the timer
increments every instruction cycle (Fosc/4). When
TMR3CS is set, the timer increments on every falling
edge of the RB5/TCLK3 pin. In either mode, the
TMR3ON bit must be set for the timer to increment.
When TMR3ON is clear, the timer will not increment or
set the TMR3IF bit.
TABLE 12-4:
REGISTERS/BITS ASSOCIATED WITH PWM
Bit 7
Bit 6
Bit 5
Bit 4
Value on
Power-on
Reset
Value on all
other
resets
(Note1)
Address
Name
Bit 3
Bit 2
Bit 1
Bit 0
16h, Bank 3
TCON1
CA2ED1
CA2ED0
CA1ED1
CA1ED0
17h, Bank 3
TCON2
CA2OVF
CA1OVF
PWM2ON
PWM1ON
T16
TMR3CS
TMR2CS
TMR1CS
0000 0000
0000 0000
CA1/PR3 TMR3ON TMR2ON TMR1ON
0000 0000
0000 0000
10h, Bank 2
TMR1
Timer1 register
xxxx xxxx
uuuu uuuu
11h, Bank 2
TMR2
Timer2 register
xxxx xxxx
uuuu uuuu
16h, Bank 1
PIR
RBIF
TMR3IF
TMR2IF
TMR1IF
CA2IF
CA1IF
TXIF
RCIF
0000 0010
0000 0010
17h, Bank 1
PIE
RBIE
TMR3IE
TMR2IE
TMR1IE
CA2IE
CA1IE
TXIE
RCIE
0000 0000
0000 0000
PEIF
T0CKIF
T0IF
INTF
PEIE
T0CKIE
T0IE
INTE
0000 0000
0000 0000
07h, Unbanked INTSTA
06h, Unbanked CPUSTA
—
—
STKAV
GLINTD
TO
PD
—
—
--11 11--
--11 qq--
10h, Bank 3
PW1DCL
DC1
DC0
—
—
—
—
—
—
xx-- ----
uu-- ----
11h, Bank 3
PW2DCL
DC1
DC0
TM2PW2
—
—
—
—
—
xx0- ----
uu0- ----
12h, Bank 3
PW1DCH
DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx
uuuu uuuu
13h, Bank 3
PW2DCH
DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx
uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends on conditions,
shaded cells are not used by PWM.
1996 Microchip Technology Inc.
DS30412C-page 77
PIC17C4X
12.2.1
Capture pin RB1/CAP2 is a multiplexed pin. When used
as a port pin, Capture2 is not disabled. However, the
user can simply disable the Capture2 interrupt by clearing CA2IE. If RB1/CAP2 is used as an output pin, the
user can activate a capture by writing to the port pin.
This may be useful during development phase to emulate a capture interrupt.
ONE CAPTURE AND ONE PERIOD
REGISTER MODE
In this mode registers PR3H/CA1H and PR3L/CA1L
constitute a 16-bit period register. A block diagram is
shown in Figure 12-7. The timer increments until it
equals the period register and then resets to 0000h.
TMR3 Interrupt Flag bit (TMR3IF) is set at this point.
This interrupt can be disabled by clearing the TMR3
Interrupt Enable bit (TMR3IE). TMR3IF must be
cleared in software.
The input on capture pin RB1/CAP2 is synchronized
internally to internal phase clocks. This imposes certain
restrictions on the input waveform (see the Electrical
Specification section for timing).
This mode is selected if control bit CA1/PR3 is clear. In
this mode, the Capture1 register, consisting of high
byte (PR3H/CA1H) and low byte (PR3L/CA1L), is configured as the period control register for TMR3.
Capture1 is disabled in this mode, and the corresponding Interrupt bit CA1IF is never set. TMR3 increments
until it equals the value in the period register and then
resets to 0000h.
The Capture2 overflow status flag bit is double buffered. The master bit is set if one captured word is
already residing in the Capture2 register and another
“event” has occurred on the RB1/CA2 pin. The new
event will not transfer the Timer3 value to the capture
register, protecting the previous unread capture value.
When the user reads both the high and the low bytes (in
any order) of the Capture2 register, the master overflow
bit is transferred to the slave overflow bit (CA2OVF) and
then the master bit is reset. The user can then read
TCON2 to determine the value of CA2OVF.
Capture2 is active in this mode. The CA2ED1 and
CA2ED0 bits determine the event on which capture will
occur. The possible events are:
•
•
•
•
Capture on every falling edge
Capture on every rising edge
Capture every 4th rising edge
Capture every 16th rising edge
The recommended sequence to read capture registers
and capture overflow flag bits is shown in
Example 12-1.
EXAMPLE 12-1: SEQUENCE TO READ
CAPTURE REGISTERS
When a capture takes place, an interrupt flag is latched
into the CA2IF bit. This interrupt can be enabled by setting the corresponding mask bit CA2IE. The Peripheral
Interrupt Enable bit (PEIE) must be set and the Global
Interrupt Disable bit (GLINTD) must be cleared for the
interrupt to be acknowledged. The CA2IF interrupt flag
bit must be cleared in software.
MOVLB 3
MOVPF CA2L,LO_BYTE
;Select Bank 3
;Read Capture2 low
;byte, store in LO_BYTE
MOVPF CA2H,HI_BYTE
;Read Capture2 high
;byte, store in HI_BYTE
MOVPF TCON2,STAT_VAL ;Read TCON2 into file
;STAT_VAL
When the capture prescale select is changed, the prescaler is not reset and an event may be generated.
Therefore, the first capture after such a change will be
ambiguous. However, it sets the time-base for the next
capture. The prescaler is reset upon chip reset.
FIGURE 12-7: TIMER3 WITH ONE CAPTURE AND ONE PERIOD REGISTER BLOCK DIAGRAM
TMR3CS
(TCON1<2>)
PR3H/CA1H
PR3L/CA1L
Comparator x16
Comparator<8>
0
Fosc/4
TMR3H
1
Equal
Reset
TMR3L
TMR3ON
(TCON2<2>) Capture1 Enable
RB5/TCLK3
Edge select
prescaler select
RB1/CAP2
Set TMR3IF
(PIR<6>)
2
CA2H
CA2L
Set CA2IF
(PIR<3>)
CA2ED1: CA2ED0
(TCON1<7:6>)
DS30412C-page 78
1996 Microchip Technology Inc.
PIC17C4X
12.2.2
The Capture2 overflow status flag bit is double buffered. The master bit is set if one captured word is
already residing in the Capture2 register and another
“event” has occurred on the RB1/CA2 pin. The new
event will not transfer the TMR3 value to the capture
register which protects the previous unread capture
value. When the user reads both the high and the low
bytes (in any order) of the Capture2 register, the master
overflow bit is transferred to the slave overflow bit
(CA2OVF) and then the master bit is reset. The user
can then read TCON2 to determine the value of
CA2OVF.
DUAL CAPTURE REGISTER MODE
This mode is selected by setting CA1/PR3. A block diagram is shown in Figure 12-8. In this mode, TMR3 runs
without a period register and increments from 0000h to
FFFFh and rolls over to 0000h. The TMR3 interrupt
Flag (TMR3IF) is set on this roll over. The TMR3IF bit
must be cleared in software.
Registers PR3H/CA1H and PR3L/CA1L make a 16-bit
capture register (Capture1). It captures events on pin
RB0/CAP1. Capture mode is configured by the
CA1ED1 and CA1ED0 bits. Capture1 Interrupt Flag bit
(CA1IF) is set on the capture event. The corresponding
interrupt mask bit is CA1IE. The Capture1 Overflow
Status bit is CA1OVF.
The operation of the Capture1 feature is identical to
Capture2 (as described in Section 12.2.1).
FIGURE 12-8: TIMER3 WITH TWO CAPTURE REGISTERS BLOCK DIAGRAM
CA1ED1, CA1ED0
2
(TCON1<5:4>)
PR3H/CA1H
Edge Select
Prescaler Select
PR3L/CA1L
Set CA1IF
(PIR<2>)
Capture Enable
RB0/CAP1
Fosc/4
Set TMR3IF
(PIR<6>)
0
TMR3H
1
TMR3ON
(TCON2<2>)
TMR3CS
(TCON1<2>)
RB5/TCLK3
Capture Enable
Edge Select
Prescaler Select
RB1/CAP2
2
TABLE 12-5:
TMR3L
CA2H
Set CA2IF
(PIR<3>)
CA2L
CA2ED1, CA2ED0
(TCON1<7:6>)
REGISTERS ASSOCIATED WITH CAPTURE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CA1ED0
T16
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note1)
Address
Name
16h, Bank 3
TCON1
CA2ED1 CA2ED0
CA1ED1
17h, Bank 3
TCON2
CA2OVF CA1OVF
PWM2ON
12h, Bank 2
TMR3L
13h, Bank 2
TMR3H
16h, Bank 1
PIR
RBIF
TMR3IF
TMR2IF
TMR1IF
CA2IF
CA1IF
TXIF
RCIF
0000 0010
0000 0010
17h, Bank 1
PIE
RBIE
TMR3IE
TMR2IE
TMR1IE
CA2IE
CA1IE
TXIE
RCIE
0000 0000
0000 0000
07h, Unbanked INTSTA
PEIF
T0CKIF
T0IF
INTF
PEIE
T0CKIE
T0IE
INTE
0000 0000
0000 0000
06h, Unbanked CPUSTA
—
—
STKAV
GLINTD
TO
PD
—
—
--11 11--
--11 qq--
TMR3CS TMR2CS TMR1CS 0000 0000
0000 0000
PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000
0000 0000
TMR3 register; low byte
xxxx xxxx
uuuu uuuu
TMR3 register; high byte
xxxx xxxx
uuuu uuuu
16h, Bank 2
PR3L/CA1L
xxxx xxxx
uuuu uuuu
17h, Bank 2
PR3H/CA1H Timer3 period register, high byte/capture1 register, high byte
Timer3 period register, low byte/capture1 register, low byte
xxxx xxxx
uuuu uuuu
14h, Bank 3
CA2L
Capture2 low byte
xxxx xxxx
uuuu uuuu
15h, Bank 3
CA2H
Capture2 high byte
xxxx xxxx
uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition,
shaded cells are not used by Capture.
Note 1: Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset.
1996 Microchip Technology Inc.
DS30412C-page 79
PIC17C4X
12.2.3
EXAMPLE 12-2: WRITING TO TMR3
EXTERNAL CLOCK INPUT FOR TIMER3
BSF
MOVFP
MOVFP
BCF
When TMR3CS is set, the 16-bit TMR3 increments on
the falling edge of clock input TCLK3. The input on the
RB5/TCLK3 pin is sampled and synchronized by the
internal phase clocks twice every instruction cycle. This
causes a delay from the time a falling edge appears on
TCLK3 to the time TMR3 is actually incremented. For
the external clock input timing requirements, see the
Electrical Specification section. Figure 12-9 shows the
timing diagram when operating from an external clock.
12.2.4
CPUSTA,
RAM_L,
RAM_H,
CPUSTA,
GLINTD
TMR3L
TMR3H
GLINTD
;Disable interrupt
;
;
;Done,enable interrupt
EXAMPLE 12-3: READING FROM TMR3
MOVPF
MOVPF
MOVFP
CPFSLT
RETURN
MOVPF
MOVPF
RETURN
READING/WRITING TIMER3
Since Timer3 is a 16-bit timer and only 8-bits at a time
can be read or written, care should be taken when
reading or writing while the timer is running. The best
method to read or write the timer is to stop the timer,
perform any read or write operation, and then restart
Timer3 (using the TMR3ON bit). However, if it is necessary to keep Timer3 free-running, care must be taken.
For writing to the 16-bit TMR3, Example 12-2 may be
used. For reading the 16-bit TMR3, Example 12-3 may
be used. Interrupts must be disabled during this routine.
TMR3L,
TMR3H,
TMPLO,
TMR3L,
TMPLO
TMPHI
WREG
WREG
TMR3L, TMPLO
TMR3H, TMPHI
;read low tmr0
;read high tmr0
;tmplo −> wreg
;tmr0l < wreg?
;no then return
;read low tmr0
;read high tmr0
;return
FIGURE 12-9: TMR1, TMR2, AND TMR3 OPERATION IN EXTERNAL CLOCK MODE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TCLK12
TMR1, TMR2, or TMR3
34h
PR1, PR2, or PR3H:PR3L
'A9h'
35h
A8h
A9h
00h
'A9h'
WR_TMR
Read_TMR
TMRxIF
Instruction
executed
MOVWF
TMRx
MOVFP
TMRx,W
MOVFP
TMRx,W
Write to TMRx
Read TMRx
Read TMRx
Note 1: TCLK12 is sampled in Q2 and Q4.
2: ↓ indicates a sampling point.
3: The latency from TCLK12 ↓ to timer increment is between 2Tosc and 6Tosc.
DS30412C-page 80
1996 Microchip Technology Inc.
PIC17C4X
FIGURE 12-10: TMR1, TMR2, AND TMR3 OPERATION IN TIMER MODE
Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4
AD15:AD0
ALE
MOVF
MOVWF
MOVF
TMR1, W
TMR1
TMR1, W
Read
TMR1
Write TMR1 Read TMR1
Instruction
fetched
TMR1
04h
05h
MOVLB 3
03h
04h
BSF
TCON2, 0
Stop TMR1
05h
NOP
BCF
TCON2, 0
Start TMR1
06h
NOP
NOP
07h
NOP
08h
NOP
00h
PR1
TMR1ON
WR_TMR1
WR_TCON2
TMR1IF
RD_TMR1
TMR1
reads 03h
TABLE 12-6:
TMR1
reads 04h
SUMMARY OF TMR1, TMR2, AND TMR3 REGISTERS
Address
Name
16h, Bank 3
TCON1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CA2ED1
CA2ED0
CA1ED1
CA1ED0
T16
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note1)
TMR3CS TMR2CS TMR1CS 0000 0000
0000 0000
17h, Bank 3
TCON2
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000
0000 0000
10h, Bank 2
TMR1
Timer1 register
xxxx xxxx
uuuu uuuu
11h, Bank 2
TMR2
Timer2 register
xxxx xxxx
uuuu uuuu
12h, Bank 2
TMR3L
TMR3 register; low byte
xxxx xxxx
uuuu uuuu
13h, Bank 2
TMR3H
TMR3 register; high byte
xxxx xxxx
uuuu uuuu
16h, Bank 1
PIR
RBIF
TMR3IF
TMR2IF
TMR1IF
CA2IF
CA1IF
TXIF
RCIF
0000 0010
0000 0010
17h, Bank 1
PIE
RBIE
TMR3IE
TMR2IE
TMR1IE
CA2IE
CA1IE
TXIE
RCIE
0000 0000
0000 0000
07h, Unbanked INTSTA
PEIF
T0CKIF
T0IF
INTF
PEIE
T0CKIE
T0IE
INTE
0000 0000
0000 0000
06h, Unbanked CPUSTA
—
—
STKAV
GLINTD
TO
PD
—
—
--11 11--
--11 qq--
14h, Bank 2
PR1
Timer1 period register
xxxx xxxx
uuuu uuuu
15h, Bank 2
PR2
Timer2 period register
xxxx xxxx
uuuu uuuu
16h, Bank 2
PR3L/CA1L
Timer3 period/capture1 register; low byte
xxxx xxxx
uuuu uuuu
17h, Bank 2
PR3H/CA1H Timer3 period/capture1 register; high byte
xxxx xxxx
uuuu uuuu
10h, Bank 3
PW1DCL
DC1
DC0
—
—
—
—
—
—
xx-- ----
uu-- ----
11h, Bank 3
PW2DCL
DC1
DC0
TM2PW2
—
—
—
—
—
xx0- ----
uu0- ----
12h, Bank 3
PW1DCH
DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx
uuuu uuuu
13h, Bank 3
PW2DCH
DC9
DC8
DC7
DC6
DC5
DC4
DC3
DC2
xxxx xxxx
uuuu uuuu
14h, Bank 3
CA2L
Capture2 low byte
xxxx xxxx
uuuu uuuu
15h, Bank 3
CA2H
Capture2 high byte
xxxx xxxx
uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition,
shaded cells are not used by TMR1, TMR2 or TMR3.
Note 1: Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset.
1996 Microchip Technology Inc.
DS30412C-page 81
PIC17C4X
NOTES:
DS30412C-page 82
1996 Microchip Technology Inc.
PIC17C4X
13.0
UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
MODULE
The SPEN (RCSTA<7>) bit has to be set in order to
configure RA4 and RA5 as the Serial Communication
Interface.
The USART module will control the direction of the
RA4/RX/DT and RA5/TX/CK pins, depending on the
states of the USART configuration bits in the RCSTA
and TXSTA registers. The bits that control I/O direction
are:
The USART module is a serial I/O module. The USART
can be configured as a full duplex asynchronous system that can communicate with peripheral devices such
as CRT terminals and personal computers, or it can be
configured as a half duplex synchronous system that
can communicate with peripheral devices such as A/D
or D/A integrated circuits, Serial EEPROMs etc. The
USART can be configured in the following modes:
•
•
•
•
•
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
SPEN
TXEN
SREN
CREN
CSRC
The Transmit Status And Control Register is shown in
Figure 13-1, while the Receive Status And Control
Register is shown in Figure 13-2.
FIGURE 13-1: TXSTA REGISTER (ADDRESS: 15h, BANK 0)
R/W - 0 R/W - 0 R/W - 0 R/W - 0
CSRC
TX9
TXEN
SYNC
bit7
U-0
—
U-0
—
R-1
TRMT
bit 7:
CSRC: Clock Source Select bit
Synchronous mode:
1 = Master Mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
Asynchronous mode:
Don’t care
bit 6:
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5:
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
SREN/CREN overrides TXEN in SYNC mode
bit 4:
SYNC: USART mode Select bit
(Synchronous/Asynchronous)
1 = Synchronous mode
0 = Asynchronous mode
R/W - x
TX9D
bit0
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
bit 3-2: Unimplemented: Read as '0'
bit 1:
TRMT: Transmit Shift Register (TSR) Empty bit
1 = TSR empty
0 = TSR full
bit 0:
TX9D: 9th bit of transmit data (can be used to calculated the parity in software)
1996 Microchip Technology Inc.
DS30412C-page 83
This document was created with FrameMaker 4 0 4
PIC17C4X
FIGURE 13-2: RCSTA REGISTER (ADDRESS: 13h, BANK 0)
R/W - 0 R/W - 0 R/W - 0 R/W - 0
SPEN
RX9
SREN
CREN
bit7
U-0
—
R- 0
FERR
R-0
OERR
R-x
RX9D
bit 0
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
bit 7:
SPEN: Serial Port Enable bit
1 = Configures RA5/RX/DT and RA4/TX/CK pins as serial port pins
0 = Serial port disabled
bit 6:
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5:
SREN: Single Receive Enable bit
This bit enables the reception of a single byte. After receiving the byte, this bit is automatically cleared.
Synchronous mode:
1 = Enable reception
0 = Disable reception
Note: This bit is ignored in synchronous slave reception.
Asynchronous mode:
Don’t care
bit 4:
CREN: Continuous Receive Enable bit
This bit enables the continuous reception of serial data.
Asynchronous mode:
1 = Enable reception
0 = Disables reception
Synchronous mode:
1 = Enables continuous reception until CREN is cleared (CREN overrides SREN)
0 = Disables continuous reception
bit 3:
Unimplemented: Read as '0'
bit 2:
FERR: Framing Error bit
1 = Framing error (Updated by reading RCREG)
0 = No framing error
bit 1:
OERR: Overrun Error bit
1 = Overrun (Cleared by clearing CREN)
0 = No overrun error
bit 0:
RX9D: 9th bit of receive data (can be the software calculated parity bit)
DS30412C-page 84
1996 Microchip Technology Inc.
PIC17C4X
FIGURE 13-3: USART TRANSMIT
Sync
Master/Slave
÷4
BRG
Sync/Async
Sync/Async
CK/TX
Sync/Async
TSR
÷ 16
Clock
Start 0 1 • • • 7 8 Stop
DT
Load
TXREG
0 1 ••• 7
Data Bus
8
TXEN/
Write to TXREG
Bit Count
Interrupt
TXSTA<0>
TXIE
FIGURE 13-4: USART RECEIVE
OSC
BRG
Interrupt
÷4
Master/Slave
Sync
CK
Buffer
Logic
Sync/Async
Async/Sync
RCIE
enable
Bit Count
÷ 16
START
Detect
SPEN
RX
Buffer
Logic
Majority
Detect
Clock
Data
SREN/
CREN/
Start_Bit
RSR
MSb
LSb
Stop 8 7 • • • 1 0
FIFO
Logic
RX9
Async/Sync
RCREG
FERR
FERR
RX9D
RX9D
7 ••• 1 0
7 ••• 1 0
Clk
FIFO
Data Bus
1996 Microchip Technology Inc.
DS30412C-page 85
PIC17C4X
13.1
USART Baud Rate Generator (BRG)
Example 13-1 shows the calculation of the baud rate
error for the following conditions:
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. Table 13-1 shows
the formula for computation of the baud rate for different USART modes. These only apply when the USART
is in synchronous master mode (internal clock) and
asynchronous mode.
FOSC = 16 MHz
Desired Baud Rate = 9600
SYNC = 0
EXAMPLE 13-1: CALCULATING BAUD
RATE ERROR
Desired Baud rate=Fosc / (64 (X + 1))
Given the desired baud rate and Fosc, the nearest integer value between 0 and 255 can be calculated using
the formula below. The error in baud rate can then be
determined.
9600 =
16000000 /(64 (X + 1))
X
25.042 = 25
Calculated Baud Rate=16000000 / (64 (25 + 1))
=
TABLE 13-1:
SYNC
BAUD RATE FORMULA
Mode
Error =
Baud Rate
0
Asynchronous
Synchronous
1
X = value in SPBRG (0 to 255)
=
FOSC/(64(X+1))
FOSC/(4(X+1))
9615
(Calculated Baud Rate - Desired Baud Rate)
Desired Baud Rate
=
(9615 - 9600) / 9600
=
0.16%
Writing a new value to the SPBRG, causes the BRG
timer to be reset (or cleared), this ensures that the BRG
does not wait for a timer overflow before outputting the
new baud rate.
TABLE 13-2:
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note1)
13h, Bank 0
RCSTA
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00u
CSRC
TX9
TXEN
SYNC
—
—
TRMT
TX9D
15h, Bank 0
TXSTA
17h, Bank 0
SPBRG
Baud rate generator register
0000 --1x
0000 --1u
xxxx xxxx
uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used by the Baud Rate Generator.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30412C-page 86
1996 Microchip Technology Inc.
PIC17C4X
TABLE 13-3:
BAUD
RATE
(K)
BAUD RATES FOR SYNCHRONOUS MODE
FOSC = 33 MHz
FOSC = 25 MHz
FOSC = 20 MHz
FOSC = 16 MHz
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
0.3
NA
—
—
NA
—
—
NA
—
—
NA
—
—
1.2
NA
—
—
NA
—
—
NA
—
—
NA
—
—
2.4
NA
—
—
NA
—
—
NA
—
—
NA
—
—
9.6
NA
—
—
NA
—
—
NA
—
—
NA
—
—
19.2
NA
—
—
NA
—
—
19.53
+1.73
255
19.23
+0.16
207
76.8
77.10
+0.39
106
77.16
+0.47
80
76.92
+0.16
64
76.92
+0.16
51
96
95.93
-0.07
85
96.15
+0.16
64
96.15
+0.16
51
95.24
-0.79
41
300
294.64
-1.79
27
297.62
-0.79
20
294.1
-1.96
16
307.69
+2.56
12
500
485.29
-2.94
16
480.77
-3.85
12
500
0
9
500
0
7
HIGH
8250
—
0
6250
—
0
5000
—
0
4000
—
0
LOW
32.22
—
255
24.41
—
255
19.53
—
255
15.625
—
255
BAUD
RATE
(K)
FOSC = 10 MHz
FOSC = 7.159 MHz
FOSC = 5.068 MHz
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
0.3
NA
—
—
NA
—
—
NA
—
—
1.2
NA
—
—
NA
—
—
NA
—
—
2.4
NA
—
—
NA
—
—
NA
—
—
9.6
9.766
+1.73
255
9.622
+0.23
185
9.6
0
131
19.2
19.23
+0.16
129
19.24
+0.23
92
19.2
0
65
76.8
75.76
-1.36
32
77.82
+1.32
22
79.2
+3.13
15
96
96.15
+0.16
25
94.20
-1.88
18
97.48
+1.54
12
300
312.5
+4.17
7
298.3
-0.57
5
316.8
+5.60
3
500
500
0
4
NA
—
—
NA
—
—
HIGH
2500
—
0
1789.8
—
0
1267
—
0
LOW
9.766
—
255
6.991
—
255
4.950
—
255
BAUD
RATE
(K)
FOSC = 3.579 MHz
FOSC = 1 MHz
FOSC = 32.768 kHz
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
0.3
NA
—
—
NA
—
—
0.303
+1.14
26
1.2
NA
—
—
1.202
+0.16
207
1.170
-2.48
6
2.4
NA
—
—
2.404
+0.16
103
NA
—
—
—
9.6
9.622
+0.23
92
9.615
+0.16
25
NA
—
19.2
19.04
-0.83
46
19.24
+0.16
12
NA
—
—
76.8
74.57
-2.90
11
83.34
+8.51
2
NA
—
—
96
99.43
_3.57
8
NA
—
—
NA
—
—
300
298.3
-0.57
2
NA
—
—
NA
—
—
—
500
NA
—
—
NA
—
—
NA
—
HIGH
894.9
—
0
250
—
0
8.192
—
0
LOW
3.496
—
255
0.976
—
255
0.032
—
255
1996 Microchip Technology Inc.
DS30412C-page 87
PIC17C4X
TABLE 13-4:
BAUD
RATE
(K)
BAUD RATES FOR ASYNCHRONOUS MODE
FOSC = 33 MHz
FOSC = 25 MHz
FOSC = 20 MHz
FOSC = 16 MHz
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
0.3
NA
—
—
NA
—
—
NA
—
—
NA
—
—
1.2
NA
—
—
NA
—
—
1.221
+1.73
255
1.202
+0.16
207
KBAUD
%ERROR
SPBRG
value
(decimal)
2.4
2.398
-0.07
214
2.396
0.14
162
2.404
+0.16
129
2.404
+0.16
103
9.6
9.548
-0.54
53
9.53
-0.76
40
9.469
-1.36
32
9.615
+0.16
25
19.2
19.09
-0.54
26
19.53
+1.73
19
19.53
+1.73
15
19.23
+0.16
12
76.8
73.66
-4.09
6
78.13
+1.73
4
78.13
+1.73
3
83.33
+8.51
2
96
103.12
+7.42
4
97.65
+1.73
3
104.2
+8.51
2
NA
—
—
300
257.81
-14.06
1
390.63
+30.21
0
312.5
+4.17
0
NA
—
—
500
515.62
+3.13
0
NA
—
—
NA
—
—
NA
—
—
HIGH
515.62
—
0
—
—
0
312.5
—
0
250
—
0
LOW
2.014
—
255
1.53
—
255
1.221
—
255
0.977
—
255
BAUD
RATE
(K)
FOSC = 10 MHz
FOSC = 7.159 MHz
FOSC = 5.068 MHz
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
0.3
NA
—
—
NA
—
—
0.31
+3.13
255
1.2
1.202
+0.16
129
1.203
_0.23
92
1.2
0
65
2.4
2.404
+0.16
64
2.380
-0.83
46
2.4
0
32
9.6
9.766
+1.73
15
9.322
-2.90
11
9.9
-3.13
7
19.2
19.53
+1.73
7
18.64
-2.90
5
19.8
+3.13
3
76.8
78.13
+1.73
1
NA
—
—
79.2
+3.13
0
96
NA
—
—
NA
—
—
NA
—
—
300
NA
—
—
NA
—
—
NA
—
—
500
NA
—
—
NA
—
—
NA
—
—
HIGH
156.3
—
0
111.9
—
0
79.2
—
0
LOW
0.610
—
255
0.437
—
255
0.309
—
255
SPBRG
value
(decimal)
BAUD
RATE
(K)
FOSC = 3.579 MHz
FOSC = 1 MHz
FOSC = 32.768 kHz
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
SPBRG
value
(decimal)
KBAUD
%ERROR
0.3
0.301
+0.23
185
0.300
+0.16
51
0.256
-14.67
1
1.2
1.190
-0.83
46
1.202
+0.16
12
NA
—
—
2.4
2.432
+1.32
22
2.232
-6.99
6
NA
—
—
9.6
9.322
-2.90
5
NA
—
—
NA
—
—
19.2
18.64
-2.90
2
NA
—
—
NA
—
—
76.8
NA
—
—
NA
—
—
NA
—
—
96
NA
—
—
NA
—
—
NA
—
—
300
NA
—
—
NA
—
—
NA
—
—
500
NA
—
—
NA
—
—
NA
—
—
HIGH
55.93
—
0
15.63
—
0
0.512
—
0
LOW
0.218
—
255
0.061
—
255
0.002
—
255
DS30412C-page 88
1996 Microchip Technology Inc.
PIC17C4X
13.2
USART Asynchronous Mode
In this mode, the USART uses standard nonreturn-to-zero (NRZ) format (one start bit, eight or nine
data bits, and one stop bit). The most common data format is 8-bits. An on-chip dedicated 8-bit baud rate generator can be used to derive standard baud rate
frequencies from the oscillator. The USART’s transmitter and receiver are functionally independent but use
the same data format and baud rate. The baud rate
generator produces a clock x64 of the bit shift rate. Parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit).
Asynchronous mode is stopped during SLEEP.
The asynchronous mode is selected by clearing the
SYNC bit (TXSTA<4>).
The USART Asynchronous module consists of the following important elements:
•
•
•
•
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
13.2.1
USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in
Figure 13-3. The heart of the transmitter is the transmit
shift register (TSR). The shift register obtains its data
from the read/write transmit buffer (TXREG). TXREG is
loaded with data in software. The TSR is not loaded
until the stop bit has been transmitted from the previous
load. As soon as the stop bit is transmitted, the TSR is
loaded with new data from the TXREG (if available).
Once TXREG transfers the data to the TSR (occurs in
one TCY at the end of the current BRG cycle), the
TXREG is empty and an interrupt bit, TXIF (PIR<1>) is
set. This interrupt can be enabled or disabled by the
TXIE bit (PIE<1>). TXIF will be set regardless of TXIE
and cannot be reset in software. It will reset only when
new data is loaded into TXREG. While TXIF indicates
the status of the TXREG, the TRMT (TXSTA<1>) bit
shows the status of the TSR. TRMT is a read only bit
which is set when the TSR is empty. No interrupt logic
is tied to this bit, so the user has to poll this bit in order
to determine if the TSR is empty.
Note:
Transmission
is
enabled
by
setting
the
TXEN (TXSTA<5>) bit. The actual transmission will not
occur until TXREG has been loaded with data and the
baud rate generator (BRG) has produced a shift clock
(Figure 13-5). The transmission can also be started by
first loading TXREG and then setting TXEN. Normally
when transmission is first started, the TSR is empty, so
a transfer to TXREG will result in an immediate transfer
to TSR resulting in an empty TXREG. A back-to-back
transfer is thus possible (Figure 13-6). Clearing TXEN
during a transmission will cause the transmission to be
aborted. This will reset the transmitter and the
RA5/TX/CK pin will revert to hi-impedance.
In order to select 9-bit transmission, the
TX9 (TXSTA<6>) bit should be set and the ninth bit
should be written to TX9D (TXSTA<0>). The ninth bit
must be written before writing the 8-bit data to the
TXREG. This is because a data write to TXREG can
result in an immediate transfer of the data to the TSR
(if the TSR is empty).
Steps to follow when setting up an Asynchronous
Transmission:
1.
2.
3.
4.
5.
6.
7.
Initialize the SPBRG register for the appropriate
baud rate.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If interrupts are desired, then set the TXIE bit.
If 9-bit transmission is desired, then set the TX9
bit.
Load data to the TXREG register.
If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
Enable the transmission by setting TXEN (starts
transmission).
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN) allows transmission to start
sooner then doing these two events in the opposite
order.
Note:
To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the proper state when transmit is
re-enabled.
The TSR is not mapped in data memory,
so it is not available to the user.
1996 Microchip Technology Inc.
DS30412C-page 89
PIC17C4X
FIGURE 13-5: ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
Word 1
BRG output
(shift clock)
TX
(RA5/TX/CK pin)
Start Bit
Bit 0
Bit 1
Bit 7/8
Stop Bit
Word 1
TXIF bit
Word 1
Transmit Shift Reg
TRMT bit
FIGURE 13-6: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG output
(shift clock)
TX
(RA5/TX/CK pin)
Start Bit
Bit 0
TXIF bit
Bit 1
Word 1
Bit 7/8
Stop Bit
Start Bit
Bit 0
Word 2
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
TRMT bit
Note: This timing diagram shows two consecutive transmissions.
TABLE 13-5:
Address
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name
Bit 7
16h, Bank 1
PIR
RBIF
13h, Bank 0
RCSTA
SPEN
16h, Bank 0
TXREG
17h, Bank 1
PIE
RBIE
15h, Bank 0
TXSTA
CSRC
17h, Bank 0
SPBRG
Bit 6
Bit 5
Bit 4
TMR3IF TMR2IF TMR1IF
RX9
SREN
CREN
Bit 3
Bit 2
CA2IF
CA1IF
—
FERR
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note1)
TXIF
RCIF
0000 0010
0000 0010
OERR
RX9D
0000 -00x
0000 -00u
xxxx xxxx
uuuu uuuu
Bit 1
Serial port transmit register
TMR3IE TMR2IE TMR1IE
TX9
TXEN
Baud rate generator register
SYNC
CA2IE
CA1IE
TXIE
RCIE
0000 0000
0000 0000
—
—
TRMT
TX9D
0000 --1x
0000 --1u
xxxx xxxx
uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for asynchronous
transmission.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30412C-page 90
1996 Microchip Technology Inc.
PIC17C4X
13.2.2
USART ASYNCHRONOUS RECEIVER
Note:
The receiver block diagram is shown in Figure 13-4.
The data comes in the RA4/RX/DT pin and drives the
data recovery block. The data recovery block is actually
a high speed shifter operating at 16 times the baud
rate, whereas the main receive serial shifter operates
at the bit rate or at FOSC.
Once asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
13.2.3
The heart of the receiver is the receive (serial) shift register (RSR). After sampling the stop bit, the received
data in the RSR is transferred to the RCREG (if it is
empty). If the transfer is complete, the interrupt bit
RCIF (PIR<0>) is set. The actual interrupt can be
enabled/disabled by setting/clearing the RCIE
(PIE<0>) bit. RCIF is a read only bit which is cleared by
the hardware. It is cleared when RCREG has been
read and is empty. RCREG is a double buffered register; (i.e. it is a two deep FIFO). It is possible for two
bytes of data to be received and transferred to the
RCREG FIFO and a third byte begin shifting to the
RSR. On detection of the stop bit of the third byte, if the
RCREG is still full, then the overrun error bit,
OERR (RCSTA<1>) will be set. The word in the RSR
will be lost. RCREG can be read twice to retrieve the
two bytes in the FIFO. The OERR bit has to be cleared
in software which is done by resetting the receive logic
(CREN is set). If the OERR bit is set, transfers from the
RSR to RCREG are inhibited, so it is essential to clear
the OERR bit if it is set. The framing error bit
FERR (RCSTA<2>) is set if a stop bit is not detected.
The FERR and the 9th receive bit are buffered the same way as the receive data.
Reading the RCREG register will allow the
RX9D and FERR bits to be loaded with values for the next received Received data;
therefore, it is essential for the user to read
the RCSTA register before reading
RCREG in order not to lose the old FERR
and RX9D information.
SAMPLING
The data on the RA4/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RA4/RX/DT pin. The sampling is done on the seventh, eighth and ninth falling
edges of a x16 clock (Figure 11-3).
The x16 clock is a free running clock, and the three
sample points occur at a frequency of every 16 falling
edges.
FIGURE 13-7: RX PIN SAMPLING SCHEME
Start bit
RX
(RA4/RX/DT pin)
Bit0
Baud CLK for all but start bit
baud CLK
x16 CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
Samples
1996 Microchip Technology Inc.
DS30412C-page 91
PIC17C4X
7.
Steps to follow when setting up an Asynchronous
Reception:
1.
2.
3.
4.
5.
6.
Initialize the SPBRG register for the appropriate
baud rate.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If interrupts are desired, then set the RCIE bit.
If 9-bit reception is desired, then set the RX9 bit.
Enable the reception by setting the CREN bit.
The RCIF bit will be set when reception completes and an interrupt will be generated if the
RCIE bit was set.
Read RCSTA to get the ninth bit (if enabled) and
FERR bit to determine if any error occurred during reception.
Read RCREG for the 8-bit received data.
If an overrun error occurred, clear the error by
clearing the OERR bit.
8.
9.
Note:
To terminate a reception, either clear the
SREN and CREN bits, or the SPEN bit.
This will reset the receive logic, so that it
will be in the proper state when receive is
re-enabled.
FIGURE 13-8: ASYNCHRONOUS RECEPTION
Start
bit
RX
(RA4/RX/DT pin)
bit0
bit1
Start
bit
bit7/8 Stop
bit
bit0
bit7/8
Stop
bit
Start
bit
bit7/8
Rcv shift
reg
Rcv buffer reg
Word 3
Word 2
RCREG
Word 1
RCREG
Read Rcv
buffer reg
RCREG
Stop
bit
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 13-6:
Address
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
16h, Bank 1
PIR
RBIF
13h, Bank 0
RCSTA
SPEN
14h, Bank 0
RCREG
RX7
17h, Bank 1
PIE
RBIE
15h, Bank 0
TXSTA
CSRC
17h, Bank 0
SPBRG
Bit 6
Bit 5
Bit 4
TMR3IF TMR2IF TMR1IF
RX9
SREN
CREN
RX6
RX5
RX4
TMR3IE TMR2IE TMR1IE
TX9
TXEN
Baud rate generator register
SYNC
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note1)
Bit 3
Bit 2
CA2IF
CA1IF
TXIF
RCIF
0000 0010
0000 0010
—
FERR
OERR
RX9D
0000 -00x
0000 -00u
uuuu uuuu
RX3
RX2
RX1
RX0
xxxx xxxx
CA2IE
CA1IE
TXIE
RCIE
0000 0000
0000 0000
—
—
TRMT
TX9D
0000 --1x
0000 --1u
xxxx xxxx
uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for asynchronous reception.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30412C-page 92
1996 Microchip Technology Inc.
PIC17C4X
13.3
USART Synchronous Master Mode
In Master Synchronous mode, the data is transmitted in
a half-duplex manner; i.e. transmission and reception
do not occur at the same time: when transmitting data,
the reception is inhibited and vice versa. The synchronous mode is entered by setting the SYNC
(TXSTA<4>) bit. In addition, the SPEN (RCSTA<7>) bit
is set in order to configure the RA5 and RA4 I/O ports
to CK (clock) and DT (data) lines respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting the CSRC (TXSTA<7>) bit.
13.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 13-3. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer TXREG.
TXREG is loaded with data in software. The TSR is not
loaded until the last bit has been transmitted from the
previous load. As soon as the last bit is transmitted, the
TSR is loaded with new data from TXREG (if available).
Once TXREG transfers the data to the TSR (occurs in
one TCY at the end of the current BRG cycle), TXREG
is empty and the TXIF (PIR<1>) bit is set. This interrupt
can be enabled/disabled by setting/clearing the TXIE
bit (PIE<1>). TXIF will be set regardless of the state of
bit TXIE and cannot be cleared in software. It will reset
only when new data is loaded into TXREG. While TXIF
indicates the status of TXREG, TRMT (TXSTA<1>)
shows the status of the TSR. TRMT is a read only bit
which is set when the TSR is empty. No interrupt logic
is tied to this bit, so the user has to poll this bit in order
to determine if the TSR is empty. The TSR is not
mapped in data memory, so it is not available to the
user.
Transmission is enabled by setting the TXEN
(TXSTA<5>) bit. The actual transmission will not occur
until TXREG has been loaded with data. The first data
bit will be shifted out on the next available rising edge
of the clock on the RA5/TX/CK pin. Data out is stable
around the falling edge of the synchronous clock
(Figure 13-10). The transmission can also be started
by first loading TXREG and then setting TXEN. This is
advantageous when slow baud rates are selected,
since BRG is kept in RESET when the TXEN, CREN,
and SREN bits are clear. Setting the TXEN bit will start
the BRG, creating a shift clock immediately. Normally
when transmission is first started, the TSR is empty, so
a transfer to TXREG will result in an immediate transfer
to the TSR, resulting in an empty TXREG.
Back-to-back transfers are possible.
RA4/RX/DT pin reverts to a hi-impedance state (for a
reception). The RA5/TX/CK pin will remain an output if
the CSRC bit is set (internal clock). The transmitter
logic is not reset, although it is disconnected from the
pins. In order to reset the transmitter, the user has to
clear the TXEN bit. If the SREN bit is set (to interrupt an
ongoing transmission and receive a single word), then
after the single word is received, SREN will be cleared
and the serial port will revert back to transmitting, since
the TXEN bit is still set. The DT line will immediately
switch from hi-impedance receive mode to transmit
and start driving. To avoid this, TXEN should be
cleared.
In order to select 9-bit transmission, the
TX9 (TXSTA<6>) bit should be set and the ninth bit
should be written to TX9D (TXSTA<0>). The ninth bit
must be written before writing the 8-bit data to TXREG.
This is because a data write to TXREG can result in an
immediate transfer of the data to the TSR (if the TSR is
empty). If the TSR was empty and TXREG was written
before writing the “new” TX9D, the “present” value of
TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
Initialize the SPBRG register for the appropriate
baud rate (see Baud Rate Generator Section for
details).
Enable the synchronous master serial port by
setting the SYNC, SPEN, and CSRC bits.
Ensure that the CREN and SREN bits are clear
(these bits override transmission when set).
If interrupts are desired, then set the TXIE bit
(the GLINTD bit must be clear and the PEIE bit
must be set).
If 9-bit transmission is desired, then set the TX9
bit.
Start transmission by loading data to the
TXREG register.
If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
Enable the transmission by setting TXEN.
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN) allows transmission to start
sooner then doing these two events in the reverse
order.
Note:
To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the proper state when transmit is
re-enabled.
Clearing TXEN during a transmission will cause the
transmission to be aborted and will reset the transmitter. The RA4/RX/DT and RA5/TX/CK pins will revert to
hi-impedance. If either CREN or SREN are set during
a transmission, the transmission is aborted and the
1996 Microchip Technology Inc.
DS30412C-page 93
PIC17C4X
TABLE 13-7:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
TMR3IF TMR2IF TMR1IF
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note1)
16h, Bank 1
PIR
RBIF
CA2IF
CA1IF
TXIF
RCIF
0000 0010
0000 0010
13h, Bank 0
RCSTA
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00u
16h, Bank 0
TXREG
TX7
TX6
TX5
TX4
TX3
TX2
TX1
TX0
xxxx xxxx
uuuu uuuu
17h, Bank 1
PIE
RBIE
CA2IE
CA1IE
TXIE
RCIE
0000 0000
0000 0000
15h, Bank 0
TXSTA
—
—
TRMT
TX9D
0000 --1x
0000 --1u
17h, Bank 0
SPBRG
xxxx xxxx
uuuu uuuu
TMR3IE TMR2IE TMR1IE
CSRC
TX9
TXEN
SYNC
Baud rate generator register
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for synchronous
master transmission.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
FIGURE 13-9: SYNCHRONOUS TRANSMISSION
Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
DT
(RA4/RX/DT pin)
bit0
bit1
bit2
Q3 Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
bit7
Word 1
bit0
Word 2
CK
(RA5/TX/CK pin)
Write to
TXREG
Write word 1
Write word 2
TXIF
Interrupt flag
TRMT
TXEN
'1'
Note: Sync master mode; BRG = 0. Continuous transmission of two 8-bit words.
FIGURE 13-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
DT
(RA4/RX/DT pin)
bit0
bit1
bit2
bit6
bit7
CK
(RA5/TX/CK pin)
Write to
TXREG
TXIF bit
TRMT bit
DS30412C-page 94
1996 Microchip Technology Inc.
PIC17C4X
13.3.2
Steps to follow when setting up a Synchronous Master
Reception:
USART SYNCHRONOUS MASTER
RECEPTION
1.
Once synchronous mode is selected, reception is
enabled by setting either the SREN (RCSTA<5>) bit or
the CREN (RCSTA<4>) bit. Data is sampled on the
RA4/RX/DT pin on the falling edge of the clock. If
SREN is set, then only a single word is received. If
CREN is set, the reception is continuous until CREN is
reset. If both bits are set, then CREN takes precedence. After clocking the last bit, the received data in
the Receive Shift Register (RSR) is transferred to
RCREG (if it is empty). If the transfer is complete, the
interrupt bit RCIF (PIR<0>) is set. The actual interrupt
can be enabled/disabled by setting/clearing the
RCIE (PIE<0>) bit. RCIF is a read only bit which is
RESET by the hardware. In this case it is reset when
RCREG has been read and is empty. RCREG is a double buffered register; i.e., it is a two deep FIFO. It is
possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin
shifting into the RSR. On the clocking of the last bit of
the third byte, if RCREG is still full, then the overrun
error bit OERR (RCSTA<1>) is set. The word in the
RSR will be lost. RCREG can be read twice to retrieve
the two bytes in the FIFO. The OERR bit has to be
cleared in software. This is done by clearing the CREN
bit. If OERR bit is set, transfers from RSR to RCREG
are inhibited, so it is essential to clear OERR bit if it is
set. The 9th receive bit is buffered the same way as the
receive data. Reading the RCREG register will allow
the RX9D and FERR bits to be loaded with values for
the next received data; therefore, it is essential for the
user to read the RCSTA register before reading
RCREG in order not to lose the old FERR and RX9D
information.
2.
3.
4.
5.
6.
7.
8.
9.
Initialize the SPBRG register for the appropriate
baud rate. See Section 13.1 for details.
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
If interrupts are desired, then set the RCIE bit.
If 9-bit reception is desired, then set the RX9 bit.
If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
The RCIF bit will be set when reception is complete and an interrupt will be generated if the
RCIE bit was set.
Read RCSTA to get the ninth bit (if enabled) and
determine if any error occurred during reception.
Read the 8-bit received data by reading
RCREG.
If any error occurred, clear the error by clearing
CREN.
Note:
To terminate a reception, either clear the
SREN and CREN bits, or the SPEN bit.
This will reset the receive logic, so that it
will be in the proper state when receive is
re-enabled.
FIGURE 13-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
DT
(RA4/RX/DT pin)
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
CK
(RA5/TX/CK pin)
Write to the
SREN bit
SREN bit
CREN bit
'0'
'0'
RCIF bit
Read
RCREG
Note: Timing diagram demonstrates SYNC master mode with SREN = 1.
1996 Microchip Technology Inc.
DS30412C-page 95
PIC17C4X
TABLE 13-8:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note1)
16h, Bank 1
PIR
RBIF
CA2IF
CA1IF
TXIF
RCIF
0000 0010
0000 0010
13h, Bank 0
RCSTA
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00u
14h, Bank 0
RCREG
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
xxxx xxxx
uuuu uuuu
17h, Bank 1
PIE
RBIE
CA2IE
CA1IE
TXIE
RCIE
0000 0000
0000 0000
—
—
TRMT
TX9D
0000 --1x
0000 --1u
xxxx xxxx
uuuu uuuu
15h, Bank 0
TXSTA
17h, Bank 0
SPBRG
CSRC
TMR3IF TMR2IF TMR1IF
Bit 3
TMR3IE TMR2IE TMR1IE
TX9
TXEN
Baud rate generator register
SYNC
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for synchronous
master reception.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30412C-page 96
1996 Microchip Technology Inc.
PIC17C4X
13.4
USART Synchronous Slave Mode
The synchronous slave mode differs from the master
mode in the fact that the shift clock is supplied externally at the RA5/TX/CK pin (instead of being supplied
internally in the master mode). This allows the device
to transfer or receive data in the SLEEP mode. The
slave
mode
is
entered
by
clearing
the
CSRC (TXSTA<7>) bit.
13.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the sync master and slave modes are
identical except in the case of the SLEEP mode.
If two words are written to TXREG and then the SLEEP
instruction executes, the following will occur. The first
word will immediately transfer to the TSR and will transmit as the shift clock is supplied. The second word will
remain in TXREG. TXIF will not be set. When the first
word has been shifted out of TSR, TXREG will transfer
the second word to the TSR and the TXIF flag will now
be set. If TXIE is enabled, the interrupt will wake the
chip from SLEEP and if the global interrupt is enabled,
then the program will branch to interrupt vector
(0020h).
Steps to follow when setting up a Synchronous Slave
Transmission:
1.
2.
3.
4.
5.
6.
7.
Enable the synchronous slave serial port by setting the SYNC and SPEN bits and clearing the
CSRC bit.
Clear the CREN bit.
If interrupts are desired, then set the TXIE bit.
If 9-bit transmission is desired, then set the TX9
bit.
Start transmission by loading data to TXREG.
If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
Enable the transmission by setting TXEN.
13.4.2
USART SYNCHRONOUS SLAVE
RECEPTION
Operation of the synchronous master and slave modes
are identical except in the case of the SLEEP mode.
Also, SREN is a don't care in slave mode.
If receive is enabled (CREN) prior to the SLEEP instruction, then a word may be received during SLEEP. On
completely receiving the word, the RSR will transfer the
data to RCREG (setting RCIF) and if the RCIE bit is set,
the interrupt generated will wake the chip from SLEEP.
If the global interrupt is enabled, the program will
branch to the interrupt vector (0020h).
Steps to follow when setting up a Synchronous Slave
Reception:
1.
2.
3.
4.
5.
6.
7.
8.
Enable the synchronous master serial port by
setting the SYNC and SPEN bits and clearing
the CSRC bit.
If interrupts are desired, then set the RCIE bit.
If 9-bit reception is desired, then set the RX9 bit.
To enable reception, set the CREN bit.
The RCIF bit will be set when reception is complete and an interrupt will be generated if the
RCIE bit was set.
Read RCSTA to get the ninth bit (if enabled) and
determine if any error occurred during reception.
Read the 8-bit received data by reading
RCREG.
If any error occurred, clear the error by clearing
the CREN bit.
Note:
To abort reception, either clear the SPEN
bit, the SREN bit (when in single receive
mode), or the CREN bit (when in continuous receive mode). This will reset the
receive logic, so that it will be in the proper
state when receive is re-enabled.
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN) allows transmission to start
sooner then doing these two events in the reverse
order.
Note:
To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the proper state when transmit is
re-enabled.
1996 Microchip Technology Inc.
DS30412C-page 97
PIC17C4X
TABLE 13-9:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note1)
16h, Bank 1
PIR
RBIF
CA2IF
CA1IF
TXIF
RCIF
0000 0010
0000 0010
13h, Bank 0
RCSTA
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00u
16h, Bank 0
TXREG
TX7
TX6
TX5
TX4
TX3
TX2
TX1
TX0
xxxx xxxx
uuuu uuuu
17h, Bank 1
PIE
RBIE
CA2IE
CA1IE
TXIE
RCIE
0000 0000
0000 0000
15h, Bank 0
TXSTA
—
—
TRMT
TX9D
0000 --1x
0000 --1u
17h, Bank 0
SPBRG
xxxx xxxx
uuuu uuuu
CSRC
TMR3IF TMR2IF TMR1IF
Bit 3
TMR3IE TMR2IE TMR1IE
TX9
TXEN
SYNC
Baud rate generator register
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for synchronous
slave transmission.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
TABLE 13-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note1)
16h, Bank1
PIR
RBIF
CA2IF
CA1IF
TXIF
RCIF
0000 0010
0000 0010
13h, Bank0
RCSTA
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00u
14h, Bank0
RCREG
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
xxxx xxxx
uuuu uuuu
17h, Bank1
PIE
RBIE
CA2IE
CA1IE
TXIE
RCIE
0000 0000
0000 0000
—
—
TRMT
TX9D
0000 --1x
0000 --1u
xxxx xxxx
uuuu uuuu
15h, Bank 0
TXSTA
17h, Bank0
SPBRG
CSRC
TMR3IF TMR2IF TMR1IF
Bit 3
TMR3IE TMR2IE TMR1IE
TX9
TXEN
Baud rate generator register
SYNC
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for synchronous
slave reception.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30412C-page 98
1996 Microchip Technology Inc.
PIC17C4X
14.0
SPECIAL FEATURES OF THE
CPU
The PIC17CXX has a Watchdog Timer which can be
shut off only through EPROM bits. It runs off its own RC
oscillator for added reliability. There are two timers that
offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in
RESET until the crystal oscillator is stable. The other is
the Power-up Timer (PWRT), which provides a fixed
delay of 96 ms (nominal) on power-up only, designed to
keep the part in RESET while the power supply stabilizes. With these two timers on-chip, most applications
need no external reset circuitry.
What sets a microcontroller apart from other processors are special circuits to deal with the needs of real
time applications. The PIC17CXX family has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external components, provide power saving operating modes and offer
code protection. These are:
• OSC selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code protection
The SLEEP mode is designed to offer a very low current power-down mode. The user can wake from
SLEEP through external reset, Watchdog Timer Reset
or through an interrupt. Several oscillator options are
also made available to allow the part to fit the application. The RC oscillator option saves system cost while
the LF crystal option saves power. Configuration bits
are used to select various options. This configuration
word has the format shown in Figure 14-1.
FIGURE 14-1: CONFIGURATION WORD
R/P - 1
PM2 (1)
bit15-7
U-x
—
U-x
—
U-x
—
bit15-7
R/P - 1
PM1
U-x
—
U-x
—
U-x
—
U-x
—
U-x
—
R/P - 1 R/P - 1 R/P - 1 R/P - 1
PM0 WDTPS1 WDTPS0 FOSC1
U-x
—
bit0
R/P - 1
FOSC0
bit0
R = Readable bit
P = Programmable bit
U = Unimplemented
- n = Value for Erased Device
(x = unknown)
bit 15-9: Unimplemented: Read as a '1'
bit 15,6,4:PM2, PM1, PM0, Processor Mode Select bits
111 = Microprocessor Mode
110 = Microcontroller mode
101 = Extended microcontroller mode
000 = Code protected microcontroller mode
bit 7, 5: Unimplemented: Read as a '0'
bit 3-2: WDTPS1:WDTPS0, WDT Postscaler Select bits
11 = WDT enabled, postscaler = 1
10 = WDT enabled, postscaler = 256
01 = WDT enabled, postscaler = 64
00 = WDT disabled, 16-bit overflow timer
bit 1-0: FOSC1:FOSC0, Oscillator Select bits
11 = EC oscillator
10 = XT oscillator
01 = RC oscillator
00 = LF oscillator
Note 1: This bit does not exist on the PIC17C42. Reading this bit will return an unknown value (x).
1996 Microchip Technology Inc.
DS30412C-page 99
This document was created with FrameMaker 4 0 4
PIC17C4X
14.1
Configuration Bits
The PIC17CXX has up to seven configuration locations
(Table 14-1). These locations can be programmed
(read as '0') or left unprogrammed (read as '1') to select
various device configurations. Any write to a configuration location, regardless of the data, will program that
configuration bit. A TABLWT instruction is required to
write to program memory locations. The configuration
bits can be read by using the TABLRD instructions.
Reading any configuration location between FE00h
and FE07h will read the low byte of the configuration
word (Figure 14-1) into the TABLATL register. The TABLATH register will be FFh. Reading a configuration
location between FE08h and FE0Fh will read the high
byte of the configuration word into the TABLATL register. The TABLATH register will be FFh.
Addresses FE00h thorough FE0Fh are only in the program memory space for microcontroller and code protected microcontroller modes. A device programmer
will be able to read the configuration word in any processor mode. See programming specifications for more
detail.
TABLE 14-1:
CONFIGURATION
LOCATIONS
Bit
Address
FOSC0
FE00h
FOSC1
FE01h
WDTPS0
FE02h
WDTPS1
FE03h
PM0
FE04h
PM1
FE06h
(1)
PM2
FE0Fh (1)
Note 1: This location does not exist on the
PIC17C42.
14.2
Oscillator Configurations
14.2.1
OSCILLATOR TYPES
The PIC17CXX can be operated in four different oscillator modes. The user can program two configuration
bits (FOSC1:FOSC0) to select one of these four
modes:
•
•
•
•
LF:
XT:
EC:
RC:
14.2.2
Low Power Crystal
Crystal/Resonator
External Clock Input
Resistor/Capacitor
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
In XT or LF modes, a crystal or ceramic resonator is
connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 14-2). The
PIC17CXX Oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers specifications.
For frequencies above 20 MHz, it is common for the
crystal to be an overtone mode crystal. Use of overtone
mode crystals require a tank circuit to attenuate the
gain at the fundamental frequency. Figure 14-3 shows
an example of this.
FIGURE 14-2: CRYSTAL OR CERAMIC
RESONATOR OPERATION
(XT OR LF OSC
CONFIGURATION)
OSC1
C1
XTAL
RF
SLEEP
OSC2
Note1
To internal
logic
C2
Note:
When programming the desired configuration locations, they must be programmed in
ascending order. Starting with address
FE00h.
PIC17CXX
See Table 14-2 and Table 14-3 for recommended
values of C1 and C2.
Note 1: A series resistor may be required for AT strip
cut crystals.
DS30412C-page 100
1996 Microchip Technology Inc.
PIC17C4X
FIGURE 14-3: CRYSTAL OPERATION,
OVERTONE CRYSTALS (XT
OSC CONFIGURATION)
C1
OSC1
TABLE 14-3:
Osc
Type
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
Freq
C1
C2
32 kHz(1) 100-150 pF
100-150 pF
1 MHz
10-33 pF
10-33 pF
2 MHz
10-33 pF
10-33 pF
XT
2 MHz
47-100 pF
47-100 pF
4 MHz
15-68 pF
15-68 pF
8 MHz (2)
15-47 pF
15-47 pF
TBD
TBD
16 MHz
15-47 pF
15-47 pF
25 MHz
0 (3)
0 (3)
32 MHz (3)
Higher capacitance increases the stability of the
oscillator but also increases the start-up time and the
oscillator current. These values are for design guidance only. RS may be required in XT mode to avoid
overdriving the crystals with low drive level specification. Since each crystal has its own characteristics,
the user should consult the crystal manufacturer for
appropriate values for external components.
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is recommended.
2: RS of 330Ω is required for a capacitor combination of 15/15 pF.
LF
SLEEP
C2
OSC2
PIC17C42
0.1 µF
To filter the fundamental frequency
1 =
(2πf)2
LC2
Where f = tank circuit resonant frequency. This should be
midway between the fundamental and the 3rd overtone
frequencies of the crystal.
TABLE 14-2:
Oscillator
Type
CAPACITOR SELECTION
FOR CERAMIC
RESONATORS
Resonator
Frequency
Capacitor Range
C1 = C2
LF
455 kHz
15 - 68 pF
2.0 MHz
10 - 33 pF
XT
4.0 MHz
22 - 68 pF
8.0 MHz
33 - 100 pF
16.0 MHz
33 - 100 pF
Higher capacitance increases the stability of the
oscillator but also increases the start-up time. These
values are for design guidance only. Since each resonator has its own characteristics, the user should
consult the resonator manufacturer for appropriate
values of external components.
Resonators Used:
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
Panasonic EFO-A455K04B
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
Murata Erie CSA16.00MX
± 0.3%
± 0.5%
± 0.5%
± 0.5%
± 0.5%
Resonators used did not have built-in capacitors.
3: Only the capacitance of the board was present.
Crystals Used:
32.768 kHz
1.0 MHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
25 MHz
32 MHz
14.2.3
Epson C-001R32.768K-A
ECS-10-13-1
ECS-20-20-1
ECS-40-20-1
ECS ECS-80-S-4
ECS-80-18-1
ECS-160-20-1
CTS CTS25M
CRYSTEK HF-2
± 20 PPM
± 50 PPM
± 50 PPM
± 50 PPM
± 50 PPM
TBD
± 50 PPM
± 50 PPM
EXTERNAL CLOCK OSCILLATOR
In the EC oscillator mode, the OSC1 input can be
driven by CMOS drivers. In this mode, the
OSC1/CLKIN pin is hi-impedance and the OSC2/CLKOUT pin is the CLKOUT output (4 TOSC).
FIGURE 14-4: EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
Clock from
ext. system
CLKOUT
(FOSC/4)
1996 Microchip Technology Inc.
OSC1
PIC17CXX
OSC2
DS30412C-page 101
PIC17C4X
14.2.4
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and
better stability. A well-designed crystal oscillator will
provide good performance with TTL gates. Two types of
crystal oscillator circuits can be used: one with series
resonance, or one with parallel resonance.
Figure 14-5 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 kΩ resistor provides the
negative feedback for stability. The 10 kΩ potentiometer
biases the 74AS04 in the linear region. This could be
used for external oscillator designs.
FIGURE 14-5: EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
4.7k
PIC17CXX
OSC1
74AS04
RC OSCILLATOR
For timing insensitive applications, the RC device
option offers additional cost savings. RC oscillator frequency is a function of the supply voltage, the resistor
(Rext) and capacitor (Cext) values, and the operating
temperature. In addition to this, oscillator frequency will
vary from unit to unit due to normal process parameter
variation. Furthermore, the difference in lead frame
capacitance between package types will also affect
oscillation frequency, especially for low Cext values.
The user also needs to take into account variation due
to tolerance of external R and C components used.
Figure 14-6 shows how the R/C combination is connected to the PIC17CXX. For Rext values below 2.2 kΩ,
the oscillator operation may become unstable, or stop
completely. For very high Rext values (e.g. 1 MΩ), the
oscillator becomes sensitive to noise, humidity and
leakage. Thus, we recommend to keep Rext between 3
kΩ and 100 kΩ.
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With little
or no external capacitance, oscillation frequency can
vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package
lead frame capacitance.
See Section 18.0 for RC frequency variation from part
to part due to normal process variation. The variation
is larger for larger R (since leakage current variation will
affect RC frequency more for large R) and for smaller C
(since variation of input capacitance will affect RC frequency more).
10k
XTAL
10k
20 pF
14.2.5
20 pF
Figure 14-6 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a
180-degree phase shift in a series resonant oscillator
circuit. The 330 kΩ resistors provide the negative feedback to bias the inverters in their linear region.
FIGURE 14-6: EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
See Section 18.0 for variation of oscillator frequency
due to VDD for given Rext/Cext values as well as frequency variation due to operating temperature for given
R, C, and VDD values.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (see Figure 3-2 for
waveform).
FIGURE 14-7: RC OSCILLATOR MODE
VDD
Rext
OSC1
330 kΩ
330 kΩ
74AS04
74AS04
To Other
Devices
74AS04
PIC17CXX
Cext
PIC17CXX
OSC1
0.1 µF
Internal
clock
VSS
OSC2/CLKOUT
Fosc/4
XTAL
DS30412C-page 102
1996 Microchip Technology Inc.
PIC17C4X
14.3
Watchdog Timer (WDT)
The Watchdog Timer’s function is to recover from software malfunction. The WDT uses an internal free running on-chip RC oscillator for its clock source. This
does not require any external components. This RC
oscillator is separate from the RC oscillator of the
OSC1/CLKIN pin. That means that the WDT will run,
even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example,
by execution of a SLEEP instruction. During normal
operation and SLEEP mode, a WDT time-out generates a device RESET. The WDT can be permanently
disabled by programming the configuration bits
WDTPS1:WDTPS0 as '00' (Section 14.1).
Under normal operation, the WDT must be cleared on
a regular interval. This time is less the minimum WDT
overflow time. Not clearing the WDT in this time frame
will cause the WDT to overflow and reset the device.
14.3.1
WDT PERIOD
The WDT has a nominal time-out period of 12 ms, (with
postscaler = 1). The time-out periods vary with temperature, VDD and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
postscaler with a division ratio of up to 1:256 can be
assigned to the WDT. Thus, typical time-out periods up
to 3.0 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler (if assigned to the WDT) and prevent it from timing out thus generating a device RESET
condition.
14.3.2
CLEARING THE WDT AND POSTSCALER
The WDT and postscaler are cleared when:
•
•
•
•
The device is in the reset state
A SLEEP instruction is executed
A CLRWDT instruction is executed
Wake-up from SLEEP by an interrupt
The WDT counter/postscaler will start counting on the
first edge after the device exits the reset state.
14.3.3
WDT PROGRAMMING CONSIDERATIONS
It should also be taken in account that under worst case
conditions (VDD = Min., Temperature = Max., max.
WDT postscaler) it may take several seconds before a
WDT time-out occurs.
The WDT and postscaler is the Power-up Timer during
the Power-on Reset sequence.
14.3.4
WDT AS NORMAL TIMER
When the WDT is selected as a normal timer, the clock
source is the device clock. Neither the WDT nor the
postscaler are directly readable or writable. The overflow time is 65536 TOSC cycles. On overflow, the TO bit
is cleared (device is not reset). The CLRWDT instruction
can be used to set the TO bit. This allows the WDT to
be a simple overflow timer. When in sleep, the WDT
does not increment.
The TO bit in the CPUSTA register will be cleared upon
a WDT time-out.
1996 Microchip Technology Inc.
DS30412C-page 103
PIC17C4X
FIGURE 14-8: WATCHDOG TIMER BLOCK DIAGRAM
On-chip RC
Oscillator(1)
Postscaler
WDT
WDTPS1:WDTPS0
4 - to - 1 MUX
WDT Enable
Note 1: This oscillator is separate from the external
RC oscillator on the OSC1 pin.
TABLE 14-4:
REGISTERS/BITS ASSOCIATED WITH THE WATCHDOG TIMER
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
—
Config
—
PM1
—
PM0
CPUSTA
—
—
STKAV
GLINTD
06h, Unbanked
WDT Overflow
Bit 3
Bit 2
WDTPS1 WDTPS0
TO
PD
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note1)
FOSC1
FOSC0
(Note 2)
(Note 2)
—
—
--11 11--
--11 qq--
Legend: - = unimplemented read as '0', q - value depends on condition, shaded cells are not used by the WDT.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
2: This value will be as the device was programmed, or if unprogrammed, will read as all '1's.
DS30412C-page 104
1996 Microchip Technology Inc.
PIC17C4X
Power-down Mode (SLEEP)
14.4
PD bit, which is set on power-up, is cleared when
SLEEP is invoked. The TO bit is cleared if WDT
time-out occurred (and caused wake-up).
The Power-down mode is entered by executing a
SLEEP instruction. This clears the Watchdog Timer and
postscaler (if enabled). The PD bit is cleared and the
TO bit is set (in the CPUSTA register). In SLEEP mode,
the oscillator driver is turned off. The I/O ports maintain
their status (driving high, low, or hi-impedance).
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GLINTD bit. If the GLINTD
bit is set (disabled), the device continues execution at
the instruction after the SLEEP instruction. If the
GLINTD bit is clear (enabled), the device executes the
instruction after the SLEEP instruction and then
branches to the interrupt vector address. In cases
where the execution of the instruction following SLEEP
is not desirable, the user should have a NOP after the
SLEEP instruction.
The MCLR/VPP pin must be at a logic high level
(VIHMC). A WDT time-out RESET does not drive the
MCLR/VPP pin low.
14.4.1
WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
•
•
•
•
A POR reset
External reset input on MCLR/VPP pin
WDT Reset (if WDT was enabled)
Interrupt from RA0/INT pin, RB port change,
T0CKI interrupt, or some Peripheral Interrupts
Note:
If the global interrupts are disabled
(GLINTD is set), but any interrupt source
has both its interrupt enable bit and the corresponding interrupt flag bits set, the
device will immediately wake-up from
sleep. The TO bit is set, and the PD bit is
cleared.
The following peripheral interrupts can wake-up from
SLEEP:
•
•
•
•
The WDT is cleared when the device wake from
SLEEP, regardless of the source of wake-up.
Capture1 interrupt
Capture2 interrupt
USART synchronous slave transmit interrupt
USART synchronous slave receive interrupt
14.4.1.1
WAKE-UP DELAY
When the oscillator type is configured in XT or LF
mode, the Oscillator Start-up Timer (OST) is activated
on wake-up. The OST will keep the device in reset for
1024TOSC. This needs to be taken into account when
considering the interrupt response time when coming
out of SLEEP.
Other peripherals can not generate interrupts since
during SLEEP, no on-chip Q clocks are present.
Any reset event will cause a device reset. Any interrupt
event is considered a continuation of program execution. The TO and PD bits in the CPUSTA register can
be used to determine the cause of device reset. The
FIGURE 14-9: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Tost(2)
CLKOUT(4)
INT
(RA0/INT pin)
INTF flag
Interrupt Latency (2)
GLINTD bit
Processor
in SLEEP
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
PC
Inst (PC) = SLEEP
Inst (PC-1)
PC+1
PC+2
0004h
Inst (PC+1)
Inst (PC+2)
SLEEP
Inst (PC+1)
0005h
Dummy Cycle
Note 1: XT or LF oscillator mode assumed.
2: Tost = 1024Tosc (drawing not to scale). This delay will not be there for RC osc mode.
3: When GLINTD = 0 processor jumps to interrupt routine after wake-up. If GLINTD = 1, execution will continue in line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
1996 Microchip Technology Inc.
DS30412C-page 105
PIC17C4X
14.4.2
MINIMIZING CURRENT CONSUMPTION
To minimize current consumption, all I/O pins should be
either at VDD, or VSS, with no external circuitry drawing
current from the I/O pin. I/O pins that are hi-impedance
inputs should be pulled high or low externally to avoid
switching currents caused by floating inputs. The
T0CKI input should be at VDD or VSS. The contributions
from on-chip pull-ups on PORTB should also be considered, and disabled when possible.
14.5
Code Protection
The code in the program memory can be protected by
selecting the microcontroller in code protected mode
(PM2:PM0 = '000').
Note:
PM2 does not exist on the PIC17C42. To
select code protected microcontroller
mode, PM1:PM0 = '00'.
In this mode, instructions that are in the on-chip program memory space, can continue to read or write the
program memory. An instruction that is executed outside of the internal program memory range will be inhibited from writing to or reading from program memory.
Note:
Microchip does not recommend code protecting windowed devices.
If the code protection bit(s) have not been programmed, the on-chip program memory can be read
out for verification purposes.
DS30412C-page 106
1996 Microchip Technology Inc.
PIC17C4X
15.0
INSTRUCTION SET SUMMARY
The PIC17CXX instruction set consists of 58 instructions. Each instruction is a 16-bit word divided into an
OPCODE and one or more operands. The opcode
specifies the instruction type, while the operand(s) further specify the operation of the instruction. The
PIC17CXX instruction set can be grouped into three
types:
• byte-oriented
• bit-oriented
• literal and control operations.
These formats are shown in Figure 15-1.
Table 15-1 shows the field descriptions for the
opcodes. These descriptions are useful for understanding the opcodes in Table 15-2 and in each specific instruction descriptions.
byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' = '0', the result is
placed in the WREG register. If 'd' = '1', the result is
placed in the file register specified by the instruction.
bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by
the operation, while 'f' represents the number of the file
in which the bit is located.
literal and control operations, 'k' represents an 8- or
11-bit constant or literal value.
The instruction set is highly orthogonal and is grouped
into:
• byte-oriented operations
• bit-oriented operations
• literal and control operations
TABLE 15-1:
OPCODE FIELD
DESCRIPTIONS
Field
f
Description
Register file address (00h to FFh)
p
Peripheral register file address (00h to 1Fh)
i
Table pointer control i = '0' (do not change)
i = '1' (increment after instruction execution)
t
Table byte select t = '0' (perform operation on lower
byte)
t = '1' (perform operation on upper byte literal field,
constant data)
WREG Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don't care location (= '0' or '1')
The assembler will generate code with x = '0'. It is
the recommended form of use for compatibility with
all Microchip software tools.
d
Destination select
0 = store result in WREG
1 = store result in file register f
Default is d = '1'
u
Unused, encoded as '0'
s
Destination select
0 = store result in file register f and in the WREG
1 = store result in file register f
Default is s = '1'
label Label name
C,DC, ALU status bits Carry, Digit Carry, Zero, Overflow
Z,OV
GLINTD Global Interrupt Disable bit (CPUSTA<4>)
TBLPTR Table Pointer (16-bit)
TBLAT Table Latch (16-bit) consists of high byte (TBLATH)
and low byte (TBLATL)
TBLATL Table Latch low byte
TBLATH Table Latch high byte
All instructions are executed within one single instruction cycle, unless:
• a conditional test is true
• the program counter is changed as a result of an
instruction
• a table read or a table write instruction is executed (in this case, the execution takes two
instruction cycles with the second cycle executed
as a NOP)
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 25 MHz, the normal
instruction execution time is 160 ns. If a conditional test
is true or the program counter is changed as a result of
an instruction, the instruction execution time is 320 ns.
TOS
Top of Stack
PC
Program Counter
BSR
Bank Select Register
WDT
Watchdog Timer Counter
TO
Time-out bit
PD
Power-down bit
dest Destination either the WREG register or the specified register file location
[ ]
Options
( )
Contents
→
Assigned to
<>
Register bit field
∈
In the set of
italics User defined term (font is courier)
1996 Microchip Technology Inc.
DS30412C-page 107
This document was created with FrameMaker 4 0 4
PIC17C4X
Table 15-2 lists the instructions recognized by the
MPASM assembler.
Note 1: Any unused opcode is Reserved. Use of
any reserved opcode may cause unexpected operation.
Note 2: The shaded instructions are not available
in the PIC17C42
All instruction examples use the following format to represent a hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
To represent a binary number:
0000 0100b
15.1
Special Function Registers as
Source/Destination
The PIC17C4X’s orthogonal instruction set allows read
and write of all file registers, including special function
registers. There are some special situations the user
should be aware of:
15.1.1
ALUSTA AS DESTINATION
If an instruction writes to ALUSTA, the Z, C, DC and OV
bits may be set or cleared as a result of the instruction
and overwrite the original data bits written. For example, executing CLRF
ALUSTA will clear register
ALUSTA, and then set the Z bit leaving 0000 0100b in
the register.
where b signifies a binary string.
15.1.2
FIGURE 15-1: GENERAL FORMAT FOR
INSTRUCTIONS
Read, write or read-modify-write on PCL may have the
following results:
Byte-oriented file register operations
15
9
8
d
OPCODE
7
0
f (FILE #)
d = 0 for destination WREG
d = 1 for destination f
f = 8-bit file register address
Byte to Byte move operations
15
13 12
8 7
OPCODE
p (FILE #)
0
f (FILE #)
p = peripheral register file address
f = 8-bit file register address
15
OPCODE
11 10
8 7
b (BIT #)
Read PC:
PCH → PCLATH; PCL → dest
Write PCL:
PCLATH → PCH;
8-bit destination value → PCL
Read-Modify-Write:
PCL→ ALU operand
PCLATH → PCH;
8-bit result → PCL
Where PCH = program counter high byte (not an
addressable register), PCLATH = Program counter
high holding latch, dest = destination, WREG or f.
15.1.3
Bit-oriented file register operations
0
f (FILE #)
PCL AS SOURCE OR DESTINATION
BIT MANIPULATION
All bit manipulation instructions are done by first reading the entire register, operating on the selected bit and
writing the result back (read-modify-write). The user
should keep this in mind when operating on special
function registers, such as ports.
b = 3-bit address
f = 8-bit file register address
Literal and control operations
15
8
7
0
OPCODE
k (literal)
k = 8-bit immediate value
Call and GOTO operations
15
13 12
OPCODE
0
k (literal)
k = 13-bit immediate value
DS30412C-page 108
1996 Microchip Technology Inc.
PIC17C4X
15.2
Q Cycle Activity
The 4 Q cycles that make up an instruction cycle (Tcy)
can be generalized as:
Each instruction cycle (Tcy) is comprised of four Q
cycles (Q1-Q4). The Q cycles provide the timing/designation for the Decode, Read, Execute, Write etc., of
each instruction cycle. The following diagram shows
the relationship of the Q cycles to the instruction cycle.
Q1: Instruction Decode Cycle or forced NOP
Q2: Instruction Read Cycle or NOP
Q3: Instruction Execute
Q4: Instruction Write Cycle or NOP
Each instruction will show the detailed Q cycle operation for the instruction.
FIGURE 15-2: Q CYCLE ACTIVITY
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Tosc
Tcy1
1996 Microchip Technology Inc.
Tcy2
Tcy3
DS30412C-page 109
PIC17C4X
TABLE 15-2: PIC17CXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
16-bit Opcode
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
f,d
ADD WREG to f
1
0000 111d ffff ffff
OV,C,DC,Z
ADDWFC
f,d
ADD WREG and Carry bit to f
1
0001 000d ffff ffff
OV,C,DC,Z
ANDWF
f,d
AND WREG with f
1
0000 101d ffff ffff
Z
CLRF
f,s
Clear f, or Clear f and Clear WREG
1
0010 100s ffff ffff
None
COMF
f,d
Complement f
1
0001 001d ffff ffff
Z
3
CPFSEQ
f
Compare f with WREG, skip if f = WREG
1 (2)
0011 0001 ffff ffff
None
6,8
CPFSGT
f
Compare f with WREG, skip if f > WREG
1 (2)
0011 0010 ffff ffff
None
2,6,8
CPFSLT
f
Compare f with WREG, skip if f < WREG
1 (2)
0011 0000 ffff ffff
None
DAW
f,s
Decimal Adjust WREG Register
1
0010 111s ffff ffff
C
2,6,8
3
DECF
f,d
Decrement f
1
0000 011d ffff ffff
OV,C,DC,Z
DECFSZ
f,d
Decrement f, skip if 0
1 (2)
0001 011d ffff ffff
None
6,8
DCFSNZ
f,d
Decrement f, skip if not 0
1 (2)
0010 011d ffff ffff
None
6,8
INCF
f,d
Increment f
1
0001 010d ffff ffff
OV,C,DC,Z
INCFSZ
f,d
Increment f, skip if 0
1 (2)
0001 111d ffff ffff
None
6,8
INFSNZ
f,d
Increment f, skip if not 0
1 (2)
0010 010d ffff ffff
None
6,8
IORWF
f,d
Inclusive OR WREG with f
1
0000 100d ffff ffff
Z
MOVFP
f,p
Move f to p
1
011p pppp ffff ffff
None
MOVPF
p,f
Move p to f
1
010p pppp ffff ffff
Z
MOVWF
f
Move WREG to f
1
0000 0001 ffff ffff
None
MULWF
f
Multiply WREG with f
1
0011 0100 ffff ffff
None
NEGW
f,s
Negate WREG
1
0010 110s ffff ffff
OV,C,DC,Z
NOP
—
No Operation
1
0000 0000 0000 0000
None
RLCF
f,d
Rotate left f through Carry
1
0001 101d ffff ffff
C
RLNCF
f,d
Rotate left f (no carry)
1
0010 001d ffff ffff
None
RRCF
f,d
Rotate right f through Carry
1
0001 100d ffff ffff
C
RRNCF
f,d
Rotate right f (no carry)
1
0010 000d ffff ffff
None
SETF
f,s
Set f
1
0010 101s ffff ffff
None
3
SUBWF
f,d
Subtract WREG from f
1
0000 010d ffff ffff
OV,C,DC,Z
1
SUBWFB
f,d
Subtract WREG from f with Borrow
1
0000 001d ffff ffff
OV,C,DC,Z
1
SWAPF
f,d
Swap f
1
0001 110d ffff ffff
None
TABLRD
t,i,f
Table Read
2 (3)
1010 10ti ffff ffff
None
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
9
1,3
7
Refer to Table 15-1 for opcode field descriptions.
2’s Complement method.
Unsigned arithmetic.
If s = '1', only the file is affected: If s = '0', both the WREG register and the file are affected; If only the Working
register (WREG) is required to be affected, then f = WREG must be specified.
During an LCALL, the contents of PCLATH are loaded into the MSB of the PC and kkkk kkkk is loaded into
the LSB of the PC (PCL)
Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruction is terminated by an interrupt event. When writing to external program memory, it is a two-cycle instruction.
Two-cycle instruction when condition is true, else single cycle instruction.
Two-cycle instruction except for TABLRD to PCL (program counter low byte) in which case it takes 3 cycles.
A “skip” means that instruction fetched during execution of current instruction is not executed, instead an
NOP is executed.
These instructions are not available on the PIC17C42.
DS30412C-page 110
1996 Microchip Technology Inc.
PIC17C4X
TABLE 15-2: PIC17CXX INSTRUCTION SET (Cont.’d)
Mnemonic,
Operands
Description
Cycles
16-bit Opcode
MSb
LSb
Status
Affected
Notes
TABLWT
t,i,f
Table Write
2
1010 11ti ffff ffff
None
TLRD
t,f
Table Latch Read
1
1010 00tx ffff ffff
None
TLWT
t,f
Table Latch Write
TSTFSZ
f
Test f, skip if 0
XORWF
f,d
Exclusive OR WREG with f
1
1010 01tx ffff ffff
None
1 (2)
0011 0011 ffff ffff
None
1
0000 110d ffff ffff
Z
5
6,8
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
f,b
Bit Clear f
1
1000 1bbb ffff ffff
None
BSF
f,b
Bit Set f
1
1000 0bbb ffff ffff
None
BTFSC
f,b
Bit test, skip if clear
1 (2)
1001 1bbb ffff ffff
None
6,8
BTFSS
f,b
Bit test, skip if set
1 (2)
1001 0bbb ffff ffff
None
6,8
BTG
f,b
Bit Toggle f
1
0011 1bbb ffff ffff
None
LITERAL AND CONTROL OPERATIONS
ADDLW
k
ADD literal to WREG
1
1011 0001 kkkk kkkk
OV,C,DC,Z
ANDLW
k
AND literal with WREG
1
1011 0101 kkkk kkkk
Z
CALL
k
Subroutine Call
2
111k kkkk kkkk kkkk
None
CLRWDT
—
Clear Watchdog Timer
1
0000 0000 0000 0100
TO,PD
GOTO
k
Unconditional Branch
2
110k kkkk kkkk kkkk
None
IORLW
k
Inclusive OR literal with WREG
1
1011 0011 kkkk kkkk
Z
LCALL
k
Long Call
2
1011 0111 kkkk kkkk
None
MOVLB
k
Move literal to low nibble in BSR
1
1011 1000 uuuu kkkk
None
MOVLR
k
Move literal to high nibble in BSR
1
1011 101x kkkk uuuu
None
MOVLW
k
Move literal to WREG
1
1011 0000 kkkk kkkk
None
MULLW
k
Multiply literal with WREG
1
1011 1100 kkkk kkkk
None
9
RETFIE
—
Return from interrupt (and enable interrupts)
2
0000 0000 0000 0101
GLINTD
7
RETLW
k
Return literal to WREG
2
1011 0110 kkkk kkkk
None
7
RETURN
—
Return from subroutine
2
0000 0000 0000 0010
None
7
SLEEP
—
Enter SLEEP Mode
1
0000 0000 0000 0011
TO, PD
SUBLW
k
Subtract WREG from literal
1
1011 0010 kkkk kkkk
OV,C,DC,Z
k
Exclusive OR literal with WREG
1
1011 0100 kkkk kkkk
Z
XORLW
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
7
7
4,7
9
Refer to Table 15-1 for opcode field descriptions.
2’s Complement method.
Unsigned arithmetic.
If s = '1', only the file is affected: If s = '0', both the WREG register and the file are affected; If only the Working
register (WREG) is required to be affected, then f = WREG must be specified.
During an LCALL, the contents of PCLATH are loaded into the MSB of the PC and kkkk kkkk is loaded into
the LSB of the PC (PCL)
Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruction is terminated by an interrupt event. When writing to external program memory, it is a two-cycle instruction.
Two-cycle instruction when condition is true, else single cycle instruction.
Two-cycle instruction except for TABLRD to PCL (program counter low byte) in which case it takes 3 cycles.
A “skip” means that instruction fetched during execution of current instruction is not executed, instead an
NOP is executed.
These instructions are not available on the PIC17C42.
1996 Microchip Technology Inc.
DS30412C-page 111
PIC17C4X
ADDLW
ADD Literal to WREG
Syntax:
[ label ] ADDLW
Operands:
0 ≤ k ≤ 255
Operation:
(WREG) + k → (WREG)
Status Affected:
OV, C, DC, Z
Encoding:
Description:
1011
1
Cycles:
1
Q Cycle Activity:
Q1
Example:
kkkk
kkkk
The contents of WREG are added to the
8-bit literal 'k' and the result is placed in
WREG.
Words:
Decode
0001
k
Q2
Q3
Q4
Read
literal 'k'
Execute
Write to
WREG
ADDLW
Before Instruction
WREG = 0x10
After Instruction
WREG = 0x25
ADDWF
ADD WREG to f
Syntax:
[ label ] ADDWF
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operation:
(WREG) + (f) → (dest)
Status Affected:
OV, C, DC, Z
Encoding:
0000
111d
f,d
ffff
ffff
Description:
Add WREG to register 'f'. If 'd' is 0 the
result is stored in WREG. If 'd' is 1 the
result is stored back in register 'f'.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
0x15
Q2
Q3
Q4
Read
register 'f'
Execute
Write to
destination
Example:
ADDWF
REG, 0
Before Instruction
WREG
REG
=
=
0x17
0xC2
After Instruction
WREG
REG
DS30412C-page 112
=
=
0xD9
0xC2
1996 Microchip Technology Inc.
PIC17C4X
ADDWFC
ADD WREG and Carry bit to f
Syntax:
[ label ] ADDWFC
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operation:
(WREG) + (f) + C → (dest)
Status Affected:
OV, C, DC, Z
Encoding:
0001
Description:
f,d
ffff
ffff
1
Cycles:
Decode
Syntax:
[ label ] ANDLW
Operands:
0 ≤ k ≤ 255
Operation:
(WREG) .AND. (k) → (WREG)
Status Affected:
Z
Q2
Q3
Q4
Read
register 'f'
Execute
Write to
destination
ADDWFC
REG
Before Instruction
Carry bit =
REG
=
WREG =
1
0x02
0x4D
0
0101
k
kkkk
kkkk
Description:
The contents of WREG are AND’ed with
the 8-bit literal 'k'. The result is placed in
WREG.
Words:
1
Cycles:
1
Decode
Example:
1011
Q Cycle Activity:
Q1
1
Q Cycle Activity:
Q1
And Literal with WREG
Encoding:
000d
Add WREG, the Carry Flag and data
memory location 'f'. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the result is
placed in data memory location 'f'.
Words:
ANDLW
Q2
Q3
Q4
Read literal
'k'
Execute
Write to
WREG
Example:
ANDLW
0x5F
Before Instruction
WREG
=
0xA3
After Instruction
WREG
=
0x03
After Instruction
Carry bit =
REG
=
WREG =
0
0x02
0x50
1996 Microchip Technology Inc.
DS30412C-page 113
PIC17C4X
ANDWF
AND WREG with f
BCF
Bit Clear f
Syntax:
[ label ] ANDWF
Syntax:
[ label ] BCF
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operands:
0 ≤ f ≤ 255
0≤b≤7
Operation:
(WREG) .AND. (f) → (dest)
Operation:
0 → (f<b>)
Status Affected:
Z
Status Affected:
None
Encoding:
0000
Description:
101d
f,d
ffff
ffff
Encoding:
1000
f,b
1bbb
ffff
ffff
The contents of WREG are AND’ed with
register 'f'. If 'd' is 0 the result is stored
in WREG. If 'd' is 1 the result is stored
back in register 'f'.
Description:
Bit 'b' in register 'f' is cleared.
Words:
1
Cycles:
1
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register 'f'
Execute
Write to
destination
Example:
ANDWF
=
=
Q3
Q4
Execute
Write
register 'f'
BCF
FLAG_REG,
7
Before Instruction
FLAG_REG = 0xC7
After Instruction
Before Instruction
WREG
REG
REG, 1
Example:
Q2
Read
register 'f'
0x17
0xC2
FLAG_REG = 0x47
After Instruction
WREG
REG
=
=
DS30412C-page 114
0x17
0x02
1996 Microchip Technology Inc.
PIC17C4X
BSF
Bit Set f
BTFSC
Bit Test, skip if Clear
Syntax:
[ label ] BSF
Syntax:
[ label ] BTFSC f,b
Operands:
0 ≤ f ≤ 255
0≤b≤7
Operands:
0 ≤ f ≤ 255
0≤b≤7
Operation:
1 → (f<b>)
Operation:
skip if (f<b>) = 0
Status Affected:
None
Status Affected:
None
Encoding:
1000
f,b
0bbb
ffff
Description:
Bit 'b' in register 'f' is set.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
ffff
Q2
Q3
Q4
Read
register 'f'
Execute
Write
register 'f'
BSF
FLAG_REG, 7
Before Instruction
FLAG_REG= 0x0A
Encoding:
1bbb
ffff
ffff
Description:
If bit 'b' in register ’f' is 0 then the next
instruction is skipped.
If bit 'b' is 0 then the next instruction
fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a two-cycle
instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
Q1
Decode
After Instruction
FLAG_REG= 0x8A
1001
Q2
Q3
Q4
Read
register 'f'
Execute
NOP
If skip:
Q1
Q2
Q3
Q4
Forced NOP
NOP
Execute
NOP
Example:
HERE
FALSE
TRUE
BTFSC
:
:
FLAG,1
Before Instruction
PC
=
address (HERE)
=
=
=
=
0;
address (TRUE)
1;
address (FALSE)
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
1996 Microchip Technology Inc.
DS30412C-page 115
PIC17C4X
BTFSS
Bit Test, skip if Set
BTG
Bit Toggle f
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] BTG f,b
Operands:
0 ≤ f ≤ 127
0≤b<7
Operands:
0 ≤ f ≤ 255
0≤b<7
Operation:
skip if (f<b>) = 1
Operation:
(f<b>) → (f<b>)
Status Affected:
None
Status Affected:
None
Encoding:
Description:
1001
0bbb
ffff
ffff
If bit 'b' in register 'f' is 1 then the next
instruction is skipped.
If bit 'b' is 1, then the next instruction
fetched during the current instruction execution, is discarded and an NOP is executed instead, making this a two-cycle
instruction.
Words:
1
Cycles:
1(2)
Q3
Q4
Read
register 'f'
Execute
NOP
Q1
Q2
Q3
Q4
Forced NOP
NOP
Execute
NOP
ffff
ffff
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register 'f'
Execute
Write
register 'f'
BTG
PORTC,
4
Before Instruction:
PORTC
=
0111 0101 [0x75]
After Instruction:
If skip:
PORTC
HERE
FALSE
TRUE
1bbb
Bit 'b' in data memory location 'f' is
inverted.
Example:
Q2
Example:
0011
Description:
Decode
Q Cycle Activity:
Q1
Decode
Encoding:
BTFSS
:
:
=
0110 0101 [0x65]
FLAG,1
Before Instruction
PC
=
address (HERE)
=
=
=
=
0;
address (FALSE)
1;
address (TRUE)
After Instruction
If FLAG<1>
PC
If FLAG<1>
PC
DS30412C-page 116
1996 Microchip Technology Inc.
PIC17C4X
CALL
Subroutine Call
CLRF
Clear f
Syntax:
[ label ] CALL k
Syntax:
[label] CLRF
Operands:
0 ≤ k ≤ 4095
Operands:
0 ≤ f ≤ 255
Operation:
PC+ 1→ TOS, k → PC<12:0>,
k<12:8> → PCLATH<4:0>;
PC<15:13> → PCLATH<7:5>
Operation:
00h → f, s ∈ [0,1]
00h → dest
Status Affected:
None
Status Affected:
None
Encoding:
Encoding:
Description:
111k
kkkk
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
HERE
Q3
Q4
Execute
NOP
Execute
NOP
CALL
Before Instruction
Address(HERE)
After Instruction
THERE
100s
ffff
ffff
Description:
Clears the contents of the specified register(s).
s = 0: Data memory location 'f' and
WREG are cleared.
s = 1: Data memory location 'f' is
cleared.
Words:
1
Cycles:
1
Decode
Read literal
'k'<7:0>
Forced NOP
NOP
PC =
TOS =
0010
Q Cycle Activity:
Q1
Decode
PC =
kkkk
Subroutine call within 8K page. First,
return address (PC+1) is pushed onto
the stack. The 13-bit value is loaded into
PC bits<12:0>. Then the upper-eight
bits of the PC are copied into PCLATH.
Call is a two-cycle instruction.
See LCALL for calls outside 8K memory
space.
Words:
Example:
kkkk
f,s
Example:
Q2
Q3
Q4
Read
register 'f'
Execute
Write
register 'f'
and other
specified
register
CLRF
FLAG_REG
Before Instruction
FLAG_REG
=
0x5A
=
0x00
After Instruction
FLAG_REG
Address(THERE)
Address (HERE + 1)
1996 Microchip Technology Inc.
DS30412C-page 117
PIC17C4X
CLRWDT
Clear Watchdog Timer
COMF
Complement f
Syntax:
[ label ] CLRWDT
Syntax:
[ label ] COMF
Operands:
None
Operands:
Operation:
00h → WDT
0 → WDT postscaler,
1 → TO
1 → PD
0 ≤ f ≤ 255
d ∈ [0,1]
Operation:
( f ) → (dest)
Status Affected:
Z
Status Affected:
Encoding:
TO, PD
Encoding:
0000
0000
0000
0100
0001
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q3
Q4
Read
register
ALUSTA
Execute
NOP
REG1
=
?
=
=
=
=
0x00
0
1
1
After Instruction
TO
PD
DS30412C-page 118
Q2
Q3
Q4
Read
register 'f'
Execute
Write
register 'f'
COMF
REG1,0
Before Instruction
Before Instruction
WDT counter
WDT Postscaler
Decode
Example:
CLRWDT
WDT counter
ffff
The contents of register 'f' are complemented. If 'd' is 0 the result is stored in
WREG. If 'd' is 1 the result is stored
back in register 'f'.
CLRWDT instruction resets the watchdog
timer. It also resets the prescaler of the
WDT. Status bits TO and PD are set.
Q2
ffff
Description:
Description:
Q Cycle Activity:
Q1
001d
f,d
=
0x13
After Instruction
REG1
WREG
=
=
0x13
0xEC
1996 Microchip Technology Inc.
PIC17C4X
CPFSEQ
Compare f with WREG,
skip if f = WREG
CPFSGT
Compare f with WREG,
skip if f > WREG
Syntax:
[ label ] CPFSEQ
Syntax:
[ label ] CPFSGT
Operands:
0 ≤ f ≤ 255
Operands:
0 ≤ f ≤ 255
Operation:
(f) – (WREG),
skip if (f) = (WREG)
(unsigned comparison)
Operation:
(f) − (WREG),
skip if (f) > (WREG)
(unsigned comparison)
Status Affected:
None
Status Affected:
None
Encoding:
0011
0001
f
ffff
ffff
Description:
Compares the contents of data memory
location 'f' to the contents of WREG by
performing an unsigned subtraction.
If 'f' = WREG then the fetched instruction is discarded and an NOP is executed instead making this a two-cycle
instruction.
Words:
1
Cycles:
1 (2)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register 'f'
Execute
NOP
Q1
Q2
Q3
Q4
Forced NOP
NOP
Execute
NOP
Decode
If skip:
Example:
HERE
NEQUAL
EQUAL
CPFSEQ REG
:
:
Before Instruction
PC Address
WREG
REG
=
=
=
HERE
?
?
0011
0010
ffff
ffff
Description:
Compares the contents of data memory
location 'f' to the contents of the WREG
by performing an unsigned subtraction.
If the contents of 'f' > the contents of
WREG then the fetched instruction is
discarded and an NOP is executed
instead making this a two-cycle instruction.
Words:
1
Cycles:
1 (2)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Execute
NOP
Q1
Q2
Q3
Q4
Forced NOP
NOP
Execute
NOP
If skip:
Example:
HERE
NGREATER
GREATER
CPFSGT REG
:
:
Before Instruction
PC
WREG
=
=
Address (HERE)
?
>
=
≤
=
WREG;
Address (GREATER)
WREG;
Address (NGREATER)
After Instruction
After Instruction
If REG
PC
If REG
PC
Encoding:
f
=
=
≠
=
WREG;
Address (EQUAL)
WREG;
Address (NEQUAL)
1996 Microchip Technology Inc.
If REG
PC
If REG
PC
DS30412C-page 119
PIC17C4X
CPFSLT
Compare f with WREG,
skip if f < WREG
DAW
Decimal Adjust WREG Register
Syntax:
[label] DAW
Syntax:
[ label ] CPFSLT
Operands:
Operands:
0 ≤ f ≤ 255
0 ≤ f ≤ 255
s ∈ [0,1]
Operation:
(f) – (WREG),
skip if (f) < (WREG)
(unsigned comparison)
Operation:
Status Affected:
None
If [WREG<3:0> >9] .OR. [DC = 1] then
WREG<3:0> + 6 → f<3:0>, s<3:0>;
else
WREG<3:0> → f<3:0>, s<3:0>;
Encoding:
Description:
0011
ffff
1
Cycles:
1 (2)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register 'f'
Execute
NOP
If skip:
Q1
Q2
Q3
Q4
Forced NOP
NOP
Execute
NOP
Example:
HERE
NLESS
LESS
CPFSLT REG
:
:
f,s
If [WREG<7:4> >9] .OR. [C = 1] then
WREG<7:4> + 6 → f<7:4>, s<7:4>
else
WREG<7:4> → f<7:4>, s<7:4>
ffff
Compares the contents of data memory
location 'f' to the contents of WREG by
performing an unsigned subtraction.
If the contents of 'f' < the contents of
WREG, then the fetched instruction is
discarded and an NOP is executed
instead making this a two-cycle instruction.
Words:
Decode
0000
f
Status Affected:
C
Encoding:
0010
111s
=
=
DAW adjusts the eight bit value in
WREG resulting from the earlier addition of two variables (each in packed
BCD format) and produces a correct
packed BCD result.
s = 0: Result is placed in Data
memory location 'f' and
WREG.
s = 1: Result is placed in Data
memory location 'f'.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register 'f'
Execute
Write
register 'f'
and other
specified
register
Address (HERE)
?
Example1:
After Instruction
If REG
PC
If REG
PC
<
=
≥
=
WREG;
Address (LESS)
WREG;
Address (NLESS)
ffff
Description:
Before Instruction
PC
W
ffff
DAW
REG1, 0
Before Instruction
WREG
REG1
C
DC
=
=
=
=
0xA5
??
0
0
After Instruction
WREG
REG1
C
DC
=
=
=
=
0x05
0x05
1
0
Example 2:
Before Instruction
WREG
REG1
C
DC
=
=
=
=
0xCE
??
0
0
After Instruction
WREG
REG1
C
DC
DS30412C-page 120
=
=
=
=
0x24
0x24
1
0
1996 Microchip Technology Inc.
PIC17C4X
DECF
Decrement f
DECFSZ
Decrement f, skip if 0
Syntax:
[ label ] DECF f,d
Syntax:
[ label ] DECFSZ f,d
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operation:
(f) – 1 → (dest)
Operation:
Status Affected:
OV, C, DC, Z
(f) – 1 → (dest);
skip if result = 0
Status Affected:
None
Encoding:
0000
Description:
1
Cycles:
1
Q Cycle Activity:
Q1
ffff
Q2
Q3
Q4
Read
register 'f'
Execute
Write to
destination
Example:
DECF
CNT,
Before Instruction
CNT
Z
ffff
Decrement register 'f'. If 'd' is 0 the
result is stored in WREG. If 'd' is 1 the
result is stored back in register 'f'.
Words:
Decode
011d
=
=
0x01
0
1
Encoding:
=
=
0x00
1
011d
ffff
ffff
Description:
The contents of register 'f' are decremented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
If the result is 0, the next instruction,
which is already fetched, is discarded,
and an NOP is executed instead making it a two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
Q1
Decode
After Instruction
CNT
Z
0001
Q2
Q3
Q4
Read
register 'f'
Execute
Write to
destination
Example:
HERE
DECFSZ
GOTO
CNT, 1
LOOP
CONTINUE
Before Instruction
PC
=
Address (HERE)
After Instruction
CNT
If CNT
PC
If CNT
PC
1996 Microchip Technology Inc.
=
=
=
≠
=
CNT - 1
0;
Address (CONTINUE)
0;
Address (HERE+1)
DS30412C-page 121
PIC17C4X
DCFSNZ
Decrement f, skip if not 0
GOTO
Unconditional Branch
Syntax:
Operands:
[label] DCFSNZ f,d
Syntax:
[ label ]
0 ≤ f ≤ 255
d ∈ [0,1]
Operands:
0 ≤ k ≤ 8191
Operation:
(f) – 1 → (dest);
skip if not 0
Operation:
k → PC<12:0>;
k<12:8> → PCLATH<4:0>,
PC<15:13> → PCLATH<7:5>
Status Affected:
None
Status Affected:
None
Encoding:
0010
011d
ffff
ffff
Encoding:
110k
GOTO k
kkkk
kkkk
kkkk
Description:
The contents of register 'f' are decremented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
If the result is not 0, the next instruction,
which is already fetched, is discarded,
and an NOP is executed instead making it a two-cycle instruction.
Description:
GOTO allows an unconditional branch
anywhere within an 8K page boundary.
The thirteen bit immediate value is
loaded into PC bits <12:0>. Then the
upper eight bits of PC are loaded into
PCLATH. GOTO is always a two-cycle
instruction.
Words:
1
Words:
1
Cycles:
2
Cycles:
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Read
register 'f'
Execute
Write to
destination
Q1
Q2
Q3
Q4
Forced NOP
NOP
Execute
NOP
Decode
If skip:
Example:
HERE
ZERO
NZERO
DCFSNZ
:
:
Q2
Decode
Read literal
'k'<7:0>
Forced NOP
NOP
Example:
Q3
Q4
Execute
NOP
Execute
NOP
GOTO THERE
After Instruction
PC =
Address (THERE)
TEMP, 1
Before Instruction
TEMP_VALUE
=
?
=
=
=
≠
=
TEMP_VALUE - 1,
0;
Address (ZERO)
0;
Address (NZERO)
After Instruction
TEMP_VALUE
If TEMP_VALUE
PC
If TEMP_VALUE
PC
DS30412C-page 122
1996 Microchip Technology Inc.
PIC17C4X
INCF
Increment f
INCFSZ
Increment f, skip if 0
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operation:
(f) + 1 → (dest)
Operation:
Status Affected:
OV, C, DC, Z
(f) + 1 → (dest)
skip if result = 0
Status Affected:
None
Encoding:
0001
Description:
010d
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Execute
Write to
destination
INCF
CNT, 1
Before Instruction
=
=
=
0xFF
0
?
After Instruction
CNT
Z
C
ffff
Read
register 'f'
Example:
CNT
Z
C
ffff
The contents of register 'f' are incremented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
Words:
Decode
INCF f,d
=
=
=
0x00
1
1
Encoding:
0001
INCFSZ f,d
111d
ffff
ffff
Description:
The contents of register 'f' are incremented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
If the result is 0, the next instruction,
which is already fetched, is discarded,
and an NOP is executed instead making
it a two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register 'f'
Execute
Write to
destination
If skip:
Q1
Q2
Q3
Q4
Forced NOP
NOP
Execute
NOP
Example:
HERE
NZERO
ZERO
INCFSZ
:
:
CNT, 1
Before Instruction
PC
=
Address (HERE)
After Instruction
CNT
If CNT
PC
If CNT
PC
1996 Microchip Technology Inc.
=
=
=
≠
=
CNT + 1
0;
Address(ZERO)
0;
Address(NZERO)
DS30412C-page 123
PIC17C4X
INFSNZ
Increment f, skip if not 0
Syntax:
[label]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operation:
(f) + 1 → (dest), skip if not 0
Status Affected:
None
Encoding:
0010
Description:
INFSNZ f,d
1
Cycles:
1(2)
Q Cycle Activity:
Q1
Decode
ffff
ffff
Q3
Q4
Read
register 'f'
Execute
Write to
destination
If skip:
Q1
Q2
Q3
Q4
Forced NOP
NOP
Execute
NOP
HERE
ZERO
NZERO
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operation:
(WREG) .OR. (k) → (WREG)
Status Affected:
Z
1011
INFSNZ
IORLW k
0011
kkkk
kkkk
Description:
The contents of WREG are OR’ed with
the eight bit literal 'k'. The result is
placed in WREG.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q2
Example:
Inclusive OR Literal with WREG
Encoding:
010d
The contents of register 'f' are incremented. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
If the result is not 0, the next instruction,
which is already fetched, is discarded,
and an NOP is executed instead making
it a two-cycle instruction.
Words:
IORLW
Q2
Q3
Q4
Read
literal 'k'
Execute
Write to
WREG
IORLW
0x35
Before Instruction
WREG
=
0x9A
After Instruction
WREG
=
0xBF
REG, 1
Before Instruction
REG
=
REG
After Instruction
REG
If REG
PC
If REG
PC
=
=
=
=
=
DS30412C-page 124
REG + 1
1;
Address (ZERO)
0;
Address (NZERO)
1996 Microchip Technology Inc.
PIC17C4X
IORWF
Inclusive OR WREG with f
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operation:
(WREG) .OR. (f) → (dest)
Status Affected:
Z
Encoding:
0000
IORWF
100d
f,d
ffff
ffff
Description:
Inclusive OR WREG with register 'f'. If
'd' is 0 the result is placed in WREG. If
'd' is 1 the result is placed back in register 'f'.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register 'f'
Execute
Write to
destination
Example:
IORWF
RESULT, 0
Before Instruction
RESULT =
WREG =
0x13
0x91
Long Call
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operation:
PC + 1 → TOS;
k → PCL, (PCLATH) → PCH
Status Affected:
None
Encoding:
0x13
0x93
1011
LCALL
0111
k
kkkk
kkkk
Description:
LCALL allows an unconditional subroutine call to anywhere within the 64k program memory space.
First, the return address (PC + 1) is
pushed onto the stack. A 16-bit destination address is then loaded into the
program counter. The lower 8-bits of
the destination address is embedded in
the instruction. The upper 8-bits of PC
is loaded from PC high holding latch,
PCLATH.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Decode
After Instruction
RESULT =
WREG =
LCALL
Forced NOP
Example:
Q2
Q3
Q4
Read
literal 'k'
NOP
Execute
Write
register PCL
NOP
MOVLW
MOVPF
LCALL
Execute
HIGH(SUBROUTINE)
WREG, PCLATH
LOW(SUBROUTINE)
Before Instruction
SUBROUTINE =
PC
=
16-bit Address
?
After Instruction
PC
1996 Microchip Technology Inc.
=
Address (SUBROUTINE)
DS30412C-page 125
PIC17C4X
MOVFP
Move f to p
Syntax:
[label]
Operands:
0 ≤ f ≤ 255
0 ≤ p ≤ 31
Operation:
(f) → (p)
Status Affected:
None
Encoding:
Description:
Cycles:
1
Q Cycle Activity:
Q1
Example:
pppp
ffff
ffff
Move data from data memory location 'f'
to data memory location 'p'. Location 'f'
can be anywhere in the 256 word data
space (00h to FFh) while 'p' can be 00h
to 1Fh.
Either ’p' or 'f' can be WREG (a useful
special situation).
MOVFP is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer
or an I/O port). Both 'f' and 'p' can be
indirectly addressed.
1
Move Literal to low nibble in BSR
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 15
Operation:
k → (BSR<3:0>)
Status Affected:
None
Encoding:
011p
Words:
Decode
MOVFP f,p
MOVLB
MOVLB k
1011
1000
uuuu
kkkk
Description:
The four bit literal 'k' is loaded in the
Bank Select Register (BSR). Only the
low 4-bits of the Bank Select Register
are affected. The upper half of the BSR
is unchanged. The assembler will
encode the “u” fields as '0'.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Read
literal 'u:k'
Execute
Write literal
'k' to
BSR<3:0>
MOVLB
0x5
Before Instruction
Q2
Q3
Q4
Read
register 'f'
Execute
Write
register 'p'
MOVFP
REG1, REG2
Before Instruction
REG1
REG2
=
=
0x33,
0x11
=
=
0x33,
0x33
BSR register
=
0x22
=
0x25
After Instruction
BSR register
Note:
For the PIC17C42, only the low four bits of
the BSR register are physically implemented. The upper nibble is read as '0'.
After Instruction
REG1
REG2
DS30412C-page 126
1996 Microchip Technology Inc.
PIC17C4X
MOVLR
Move Literal to high nibble in
BSR
MOVLW
Move Literal to WREG
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
Operands:
0 ≤ k ≤ 15
0 ≤ k ≤ 255
Operation:
k → (BSR<7:4>)
k → (WREG)
Operation:
Status Affected:
None
Status Affected:
None
Encoding:
Encoding:
1011
Description:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
101x
kkkk
uuuu
The 4-bit literal 'k' is loaded into the
most significant 4-bits of the Bank
Select Register (BSR). Only the high
4-bits of the Bank Select Register
are affected. The lower half of the
BSR is unchanged. The assembler
will encode the “u” fields as 0.
Words:
Example:
MOVLR k
1011
Q4
Read literal
'k:u'
Execute
Write
literal 'k' to
BSR<7:4>
MOVLR
kkkk
kkkk
The eight bit literal 'k' is loaded into
WREG.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Example:
Q3
0000
Description:
Decode
Q2
MOVLW k
Q2
Q3
Q4
Read
literal 'k'
Execute
Write to
WREG
MOVLW
0x5A
After Instruction
WREG
=
0x5A
5
Before Instruction
BSR register
=
0x22
=
0x52
After Instruction
BSR register
Note:
This instruction is not available in the
PIC17C42 device.
1996 Microchip Technology Inc.
DS30412C-page 127
PIC17C4X
MOVPF
Move p to f
Syntax:
[label]
Operands:
0 ≤ f ≤ 255
0 ≤ p ≤ 31
Operation:
(p) → (f)
Status Affected:
Z
Encoding:
pppp
ffff
ffff
Move data from data memory location
'p' to data memory location 'f'. Location
'f' can be anywhere in the 256 byte data
space (00h to FFh) while 'p' can be 00h
to 1Fh.
Either 'p' or 'f' can be WREG (a useful
special situation).
MOVPF is particularly useful for transferring a peripheral register (e.g. the timer
or an I/O port) to a data memory location. Both 'f' and 'p' can be indirectly
addressed.
Words:
1
Cycles:
1
Move WREG to f
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
Operation:
(WREG) → (f)
Status Affected:
None
Encoding:
010p
Description:
0000
MOVWF
0001
f
ffff
ffff
Description:
Move data from WREG to register 'f'.
Location 'f' can be anywhere in the 256
word data space.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register 'f'
Execute
Write
register 'f'
Example:
MOVWF
REG
Before Instruction
WREG
REG
=
=
0x4F
0xFF
After Instruction
Q Cycle Activity:
Q1
Decode
MOVPF p,f
MOVWF
Q2
Q3
Q4
Read
register 'p'
Execute
Write
register 'f'
Example:
MOVPF
WREG
REG
=
=
0x4F
0x4F
REG1, REG2
Before Instruction
REG1
REG2
=
=
0x11
0x33
=
=
0x11
0x11
After Instruction
REG1
REG2
DS30412C-page 128
1996 Microchip Technology Inc.
PIC17C4X
MULLW
Multiply Literal with WREG
MULWF
Multiply WREG with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 255
Operation:
(k x WREG) → PRODH:PRODL
Operation:
(WREG x f) → PRODH:PRODL
Status Affected:
None
Status Affected:
None
Encoding:
MULLW
1011
1100
k
kkkk
kkkk
Encoding:
0011
MULWF
0100
f
ffff
ffff
Description:
An unsigned multiplication is carried
out between the contents of WREG
and the 8-bit literal 'k'. The 16-bit
result is placed in PRODH:PRODL
register pair. PRODH contains the
high byte.
WREG is unchanged.
None of the status flags are affected.
Note that neither overflow nor carry
is possible in this operation. A zero
result is possible but not detected.
Description:
An unsigned multiplication is carried
out between the contents of WREG
and the register file location 'f'. The
16-bit result is stored in the
PRODH:PRODL register pair.
PRODH contains the high byte.
Both WREG and 'f' are unchanged.
None of the status flags are affected.
Note that neither overflow nor carry
is possible in this operation. A zero
result is possible but not detected.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Read
literal 'k'
Execute
Write
registers
PRODH:
PRODL
MULLW
0xC4
Before Instruction
WREG
PRODH
PRODL
Q Cycle Activity:
Q1
Decode
Example:
Note:
Q3
Q4
Execute
Write
registers
PRODH:
PRODL
MULWF
REG
Before Instruction
=
=
=
0xE2
?
?
WREG
REG
PRODH
PRODL
=
=
=
0xC4
0xAD
0x08
After Instruction
After Instruction
WREG
PRODH
PRODL
Q2
Read
register 'f'
WREG
REG
PRODH
PRODL
This instruction is not available in the
PIC17C42 device.
Note:
1996 Microchip Technology Inc.
=
=
=
=
0xC4
0xB5
?
?
=
=
=
=
0xC4
0xB5
0x8A
0x94
This instruction is not available in the
PIC17C42 device.
DS30412C-page 129
PIC17C4X
NEGW
Negate W
Syntax:
[label]
Operands:
0 ≤ F ≤ 255
s ∈ [0,1]
Operation:
WREG + 1 → (f);
WREG + 1 → s
Status Affected:
OV, C, DC, Z
Encoding:
0010
Description:
NEGW
110s
f,s
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
ffff
ffff
Syntax:
[ label ]
Operands:
None
Operation:
No operation
Status Affected:
None
0000
NOP
0000
Description:
No operation.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
0000
0000
Q2
Q3
Q4
NOP
Execute
NOP
Example:
Q2
Q3
Q4
Read
register 'f'
Execute
Write
register 'f'
and other
specified
register
Example:
No Operation
Encoding:
WREG is negated using two’s complement. If 's' is 0 the result is placed in
WREG and data memory location 'f'. If
's' is 1 the result is placed only in data
memory location 'f'.
Words:
NOP
NEGW
None.
REG,0
Before Instruction
WREG
REG
=
=
0011 1010 [0x3A],
1010 1011 [0xAB]
After Instruction
WREG
REG
=
=
DS30412C-page 130
1100 0111 [0xC6]
1100 0111 [0xC6]
1996 Microchip Technology Inc.
PIC17C4X
RETFIE
Return from Interrupt
RETLW
Return Literal to WREG
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
0 ≤ k ≤ 255
Operation:
TOS → (PC);
0 → GLINTD;
PCLATH is unchanged.
Operation:
k → (WREG); TOS → (PC);
PCLATH is unchanged
Status Affected:
None
Status Affected:
GLINTD
Encoding:
Encoding:
0000
RETFIE
0000
0000
0101
1
Cycles:
2
1
Cycles:
2
Q Cycle Activity:
Q1
Decode
Forced NOP
Example:
Q4
Read
register
T0STA
NOP
Execute
NOP
Decode
Forced NOP
Execute
NOP
Example:
Q2
Q3
Q4
Read
literal 'k'
NOP
Execute
Write to
WREG
NOP
Execute
CALL TABLE ;
;
;
;
:
TABLE
ADDWF PC
;
RETLW k0
;
RETLW k1
;
:
:
RETLW kn
;
RETFIE
After Interrupt
PC
=
GLINTD =
kkkk
Words:
Words:
Q3
kkkk
WREG is loaded with the eight bit literal
'k'. The program counter is loaded from
the top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Return from Interrupt. Stack is POP’ed
and Top of Stack (TOS) is loaded in the
PC. Interrupts are enabled by clearing
the GLINTD bit. GLINTD is the global
interrupt disable bit (CPUSTA<4>).
Q2
0110
Description:
Description:
Q Cycle Activity:
Q1
1011
RETLW k
TOS
0
WREG contains table
offset value
WREG now has
table value
WREG = offset
Begin table
End of table
Before Instruction
WREG
=
0x07
After Instruction
WREG
1996 Microchip Technology Inc.
=
value of k7
DS30412C-page 131
PIC17C4X
RETURN
Return from Subroutine
Syntax:
[ label ]
Operands:
None
Operation:
TOS → PC;
Status Affected:
None
RLCF
Rotate Left f through Carry
Syntax:
[ label ] RLCF
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operation:
f<n> → d<n+1>;
f<7> → C;
C → d<0>
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter.
Status Affected:
C
Words:
1
Description:
Cycles:
2
Encoding:
Description:
Q Cycle Activity:
Q1
Decode
Forced NOP
0000
RETURN
0000
0000
0010
Q2
Q3
Q4
Read
register
PCL*
NOP
Execute
NOP
Execute
NOP
* Remember reading PCL causes PCLATH to be updated.
This will be the high address of where the RETURN instruction is located.
Example:
After Interrupt
PC = TOS
RETURN
Encoding:
0001
101d
ffff
ffff
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is stored
back in register 'f'.
register f
C
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
f,d
Q2
Q3
Q4
Read
register 'f'
Execute
Write to
destination
Example:
RLCF
REG,0
Before Instruction
REG
C
=
=
1110 0110
0
After Instruction
REG
WREG
C
DS30412C-page 132
=
=
=
1110 0110
1100 1100
1
1996 Microchip Technology Inc.
PIC17C4X
RLNCF
Rotate Left f (no carry)
RRCF
Rotate Right f through Carry
Syntax:
[ label ] RLNCF
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operation:
f<n> → d<n+1>;
f<7> → d<0>
Operation:
Status Affected:
None
f<n> → d<n-1>;
f<0> → C;
C → d<7>
Status Affected:
C
Encoding:
0010
Description:
001d
f,d
ffff
ffff
The contents of register 'f' are rotated
one bit to the left. If 'd' is 0 the result is
placed in WREG. If 'd' is 1 the result is
stored back in register 'f'.
Encoding:
0001
Description:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q3
Q4
Read
register 'f'
Execute
Write to
destination
RLNCF
Before Instruction
C
REG
=
=
0
1110 1011
=
=
1
Cycles:
1
Q Cycle Activity:
Q1
1101 0111
Q2
Q3
Q4
Execute
Write to
destination
RRCF
REG1,0
Before Instruction
=
=
1110 0110
0
After Instruction
REG1
WREG
C
1996 Microchip Technology Inc.
ffff
Read
register 'f'
Example:
REG1
C
After Instruction
C
REG
REG, 1
Words:
Decode
ffff
register f
C
Q2
Example:
100d
The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in
WREG. If 'd' is 1 the result is placed
back in register 'f'.
register f
Words:
RRCF f,d
=
=
=
1110 0110
0111 0011
0
DS30412C-page 133
PIC17C4X
RRNCF
Rotate Right f (no carry)
SETF
Set f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operands:
0 ≤ f ≤ 255
s ∈ [0,1]
Operation:
f<n> → d<n-1>;
f<0> → d<7>
Operation:
FFh → f;
FFh → d
Status Affected:
None
Status Affected:
None
Encoding:
0010
Description:
RRNCF f,d
000d
ffff
ffff
The contents of register 'f' are rotated
one bit to the right. If 'd' is 0 the result is
placed in WREG. If 'd' is 1 the result is
placed back in register 'f'.
register f
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Execute
Write to
destination
RRNCF
REG, 1
Before Instruction
=
=
?
1101 0111
After Instruction
WREG
REG
=
=
Example 2:
0
1110 1011
RRNCF
REG, 0
=
=
?
1101 0111
After Instruction
WREG
REG
=
=
DS30412C-page 134
ffff
ffff
Words:
1
Cycles:
1
Q2
Q3
Q4
Read
register 'f'
Execute
Write
register 'f'
and other
specified
register
Example1:
SETF
REG, 0
Before Instruction
REG
WREG
=
=
0xDA
0x05
After Instruction
REG
WREG
Example2:
=
0xFF
=
0xFF
SETF
REG, 1
Before Instruction
Before Instruction
WREG
REG
101s
If 's' is 0, both the data memory location
'f' and WREG are set to FFh. If 's' is 1
only the data memory location 'f' is set
to FFh.
Q Cycle Activity:
Q1
Read
register 'f'
Example 1:
0010
Description:
Decode
Decode
WREG
REG
Encoding:
SETF f,s
1110 1011
1101 0111
REG
WREG
=
=
0xDA
0x05
After Instruction
REG
WREG
=
=
0xFF
0x05
1996 Microchip Technology Inc.
PIC17C4X
SLEEP
Enter SLEEP mode
SUBLW
Subtract WREG from Literal
Syntax:
[ label ] SLEEP
Syntax:
[ label ] SUBLW k
Operands:
None
Operands:
0 ≤ k ≤ 255
Operation:
00h → WDT;
0 → WDT postscaler;
1 → TO;
0 → PD
Operation:
k – (WREG) → (WREG)
Status Affected:
OV, C, DC, Z
Status Affected:
TO, PD
Encoding:
0000
Description:
0000
0000
1
Cycles:
1
Q Cycle Activity:
Q1
0010
kkkk
kkkk
Description:
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example 1:
Q2
Q3
Q4
Read
literal 'k'
Execute
Write to
WREG
SUBLW
0x02
Before Instruction
Decode
Example:
Q2
Q3
Q4
Read
register
PCLATH
Execute
NOP
SLEEP
Before Instruction
?
?
After Instruction
TO =
PD =
1011
WREG is subtracted from the eight bit
literal 'k'. The result is placed in
WREG.
0011
The power down status bit (PD) is
cleared. The time-out status bit (TO) is
set. Watchdog Timer and its prescaler
are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
Words:
TO =
PD =
Encoding:
1†
0
† If WDT causes wake-up, this bit is cleared
WREG
C
=
=
1
?
After Instruction
WREG
C
Z
=
=
=
1
1
0
; result is positive
Example 2:
Before Instruction
WREG
C
=
=
2
?
After Instruction
WREG
C
Z
=
=
=
0
1
1
; result is zero
Example 3:
Before Instruction
WREG
C
=
=
3
?
After Instruction
WREG
C
Z
1996 Microchip Technology Inc.
=
=
=
FF ; (2’s complement)
0
; result is negative
1
DS30412C-page 135
PIC17C4X
SUBWF
Subtract WREG from f
Syntax:
[ label ] SUBWF f,d
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operation:
(f) – (W) → (dest)
Status Affected:
OV, C, DC, Z
Encoding:
0000
Description:
010d
ffff
Subtract WREG from register 'f' (2’s
complement method). If 'd' is 0 the
result is stored in WREG. If 'd' is 1 the
result is stored back in register 'f'.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register 'f'
Execute
Write to
destination
Example 1:
SUBWF
REG1, 1
Before Instruction
REG1
WREG
C
=
=
=
=
=
=
=
1
2
1
0
=
=
=
=
=
=
=
=
DS30412C-page 136
0000
Description:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
001d
ffff
ffff
Subtract WREG and the carry flag
(borrow) from register 'f' (2’s complement method). If 'd' is 0 the result is
stored in WREG. If 'd' is 1 the result is
stored back in register 'f'.
Words:
REG1
WREG
C
Z
REG1
WREG
C
Z
Example3:
1
2
?
FF
2
0
0
OV, C, DC, Z
Encoding:
Q2
Q3
Q4
Read
register 'f'
Execute
Write to
destination
SUBWFB
REG1, 1
=
=
=
0x19
0x0D
1
(0001 1001)
(0000 1101)
=
=
=
=
0x0C
0x0D
1
0
(0000 1011)
(0000 1101)
; result is positive
SUBWFB
REG1,0
=
=
=
0x1B
0x1A
0
(0001 1011)
(0001 1010)
0x1B
0x00
1
1
(0001 1011)
After Instruction
; result is zero
=
=
=
=
SUBWFB
; result is zero
REG1,1
Before Instruction
REG1
WREG
C
After Instruction
REG1
WREG
C
Z
Status Affected:
REG1
WREG
C
Before Instruction
=
=
=
(f) – (W) – C → (dest)
Before Instruction
Example 3:
REG1
WREG
C
Operation:
Example2:
2
2
?
0
2
1
1
0 ≤ f ≤ 255
d ∈ [0,1]
After Instruction
; result is positive
After Instruction
REG1
WREG
C
Z
[ label ] SUBWFB f,d
REG1
WREG
C
Before Instruction
=
=
=
Syntax:
Operands:
Before Instruction
Example 2:
REG1
WREG
C
Subtract WREG from f with
Borrow
Example 1:
3
2
?
After Instruction
REG1
WREG
C
Z
ffff
SUBWFB
=
=
=
0x03
0x0E
1
(0000 0011)
(0000 1101)
0xF5
0x0E
0
0
(1111 0100) [2’s comp]
(0000 1101)
; result is negative
After Instruction
; result is negative
REG1
WREG
C
Z
=
=
=
=
1996 Microchip Technology Inc.
PIC17C4X
SWAPF
Swap f
TABLRD
Table Read
Syntax:
[ label ] SWAPF f,d
Syntax:
[ label ] TABLRD t,i,f
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
Operands:
Operation:
f<3:0> → dest<7:4>;
f<7:4> → dest<3:0>
0 ≤ f ≤ 255
i ∈ [0,1]
t ∈ [0,1]
Operation:
Status Affected:
None
If t = 1,
TBLATH → f;
If t = 0,
TBLATL → f;
Prog Mem (TBLPTR) → TBLAT;
If i = 1,
TBLPTR + 1 → TBLPTR
Status Affected:
None
Encoding:
0001
110d
ffff
ffff
Description:
The upper and lower nibbles of register
'f' are exchanged. If 'd' is 0 the result is
placed in WREG. If 'd' is 1 the result is
placed in register 'f'.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Encoding:
Description:
Q2
Q3
Q4
Read
register 'f'
Execute
Write to
destination
Example:
SWAPF
REG,
1010
1.
2.
0
Before Instruction
REG
=
0x53
3.
After Instruction
REG
=
0x35
ffff
1
Cycles:
2 (3 cycle if f = PCL)
Decode
ffff
A byte of the table latch (TBLAT)
is moved to register file 'f'.
If t = 0: the high byte is moved;
If t = 1: the low byte is moved
Then the contents of the program
memory location pointed to by
the
16-bit
Table
Pointer
(TBLPTR) is loaded into the
16-bit Table Latch (TBLAT).
If i = 1: TBLPTR is incremented;
If i = 0: TBLPTR is not
incremented
Words:
Q Cycle Activity:
Q1
1996 Microchip Technology Inc.
10ti
Q2
Q3
Q4
Read
register
TBLATH or
TBLATL
Execute
Write
register 'f'
DS30412C-page 137
PIC17C4X
TABLRD
Table Read
Example1:
TABLRD
1, 1, REG ;
Before Instruction
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0x1234
TABLWT
Table Write
Syntax:
[ label ] TABLWT t,i,f
Operands:
0 ≤ f ≤ 255
i ∈ [0,1]
t ∈ [0,1]
Operation:
If t = 0,
f → TBLATL;
If t = 1,
f → TBLATH;
TBLAT → Prog Mem (TBLPTR);
If i = 1,
TBLPTR + 1 → TBLPTR
Status Affected:
None
After Instruction (table write completion)
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
Example2:
TABLRD
=
=
=
=
=
0xAA
0x12
0x34
0xA357
0x5678
0, 0, REG ;
Before Instruction
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0x1234
Encoding:
Description:
1010
1.
2.
After Instruction (table write completion)
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
=
=
=
=
=
0x55
0x12
0x34
0xA356
0x1234
Note:
ffff
ffff
The MCLR/VPP pin must be at the programming
voltage for successful programming of internal
memory.
If MCLR/VPP = VDD
the programming sequence of internal memory
will be executed, but will not be successful
(although the internal memory location may be
disturbed)
3.
The TBLPTR can be automatically incremented
If i = 0; TBLPTR is not
incremented
If i = 1; TBLPTR is incremented
Words:
1
Cycles:
2 (many if write is to on-chip
EPROM program memory)
Q Cycle Activity:
Q1
Decode
DS30412C-page 138
11ti
Load value in ’f’ into 16-bit table
latch (TBLAT)
If t = 0: load into low byte;
If t = 1: load into high byte
The contents of TBLAT is written
to the program memory location
pointed to by TBLPTR
If TBLPTR points to external
program memory location, then
the instruction takes two-cycle
If TBLPTR points to an internal
EPROM location, then the
instruction is terminated when
an interrupt is received.
Q2
Q3
Q4
Read
register 'f'
Execute
Write
register
TBLATH or
TBLATL
1996 Microchip Technology Inc.
PIC17C4X
TABLWT
Table Write
Example1:
TABLWT
0, 1, REG
Before Instruction
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0xFFFF
TLRD
Table Latch Read
Syntax:
[ label ] TLRD t,f
Operands:
0 ≤ f ≤ 255
t ∈ [0,1]
Operation:
If t = 0,
TBLATL → f;
If t = 1,
TBLATH → f
Status Affected:
None
After Instruction (table write completion)
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR - 1)
Example 2:
TABLWT
=
=
=
=
=
0x53
0x53
0x55
0xA357
0x5355
Encoding:
1010
0x53
0xAA
0x55
0xA356
0xFFFF
After Instruction (table write completion)
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
Program
Memory
=
=
=
=
=
15
0x53
0xAA
0x53
0xA356
0xAA53
0
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Data
Memory
ffff
Read data from 16-bit table latch
(TBLAT) into file register 'f'. Table Latch
is unaffected.
If t = 1; high byte is read
If t = 0; low byte is read
This instruction is used in conjunction
with TABLRD to transfer data from program memory to data memory.
Before Instruction
=
=
=
=
=
ffff
Description:
1, 0, REG
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
00tx
Q2
Q3
Q4
Read
register
TBLATH or
TBLATL
Execute
Write
register 'f'
Example:
TLRD
t, RAM
Before Instruction
TBLPTR
15
16 bits
8
7
TBLAT
t
RAM
TBLAT
0
8 bits
=
=
=
0
?
0x00AF
(TBLATH = 0x00)
(TBLATL = 0xAF)
After Instruction
RAM
TBLAT
=
=
0xAF
0x00AF
(TBLATH = 0x00)
(TBLATL = 0xAF)
Before Instruction
t
RAM
TBLAT
=
=
=
1
?
0x00AF
(TBLATH = 0x00)
(TBLATL = 0xAF)
After Instruction
RAM
TBLAT
Program
Memory
=
=
0x00
0x00AF
(TBLATH = 0x00)
(TBLATL = 0xAF)
15
0
Data
Memory
TBLPTR
15
16 bits
1996 Microchip Technology Inc.
8
7
TBLAT
0
8 bits
DS30412C-page 139
PIC17C4X
TLWT
Table Latch Write
TSTFSZ
Test f, skip if 0
Syntax:
[ label ] TLWT t,f
Syntax:
[ label ] TSTFSZ f
Operands:
0 ≤ f ≤ 255
t ∈ [0,1]
Operands:
0 ≤ f ≤ 255
Operation:
skip if f = 0
Operation:
If t = 0,
f → TBLATL;
If t = 1,
f → TBLATH
Status Affected:
None
Encoding:
0011
0011
ffff
ffff
Description:
If 'f' = 0, the next instruction, fetched
during the current instruction execution,
is discarded and an NOP is executed
making this a two-cycle instruction.
Data from file register 'f' is written into
the 16-bit table latch (TBLAT).
If t = 1; high byte is written
If t = 0; low byte is written
This instruction is used in conjunction
with TABLWT to transfer data from data
memory to program memory.
Words:
1
Cycles:
1 (2)
Words:
1
If skip:
Cycles:
1
Status Affected:
None
Encoding:
1010
Description:
Q Cycle Activity:
Q1
Decode
01tx
ffff
ffff
Q2
Q3
Q4
Read
register 'f'
Execute
Write
register
TBLATH or
TBLATL
Example:
TLWT
t, RAM
Before Instruction
t
RAM
TBLAT
=
=
=
0
0xB7
0x0000
(TBLATH = 0x00)
(TBLATL = 0x00)
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register 'f'
Execute
NOP
Q1
Q2
Q3
Q4
Forced NOP
NOP
Execute
NOP
Example:
HERE
NZERO
ZERO
TSTFSZ
:
CNT
:
Before Instruction
PC = Address(HERE)
After Instruction
If CNT
PC
If CNT
PC
=
=
≠
=
0x00,
Address (ZERO)
0x00,
Address (NZERO)
After Instruction
RAM
TBLAT
=
=
0xB7
0x00B7
(TBLATH = 0x00)
(TBLATL = 0xB7)
Before Instruction
t
RAM
TBLAT
=
=
=
1
0xB7
0x0000
(TBLATH = 0x00)
(TBLATL = 0x00)
After Instruction
RAM
TBLAT
=
=
DS30412C-page 140
0xB7
0xB700
(TBLATH = 0xB7)
(TBLATL = 0x00)
1996 Microchip Technology Inc.
PIC17C4X
XORLW
Exclusive OR Literal with
WREG
XORWF
Exclusive OR WREG with f
Syntax:
[ label ] XORWF
Syntax:
[ label ] XORLW k
Operands:
Operands:
0 ≤ k ≤ 255
0 ≤ f ≤ 255
d ∈ [0,1]
Operation:
(WREG) .XOR. k → (WREG)
Operation:
(WREG) .XOR. (f) → (dest)
Status Affected:
Z
Status Affected:
Z
Encoding:
1011
0100
kkkk
kkkk
Description:
The contents of WREG are XOR’ed
with the 8-bit literal 'k'. The result is
placed in WREG.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Example:
Q2
Q3
Q4
Read
literal 'k'
Execute
Write to
WREG
XORLW
=
=
110d
ffff
ffff
Description:
Exclusive OR the contents of WREG
with register 'f'. If 'd' is 0 the result is
stored in WREG. If 'd' is 1 the result is
stored back in the register 'f'.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read
register 'f'
Execute
Write to
destination
Example:
0xB5
After Instruction
WREG
0000
0xAF
Before Instruction
WREG
Encoding:
f,d
0x1A
XORWF
REG, 1
Before Instruction
REG
WREG
=
=
0xAF
0xB5
After Instruction
REG
WREG
1996 Microchip Technology Inc.
=
=
0x1A
0xB5
DS30412C-page 141
PIC17C4X
NOTES:
DS30412C-page 142
1996 Microchip Technology Inc.
PIC17C4X
16.0
DEVELOPMENT SUPPORT
16.1
Development Tools
The PIC16/17 microcontrollers are supported with a full
range of hardware and software development tools:
• PICMASTER/PICMASTER CE Real-Time
In-Circuit Emulator
• ICEPIC Low-Cost PIC16C5X and PIC16CXXX
In-Circuit Emulator
• PRO MATE II Universal Programmer
• PICSTART Plus Entry-Level Prototype
Programmer
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
• MPLAB-SIM Software Simulator
• MPLAB-C (C Compiler)
• Fuzzy logic development system (fuzzyTECH−MP)
16.2
PICMASTER: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
16.3
ICEPIC: Low-cost PIC16CXXX
In-Circuit Emulator
ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC16C5X and PIC16CXXX families of 8-bit
OTP microcontrollers.
ICEPIC is designed to operate on PC-compatible
machines ranging from 286-AT through Pentium
based machines under Windows 3.x environment.
ICEPIC features real time, non-intrusive emulation.
16.4
PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone
mode as well as PC-hosted mode.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC16C5X, PIC16CXXX, PIC17CXX and
PIC14000 devices. It can also set configuration and
code-protect bits in this mode.
The PICMASTER Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX and PIC17CXX families.
PICMASTER is supplied with the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
16.5
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different processors. The universal architecture of the PICMASTER
allows expansion to support all new Microchip microcontrollers.
PICSTART Plus supports all PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX and PIC17CXX devices with
up to 40 pins. Larger pin count devices such as the
PIC16C923 and PIC16C924 may be supported with an
adapter socket.
PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is
not recommended for production programming.
The PICMASTER Emulator System has been
designed as a real-time emulation system with
advanced features that are generally found on more
expensive development tools. The PC compatible 386
(and higher) machine platform and Microsoft Windows
3.x environment were chosen to best make these features available to you, the end user.
A CE compliant version of PICMASTER is available for
European Union (EU) countries.
1996 Microchip Technology Inc.
DS30412C-page 143
This document was created with FrameMaker 4 0 4
PIC17C4X
16.6
PICDEM-1 Low-Cost PIC16/17
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-16B programmer, and easily test firmware. The user can also connect the PICDEM-1
board to the PICMASTER emulator and download
the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
16.7
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-16C, and easily test firmware.
The PICMASTER emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding additional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
16.8
PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the necessary hardware and software is included to run the
basic demonstration programs. The user can program the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and
easily test firmware. The PICMASTER emulator may
also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features
DS30412C-page 144
include an RS-232 interface, push-button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM-3 board is an LCD panel, with 4 commons
and 12 segments, that is capable of displaying time,
temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1
software for showing the demultiplexed LCD signals on
a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
PICDEM-3 will be available in the 3rd quarter of 1996.
16.9
MPLAB Integrated Development
Environment Software
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application
which contains:
• A full featured editor
• Three operating modes
- editor
- emulator
- simulator
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PIC16/17 tools (automatically updates all
project information)
• Debug using:
- source files
- absolute listing file
• Transfer data dynamically via DDE (soon to be
replaced by OLE)
• Run up to four emulators on the same PC
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
16.10
Assembler (MPASM)
The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX, and PIC17CXX families.
MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
1996 Microchip Technology Inc.
PIC17C4X
MPASM allow full symbolic debugging from the
Microchip
Universal
Emulator
System
(PICMASTER).
Both versions include Microchip’s fuzzyLAB demonstration board for hands-on experience with fuzzy logic
systems implementation.
MPASM has the following features to assist in developing software for specific use applications.
16.14
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol,
and special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal
source and listing formats.
MPASM provides a rich directive language to support
programming of the PIC16/17. Directives are helpful in
making the development of your assemble source
code shorter and more maintainable.
16.11
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C and MPASM. The Software Simulator offers
the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
C Compiler (MPLAB-C)
The MPLAB-C Code Development System is a
complete ‘C’ compiler and integrated development
environment for Microchip’s PIC16/17 family of microcontrollers. The compiler provides powerful integration
capabilities and ease of use not found with other
compilers.
For easier source level debugging, the compiler provides symbol information that is compatible with the
MPLAB IDE memory display (PICMASTER emulator
software versions 1.13 and later).
16.13
MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can
visually configure all the peripherals in a PIC16/17
device and, with a click of the mouse, generate all the
initialization and many functional code modules in C
language. The output is fully compatible with Microchip’s MPLAB-C C compiler. The code produced is
highly modular and allows easy integration of your own
code. MP-DriveWay is intelligent enough to maintain
your code through subsequent code generation.
16.15
SEEVAL Evaluation and
Programming System
Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PIC16/17 series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The input/
output radix can be set by the user and the execution
can be performed in; single step, execute until break,
or in a trace mode.
16.12
MP-DriveWay – Application Code
Generator
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
16.16
TrueGauge Intelligent Battery
Management
The TrueGauge development tool supports system
development with the MTA11200B TrueGauge Intelligent Battery Management IC. System design verification can be accomplished before hardware prototypes
are built. User interface is graphically-oriented and
measured data can be saved in a file for exporting to
Microsoft Excel.
16.17
KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
Fuzzy Logic Development System
(fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, edition for implementing more complex systems.
1996 Microchip Technology Inc.
DS30412C-page 145
DS30412C-page 146
SW006005
SW006005
SW006005
SW007002
SW007002
SW007002
SW007002
PIC16C61
PIC16C62, 62A,
64, 64A
PIC16C620, 621, 622
SW006005
SW007002
SW007002
SW007002
SW007002
SW007002
SW007002
SW007002
SW007002
PIC16C71
PIC16C710, 711
PIC16C72
PIC16F83
PIC16C84
PIC16F84
PIC16C923, 924*
SW006006
SW006006
SW006006
SW006006
SW006006
SW006006
SW006006
—
SW006006
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
—
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
DV005001/
DV005002
—
—
fuzzyTECH-MP
Explorer/Edition
Fuzzy Logic
Dev. Tool
—
Product
All 2 wire and 3 wire
Serial EEPROM's
MTA11200B
HCS200, 300, 301 *
SEEVAL Designers Kit
DV243001
N/A
N/A
TRUEGAUGE Development Kit
N/A
DV114001
N/A
PIC17C42,
SW007002
SW006005
SW006006
42A, 43, 44
*Contact Microchip Technology for availability date
**MPLAB Integrated Development Environment includes MPLAB-SIM Simulator and
MPASM Assembler
SW006005
SW006005
SW006005
SW006005
SW006005
SW006005
SW006005
SW006005
SW007002
PIC16C63, 65, 65A,
73, 73A, 74, 74A
PIC16C642, 662*
SW006006
SW006006
SW006006
—
SW006006
—
MP-DriveWay
Applications
Code
Generator
—
N/A
PG306001
Hopping Code Security Programmer Kit
N/A
N/A
DM303001
Hopping Code Security Eval/Demo Kit
N/A
****PRO MATE PICSTART Lite PICSTART Plus
*** PICMASTER/
ICEPIC
Low-Cost
PICMASTER-CE
Ultra Low-Cost
Low-Cost
II Universal
In-Circuit
In-Circuit
Dev. Kit
Universal
Microchip
Emulator
Emulator
Dev. Kit
Programmer
EM167015/
—
DV007003
—
DV003001
EM167101
EM147001/
—
DV007003
—
DV003001
EM147101
EM167015/
EM167201
DV007003
DV162003
DV003001
EM167101
EM167033/
—DV007003
—
DV003001
EM167113
EM167021/
EM167205
DV007003
DV162003
DV003001
N/A
EM167025/
EM167203
DV007003
DV162002
DV003001
EM167103
EM167023/
EM167202
DV007003
DV162003
DV003001
EM167109
EM167025/
EM167204
DV007003
DV162002
DV003001
EM167103
EM167035/
—DV007003
DV162002
DV003001
EM167105
EM167027/
EM167205
DV007003
DV162003
DV003001
EM167105
EM167027/
—
DV007003
DV162003
DV003001
EM167105
EM167025/
—
DV007003
DV162002
DV003001
EM167103
EM167029/
—
DV007003
DV162003
DV003001
EM167107
EM167029/
EM167206
DV007003
DV162003
DV003001
EM167107
EM167029/
—
DV007003
DV162003
DV003001
EM167107
EM167031/
—
DV007003
—
DV003001
EM167111
EM177007/
—
DV007003
—
DV003001
EM177107
***All PICMASTER and PICMASTER-CE ordering part numbers above include
PRO MATE II programmer
****PRO MATE socket modules are ordered separately. See development systems
ordering guide for specific ordering part numbers
TABLE 16-1:
SW006005
SW006005
SW007002
PIC16C52, 54, 54A,
55, 56, 57, 58A
PIC16C554, 556, 558
SW006005
SW006005
MPLAB C
Compiler
SW007002
** MPLAB
Integrated
Development
Environment
SW007002
PIC14000
PIC12C508, 509
Product
PIC17C4X
DEVELOPMENT TOOLS FROM MICROCHIP
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
17.0
PIC17C42 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias..................................................................................................................-55 to +125˚C
Storage temperature ............................................................................................................................... -65˚C to +150˚C
Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ..........................................................................................-0.6V to +14V
Voltage on RA2 and RA3 with respect to VSS..............................................................................................-0.6V to +12V
Voltage on all other pins with respect to VSS ..................................................................................... -0.6V to VDD + 0.6V
Total power dissipation (Note 1).................................................................................................................................1.0W
Maximum current out of VSS pin(s) - Total .............................................................................................................250 mA
Maximum current into VDD pin(s) - Total ................................................................................................................200 mA
Input clamp current, IIK (VI < 0 or VI > VDD) ......................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ...............................................................................................................±20 mA
Maximum output current sunk by any I/O pin (except RA2 and RA3)......................................................................35 mA
Maximum output current sunk by RA2 or RA3 pins .................................................................................................60 mA
Maximum output current sourced by any I/O pin .....................................................................................................20 mA
Maximum current sunk by PORTA and PORTB (combined)..................................................................................150 mA
Maximum current sourced by PORTA and PORTB (combined).............................................................................100 mA
Maximum current sunk by PORTC, PORTD and PORTE (combined)...................................................................150 mA
Maximum current sourced by PORTC, PORTD and PORTE (combined)..............................................................100 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a "low" level to the MCLR pin rather than
pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1996 Microchip Technology Inc.
DS30412C-page 147
This document was created with FrameMaker 4 0 4
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
TABLE 17-1:
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
OSC
RC
XT
EC
LF
PIC17C42-16
VDD:
IDD:
IPD:
Freq:
VDD:
IDD:
IPD:
Freq:
VDD:
IDD:
IPD:
Freq:
VDD:
IDD:
IPD:
Freq:
DS30412C-page 148
4.5V to 5.5V
6 mA max.
5 µA max. at 5.5V (WDT disabled)
4 MHz max.
4.5V to 5.5V
24 mA max.
5 µA max. at 5.5V (WDT disabled)
16 MHz max.
4.5V to 5.5V
24 mA max.
5 µA max. at 5.5V (WDT disabled)
16 MHz max.
4.5V to 5.5V
150 µA max. at 32 kHz (WDT enabled)
5 µA max. at 5.5V (WDT disabled)
2 MHz max.
PIC17C42-25
VDD:
IDD:
IPD:
Freq:
VDD:
IDD:
IPD:
Freq:
VDD:
IDD:
IPD:
Freq:
VDD:
IDD:
IPD:
Freq:
4.5V to 5.5V
6 mA max.
5 µA max. at 5.5V (WDT disabled)
4 MHz max.
4.5V to 5.5V
38 mA max.
5 µA max. at 5.5V (WDT disabled)
25 MHz max.
4.5V to 5.5V
38 mA max.
5 µA max. at 5.5V (WDT disabled)
25 MHz max.
4.5V to 5.5V
150 µA max. at 32 kHz (WDT enabled)
5 µA max. at 5.5V (WDT disabled)
2 MHz max.
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
17.1
DC CHARACTERISTICS:
DC CHARACTERISTICS
Parameter
No.
Sym
D001
D002
VDD
VDR
D003
VPOR
D004
SVDD
D010
D011
D012
D013
D014
IDD
Characteristic
Supply Voltage
RAM Data Retention
Voltage (Note 1)
VDD start voltage to
ensure internal
Power-on Reset signal
VDD rise rate to
ensure internal
Power-on Reset signal
Supply Current
(Note 2)
PIC17C42-16 (Commercial, Industrial)
PIC17C42-25 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Min
Typ† Max
Units
4.5
1.5 *
–
–
5.5
–
V
V
–
VSS
–
V
0.060*
–
–
–
–
–
–
–
3
6
11
19
95
6
12 *
24 *
38
150
Conditions
Device in SLEEP mode
See section on Power-on Reset for
details
mV/ms See section on Power-on Reset for
details
mA
mA
mA
mA
µA
FOSC = 4 MHz (Note 4)
FOSC = 8 MHz
FOSC = 16 MHz
FOSC = 25 MHz
FOSC = 32 kHz
WDT enabled (EC osc configuration)
VDD = 5.5V, WDT enabled
VDD = 5.5V, WDT disabled
D020
IPD
Power-down Current
–
10
40
µA
D021
(Note 3)
–
<1
5
µA
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD or VSS, T0CKI = VDD,
MCLR = VDD; WDT enabled/disabled as specified.
Current consumed from the oscillator and I/O’s driving external capacitive or resistive loads need to be considered.
For the RC oscillator, the current through the external pull-up resistor (R) can be estimated as: VDD / (2 • R).
For capacitive loads, The current can be estimated (for an individual I/O pin) as (CL • VDD) • f
CL = Total capacitive load on the I/O pin; f = average frequency on the I/O pin switches.
The capacitive currents are most significant when the device is configured for external execution (includes
extended microcontroller mode).
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
1996 Microchip Technology Inc.
DS30412C-page 149
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
17.2
DC CHARACTERISTICS:
PIC17C42-16 (Commercial, Industrial)
PIC17C42-25 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in Section 17.1
DC CHARACTERISTICS
Parameter
No.
Sym
VIL
D030
D031
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
with Schmitt Trigger buffer
MCLR, OSC1 (in EC and RC
mode)
OSC1 (in XT, and LF mode)
Input High Voltage
VIH
I/O ports
with TTL buffer
with Schmitt Trigger buffer
MCLR
OSC1 (XT, and LF mode)
VHYS Hysteresis of
Schmitt Trigger inputs
Input Leakage Current
(Notes 2, 3)
IIL
I/O ports (except RA2, RA3)
D032
D033
D040
D041
D042
D043
D050
D060
Min
Typ†
Max
Units
VSS
VSS
–
–
0.8
0.2VDD
V
V
Vss
–
0.2VDD
V
–
0.5VDD
–
V
VDD
VDD
VDD
–
–
V
V
V
V
V
–
2.0
–
0.8VDD
–
0.8VDD
–
–
0.5VDD
0.15VDD*
–
Conditions
Note1
Note1
–
–
±1
µA
Vss ≤ VPIN ≤ VDD,
I/O Pin at hi-impedance
PORTB weak pull-ups disabled
–
–
±2
µA
VPIN = Vss or VPIN = VDD
D061
MCLR
D062
RA2, RA3
±2
µA
Vss ≤ VRA2, VRA3 ≤ 12V
D063
OSC1, TEST
–
–
±1
µA
Vss ≤ VPIN ≤ VDD
D064
MCLR
–
–
10
µA
VMCLR = VPP = 12V
(when not programming)
D070
*
†
‡
††
Note 1:
2:
3:
4:
5:
6:
60
200
400
µA VPIN = VSS, RBPU = 0
IPURB PORTB weak pull-up current
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
These parameters are for design guidance only and are not tested, nor characterized.
Design guidance to attain the AC timing specifications. These loads are not tested.
In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXX devices be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17CXX Programming
Specifications (Literature number DS30139).
The MCLR/Vpp pin may be kept in this range at times other than programming, but this is not recommended.
For TTL buffers, the better of the two specifications may be used.
DS30412C-page 150
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in Section 17.1
DC CHARACTERISTICS
Parameter
No.
Sym
D080
D081
VOL
D082
D083
Characteristic
Min
Typ†
Max
Units
Output Low Voltage
I/O ports (except RA2 and RA3)
with TTL buffer
–
–
–
–
0.1VDD
0.4
V
V
RA2 and RA3
–
OSC2/CLKOUT
–
(RC and EC osc modes)
Output High Voltage (Note 3)
I/O ports (except RA2 and RA3) 0.9VDD
with TTL buffer
2.4
–
–
3.0
0.4
V
V
–
–
–
–
V
V
D092
RA2 and RA3
–
–
12
V
D093
OSC2/CLKOUT
(RC and EC osc modes)
Capacitive Loading Specs on
Output Pins
OSC2 pin
2.4
–
–
V
–
–
25 ††
pF
All I/O pins and OSC2
(in RC mode)
System Interface Bus
(PORTC, PORTD and PORTE)
–
–
50 ††
pF
–
–
100 ††
pF
D090
D091
VOH
D100
COSC2
D101
CIO
D102
CAD
*
†
‡
††
Note 1:
2:
3:
4:
5:
6:
Conditions
IOL = 4 mA
IOL = 6 mA, VDD = 4.5V
Note 6
IOL = 60.0 mA, VDD = 5.5V
IOL = 2 mA, VDD = 4.5V
IOH = -2 mA
IOH = -6.0 mA, VDD = 4.5V
Note 6
Pulled-up to externally applied
voltage
IOH = -5 mA, VDD = 4.5V
In EC or RC osc modes when
OSC2 pin is outputting
CLKOUT.
External clock is used to drive
OSC1.
In Microprocessor or
Extended Microcontroller
mode
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
These parameters are for design guidance only and are not tested, nor characterized.
Design guidance to attain the AC timing specifications. These loads are not tested.
In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXX devices be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17CXX Programming
Specifications (Literature number DS30139).
The MCLR/Vpp pin may be kept in this range at times other than programming, but this is not recommended.
For TTL buffers, the better of the two specifications may be used.
1996 Microchip Technology Inc.
DS30412C-page 151
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +40˚C
Operating voltage VDD range as described in Section 17.1
DC CHARACTERISTICS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
12.75
4.75
–
5.0
13.25
5.25
V
V
–
–
25 ‡
–
50 ‡
30 ‡
mA
mA
10
100
1000
µs Terminated via internal/external interrupt or a reset
Internal Program Memory
Programming Specs (Note 4)
VPP Voltage on MCLR/VPP pin
VDDP Supply voltage during
programming
Current into MCLR/VPP pin
IPP
IDDP Supply current during
programming
TPROG Programming pulse width
D110
D111
D112
D113
D114
*
†
‡
Note 1:
2:
3:
4:
5:
6:
Note:
Note 5
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
These parameters are for design guidance only and are not tested, nor characterized.
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXX devices be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17CXX Programming
Specifications (Literature number DS30139).
The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
For TTL buffers, the better of the two specifications may be used.
When using the Table Write for internal programming, the device temperature must be less than 40˚C.
DS30412C-page 152
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
17.3
Timing Parameter Symbology
The timing parameter symbols have been created using one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase symbols (pp) and their meanings:
pp
ad
Address/Data
al
ALE
cc
Capture1 and Capture2
ck
CLKOUT or clock
dt
Data in
in
INT pin
io
I/O port
mc
MCLR
oe
OE
os
OSC1
Uppercase symbols and their meanings:
S
D
Driven
E
Edge
F
Fall
H
High
I
Invalid (Hi-impedance)
1996 Microchip Technology Inc.
T
Time
ost
pwrt
rb
rd
rw
t0
t123
wdt
wr
Oscillator Start-up Timer
Power-up Timer
PORTB
RD
RD or WR
T0CKI
TCLK12 and TCLK3
Watchdog Timer
WR
L
P
R
V
Z
Low
Period
Rise
Valid
Hi-impedance
DS30412C-page 153
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 17-1: PARAMETER MEASUREMENT INFORMATION
All timings are measure between high and low measurement points as indicated in the figures below.
INPUT LEVEL CONDITIONS
PORTC, D and E pins
VIH = 2.4V
VIL = 0.4V
Data in valid
All other input pins
Data in invalid
VIH = 0.9VDD
VIL = 0.1VDD
Data in valid
Data in invalid
OUTPUT LEVEL CONDITIONS
0.25V
VOH = 0.7VDD
VDD/2
VOL = 0.3VDD
0.25V
0.25V
0.25V
Data out valid
Data out invalid
Output
driven
Output
hi-impedance
0.9VDD
0.1VDD
Rise Time
Fall Time
LOAD CONDITIONS
Load Condition 1
Load Condition 2
VDD/2
RL
Pin
Pin
CL
CL
VSS
VSS
RL = 464
CL ≤ 50 pF
DS30412C-page 154
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
17.4
Timing Diagrams and Specifications
FIGURE 17-2: EXTERNAL CLOCK TIMING
Q4
Q1
Q3
Q2
Q4
Q1
OSC1
1
3
3
4
4
2
OSC2 †
† In EC and RC modes only.
TABLE 17-2:
Parameter
No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
Fosc
1
Tosc
Characteristic
External CLKIN Frequency
(Note 1)
Oscillator Frequency
(Note 1)
External CLKIN Period
(Note 1)
Oscillator Period
(Note 1)
2
3
Min
Typ†
Max
Units
Conditions
DC
DC
—
—
16
25
MHz
MHz
EC osc mode - PIC17C42-16
- PIC17C42-25
DC
1
1
DC
62.5
40
250
62.5
40
500
160
10 ‡
—
—
—
—
—
—
—
—
—
—
4/Fosc
—
4
16
25
2
—
—
—
1,000
1,000
—
DC
—
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
RC osc mode
XT osc mode - PIC17C42-16
- PIC17C42-25
LF osc mode
EC osc mode - PIC17C42-16
- PIC17C42-25
RC osc mode
XT osc mode - PIC17C42-16
- PIC17C42-25
LF osc mode
TCY Instruction Cycle Time (Note 1)
TosL, Clock in (OSC1) High or Low Time
EC oscillator
TosH
4
TosR, Clock in (OSC1) Rise or Fall Time
—
—
5‡
ns
EC oscillator
TosF
†
Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
‡
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1 pin.
When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices.
1996 Microchip Technology Inc.
DS30412C-page 155
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 17-3: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
22
23
OSC2 †
13
12
14
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
† In EC and RC modes only.
TABLE 17-3:
Parameter
No.
CLKOUT AND I/O TIMING REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
10
TosH2ckL
OSC1↑ to CLKOUT↓
—
15 ‡
30 ‡
ns
Note 1
11
TosH2ckH
OSC1↑ to CLKOUT↑
—
15 ‡
30 ‡
ns
Note 1
12
TckR
CLKOUT rise time
—
5‡
15 ‡
ns
Note 1
13
TckF
CLKOUT fall time
—
5‡
15 ‡
ns
Note 1
Note 1
14
TckH2ioV
CLKOUT↑ to Port out valid
15
TioV2ckH
Port in valid before CLKOUT↑
—
—
0.5TCY + 20‡
ns
0.25TCY + 25 ‡
—
—
ns
16
TckH2ioI
Note 1
Port in hold after CLKOUT↑
0‡
—
—
ns
Note 1
17
TosH2ioV
OSC1↑ (Q1 cycle) to Port out valid
—
—
100 ‡
ns
20
TioR
Port output rise time
—
10 ‡
35 ‡
ns
21
TioF
Port output fall time
—
10 ‡
35 ‡
ns
22
TinHL
INT pin high or low time
25 *
—
—
ns
23
TrbHL
RB7:RB0 change INT high or low time
25 *
—
—
ns
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
‡
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: Measurements are taken in EC Mode where OSC2 output = 4 x TOSC = TCY.
DS30412C-page 156
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
35
Address /
Data
TABLE 17-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym
30
TmcL
MCLR Pulse Width (low)
31
Twdt
Watchdog Timer Time-out Period
(Prescale = 1)
32
Tost
33
Tpwrt
35
*
†
‡
§
Characteristic
Min
TmcL2adI MCLR to System Interface bus
(AD15:AD0) invalid
Max
Units
100 *
—
—
ns
5*
12
25 *
ms
Oscillation Start-up Timer Period
Power-up Timer Period
Typ†
1024 TOSC §
ms
40 *
96
200 *
ms
—
—
100 *
ns
Conditions
TOSC = OSC1 period
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
These parameters are for design guidance only and are not tested, nor characterized.
This specification ensured by design.
1996 Microchip Technology Inc.
DS30412C-page 157
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 17-5: TIMER0 CLOCK TIMINGS
RA1/T0CKI
40
41
42
TABLE 17-5:
Parameter
No.
TIMER0 CLOCK REQUIREMENTS
Sym Characteristic
40
Tt0H T0CKI High Pulse Width
41
Tt0L T0CKI Low Pulse Width
42
Tt0P T0CKI Period
*
Min
No Prescaler
With Prescaler
No Prescaler
With Prescaler
Typ† Max Units Conditions
0.5TCY + 20 §
10*
0.5TCY + 20 §
10*
TCY + 40 §
N
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
N = prescale value
(1, 2, 4, ..., 256)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification ensured by design.
†
§
FIGURE 17-6: TIMER1, TIMER2, AND TIMER3 CLOCK TIMINGS
TCLK12
or
TCLK3
46
45
47
48
48
TMRx
TABLE 17-6:
TIMER1, TIMER2, AND TIMER3 CLOCK REQUIREMENTS
Parameter
No.
Sym
45
46
47
Tt123H
Tt123L
Tt123P
48
*
†
§
Characteristic
TCLK12 and TCLK3 high time
TCLK12 and TCLK3 low time
TCLK12 and TCLK3 input period
Min
0.5 TCY + 20 §
0.5 TCY + 20 §
TCY + 40 §
N
2TOSC §
Typ
†
Max
—
—
—
—
—
—
Units Conditions
ns
ns
ns
N = prescale value
(1, 2, 4, 8)
TckE2tmrI Delay from selected External Clock Edge to
— 6 Tosc § —
Timer increment
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification ensured by design.
DS30412C-page 158
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 17-7: CAPTURE TIMINGS
CAP1
and CAP2
(Capture Mode)
50
51
52
TABLE 17-7:
Parameter
No.
50
51
52
*
†
CAPTURE REQUIREMENTS
Sym Characteristic
Min
TccL Capture1 and Capture2 input low time
TccH Capture1 and Capture2 input high time
TccP Capture1 and Capture2 input period
10 *
10 *
Typ† Max Units Conditions
—
—
—
—
ns
ns
2 TCY §
N
—
—
ns
N = prescale value
(4 or 16)
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification ensured by design.
§
FIGURE 17-8: PWM TIMINGS
PWM1
and PWM2
(PWM Mode)
53
TABLE 17-8:
Parameter
No.
53
54
*
†
§
54
PWM REQUIREMENTS
Sym Characteristic
TccR PWM1 and PWM2 output rise time
TccF PWM1 and PWM2 output fall time
Min
—
—
Typ† Max Units Conditions
10 * 35 *§
10 * 35 *§
ns
ns
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification ensured by design.
1996 Microchip Technology Inc.
DS30412C-page 159
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 17-9: USART MODULE: SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RA5/TX/CK
pin
121
121
RA4/RX/DT
pin
120
TABLE 17-9:
Parameter
No.
120
†
122
SERIAL PORT SYNCHRONOUS TRANSMISSION REQUIREMENTS
Sym
Characteristic
TckH2dtV
SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid
Min
Typ†
Max
Units Conditions
—
—
65
ns
121
TckRF
Clock out rise time and fall time (Master
Mode)
—
10
35
ns
122
TdtRF
Data out rise time and fall time
—
10
35
ns
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 17-10: USART MODULE: SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RA5/TX/CK
pin
RA4/RX/DT
pin
125
126
TABLE 17-10: SERIAL PORT SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
†
Sym
Characteristic
Min
Typ†
Max
125
TdtV2ckL
SYNC RCV (MASTER & SLAVE)
Data hold before CK↓ (DT hold time)
15
—
—
Units Conditions
ns
126
TckL2dtl
Data hold after CK↓ (DT hold time)
15
—
—
ns
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30412C-page 160
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 17-11: MEMORY INTERFACE WRITE TIMING
Q1
Q2
Q3
Q4
Q2
Q1
OSC1
ALE
OE
151
WR
150
AD<15:0>
154
data out
addr out
addr out
152
153
TABLE 17-11: MEMORY INTERFACE WRITE REQUIREMENTS
Parameter
No.
*
†
§
Sym
Characteristic
Min
Typ†
Max
150
TadV2alL
AD<15:0> (address) valid to ALE↓
(address setup time)
151
TalL2adI
ALE↓ to address out invalid
(address hold time)
152
TadV2wrL
Data out valid to WR↓
(data setup time)
153
TwrH2adI
154
TwrL
Units Conditions
0.25Tcy - 30
—
—
ns
0
—
—
ns
0.25Tcy - 40
—
—
ns
WR↑ to data out invalid
(data hold time)
—
0.25TCY §
—
ns
WR pulse width
—
0.25TCY §
—
ns
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification is guaranteed by design.
1996 Microchip Technology Inc.
DS30412C-page 161
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 17-12: MEMORY INTERFACE READ TIMING
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
166
ALE
164
168
160
OE
165
AD<15:0>
Data in
Addr out
150
Addr out
162
151
WR
161
163
167
'1'
'1'
TABLE 17-12: MEMORY INTERFACE READ REQUIREMENTS
Parameter
No.
*
†
§
Sym
Characteristic
150
TadV2alL
AD<15:0> (address) valid to ALE↓
(address setup time)
151
TalL2adI
ALE↓ to address out invalid
(address hold time)
Min
Typ†
Max
Units Conditions
0.25Tcy - 30
—
—
ns
5*
—
—
ns
160
TadZ2oeL
AD<15:0> high impedance to OE↓
0*
—
—
ns
161
ToeH2adD
OE↑ to AD<15:0> driven
0.25Tcy - 15
—
—
ns
162
TadV2oeH
Data in valid before OE↑
(data setup time)
35
—
—
ns
163
ToeH2adI
OE↑to data in invalid (data hold time)
0
—
—
ns
164
TalH
ALE pulse width
—
0.25TCY §
—
ns
165
ToeL
OE pulse width
0.5Tcy - 35 §
—
—
ns
166
TalH2alH
ALE↑ to ALE↑ (cycle time)
—
TCY §
—
ns
167
Tacc
Address access time
—
—
0.75 TCY-40
ns
168
Toe
Output enable access time
(OE low to Data Valid)
—
—
0.5 TCY - 60
ns
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification guaranteed by design.
DS30412C-page 162
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
18.0
PIC17C42 DC AND AC CHARACTERISTICS
The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs
or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3σ ) and (mean - 3σ)
respectively where σ is standard deviation.
TABLE 18-1:
PIN CAPACITANCE PER PACKAGE TYPE
Typical Capacitance (pF)
Pin Name
40-pin DIP
44-pin PLCC
44-pin MQFP
44-pin TQFP
All pins, except MCLR,
VDD, and VSS
10
10
10
10
MCLR pin
20
20
20
20
FIGURE 18-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE
FOSC
FOSC (25°C)
Frequency normalized to +25°C
1.10
Rext ≥ 10 kΩ
Cext = 100 pF
1.08
1.06
1.04
1.02
1.00
VDD = 5.5V
0.98
0.96
0.94
VDD = 3.5V
0.92
0.90
0
10
20
25
30
40
50
60
70
T(°C)
1996 Microchip Technology Inc.
DS30412C-page 163
This document was created with FrameMaker 4 0 4
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 18-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
4.0
3.5
R = 10k
FOSC (MHz)
3.0
2.5
2.0
1.5
Cext = 22 pF, T = 25°C
1.0
0.5
R = 100k
0.0
4.0
4.5
5.0
5.5
6.0
6.5
6.0
6.5
VDD (Volts)
FIGURE 18-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
4.0
3.5
R = 3.3k
FOSC (MHz)
3.0
2.5
R = 5.1k
2.0
1.5
R = 10k
1.0
Cext = 100 pF, T = 25°C
0.5
R = 100k
0.0
4.0
4.5
5.0
5.5
VDD (Volts)
DS30412C-page 164
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 18-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
2.0
1.8
1.6
1.4
R = 3.3k
FOSC (MHz)
1.2
R = 5.1k
1.0
0.8
R = 10k
0.6
0.4
Cext = 300 pF, T = 25°C
0.2
R = 160k
0.0
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
TABLE 18-2:
RC OSCILLATOR FREQUENCIES
Cext
Rext
22 pF
10k
100k
3.3k
5.1k
10k
100k
3.3k
5.1k
10k
160k
100 pF
300 pF
1996 Microchip Technology Inc.
Average
Fosc @ 5V, 25°C
3.33 MHz
353 kHz
3.54 MHz
2.43 MHz
1.30 MHz
129 kHz
1.54 MHz
980 kHz
564 kHz
35 kHz
± 12%
± 13%
± 10%
± 14%
± 17%
± 10%
± 14%
± 12%
± 16%
± 18%
DS30412C-page 165
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 18-5: TRANSCONDUCTANCE (gm) OF LF OSCILLATOR vs. VDD
500
450
400
350
Max @ -40°C
gm(µA/V)
300
Typ @ 25°C
250
200
150
Min @ 85°C
100
50
0
2.5
3.0
3.5
4.0
4.5
5.5
5.0
6.0
VDD (Volts)
FIGURE 18-6: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR vs. VDD
20
18
Max @ -40°C
16
14
Typ @ 25°C
gm(mA/V)
12
10
8
6
Min @ 85°C
4
2
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30412C-page 166
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 18-7: TYPICAL IDD vs. FREQUENCY (EXTERNAL CLOCK 25°C)
100000
IDD (µA)
10000
1000
7.0V
6.5V
6.0V
5.5V
5.0V
4.5V
100
4.0V
10
10k
100k
1M
External Clock Frequency (Hz)
10M
100M
FIGURE 18-8: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK 125°C TO -40°C)
100000
IDD (µA)
10000
7.0V
6.5V
6.0V
5.5V
5.0V
1000
4.5V
4.0V
100
10k
100k
1M
10M
100M
External Clock Frequency (Hz)
1996 Microchip Technology Inc.
DS30412C-page 167
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 18-9: TYPICAL IPD vs. VDD WATCHDOG DISABLED 25°C
12
10
IPD(nA)
8
6
4
2
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VDD (Volts)
IPD(nA)
FIGURE 18-10: MAXIMUM IPD vs. VDD WATCHDOG DISABLED
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
Temp. = 85°C
Temp. = 70°C
Temp. = 0°C
4.0
4.5
5.0
5.5
6.0
Temp. = -40°C
6.5
7.0
VDD (Volts)
DS30412C-page 168
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 18-11: TYPICAL IPD vs. VDD WATCHDOG ENABLED 25°C
30
25
IPD(µA)
20
15
10
5
0
4.0
4.5
5.0
5.5
6.5
6.0
7.0
VDD (Volts)
FIGURE 18-12: MAXIMUM IPD vs. VDD WATCHDOG ENABLED
60
50
-40°C
70°C
IPD(µA)
40
0°C
85°C
30
20
10
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VDD (Volts)
1996 Microchip Technology Inc.
DS30412C-page 169
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 18-13: WDT TIMER TIME-OUT PERIOD vs. VDD
30
25
Max. 85°C
WDT Period (ms)
20
Max. 70°C
Min. 0°C
15
Typ. 25°C
10
Min. -40°C
5
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
2.5
3.0
VDD (Volts)
FIGURE 18-14: IOH vs. VOH, VDD = 3V
0
-2
IOH(mA)
-4
-6
Min @ 85°C
-8
Typ @ 25°C
-10
-12
-14
Max @ -40°C
-16
-18
0.0
0.5
1.0
1.5
2.0
VDD (Volts)
DS30412C-page 170
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 18-15: IOH vs. VOH, VDD = 5V
IOH(mA)
0
-5
-10
Min @ 85°C
-15
-20
Max @ -40°C
-25
Typ @ 25°C
-30
-35
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD (Volts)
FIGURE 18-16: IOL vs. VOL, VDD = 3V
30
Max. -40°C
25
Typ. 25°C
IOL(mA)
20
15
Min. +85°C
10
5
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VDD (Volts)
1996 Microchip Technology Inc.
DS30412C-page 171
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 18-17: IOL vs. VOL, VDD = 5V
90
80
70
IOH(mA)
Max @ -40°C
Typ @ 25°C
60
50
Min @ +85°C
40
30
20
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VDD (Volts)
FIGURE 18-18: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS (TTL) VS. VDD
2.0
1.8
Max (-40°C to +85°C)
1.6
VTH(Volts)
Typ @ 25°C
1.4
1.2
1.0
Min (-40°C to +85°C)
0.8
0.6
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30412C-page 172
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 18-19: VTH, VIL of I/O PINS (SCHMITT TRIGGER) VS. VDD
5.0
VIH, max (-40°C to +85°C)
4.5
VIH, typ (25°C)
4.0
VIH, min (-40°C to +85°C)
VIH, VIL(Volts)
3.5
3.0
VIL, max (-40°C to +85°C)
2.5
VIL, typ (25°C)
VIL, min (-40°C to +85°C)
2.0
1.5
1.0
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 18-20: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT
(IN XT AND LF MODES) vs. VDD
3.4
3.2
Typ (25°C)
3.0
Max (-40°C to +85°C)
VTH,(Volts)
2.8
2.6
2.4
2.2
2.0
Min (-40°C to +85°C)
1.8
1.6
1.4
1.2
1.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
1996 Microchip Technology Inc.
DS30412C-page 173
PIC17C4X
NOTES:
DS30412C-page 174
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
19.0
PIC17CR42/42A/43/R43/44 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias..................................................................................................................-55 to +125˚C
Storage temperature ............................................................................................................................... -65˚C to +150˚C
Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ..........................................................................................-0.6V to +14V
Voltage on RA2 and RA3 with respect to VSS..............................................................................................-0.6V to +14V
Voltage on all other pins with respect to VSS ..................................................................................... -0.6V to VDD + 0.6V
Total power dissipation (Note 1).................................................................................................................................1.0W
Maximum current out of VSS pin(s) - total ..............................................................................................................250 mA
Maximum current into VDD pin(s) - total .................................................................................................................200 mA
Input clamp current, IIK (VI < 0 or VI > VDD) ......................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ...............................................................................................................±20 mA
Maximum output current sunk by any I/O pin (except RA2 and RA3)......................................................................35 mA
Maximum output current sunk by RA2 or RA3 pins .................................................................................................60 mA
Maximum output current sourced by any I/O pin .....................................................................................................20 mA
Maximum current sunk by PORTA and PORTB (combined)..................................................................................150 mA
Maximum current sourced by PORTA and PORTB (combined).............................................................................100 mA
Maximum current sunk by PORTC, PORTD and PORTE (combined)...................................................................150 mA
Maximum current sourced by PORTC, PORTD and PORTE (combined)..............................................................100 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a "low" level to the MCLR pin rather than
pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1996 Microchip Technology Inc.
DS30412C-page 175
This document was created with FrameMaker 4 0 4
DS30412C-page 176
PIC17CR42-25
PIC17C42A-25
PIC17C43-25
PIC17CR43-25
PIC17C44-25
PIC17CR42-33
PIC17C42A-33
PIC17C43-33
PIC17CR43-33
PIC17C44-33
JW Devices
(Ceramic Windowed
Devices)
VDD: 2.5V to 6.0V
VDD: 4.5V to 6.0V
VDD: 4.5V to 6.0V
VDD: 4.5V to 6.0V
VDD: 4.5V to 6.0V
IDD: 6 mA max.
IDD: 6 mA max.
IDD: 6 mA max.
IDD: 6 mA max.
IDD: 6 mA max.
IPD: 5 µA max. at 5.5V
IPD: 5 µA max. at 5.5V
IPD: 5 µA max. at 5.5V
IPD: 5 µA max. at 5.5V
IPD: 5 µA max. at 5.5V
WDT disabled
WDT disabled
WDT disabled
WDT disabled
WDT disabled
Freq: 4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
XT VDD: 2.5V to 6.0V
VDD: 4.5V to 6.0V
VDD: 4.5V to 6.0V
VDD: 4.5V to 6.0V
VDD: 4.5V to 6.0V
IDD: 12 mA max.
IDD: 24 mA max.
IDD: 38 mA max.
IDD: 38 mA max.
IDD: 38 mA max.
IPD: 5 µA max. at 5.5V
IPD: 5 µA max. at 5.5V
IPD: 5 µA max. at 5.5V
IPD: 5 µA max. at 5.5V
IPD: 5 µA max. at 5.5V
WDT disabled
WDT disabled
WDT disabled
WDT disabled
WDT disabled
Freq: 8 MHz max.
Freq: 16 MHz max.
Freq: 25 MHz max.
Freq: 33 MHz max.
Freq: 33 MHz max.
EC VDD: 2.5V to 6.0V
VDD: 4.5V to 6.0V
VDD: 4.5V to 6.0V
VDD: 4.5V to 6.0V
VDD: 4.5V to 6.0V
IDD: 12 mA max.
IDD: 24 mA max.
IDD: 38 mA max.
IDD: 38 mA max.
IDD: 38 mA max.
IPD: 5 µA max. at 5.5V
IPD: 5 µA max. at 5.5V
IPD: 5 µA max. at 5.5V
IPD: 5 µA max. at 5.5V
IPD: 5 µA max. at 5.5V
WDT disabled
WDT disabled
WDT disabled
WDT disabled
WDT disabled
Freq: 8 MHz max.
Freq: 16 MHz Max
Freq: 25 MHz max.
Freq: 33 MHz max.
Freq: 33 MHz max.
LF VDD: 2.5V to 6.0V
VDD: 2.5V to 6.0V
VDD: 4.5V to 6.0V
VDD: 4.5V to 6.0V
VDD: 4.5V to 6.0V
IDD: 150 µA max. at 32 kHz IDD: 95 µA typ. at 32 kHz IDD: 95 µA typ. at 32 kHz IDD: 95 µA typ. at 32 kHz IDD: 150 µA max. at 32 kHz
IPD: 5 µA max. at 5.5V
IPD: < 1 µA typ. at 5.5V
IPD: < 1 µA typ. at 5.5V
IPD: < 1 µA typ. at 5.5V
IPD: 5 µA max. at 5.5V
WDT disabled
WDT disabled
WDT disabled
WDT disabled
WDT disabled
Freq: 2 MHz max.
Freq: 2 MHz max.
Freq: 2 MHz max.
Freq: 2 MHz max.
Freq: 2 MHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user
select the device type that ensures the specifications required.
PIC17CR42-16
PIC17C42A-16
PIC17C43-16
PIC17CR43-16
PIC17C44-16
TABLE 19-1:
RC
OSC
PIC17LCR42-08
PIC17LC42A-08
PIC17LC43-08
PIC17LCR43-08
PIC17LC44-08
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
19.1
DC CHARACTERISTICS:
DC CHARACTERISTICS
Parameter
No.
D001
D002
Sym
VDD
VDR
D003
VPOR
D004
SVDD
D010
D011
D012
D013
D015
D014
IDD
PIC17CR42/42A/43/R43/44-16 (Commercial, Industrial)
PIC17CR42/42A/43/R43/44-25 (Commercial, Industrial)
PIC17CR42/42A/43/R43/44-33 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Characteristic
Min
Typ† Max Units
Conditions
Supply Voltage
4.5
–
6.0
V
RAM Data Retention
1.5 *
–
–
V
Device in SLEEP mode
Voltage (Note 1)
VDD start voltage to
–
VSS
–
V
See section on Power-on Reset for
ensure internal
details
Power-on Reset signal
VDD rise rate to
0.060 *
–
–
mV/ms See section on Power-on Reset for
ensure internal
details
Power-on Reset signal
FOSC = 4 MHz (Note 4)
mA
6
3
Supply Current
–
mA
12 *
6
(Note 2)
–
FOSC = 8 MHz
mA
24 *
11
–
FOSC = 16 MHz
mA
38
19
–
FOSC = 25 MHz
mA
50
25
–
FOSC = 33 MHz
µA
150
95
–
FOSC = 32 kHz,
WDT enabled (EC osc configuration)
Power-down
–
10
40
µA
VDD = 5.5V, WDT enabled
D020
IPD
Current (Note 3)
–
<1
5
µA
VDD = 5.5V, WDT disabled
D021
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD or VSS, T0CKI = VDD,
MCLR = VDD; WDT enabled/disabled as specified.
Current consumed from the oscillator and I/O’s driving external capacitive or resistive loads needs to be considered.
For the RC oscillator, the current through the external pull-up resistor (R) can be estimated as: VDD / (2 • R).
For capacitive loads, the current can be estimated (for an individual I/O pin) as (CL • VDD) • f
CL = Total capacitive load on the I/O pin; f = average frequency the I/O pin switches.
The capacitive currents are most significant when the device is configured for external execution (includes
extended microcontroller mode).
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
1996 Microchip Technology Inc.
DS30412C-page 177
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
19.2
DC CHARACTERISTICS:
DC CHARACTERISTICS
Parameter
No.
Sym
D001
D002
VDD
VDR
D003
VPOR
D004
SVDD
D010
D011
D014
IDD
Characteristic
PIC17LC42A/43/LC44 (Commercial, Industrial)
PIC17LCR42/43 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Min
Supply Voltage
2.5
RAM Data Retention
1.5 *
Voltage (Note 1)
VDD start voltage to
–
ensure internal
Power-on Reset signal
VDD rise rate to
0.060 *
ensure internal
Power-on Reset signal
Supply Current
–
(Note 2)
–
–
Typ† Max
Units
–
–
6.0
–
V
V
VSS
–
V
–
–
3
6
95
6
12 *
150
Conditions
Device in SLEEP mode
See section on Power-on Reset for
details
mV/ms See section on Power-on Reset for
details
mA
mA
µA
FOSC = 4 MHz (Note 4)
FOSC = 8 MHz
FOSC = 32 kHz,
WDT disabled (EC osc configuration)
VDD = 5.5V, WDT enabled
VDD = 5.5V, WDT disabled
D020
IPD
Power-down
–
10
40
µA
D021
Current (Note 3)
–
<1
5
µA
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD or VSS, T0CKI = VDD, MCLR
= VDD; WDT enabled/disabled as specified.
Current consumed from the oscillator and I/O’s driving external capacitive or resistive loads needs to be considered.
For the RC oscillator, the current through the external pull-up resistor (R) can be estimated as: VDD / (2 • R).
For capacitive loads, the current can be estimated (for an individual I/O pin) as (CL • VDD) • f
CL = Total capacitive load on the I/O pin; f = average frequency the I/O pin switches.
The capacitive currents are most significant when the device is configured for external execution (includes
extended microcontroller mode).
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.
DS30412C-page 178
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
19.3
DC CHARACTERISTICS:
PIC17CR42/42A/43/R43/44-16 (Commercial, Industrial)
PIC17CR42/42A/43/R43/44-25 (Commercial, Industrial)
PIC17CR42/42A/43/R43/44-33 (Commercial, Industrial)
PIC17LCR42/42A/43/R43/44-08 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in Section 19.1
DC CHARACTERISTICS
Parameter
No.
Sym
VIL
D030
D031
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
with Schmitt Trigger buffer
D032
D033
VIH
D040
MCLR, OSC1 (in EC and RC
mode)
OSC1 (in XT, and LF mode)
Input High Voltage
I/O ports
with TTL buffer
Min
Typ†
Max
Units
VSS
VSS
VSS
–
–
–
0.8
0.2VDD
0.2VDD
V
V
V
4.5V ≤ VDD ≤ 5.5V
2.5V ≤ VDD ≤ 4.5V
Vss
–
0.2VDD
V
Note1
–
0.5VDD
–
V
–
–
–
VDD
VDD
VDD
V
V
V
4.5V ≤ VDD ≤ 5.5V
2.5V ≤ VDD ≤ 4.5V
VDD
–
–
V
V
V
Note1
2.0
1 + 0.2VDD
with Schmitt Trigger buffer
0.8VDD
D041
D042
D043
D050
MCLR
OSC1 (XT, and LF mode)
VHYS Hysteresis of
Schmitt Trigger inputs
Input Leakage Current
(Notes 2, 3)
IIL
I/O ports (except RA2, RA3)
D060
0.8VDD
–
–
0.5VDD
0.15VDD *
–
–
–
±1
Conditions
µA Vss ≤ VPIN ≤ VDD,
I/O Pin at hi-impedance
PORTB weak pull-ups
disabled
D061
D062
D063
D063B
MCLR
RA2, RA3
OSC1, TEST (EC, RC modes)
OSC1, TEST (XT, LF modes)
–
–
–
–
–
–
±2
±2
±1
VPIN
D064
MCLR
–
–
10
µA VMCLR = VPP = 12V
(when not programming)
60
200
400
µA
IPURB PORTB weak pull-up current
D070
*
†
‡
Note 1:
2:
3:
4:
5:
6:
µA
µA
µA
µA
VPIN = Vss or VPIN = VDD
Vss ≤ VRA2, VRA3 ≤ 12V
Vss ≤ VPIN ≤ VDD
RF ≥ 1 MΩ, see Figure 14.2
VPIN = VSS, RBPU = 0
4.5V ≤ VDD ≤ 6.0V
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
These parameters are for design guidance only and are not tested, nor characterized.
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXX devices be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17CXX Programming
Specifications (Literature number DS30139).
The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
For TTL buffers, the better of the two specifications may be used.
1996 Microchip Technology Inc.
DS30412C-page 179
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in Section 19.1
DC CHARACTERISTICS
Parameter
No.
Sym
D080
VOL
D081
Characteristic
RA2 and RA3
OSC2/CLKOUT
(RC and EC osc modes)
D090
VOH
D091
D092
RA2 and RA3
D093
D094
OSC2/CLKOUT
(RC and EC osc modes)
D100
COSC2
Capacitive Loading Specs
on Output Pins
OSC2/CLKOUT pin
D101
CIO
D102
CAD
‡
Note 1:
2:
3:
4:
5:
6:
Max
Units
–
–
–
–
–
–
0.1VDD
0.1VDD *
0.4
V
V
V
–
–
–
–
–
–
3.0
0.4
0.1VDD *
V
V
V
0.9VDD
0.9VDD *
2.4
–
–
–
–
–
–
V
V
V
–
–
12
V
2.4
0.9VDD *
–
–
–
–
V
V
–
–
25
–
–
50
pF In EC or RC osc modes
when OSC2 pin is outputting
CLKOUT.
external clock is used to
drive OSC1.
pF
–
–
50
Output High Voltage (Note 3)
I/O ports (except RA2 and RA3)
with TTL buffer
*
†
Typ†
Output Low Voltage
I/O ports (except RA2 and RA3)
with TTL buffer
D082
D083
D084
Min
All I/O pins and OSC2
(in RC mode)
System Interface Bus
(PORTC, PORTD and PORTE)
Conditions
IOL = VDD/1.250 mA
4.5V ≤ VDD ≤ 6.0V
VDD = 2.5V
IOL = 6 mA, VDD = 4.5V
Note 6
IOL = 60.0 mA, VDD = 6.0V
IOL = 1 mA, VDD = 4.5V
IOL = VDD/5 mA
(PIC17LC43/LC44 only)
IOH = -VDD/2.500 mA
4.5V ≤ VDD ≤ 6.0V
VDD = 2.5V
IOH = -6.0 mA, VDD=4.5V
Note 6
Pulled-up to externally
applied voltage
IOH = -5 mA, VDD = 4.5V
IOH = -VDD/5 mA
(PIC17LC43/LC44 only)
pF In Microprocessor or
Extended Microcontroller
mode
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
These parameters are for design guidance only and are not tested, nor characterized.
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXX devices be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17CXX Programming
Specifications (Literature number DS30139).
The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
For TTL buffers, the better of the two specifications may be used.
DS30412C-page 180
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +40˚C
Operating voltage VDD range as described in Section 19.1
DC CHARACTERISTICS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
12.75
4.75
–
5.0
13.25
5.25
V
V
–
–
25 ‡
–
50 ‡
30 ‡
mA
mA
10
100
1000
µs Terminated via internal/
external interrupt or a reset
Internal Program Memory
Programming Specs (Note 4)
VPP Voltage on MCLR/VPP pin
VDDP Supply voltage during
programming
Current into MCLR/VPP pin
IPP
IDDP Supply current during
programming
TPROG Programming pulse width
D110
D111
D112
D113
D114
*
†
‡
Note 1:
2:
3:
4:
5:
6:
Note:
Note 5
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
These parameters are for design guidance only and are not tested, nor characterized.
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC17CXX devices be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
These specifications are for the programming of the on-chip program memory EPROM through the use of the
table write instructions. The complete programming specifications can be found in: PIC17CXX Programming
Specifications (Literature number DS30139).
The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
For TTL buffers, the better of the two specifications may be used.
When using the Table Write for internal programming, the device temperature must be less than 40˚C.
1996 Microchip Technology Inc.
DS30412C-page 181
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
19.4
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
3. TCC:ST
(I2C specifications only)
2. TppS
4. Ts
(I2C specifications only)
T
F
Frequency
Lowercase symbols (pp) and their meanings:
pp
ad
Address/Data
al
ALE
cc
Capture1 and Capture2
ck
CLKOUT or clock
dt
Data in
in
INT pin
io
I/O port
mc
MCLR
oe
OE
os
OSC1
Uppercase symbols and their meanings:
S
D
Driven
E
Edge
F
Fall
H
High
I
Invalid (Hi-impedance)
DS30412C-page 182
T
Time
ost
pwrt
rb
rd
rw
t0
t123
wdt
wr
Oscillator Start-Up Timer
Power-Up Timer
PORTB
RD
RD or WR
T0CKI
TCLK12 and TCLK3
Watchdog Timer
WR
L
P
R
V
Z
Low
Period
Rise
Valid
Hi-impedance
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 19-1: PARAMETER MEASUREMENT INFORMATION
All timings are measure between high and low measurement points as indicated in the figures below.
INPUT LEVEL CONDITIONS
PORTC, D and E pins
VIH = 2.4V
VIL = 0.4V
Data in valid
All other input pins
Data in invalid
VIH = 0.9VDD
VIL = 0.1VDD
Data in valid
Data in invalid
OUTPUT LEVEL CONDITIONS
0.25V
VOH = 0.7VDD
VDD/2
VOL = 0.3VDD
0.25V
0.25V
0.25V
Data out valid
Output
driven
Output
hi-impedance
Data out invalid
0.9 VDD
0.1 VDD
Rise Time
Fall Time
LOAD CONDITIONS
Load Condition 1
Pin
CL
VSS
50 pF ≤ CL
1996 Microchip Technology Inc.
DS30412C-page 183
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
19.5
Timing Diagrams and Specifications
FIGURE 19-2: EXTERNAL CLOCK TIMING
Q4
Q1
Q3
Q2
Q4
Q1
OSC1
3
1
2
3
4
4
OSC2 †
† In EC and RC modes only.
TABLE 19-2:
Param
No.
1
2
3
4
†
‡
Note
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
—
8
MHz EC osc mode - 08 devices (8 MHz devices)
Fosc External CLKIN Frequency DC
DC
—
16
MHz
- 16 devices (16 MHz devices)
(Note 1)
DC
—
25
MHz
- 25 devices (25 MHz devices)
DC
—
33
MHz
- 33 devices (33 MHz devices)
Oscillator Frequency
DC
—
4
MHz RC osc mode
(Note 1)
1
—
8
MHz XT osc mode - 08 devices (8 MHz devices)
1
—
16
MHz
- 16 devices (16 MHz devices)
1
—
25
MHz
- 25 devices (25 MHz devices)
1
—
33
MHz
- 33 devices (33 MHz devices)
DC
—
2
MHz LF osc mode
Tosc External CLKIN Period
125
—
—
ns
EC osc mode - 08 devices (8 MHz devices)
(Note 1)
62.5
—
—
ns
- 16 devices (16 MHz devices)
40
—
—
ns
- 25 devices (25 MHz devices)
30.3
—
—
ns
- 33 devices (33 MHz devices)
Oscillator Period
250
—
—
ns
RC osc mode
(Note 1)
125
—
1,000
ns
XT osc mode - 08 devices (8 MHz devices)
62.5
—
1,000
ns
- 16 devices (16 MHz devices)
40
—
1,000
ns
- 25 devices (25 MHz devices)
30.3
—
1,000
ns
- 33 devices (33 MHz devices)
500
—
—
ns
LF osc mode
121.2 4/Fosc
DC
ns
TCY Instruction Cycle Time
(Note 1)
TosL, Clock in (OSC1)
10 ‡
—
—
ns
EC oscillator
TosH high or low time
TosR, Clock in (OSC1)
—
—
5‡
ns
EC oscillator
TosF rise or fall time
Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
These parameters are for design guidance only and are not tested, nor characterized.
1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
DS30412C-page 184
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 19-3: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
22
23
OSC2 †
13
12
18
14
16
19
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
† In EC and RC modes only.
TABLE 19-3:
CLKOUT AND I/O TIMING REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
10
TosH2ckL
OSC1↓ to CLKOUT↓
—
15 ‡
30 ‡
ns
Note 1
11
TosH2ckH
OSC1↓ to CLKOUT↑
—
15 ‡
30 ‡
ns
Note 1
12
TckR
CLKOUT rise time
—
5‡
15 ‡
ns
Note 1
13
TckF
CLKOUT fall time
—
5‡
15 ‡
ns
Note 1
14
TckH2ioV
CLKOUT ↑ to Port PIC17CR42/42A/43/
out valid
R43/44
—
—
0.5TCY + 20 ‡
ns
Note 1
—
—
0.5TCY + 50 ‡
ns
Note 1
0.25TCY + 25 ‡
—
—
ns
Note 1
0.25TCY + 50 ‡
—
—
ns
Note 1
Note 1
PIC17LCR42/42A/43/
R43/44
15
TioV2ckH
Port in valid before PIC17CR42/42A/43/
CLKOUT↑
R43/44
PIC17LCR42/42A/43/
R43/44
16
TckH2ioI
Port in hold after CLKOUT↑
0‡
—
—
ns
17
TosH2ioV
OSC1↓ (Q1 cycle) to Port out valid
—
—
100 ‡
ns
18
TosH2ioI
OSC1↓ (Q2 cycle) to Port input invalid
(I/O in hold time)
0‡
—
—
ns
19
TioV2osH
Port input valid to OSC1↓
(I/O in setup time)
30 ‡
—
—
ns
20
TioR
Port output rise time
—
10 ‡
35 ‡
ns
21
TioF
Port output fall time
—
10 ‡
35 ‡
ns
22
TinHL
INT pin high or low time
25 *
—
—
ns
23
TrbHL
RB7:RB0 change INT high or low time
25 *
—
—
ns
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
‡
These parameters are for design guidance only and are not tested, nor characterized.
Note 1: Measurements are taken in EC Mode where CLKOUT output is 4 x TOSC.
1996 Microchip Technology Inc.
DS30412C-page 185
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Timeout
32
OSC
Timeout
Internal
RESET
Watchdog
Timer
RESET
31
35
Address /
Data
TABLE 19-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym
Characteristic
30
TmcL
MCLR Pulse Width (low)
31
Twdt
Watchdog Timer Time-out Period
(Prescale = 1)
32
Tost
Oscillation Start-up Timer Period
33
Tpwrt
35
*
†
‡
§
Typ†
Max
Units
Conditions
100 *
—
—
ns
VDD = 5V
5*
12
25 *
ms
VDD = 5V
—
1024TOSC§
—
ms
TOSC = OSC1 period
40 *
96
200 *
ms
VDD = 5V
PIC17CR42/42A/
43/R43/44
—
—
100 *
ns
PIC17LCR42/
42A/43/R43/44
—
—
120 *
ns
Power-up Timer Period
TmcL2adI MCLR to System Interface bus (AD15:AD0>)
invalid
Min
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
These parameters are for design guidance only and are not tested, nor characterized.
This specification ensured by design.
DS30412C-page 186
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 19-5: TIMER0 CLOCK TIMINGS
RA1/T0CKI
40
41
42
TABLE 19-5:
Parameter
No.
TIMER0 CLOCK REQUIREMENTS
Sym Characteristic
Min
40
Tt0H T0CKI High Pulse Width
No Prescaler
41
Tt0L T0CKI Low Pulse Width
With Prescaler
No Prescaler
With Prescaler
42
Tt0P T0CKI Period
*
†
Typ† Max Units Conditions
0.5TCY + 20 §
10*
0.5TCY + 20 §
10*
Greater of:
20 ns or Tcy + 40 §
N
—
—
ns
—
—
—
—
—
—
—
—
ns
ns
ns
ns
N = prescale value
(1, 2, 4, ..., 256)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification ensured by design.
§
FIGURE 19-6: TIMER1, TIMER2, AND TIMER3 CLOCK TIMINGS
TCLK12
or
TCLK3
46
45
47
48
48
TMRx
TABLE 19-6:
Parameter
No.
45
46
47
48
*
†
§
TIMER1, TIMER2, AND TIMER3 CLOCK REQUIREMENTS
Sym
Characteristic
Tt123H TCLK12 and TCLK3 high time
Tt123L TCLK12 and TCLK3 low time
Tt123P TCLK12 and TCLK3 input period
Min
0.5TCY + 20 §
0.5TCY + 20 §
TCY + 40 §
N
2TOSC §
Typ
†
Max
—
—
—
—
—
—
Units Conditions
ns
ns
ns
N = prescale value
(1, 2, 4, 8)
TckE2tmrI Delay from selected External Clock Edge to
6Tosc §
Timer increment
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification ensured by design.
1996 Microchip Technology Inc.
DS30412C-page 187
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 19-7: CAPTURE TIMINGS
CAP1
and CAP2
(Capture Mode)
50
51
52
TABLE 19-7:
Parameter
No.
50
51
52
*
†
CAPTURE REQUIREMENTS
Sym Characteristic
Min
Typ† Max Units Conditions
TccL Capture1 and Capture2 input low time
TccH Capture1 and Capture2 input high time
TccP Capture1 and Capture2 input period
10 *
10 *
—
—
—
—
ns
ns
2TCY §
N
—
—
ns
N = prescale value
(4 or 16)
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification ensured by design.
§
FIGURE 19-8: PWM TIMINGS
PWM1
and PWM2
(PWM Mode)
53
TABLE 19-8:
Parameter
No.
53
54
*
†
§
54
PWM REQUIREMENTS
Sym Characteristic
Min
Typ† Max Units Conditions
TccR PWM1 and PWM2 output rise time
—
10 * 35 *§ ns
TccF PWM1 and PWM2 output fall time
—
10 * 35 *§ ns
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification ensured by design.
DS30412C-page 188
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 19-9: USART MODULE: SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RA5/TX/CK
pin
121
121
RA4/RX/DT
pin
122
120
TABLE 19-9:
SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Sym
120
Characteristic
TckH2dtV SYNC XMIT (MASTER &
SLAVE)
Clock high to data out valid
PIC17CR42/42A/43/R43/44
Min
Typ†
Max
—
—
50
Units Conditions
ns
PIC17LCR42/42A/43/R43/44
—
—
75
ns
121
TckRF
Clock out rise time and fall time PIC17CR42/42A/43/R43/44
(Master Mode)
PIC17LCR42/42A/43/R43/44
—
—
25
ns
—
—
40
ns
122
TdtRF
Data out rise time and fall time PIC17CR42/42A/43/R43/44
—
—
25
ns
—
—
40
ns
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
PIC17LCR42/42A/43/R43/44
FIGURE 19-10: USART MODULE: SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RA5/TX/CK
pin
125
RA4/RX/DT
pin
126
TABLE 19-10: SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
†
Sym
Characteristic
Min
Typ†
Max
Units Conditions
125
TdtV2ckL
SYNC RCV (MASTER & SLAVE)
Data hold before CK↓ (DT hold time)
15
—
—
ns
126
TckL2dtl
Data hold after CK↓ (DT hold time)
15
—
—
ns
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1996 Microchip Technology Inc.
DS30412C-page 189
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 19-11: MEMORY INTERFACE WRITE TIMING (NOT SUPPORTED IN PIC17LC4X DEVICES)
Q1
Q2
Q3
Q4
Q2
Q1
OSC1
ALE
OE
151
WR
150
AD<15:0>
154
data out
addr out
152
addr out
153
TABLE 19-11: MEMORY INTERFACE WRITE REQUIREMENTS (NOT SUPPORTED IN PIC17LC4X
DEVICES)
Parameter
No.
Sym
Characteristic
150
TadV2alL
AD<15:0> (address) valid to ALE↓
(address setup time)
151
TalL2adI
ALE↓ to address out invalid
(address hold time)
152
TadV2wrL
Data out valid to WR↓
(data setup time)
153
TwrH2adI
TwrL
154
*
†
§
Min
Typ†
Max
Units Conditions
0.25Tcy - 10
—
—
ns
0
—
—
ns
0.25Tcy - 40
—
—
ns
WR↑ to data out invalid
(data hold time)
—
0.25TCY §
—
ns
WR pulse width
—
0.25TCY §
—
ns
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification ensured by design.
DS30412C-page 190
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 19-12: MEMORY INTERFACE READ TIMING (NOT SUPPORTED IN PIC17LC4X DEVICES)
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
166
ALE
164
168
160
OE
165
AD<15:0>
Data in
Addr out
Addr out
162
150
WR
161
151
163
167
'1'
'1'
TABLE 19-12: MEMORY INTERFACE READ REQUIREMENTS (NOT SUPPORTED IN PIC17LC4X
DEVICES)
Parameter
No.
*
†
§
Sym
Characteristic
150
TadV2alL
AD15:AD0 (address) valid to ALE↓
(address setup time)
151
TalL2adI
ALE↓ to address out invalid
(address hold time)
Min
Typ†
Max
Units Conditions
0.25Tcy - 10
—
—
ns
5*
—
—
ns
160
TadZ2oeL
AD15:AD0 hi-impedance to OE↓
0*
—
—
ns
161
ToeH2adD
OE↑ to AD15:AD0 driven
0.25Tcy - 15
—
—
ns
162
TadV2oeH
Data in valid before OE↑
(data setup time)
35
—
—
ns
163
ToeH2adI
OE↑to data in invalid (data hold time)
0
—
—
ns
164
TalH
ALE pulse width
—
0.25TCY §
—
ns
165
ToeL
OE pulse width
0.5Tcy - 35 §
—
—
ns
166
TalH2alH
ALE↑ to ALE↑(cycle time)
—
TCY §
—
ns
167
Tacc
Address access time
—
—
0.75TCY - 30
ns
168
Toe
Output enable access time
(OE low to Data Valid)
—
—
0.5TCY - 45
ns
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification ensured by design.
1996 Microchip Technology Inc.
DS30412C-page 191
PIC17C4X
NOTES:
DS30412C-page 192
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
20.0
PIC17CR42/42A/43/R43/44 DC AND AC CHARACTERISTICS
The graphs and tables provided in this section are for design guidance and are not tested nor guaranteed. In some
graphs or tables the data presented is outside specified operating range (e.g. outside specified VDD range). This is for
information only and devices are ensured to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3σ) and (mean - 3σ)
respectively where σ is standard deviation.
TABLE 20-1:
PIN CAPACITANCE PER PACKAGE TYPE
Typical Capacitance (pF)
Pin Name
40-pin DIP
44-pin PLCC
44-pin MQFP
44-pin TQFP
10
10
10
10
20
20
20
20
All pins, except MCLR,
VDD, and VSS
MCLR pin
FIGURE 20-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE
FOSC
FOSC (25°C)
Frequency normalized to +25°C
1.10
Rext ≥ 10 kΩ
Cext = 100 pF
1.08
1.06
1.04
1.02
1.00
VDD = 5.5V
0.98
0.96
0.94
VDD = 3.5V
0.92
0.90
0
10
20
25
30
40
50
60
70
T(°C)
1996 Microchip Technology Inc.
DS30412C-page 193
This document was created with FrameMaker 4 0 4
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 20-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
4.0
3.5
R = 10k
FOSC (MHz)
3.0
2.5
2.0
1.5
Cext = 22 pF, T = 25°C
1.0
0.5
R = 100k
0.0
4.0
4.5
5.0
5.5
6.0
6.5
6.0
6.5
VDD (Volts)
FIGURE 20-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
4.0
3.5
R = 3.3k
FOSC (MHz)
3.0
2.5
R = 5.1k
2.0
1.5
R = 10k
1.0
Cext = 100 pF, T = 25°C
0.5
R = 100k
0.0
4.0
4.5
5.0
5.5
VDD (Volts)
DS30412C-page 194
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 20-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD
2.0
1.8
1.6
1.4
R = 3.3k
FOSC (MHz)
1.2
R = 5.1k
1.0
0.8
R = 10k
0.6
0.4
Cext = 300 pF, T = 25°C
0.2
R = 160k
0.0
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
TABLE 20-2:
RC OSCILLATOR FREQUENCIES
Cext
Rext
22 pF
10k
100k
3.3k
5.1k
10k
100k
3.3k
5.1k
10k
160k
100 pF
300 pF
1996 Microchip Technology Inc.
Average
Fosc @ 5V, 25°C
3.33 MHz
353 kHz
3.54 MHz
2.43 MHz
1.30 MHz
129 kHz
1.54 MHz
980 kHz
564 kHz
35 kHz
± 12%
± 13%
± 10%
± 14%
± 17%
± 10%
± 14%
± 12%
± 16%
± 18%
DS30412C-page 195
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 20-5: TRANSCONDUCTANCE (gm) OF LF OSCILLATOR vs. VDD
500
450
400
350
Max @ -40°C
gm(µA/V)
300
Typ @ 25°C
250
200
150
Min @ 85°C
100
50
0
2.5
3.0
3.5
4.0
4.5
5.5
5.0
6.0
VDD (Volts)
FIGURE 20-6: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR vs. VDD
20
18
Max @ -40°C
16
14
Typ @ 25°C
gm(mA/V)
12
10
8
6
Min @ 85°C
4
2
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30412C-page 196
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 20-7: TYPICAL IDD vs. FREQUENCY (EXTERNAL CLOCK 25°C)
100000
IDD (µA)
10000
1000
7.0V
6.5V
6.0V
5.5V
5.0V
4.5V
100
4.0V
10
10k
100k
1M
External Clock Frequency (Hz)
10M
100M
FIGURE 20-8: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK 125°C TO -40°C)
100000
IDD (µA)
10000
1000
7.0V
6.5V
6.0V
5.5V
5.0V
4.5V
4.0V
100
10k
100k
1M
10M
100M
External Clock Frequency (Hz)
1996 Microchip Technology Inc.
DS30412C-page 197
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 20-9: TYPICAL IPD vs. VDD WATCHDOG DISABLED 25°C
12
10
IPD(nA)
8
6
4
2
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VDD (Volts)
IPD(nA)
FIGURE 20-10: MAXIMUM IPD vs. VDD WATCHDOG DISABLED
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
Temp. = 85°C
Temp. = 70°C
Temp. = 0°C
4.0
4.5
5.0
5.5
6.0
Temp. = -40°C
6.5
7.0
VDD (Volts)
DS30412C-page 198
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 20-11: TYPICAL IPD vs. VDD WATCHDOG ENABLED 25°C
30
25
IPD(µA)
20
15
10
5
0
4.0
4.5
5.0
5.5
6.5
6.0
7.0
VDD (Volts)
FIGURE 20-12: MAXIMUM IPD vs. VDD WATCHDOG ENABLED
60
50
-40°C
70°C
IPD(µA)
40
0°C
85°C
30
20
10
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VDD (Volts)
1996 Microchip Technology Inc.
DS30412C-page 199
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 20-13: WDT TIMER TIME-OUT PERIOD vs. VDD
30
25
Max. 85°C
WDT Period (ms)
20
Max. 70°C
Min. 0°C
15
Typ. 25°C
10
Min. -40°C
5
0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
2.5
3.0
VDD (Volts)
FIGURE 20-14: IOH vs. VOH, VDD = 3V
0
-2
IOH(mA)
-4
-6
Min @ 85°C
-8
Typ @ 25°C
-10
-12
-14
Max @ -40°C
-16
-18
0.0
0.5
1.0
1.5
2.0
VDD (Volts)
DS30412C-page 200
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 20-15: IOH vs. VOH, VDD = 5V
IOH(mA)
0
-5
-10
Min @ 85°C
-15
-20
Max @ -40°C
-25
Typ @ 25°C
-30
-35
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD (Volts)
FIGURE 20-16: IOL vs. VOL, VDD = 3V
30
Max. -40°C
25
Typ. 25°C
IOL(mA)
20
15
Min. +85°C
10
5
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VDD (Volts)
1996 Microchip Technology Inc.
DS30412C-page 201
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 20-17: IOL vs. VOL, VDD = 5V
90
80
70
IOH(mA)
Max @ -40°C
Typ @ 25°C
60
50
Min @ +85°C
40
30
20
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VDD (Volts)
FIGURE 20-18: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS (TTL) VS. VDD
2.0
1.8
Max (-40°C to +85°C)
1.6
VTH(Volts)
Typ @ 25°C
1.4
1.2
1.0
Min (-40°C to +85°C)
0.8
0.6
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30412C-page 202
1996 Microchip Technology Inc.
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 20-19: VTH, VIL of I/O PINS (SCHMITT TRIGGER) VS. VDD
5.0
VIH, max (-40°C to +85°C)
4.5
VIH, typ (25°C)
4.0
VIH, min (-40°C to +85°C)
VIH, VIL(Volts)
3.5
3.0
VIL, max (-40°C to +85°C)
2.5
VIL, typ (25°C)
VIL, min (-40°C to +85°C)
2.0
1.5
1.0
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 20-20: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT
(IN XT AND LF MODES) vs. VDD
3.4
3.2
Typ (25°C)
3.0
Max (-40°C to +85°C)
VTH,(Volts)
2.8
2.6
2.4
2.2
2.0
Min (-40°C to +85°C)
1.8
1.6
1.4
1.2
1.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
1996 Microchip Technology Inc.
DS30412C-page 203
PIC17C4X
NOTES:
DS30412C-page 204
1996 Microchip Technology Inc.
PIC17C4X
21.0
PACKAGING INFORMATION
21.1
40-Lead Ceramic CERDIP Dual In-line, and CERDIP Dual In-line with Window (600 mil)
N
E1 E
α
C
Pin No. 1
Indicator
Area
eA
eB
D
S
S1
Base
Plane
Seating
Plane
L
B1
A1 A3 A A2
e1
B
D1
Package Group: Ceramic CERDIP Dual In-Line (CDP)
Millimeters
Symbol
Min
Max
Inches
Notes
Min
Max
α
0°
10°
0°
10°
A
A1
A2
A3
B
B1
C
D
D1
E
E1
e1
eA
eB
L
N
S
S1
4.318
0.381
3.810
3.810
0.355
1.270
0.203
51.435
48.260
15.240
12.954
2.540
14.986
15.240
3.175
40
1.016
0.381
5.715
1.778
4.699
4.445
0.585
1.651
0.381
52.705
48.260
15.875
15.240
2.540
16.002
18.034
3.810
40
2.286
1.778
0.170
0.015
0.150
0.150
0.014
0.050
0.008
2.025
1.900
0.600
0.510
0.100
0.590
0.600
0.125
40
0.040
0.015
0.225
0.070
0.185
0.175
0.023
0.065
0.015
2.075
1.900
0.625
0.600
0.100
0.630
0.710
0.150
40
0.090
0.070
Typical
Typical
Reference
Reference
Typical
1996 Microchip Technology Inc.
Notes
Typical
Typical
Reference
Reference
Typical
DS30412C-page 205
This document was created with FrameMaker 4 0 4
PIC17C4X
21.2
40-Lead Plastic Dual In-line (600 mil)
N
α
E1 E
C
eA
eB
Pin No. 1
Indicator
Area
D
S
S1
Base
Plane
Seating
Plane
L
B1
A1 A2 A
e1
B
D1
Package Group: Plastic Dual In-Line (PLA)
Millimeters
Symbol
Min
α
0°
10°
0°
10°
A
A1
A2
B
B1
C
D
D1
E
E1
e1
eA
eB
L
N
S
S1
–
0.381
3.175
0.355
1.270
0.203
51.181
48.260
15.240
13.462
2.489
15.240
15.240
2.921
40
1.270
0.508
5.080
–
4.064
0.559
1.778
0.381
52.197
48.260
15.875
13.970
2.591
15.240
17.272
3.683
40
–
–
–
0.015
0.125
0.014
0.050
0.008
2.015
1.900
0.600
0.530
0.098
0.600
0.600
0.115
40
0.050
0.020
0.200
–
0.160
0.022
0.070
0.015
2.055
1.900
0.625
0.550
0.102
0.600
0.680
0.145
40
–
–
DS30412C-page 206
Max
Inches
Notes
Typical
Typical
Reference
Typical
Reference
Min
Max
Notes
Typical
Typical
Reference
Typical
Reference
1996 Microchip Technology Inc.
PIC17C4X
21.3
44-Lead Plastic Leaded Chip Carrier (Square)
D
-A-
D1
-D-
3
-F-
0.812/0.661 N Pics
.032/.026
1.27
.050
2 Sides
0.177
.007 S B D-E S
-HA
A1
3
D3/E3
D2
0.38
.015
3
-G-
8
F-G S
D
0.177
.007 S B A S
2 Sides
9
0.101 Seating
.004 Plane
-C-
4
E2
E1
E
0.38
.015
F-G S
4
-B-
3
-E-
0.177
.007 S A F-G S
10
0.254
.010 Max
2
0.254
.010 Max
11
-H-
11
0.508
.020
0.508
.020
-H-
2
0.812/0.661
3
.032/.026
1.524
.060 Min
6
6
-C1.651
.065
1.651
.065
R 1.14/0.64
.045/.025
R 1.14/0.64
.045/.025
5
0.533/0.331
.021/.013
0.64 Min
.025
0.177
, D-E S
.007 M A F-G S
Package Group: Plastic Leaded Chip Carrier (PLCC)
Millimeters
Symbol
Min
Max
A
4.191
A1
D
D1
D2
D3
E
E1
E2
E3
N
CP
LT
2.413
17.399
16.510
15.494
12.700
17.399
16.510
15.494
12.700
44
–
0.203
1996 Microchip Technology Inc.
Inches
Notes
Min
Max
4.572
0.165
0.180
2.921
17.653
16.663
16.002
12.700
17.653
16.663
16.002
12.700
44
0.102
0.381
0.095
0.685
0.650
0.610
0.500
0.685
0.650
0.610
0.500
44
–
0.008
0.115
0.695
0.656
0.630
0.500
0.695
0.656
0.630
0.500
44
0.004
0.015
Reference
Reference
Notes
Reference
Reference
DS30412C-page 207
PIC17C4X
44-Lead Plastic Surface Mount (MQFP 10x10 mm Body 1.6/0.15 mm Lead Form)
21.4
4 D
D1 5
0.20 M C A-B S
D S
0.20 M H A-B S
D S
7
0.20 min.
0.05 mm/mm A-B
D3
0.13 R min.
Index
area 6
9
PARTING
LINE
0.13/0.30 R
α
b
L
C
E3
E1 E
1.60 Ref.
0.20 M C A-B S
D S
4
TYP 4x
10
e
0.20 M H A-B S
B
D S
5
7
0.05 mm/mm D
A2
A
Base
Plane
Seating
Plane
A1
Package Group: Plastic MQFP
Millimeters
Symbol
Min
Max
α
0°
A
A1
A2
b
C
D
D1
D3
E
E1
E3
e
L
N
CP
2.000
0.050
1.950
0.300
0.150
12.950
9.900
8.000
12.950
9.900
8.000
0.800
0.730
44
0.102
DS30412C-page 208
Inches
Notes
Min
Max
7°
0°
7°
2.350
0.250
2.100
0.450
0.180
13.450
10.100
8.000
13.450
10.100
8.000
0.800
1.030
44
–
0.078
0.002
0.768
0.011
0.006
0.510
0.390
0.315
0.510
0.390
0.315
0.031
0.028
44
0.004
0.093
0.010
0.083
0.018
0.007
0.530
0.398
0.315
0.530
0.398
0.315
0.032
0.041
44
–
Typical
Reference
Reference
Notes
Typical
Reference
Reference
1996 Microchip Technology Inc.
PIC17C4X
21.5
44-Lead Plastic Surface Mount (TQFP 10x10 mm Body 1.0/0.10 mm Lead Form)
D
D1
1.0ø (0.039ø) Ref.
Pin#1
2
11°/13°(4x)
Pin#1
2
E
0° Min
E1
Θ
11°/13°(4x)
Detail B
e
3.0ø (0.118ø) Ref.
Option 1 (TOP side)
Option 2 (TOP side)
A1
A2
Detail B
A
L
Detail A
R 1 0.08 Min
R 0.08/0.20
Base Metal
Lead Finish
b
L
c
1.00 Ref.
Gage Plane
0.250
c1
L1
1.00 Ref
b1
Detail A
S
0.20
Min
Detail B
Package Group: Plastic TQFP
Millimeters
Symbol
Min
Max
A
A1
A2
D
D1
E
E1
L
e
b
b1
c
c1
N
1.00
0.05
0.95
11.75
9.90
11.75
9.90
0.45
Θ
Inches
Notes
Min
Max
1.20
0.15
1.05
12.25
10.10
12.25
10.10
0.75
0.039
0.002
0.037
0.463
0.390
0.463
0.390
0.018
0.047
0.006
0.041
0.482
0.398
0.482
0.398
0.030
0.30
0.30
0.09
0.09
44
0.45
0.40
0.20
0.16
44
0.012
0.012
0.004
0.004
44
0.018
0.016
0.008
0.006
44
0°
7°
0°
7°
0.80 BSC
Notes
0.031 BSC
Note 1: Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.25m/m (0.010”) per
side. D1 and E1 dimensions including mold mismatch.
2: Dimension “b” does not include Dambar protrusion, allowable Dambar protrusion shall be 0.08m/m
(0.003”)max.
3: This outline conforms to JEDEC MS-026.
1996 Microchip Technology Inc.
DS30412C-page 209
PIC17C4X
21.6
Package Marking Information
40-Lead PDIP/CERDIP
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
AABBCDE
40 Lead CERDIP Windowed
Example
PIC17C43-25I/P
L006
9441CCA
Example
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
PIC17C44
/JW
L184
AABBCDE
44-Lead PLCC
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
44-Lead MQFP
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
44-Lead TQFP
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
9444CCT
Example
PIC17C42
-16I/L
L013
9445CCN
Example
PIC17C44
-25/PT
L247
9450CAT
Example
PIC17C44
-25/TQ
L247
9450CAT
Legend: MM...M
XX...X
AA
BB
C
Microchip part number information
Customer specific information*
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
C = Chandler, Arizona, U.S.A.,
S = Tempe, Arizona, U.S.A.
D
Mask revision number
E
Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line,
it will be carried over to the next line thus limiting the number of available
characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week
code, facility code, mask rev#, and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales
Office. For QTP devices, any special marking adders are included in QTP
price.
DS30412C-page 210
1996 Microchip Technology Inc.
PIC17C4X
APPENDIX A: MODIFICATIONS
APPENDIX B: COMPATIBILITY
The following is the list of modifications over the
PIC16CXX microcontroller family:
To convert code written for PIC16CXX to PIC17CXX,
the user should take the following steps:
1.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
Instruction word length is increased to 16-bit.
This allows larger page sizes both in program
memory (8 Kwords verses 2 Kwords) and register file (256 bytes versus 128 bytes).
Four modes of operation: microcontroller, protected microcontroller, extended microcontroller,
and microprocessor.
22 new instructions.
The MOVF, TRIS and OPTION instructions have
been removed.
4 new instructions for transferring data between
data memory and program memory. This can be
used to “self program” the EPROM program
memory.
Single cycle data memory to data memory transfers possible (MOVPF and MOVFP instructions).
These instructions do not affect the Working register (WREG).
W register (WREG) is now directly addressable.
A PC high latch register (PCLATH) is extended
to 8-bits. The PCLATCH register is now both
readable and writable.
Data memory paging is redefined slightly.
DDR registers replaces function of TRIS registers.
Multiple Interrupt vectors added. This can
decrease the latency for servicing the interrupt.
Stack size is increased to 16 deep.
BSR register for data memory paging.
Wake up from SLEEP operates slightly differently.
The Oscillator Start-Up Timer (OST) and
Power-Up Timer (PWRT) operate in parallel and
not in series.
PORTB interrupt on change feature works on all
eight port pins.
TMR0 is 16-bit plus 8-bit prescaler.
Second indirect addressing register added
(FSR1 and FSR2). Configuration bits can select
the FSR registers to auto-increment, auto-decrement, remain unchanged after an indirect
address.
Hardware multiplier added (8 x 8 → 16-bit)
(PIC17C43 and PIC17C44 only).
Peripheral modules operate slightly differently.
Oscillator modes slightly redefined.
Control/Status bits and registers have been
placed in different registers and the control bit
for globally enabling interrupts has inverse
polarity.
Addition of a test mode pin.
In-circuit serial programming is not implemented.
2.
3.
4.
Remove any TRIS and OPTION instructions,
and implement the equivalent code.
Separate the interrupt service routine into its
four vectors.
Replace:
MOVF
REG1, W
with:
MOVFP
REG1, WREG
Replace:
MOVF
REG1, W
MOVWF
REG2
with:
MOVPF
REG1, REG2 ; Addr(REG1)<20h
or
MOVFP
REG1, REG2 ; Addr(REG2)<20h
Note:
5.
6.
7.
8.
9.
If REG1 and REG2 are both at addresses
greater then 20h, two instructions are
required.
MOVFP
REG1, WREG ;
MOVPF
WREG, REG2 ;
Ensure that all bit names and register names are
updated to new data memory map location.
Verify data memory banking.
Verify mode of operation for indirect addressing.
Verify peripheral routines for compatibility.
Weak pull-ups are enabled on reset.
To convert code from the PIC17C42 to all the other
PIC17C4X devices, the user should take the following
steps.
1.
2.
3.
If the hardware multiply is to be used, ensure
that any variables at address 18h and 19h are
moved to another address.
Ensure that the upper nibble of the BSR was not
written with a non-zero value. This may cause
unexpected operation since the RAM bank is no
longer 0.
The disabling of global interrupts has been
enhanced so there is no additional testing of the
GLINTD bit after a BSF CPUSTA, GLINTD
instruction.
1996 Microchip Technology Inc.
DS30412C-page 211
This document was created with FrameMaker 4 0 4
PIC17C4X
APPENDIX C: WHAT’S NEW
APPENDIX D: WHAT’S CHANGED
The structure of the document has been made consistent with other data sheets. This ensures that important
topics are covered across all PIC16/17 families. Here is
an overview of new features.
To make software more portable across the different
PIC16/17 families, the name of several registers and
control bits have been changed. This allows control bits
that have the same function, to have the same name
(regardless of processor family). Care must still be
taken, since they may not be at the same special function register address. The following shows the register
and bit names that have been changed:
Added the following devices:
PIC17CR42
PIC17C42A
PIC17CR43
A 33 MHz option is now available.
Old Name
New Name
TX8/9
TX9
RC8/9
RX9
RCD8
RX9D
TXD8
TX9D
Instruction DECFSNZ corrected to DCFSNZ
Instruction INCFSNZ corrected to INFSNZ
Enhanced discussion on PWM to include equation for
determining bits of PWM resolution.
Section 13.2.2 and 13.3.2 have had the description of
updating the FERR and RX9 bits enhanced.
The location of configuration bit PM2 was changed
(Figure 6-1 and Figure 14-1).
Enhanced description of the operation of the INTSTA
register.
Added note to discussion of interrupt operation.
Tightened electrical spec D110.
Corrected steps for setting up USART Asynchronous
Reception.
DS30412C-page 212
1996 Microchip Technology Inc.
PIC14000
20
o
em
y
or
(x
)
r
wo
2
/I
I
SP
C
,U
T)
R
SA
Peripherals
g
in
m
am
4K
192
s
te
by
TMR0
I2C/
ADTMR SMBus
M
14
11
22
2.7-6.0
Internal Oscillator,
Bandgap Reference,
Temperature Sensor,
Calibration Factors,
Yes Low Voltage Detector,
SLEEP, HIBERNATE,
Comparators with
Programmable References
(2)
)
r
ts
gr
ol
rte nels
p
ro
V
s
e
(
)
P
m
hi
e
v
n
s
l
a
(
-c
rc
ia
ue
on ha
)(
e(
ge
y
gr
n
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q
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C
o
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e
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C
o
t(
a
S
lO
Pr
D )
Fr
R
od
or
tS
em
pt ins
na res
A/ -res
e
M
M
ui
u
lP
o
um
M
g
c
i
r
r
e
O
r
u
t
a
r
h
i
e
im
ri
R
ta
lta
di at
op ig
te /O P
m
-C
ax
Se
In
Sl (h
EP
I
Vo
Da
Ti
Ad Fe
M
In
y
nc
r
pe
fO
n
io
at
14
Memory
)
ds
Pa
a
ck
ge
s
28-pin DIP, SOIC, SSOP
(.300 mil)
Features
E.1
)
Hz
(M
Clock
PIC17C4X
APPENDIX E: PIC16/17 MICROCONTROLLERS
PIC14000 Devices
1996 Microchip Technology Inc.
DS30412C-page 213
This document was created with FrameMaker 4 0 4
20
20
20
20
20
20
20
20
PIC16C54A
PIC16CR54A
PIC16C55
PIC16C56
PIC16C57
PIC16CR57B
PIC16C58A
PIC16CR58A
im
um
qu
—
2K
—
2K
1K
512
—
512
RO
en
2K
—
2K
—
—
—
512
—
—
—
73
73
72
72
25
24
25
25
25
25
RA
D
M
M
at
a
Fr
e
512
yte
s)
em
or
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
)
12
12
20
20
12
20
12
12
12
12
ns
2.5-6.25
2.0-6.25
2.5-6.25
2.5-6.25
2.5-6.25
2.5-6.25
2.0-6.25
2.0-6.25
2.5-6.25
2.5-6.25
e
33
33
33
33
33
33
33
33
33
33
ng
M
cy
of
O
p
er
at
ion
P
(
r
M
og
Hz
(x ram
)
12 M
wo em
rd or
s) y
OM
EP
R
384
y(
b
Ti
m
M
er
(s
le
od
u
Peripherals
es
s
In
ax
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
28-pin DIP, SOIC, SSOP
28-pin DIP, SOIC, SSOP
18-pin DIP, SOIC; 20-pin SSOP
28-pin DIP, SOIC, SSOP
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC
Features
All PIC16/17 Family devices have Power-On Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
4
20
PIC16C54
M
PIC16C52
Pi
I/O
on
cti
Memory
e
)
Nu
Ra
ag
Vo
lt
lts
(V
o
m
be
r
of
str
u
P
DS30412C-page 214
ag
E.2
ac
k
Clock
PIC17C4X
PIC16C5X Family of Devices
1996 Microchip Technology Inc.
1996 Microchip Technology Inc.
20
20
20
20
20
PIC16C556
PIC16C558
PIC16C620
PIC16C621
PIC16C622
2K
1K
512
2K
1K
512
128
80
80
128
80
80
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
H
2
2
2
—
—
—
Yes
Yes
Yes
—
—
—
3
4
4
4
3
3
13
13
13
13
13
13
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
Yes
Yes
Yes
—
—
—
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
18-pin DIP, SOIC; 20-pin SSOP
et
es
R
R
es
ut
-o
ag
ge
n
k
a
c
lt
ow
Pa
Vo
Br
e
g
an
)
ts
ol
(V
Features
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O
current capability.
All PIC16C6XXX Family devices use serial programming with clock pin RB6 and data pin RB7.
20
PIC16C554
(M
Peripherals
y
or
em s)
M rd
ge
ra
o
lta
pe
am 4 w
o
r
O
V
s)
of
og x1
e
te
y
s
Pr (
nc
nc
by
s)
ce
(
e
(
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y
s)
ur
le
er
qu
r
(
f
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r
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Fr
Re
od
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M
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up
um
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Pi
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m
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a
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O
i
P
o
n
n
/
I
I
I
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T
E
M
C
n
tio
Memory
E.3
z)
Clock
PIC17C4X
PIC16CXXX Family of Devices
DS30412C-page 215
DS30412C-page 216
20
20
20
20
20
PIC16CR63(1)
PIC16C64
PIC16C64A(1)
PIC16CR64(1)
PIC16C65
Features
—
4K
4K
—
2K
2K
—
4K
—
2K
2K
4K
—
—
2K
—
—
4K
—
2K
—
—
192 TMR0,
TMR1, TMR2
192 TMR0,
TMR1, TMR2
192 TMR0,
TMR1, TMR2
128 TMR0,
TMR1, TMR2
128 TMR0,
TMR1, TMR2
128 TMR0,
TMR1, TMR2
192 TMR0,
TMR1, TMR2
192 TMR0,
TMR1, TMR2
128 TMR0,
TMR1, TMR2
128 TMR0,
TMR1, TMR2
128 TMR0,
TMR1, TMR2
H
2 SPI/I2C, Yes
USART
11
11
11
2 SPI/I2C, Yes
USART
2 SPI/I2C, Yes
USART
8
8
8
10
10
7
7
7
Yes
1 SPI/I2C
Yes
Yes
1 SPI/I2C
1 SPI/I2C
—
—
2 SPI/I2C,
USART
2 SPI/I2C,
USART
—
—
—
1 SPI/I2C
1 SPI/I2C
1 SPI/I2C
33
33
33
33
33
33
22
22
22
22
22
2.5-6.0
2.5-6.0
3.0-6.0
2.5-6.0
2.5-6.0
3.0-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
3.0-6.0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
28-pin SDIP, SOIC, SSOP
40-pin DIP;
44-pin PLCC, MQFP
40-pin DIP;
44-pin PLCC, MQFP
Yes 40-pin DIP;
44-pin PLCC, MQFP, TQFP
Yes 40-pin DIP;
44-pin PLCC, MQFP, TQFP
—
Yes 40-pin DIP;
44-pin PLCC, MQFP, TQFP
Yes 40-pin DIP;
44-pin PLCC, MQFP, TQFP
—
Yes 28-pin SDIP, SOIC
Yes 28-pin SDIP, SOIC
Yes 28-pin SDIP, SOIC, SSOP
Yes 28-pin SDIP, SOIC, SSOP
—
All PIC16/17 family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and high I/O current capability.
All PIC16C6X family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local sales office for availability of these devices.
20
20
PIC16C63
PIC16CR65(1)
20
PIC16CR62(1)
20
20
PIC16C62A(1)
PIC16C65A(1)
20
PIC16C62
(M
s)
Peripherals
y
(
or
le
T)
m )
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In
Br
Pa
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EP
RO
Ti
Pa
Vo
I/O
M
on
Memory
E.4
z)
Clock
PIC17C4X
PIC16C6X Family of Devices
1996 Microchip Technology Inc.
(M
14
d
r
wo
Memory
M
e(
ul
od
R
SA
T)
Peripherals
s)
ls
ne
n
ha
Features
1996 Microchip Technology Inc.
1K
20
20
20
20
20
20
PIC16C72
PIC16C73
PIC16C73A(1)
PIC16C74
PIC16C74A(1)
—
—
—
8
8
192 TMR0,
2 SPI/I2C, Yes
TMR1, TMR2
USART
192 TMR0,
2 SPI/I2C, Yes
TMR1, TMR2
USART
5
5
5
4
4
4
—
192 TMR0,
2 SPI/I2C,
TMR1, TMR2
USART
—
—
—
—
192 TMR0,
2 SPI/I2C,
TMR1, TMR2
USART
—
—
—
—
TMR0
TMR0
TMR0
128 TMR0,
1 SPI/I2C
TMR1, TMR2
68
36
36
12
12
11
11
8
4
4
4
33
33
22
22
22
13
13
13
2.5-6.0
3.0-6.0
2.5-6.0
3.0-6.0
2.5-6.0
3.0-6.0
3.0-6.0
3.0-6.0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
18-pin DIP, SOIC
28-pin SDIP, SOIC
40-pin DIP;
44-pin PLCC, MQFP
Yes 40-pin DIP;
44-pin PLCC, MQFP, TQFP
—
Yes 28-pin SDIP, SOIC
—
Yes 28-pin SDIP, SOIC, SSOP
Yes 18-pin DIP, SOIC;
20-pin SSOP
—
Yes 18-pin DIP, SOIC;
20-pin SSOP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current
capability.
All PIC16C7X Family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local sales office for availability of these devices.
4K
4K
4K
4K
2K
1K
20
PIC16C71
PIC16C711
512
20
PIC16C710
y
or
(x
g
in
m
U
m
,
M 2C
C
)
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O
ts
W
it)
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s)
em
of
ol
/P PI/I
rt
te
-b
ro
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M
V
s
e
y
o
c
8
(
)
P
r
(
S
P
l
et
ce
(b
(s
en
am
pa s) (
e
ge
er
y
es
ur
le
ria
t
gr
qu
r
v
n
r
m
o
u
(
e
o
e
R
o
t
a
o
la
ve
Fr
Pr
R
od
or
tS s
es
ut
tS
/C
em
lS
M
e
M
ui
on rup
-o
n
re al P
ag
um
le
M
i
g
c
r
O
l
n
C
r
u
k
r
a
i
i
m
P
e
R
i
c
r
ra
ta
lt
pt
D
te
ow
m
-C
ax
EP
Pa
Se
In
A/
Pa
I/O
Vo
Da
Ti
M
In
Br
Ca
p
a
er
n
tio
s)
E.5
)
Hz
Clock
PIC17C4X
PIC16C7X Family of Devices
DS30412C-page 217
10
10
10
10
PIC16F84(1)
PIC16CR84(1)
PIC16F83(1)
PIC16CR83(1)
F
—
512
—
1K
—
—
—
—
—
1K
—
1K
—
—
512
EE
(M
36
36
68
68
Da
64
64
64
64
ta
Da
em
64
ta
y
or
P
(
er
T
TMR0
TMR0
TMR0
TMR0
o
M
4
4
4
4
4
Peripherals
)
ts
ol
(V
Features
13
13
13
13
13
2.0-6.0 18-pin DIP, SOIC
2.0-6.0 18-pin DIP, SOIC
2.0-6.0 18-pin DIP, SOIC
2.0-6.0 18-pin DIP, SOIC
2.0-6.0 18-pin DIP, SOIC
s
ce
ge
ur
o
an
S
R
es
pt ins
ge
ag
ru
a
k
r
P
lt
c
te
In
Pa
Vo
I/O
s)
e(
l
du
)
es
t
by
Memory
im
TMR0
EE
M
RO
s)
e
yt
(b
y
or
em
M
M
am
r
og
Pr
36
M
RO
M
ra
pe
O
O
PR
of
n
tio
)
Hz
All PIC16/17 family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and
high I/O current capability.
All PIC16C8X family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local sales office for availability of these devices.
10
PIC16C84
a
M
um
xim
cy
n
ue
q
re
h
DS30412C-page 218
as
E.6
Fl
Clock
PIC17C4X
PIC16C8X Family of Devices
1996 Microchip Technology Inc.
1996 Microchip Technology Inc.
y
or
em
M
M
T)
R
SA
)
(s
le
u
od
ls
ne
n
ha
Features
4K
8
PIC16C924
176 TMR0,
1 SPI/I2C
TMR1, TMR2
176 TMR0,
1 SPI/I2C
TMR1, TMR2
am
—
—
5
—
4 Com
32 Seg
4 Com
32 Seg
,U
9
8
25
25
27
27
3.0-6.0
3.0-6.0
Yes
Yes
—
—
64-pin SDIP(1), TQFP,
68-pin PLCC, DIE
64-pin SDIP(1), TQFP,
68-pin PLCC, DIE
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
All PIC16CXX Family devices use serial programming with clock pin RB6 and data pin RB7.
1: Please contact your local Microchip representative for availability of this package.
4K
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PIC17C4X
PIC16C9XX Family Of Devices
DS30412C-page 219
25
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PIC17CR42
PIC17C43
PIC17CR43
PIC17C44
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TMR0,TMR1, 2 2
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58
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55
Features
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40-pin DIP;
44-pin PLCC, TQFP, MQFP
40-pin DIP;
44-pin PLCC, TQFP, MQFP
40-pin DIP;
44-pin PLCC, TQFP, MQFP
40-pin DIP;
44-pin PLCC, TQFP, MQFP
40-pin DIP;
44-pin PLCC, TQFP, MQFP
40-pin DIP;
44-pin PLCC, MQFP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
25
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PIC17C42
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DS30412C-page 220
ag
E.8
ac
k
Clock
PIC17C4X
PIC17CXX Family of Devices
1996 Microchip Technology Inc.
PIC17C4X
PIN COMPATIBILITY
Devices that have the same package type and VDD,
VSS and MCLR pin locations are said to be pin
compatible. This allows these different devices to
operate in the same socket. Compatible devices may
only requires minor software modification to allow
proper operation in the application socket
(ex., PIC16C56 and PIC16C61 devices). Not all
devices in the same package size are pin compatible;
for example, the PIC16C62 is compatible with the
PIC16C63, but not the PIC16C55.
Pin compatibility does not mean that the devices offer
the same features. As an example, the PIC16C54 is
pin compatible with the PIC16C71, but does not have
an A/D converter, weak pull-ups on PORTB, or
interrupts.
TABLE E-1:
PIN COMPATIBLE DEVICES
Pin Compatible Devices
Package
PIC12C508, PIC12C509
8-pin
PIC16C54, PIC16C54A,
PIC16CR54A,
PIC16C56,
PIC16C58A, PIC16CR58A,
PIC16C61,
PIC16C554, PIC16C556, PIC16C558
PIC16C620, PIC16C621, PIC16C622,
PIC16C710, PIC16C71, PIC16C711,
PIC16F83, PIC16CR83,
PIC16C84, PIC16F84A, PIC16CR84
18-pin
20-pin
PIC16C55,
PIC16C57, PIC16CR57B
28-pin
PIC16C62, PIC16CR62, PIC16C62A, PIC16C63,
PIC16C72, PIC16C73, PIC16C73A
28-pin
PIC16C64, PIC16CR64, PIC16C64A,
PIC16C65, PIC16C65A,
PIC16C74, PIC16C74A
40-pin
PIC17C42, PIC17CR42, PIC17C42A,
PIC17C43, PIC17CR43, PIC17C44
40-pin
PIC16C923, PIC16C924
64/68-pin
1996 Microchip Technology Inc.
DS30412C-page 221
PIC17C4X
NOTES:
DS30412C-page 222
1996 Microchip Technology Inc.
PIC17C4X
APPENDIX F: ERRATA FOR
PIC17C42 SILICON
The PIC17C42 devices that you have received have the
following anomalies. At present there is no intention for
future revisions to the present PIC17C42 silicon. If
these cause issues for the application, it is recommended that you select the PIC17C42A device.
Note:
1.
Design considerations
The device must not be operated outside of the specified voltage range. An external reset circuit must be
used to ensure the device is in reset when a brown-out
occurs or the VDD rise time is too long. Failure to
ensure that the device is in reset when device voltage
is out of specification may cause the device to lock-up
and ignore the MCLR pin.
New designs should use the PIC17C42A.
When the Oscillator Start-Up Timer (OST) is
enabled (in LF or XT oscillator modes), any interrupt that wakes the processor may cause a WDT
reset. This occurs when the WDT is greater than
or equal to 50% time-out period when the SLEEP
instruction is executed. This will not occur in
either the EC or RC oscillator modes.
Work-arounds
a)
b)
Always ensure that the CLRWDT instruction is
executed before the WDT increments past 50%
of the WDT period. This will keep the “false”
WDT reset from occurring.
When using the WDT as a normal timer (WDT
disabled), ensure that the WDT is less than or
equal to 50% time-out period when the SLEEP
instruction is executed. This can be done by
monitoring the TO bit for changing state from set
to clear. Example 1 shows putting the PIC17C42
to sleep.
EXAMPLE F-1:
LOOP
2.
BTFSS
CLRWDT
BTFSC
GOTO
SLEEP
PIC17C42 TO SLEEP
CPUSTA, TO
CPUSTA, TO
LOOP
;
;
;
;
;
TO = 0?
YES, WDT = 0
WDT rollover?
NO, Wait
YES, goto Sleep
When the clock source of Timer1 or Timer2 is
selected to external clock, the overflow interrupt
flag will be set twice, once when the timer equals
the period, and again when the timer value is
reset to 0h. If the latency to clear TMRxIF is
greater than the time to the next clock pulse, no
problems will be noticed. If the latency is less
than the time to the next timer clock pulse, the
interrupt will be serviced twice.
Work-arounds
a)
b)
Ensure that the timer has rolled over to 0h before
clearing the flag bit.
Clear the timer in software. Clearing the timer in
software causes the period to be one count less
than expected.
1996 Microchip Technology Inc.
DS30412C-page 223
This document was created with FrameMaker 4 0 4
PIC17C4X
NOTES:
DS30412C-page 224
1996 Microchip Technology Inc.
PIC17C4X
INDEX
A
ADDLW ............................................................................ 112
ADDWF ............................................................................ 112
ADDWFC ......................................................................... 113
ALU ...................................................................................... 9
ALU STATUS Register (ALUSTA) ..................................... 36
ALUSTA ............................................................... 34, 36, 108
ALUSTA Register ............................................................... 36
ANDLW ............................................................................ 113
ANDWF ............................................................................ 114
Application Notes
AN552 ........................................................................ 55
Assembler ........................................................................ 144
Asynchronous Master Transmission .................................. 90
Asynchronous Transmitter ................................................. 89
B
Bank Select Register (BSR) ............................................... 42
Banking .............................................................................. 42
Baud Rate Formula ............................................................ 86
Baud Rate Generator (BRG) .............................................. 86
Baud Rates
Asynchronous Mode .................................................. 88
Synchronous Mode .................................................... 87
BCF .................................................................................. 114
Bit Manipulation ............................................................... 108
Block Diagrams
On-chip Reset Circuit ................................................. 15
PIC17C42 .................................................................. 10
PORTD ...................................................................... 60
PORTE ....................................................................... 62
PWM .......................................................................... 75
RA0 and RA1 ............................................................. 53
RA2 and RA3 ............................................................. 54
RA4 and RA5 ............................................................. 54
RB3:RB2 Port Pins .................................................... 56
RB7:RB4 and RB1:RB0 Port Pins ............................. 55
RC7:RC0 Port Pins .................................................... 58
Timer3 with One Capture and One Period Register .. 78
TMR1 and TMR2 in 16-bit Timer/Counter Mode ........ 74
TMR1 and TMR2 in Two 8-bit Timer/Counter Mode .. 73
TMR3 with Two Capture Registers ............................ 79
WDT ......................................................................... 104
BORROW ............................................................................ 9
BRG ................................................................................... 86
Brown-out Protection ......................................................... 18
BSF .................................................................................. 115
BSR .............................................................................. 34, 42
BSR Operation ................................................................... 42
BTFSC ............................................................................. 115
BTFSS ............................................................................. 116
BTG .................................................................................. 116
C
C .................................................................................... 9, 36
C Compiler (MP-C) .......................................................... 145
CA1/PR3 ............................................................................ 72
CA1ED0 ............................................................................. 71
CA1ED1 ............................................................................. 71
CA1IE .................................................................................23
CA1IF .................................................................................24
CA1OVF .............................................................................72
CA2ED0 ..............................................................................71
CA2ED1 ..............................................................................71
CA2H ............................................................................20, 35
CA2IE ...........................................................................23, 78
CA2IF ...........................................................................24, 78
CA2L .............................................................................20, 35
CA2OVF .............................................................................72
Calculating Baud Rate Error ...............................................86
CALL ...........................................................................39, 117
Capacitor Selection
Ceramic Resonators .................................................101
Crystal Oscillator ......................................................101
Capture .........................................................................71, 78
Capture Sequence to Read Example .................................78
Capture1
Mode ...........................................................................71
Overflow .....................................................................72
Capture2
Mode ...........................................................................71
Overflow .....................................................................72
Carry (C) ...............................................................................9
Ceramic Resonators .........................................................100
Circular Buffer .....................................................................39
Clearing the Prescaler ......................................................103
Clock/Instruction Cycle (Figure) .........................................14
Clocking Scheme/Instruction Cycle (Section) .....................14
CLRF ................................................................................117
CLRWDT ..........................................................................118
Code Protection ..........................................................99, 106
COMF ...............................................................................118
Configuration
Bits ............................................................................100
Locations ..................................................................100
Oscillator ...................................................................100
Word ...........................................................................99
CPFSEQ ...........................................................................119
CPFSGT ...........................................................................119
CPFSLT ............................................................................120
CPU STATUS Register (CPUSTA) ....................................37
CPUSTA ...............................................................34, 37, 105
CREN .................................................................................84
Crystal Operation, Overtone Crystals ...............................101
Crystal or Ceramic Resonator Operation .........................100
Crystal Oscillator ..............................................................100
CSRC .................................................................................83
D
Data Memory
GPR ......................................................................29, 32
Indirect Addressing .....................................................39
Organization ...............................................................32
SFR ......................................................................29, 32
Transfer to Program Memory .....................................43
DAW .................................................................................120
DC ..................................................................................9, 36
DDRB .....................................................................19, 34, 55
DDRC .....................................................................19, 34, 58
DDRD .....................................................................19, 34, 60
DDRE .....................................................................19, 34, 62
DECF ................................................................................121
DECFSNZ .........................................................................122
DECFSZ ...........................................................................121
1996 Microchip Technology Inc.
DS30412C-page 225
This document was created with FrameMaker 4 0 4
PIC17C4X
Delay From External Clock Edge ....................................... 68
Development Support ...................................................... 143
Development Tools .......................................................... 143
Device Drawings
44-Lead Plastic Surface Mount (MQFP
10x10 mm Body 1.6/0.15 mm Lead Form) .............. 209
DIGIT BORROW .................................................................. 9
Digit Carry (DC) .................................................................... 9
Duty Cycle .......................................................................... 75
E
Electrical Characteristics
PIC17C42
Absolute Maximum Ratings ............................. 147
Capture Timing ................................................ 159
CLKOUT and I/O Timing .................................. 156
DC Characteristics ........................................... 149
External Clock Timing ...................................... 155
Memory Interface Read Timing ........................ 162
Memory Interface Write Timing ........................ 161
PWM Timing .................................................... 159
RESET, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer .............................. 157
Timer0 Clock Timings ...................................... 158
Timer1, Timer2 and Timer3 Clock Timing ........ 158
USART Module, Synchronous Receive ........... 160
USART Module, Synchronous Transmission ... 160
PIC17C43/44
Absolute Maximum Ratings ............................. 175
Capture Timing ................................................ 188
CLKOUT and I/O Timing .................................. 185
DC Characteristics ........................................... 177
External Clock Timing ...................................... 184
Memory Interface Read Timing ........................ 191
Memory Interface Write Timing ........................ 190
Parameter Measurement Information .............. 183
RESET, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer Timing .................. 186
Timer0 Clock Timing ........................................ 187
Timer1, Timer2 and Timer3 Clock Timing ........ 187
Timing Parameter Symbology .......................... 182
USART Module Synchronous Receive
Timing .............................................................. 189
USART Module Synchronous Transmission
Timing .............................................................. 189
EPROM Memory Access Time Order Suffix ...................... 31
Extended Microcontroller ................................................... 29
Extended Microcontroller Mode ......................................... 31
External Memory Interface ................................................. 31
External Program Memory Waveforms .............................. 31
F
Family of Devices ................................................................. 6
PIC14000 .................................................................. 213
PIC16C5X ................................................................ 214
PIC16CXXX .............................................................. 215
PIC16C6X ................................................................ 216
PIC16C7X ................................................................ 217
PIC16C8X ................................................................ 218
PIC16C9XX............................................................... 219
PIC17CXX ................................................................ 220
FERR ........................................................................... 84, 91
FOSC0 ............................................................................... 99
DS30412C-page 226
FOSC1 ............................................................................... 99
FS0 .................................................................................... 36
FS1 .................................................................................... 36
FS2 .................................................................................... 36
FS3 .................................................................................... 36
FSR0 ............................................................................ 34, 40
FSR1 ............................................................................ 34, 40
Fuzzy Logic Dev. System (fuzzyTECH-MP) .......... 143, 145
G
General Format for Instructions ....................................... 108
General Purpose RAM ....................................................... 29
General Purpose RAM Bank ............................................. 42
General Purpose Register (GPR) ...................................... 32
GLINTD .......................................................... 25, 37, 78, 105
GOTO .............................................................................. 122
GPR (General Purpose Register) ...................................... 32
Graphs
IOH vs. VOH, VDD = 3V ..................................... 170, 200
IOH vs. VOH, VDD = 5V ..................................... 171, 201
IOL vs. VOL, VDD = 3V ...................................... 171, 201
IOL vs. VOL, VDD = 5V ...................................... 172, 202
Maximum IDD vs. Frequency
(External Clock 125°C to -40°C) ...................... 167, 197
Maximum IPD vs. VDD Watchdog Disabled ...... 168, 198
Maximum IPD vs. VDD Watchdog Enabled ...... 169, 199
RC Oscillator Frequency vs.
VDD (Cext = 100 pF) ........................................ 164, 194
RC Oscillator Frequency vs.
VDD (Cext = 22 pF) .......................................... 164, 194
RC Oscillator Frequency vs.
VDD (Cext = 300 pF) ........................................ 165, 195
Transconductance of LF Oscillator vs.VDD ...... 166, 196
Transconductance of XT Oscillator vs. VDD .... 166, 196
Typical IDD vs. Frequency
(External Clock 25°C) ...................................... 167, 197
Typical IPD vs. VDD Watchdog Disabled 25°C . 168, 198
Typical IPD vs. VDD Watchdog Enabled 25°C .. 169, 199
Typical RC Oscillator vs. Temperature ............ 163, 193
VTH (Input Threshold Voltage) of I/O Pins vs.
VDD .................................................................. 172, 202
VTH (Input Threshold Voltage) of OSC1 Input
(In XT, HS, and LP Modes) vs. VDD ................ 173, 203
VTH, VIL of MCLR, T0CKI and OSC1
(In RC Mode) vs. VDD ...................................... 173, 203
WDT Timer Time-Out Period vs. VDD .............. 170, 200
H
Hardware Multiplier ............................................................ 49
I
I/O Ports
Bi-directional .............................................................. 64
I/O Ports .................................................................... 53
Programming Considerations .................................... 64
Read-Modify-Write Instructions ................................. 64
Successive Operations .............................................. 64
INCF ................................................................................ 123
INCFSNZ ......................................................................... 124
INCFSZ ............................................................................ 123
INDF0 .......................................................................... 34, 40
INDF1 .......................................................................... 34, 40
1996 Microchip Technology Inc.
PIC17C4X
Indirect Addressing
Indirect Addressing .................................................... 39
Operation ................................................................... 40
Registers .................................................................... 40
Initialization Conditions For Special Function Registers .... 19
Initializing PORTB .............................................................. 57
Initializing PORTC .............................................................. 58
Initializing PORTD .............................................................. 60
Initializing PORTE .............................................................. 62
Instruction Flow/Pipelining ................................................. 14
Instruction Set .................................................................. 110
ADDLW .................................................................... 112
ADDWF .................................................................... 112
ADDWFC ................................................................. 113
ANDLW .................................................................... 113
ANDWF .................................................................... 114
BCF .......................................................................... 114
BSF .......................................................................... 115
BTFSC ..................................................................... 115
BTFSS ..................................................................... 116
BTG .......................................................................... 116
CALL ........................................................................ 117
CLRF ........................................................................ 117
CLRWDT .................................................................. 118
COMF ...................................................................... 118
CPFSEQ .................................................................. 119
CPFSGT .................................................................. 119
CPFSLT ................................................................... 120
DAW ......................................................................... 120
DECF ....................................................................... 121
DECFSNZ ................................................................ 122
DECFSZ ................................................................... 121
GOTO ...................................................................... 122
INCF ......................................................................... 123
INCFSNZ ................................................................. 124
INCFSZ .................................................................... 123
IORLW ..................................................................... 124
IORWF ..................................................................... 125
LCALL ...................................................................... 125
MOVFP .................................................................... 126
MOVLB .................................................................... 126
MOVLR .................................................................... 127
MOVLW ................................................................... 127
MOVPF .................................................................... 128
MOVWF ................................................................... 128
MULLW .................................................................... 129
MULWF .................................................................... 129
NEGW ...................................................................... 130
NOP ......................................................................... 130
RETFIE .................................................................... 131
RETLW .................................................................... 131
RETURN .................................................................. 132
RLCF ........................................................................ 132
RLNCF ..................................................................... 133
RRCF ....................................................................... 133
RRNCF .................................................................... 134
SETF ........................................................................ 134
SLEEP ..................................................................... 135
SUBLW .................................................................... 135
SUBWF .................................................................... 136
SUBWFB .................................................................. 136
SWAPF .................................................................... 137
TABLRD ........................................................... 137, 138
TABLWT .......................................................... 138, 139
TLRD ........................................................................ 139
TLWT ....................................................................... 140
1996 Microchip Technology Inc.
TSTFSZ ....................................................................140
XORLW ....................................................................141
XORWF ....................................................................141
Instruction Set Summary ..................................................107
INT Pin ................................................................................26
INTE ...................................................................................22
INTEDG ........................................................................38, 67
Interrupt on Change Feature ..............................................55
Interrupt Status Register (INTSTA) ....................................22
Interrupts
Context Saving ...........................................................27
Flag bits
TMR1IE ..............................................................21
TMR1IF ..............................................................21
TMR2IE ..............................................................21
TMR2IF ..............................................................21
TMR3IE ..............................................................21
TMR3IF ..............................................................21
Interrupts ....................................................................21
Logic ...........................................................................21
Operation ....................................................................25
Peripheral Interrupt Enable .........................................23
Peripheral Interrupt Request ......................................24
PWM ...........................................................................76
Status Register ...........................................................22
Table Write Interaction ...............................................45
Timing .........................................................................26
Vectors
Peripheral Interrupt .............................................26
RA0/INT Interrupt ...............................................26
T0CKI Interrupt ...................................................26
TMR0 Interrupt ...................................................26
Vectors/Priorities ........................................................25
Wake-up from SLEEP ..............................................105
INTF ....................................................................................22
INTSTA ...............................................................................34
INTSTA Register ................................................................22
IORLW ..............................................................................124
IORWF ..............................................................................125
L
LCALL ...............................................................................125
Long Writes ........................................................................45
M
Memory
External Interface .......................................................31
External Memory Waveforms .....................................31
Memory Map (Different Modes) ..................................30
Mode Memory Access ................................................30
Organization ...............................................................29
Program Memory ........................................................29
Program Memory Map ................................................29
Microcontroller ....................................................................29
Microprocessor ...................................................................29
Minimizing Current Consumption .....................................106
MOVFP .............................................................................126
MOVLB .............................................................................126
MOVLR .............................................................................127
MOVLW ............................................................................127
MOVPF .............................................................................128
MOVWF ............................................................................128
MPASM Assembler ..................................................143, 144
DS30412C-page 227
PIC17C4X
MP-C C Compiler ............................................................. 145
MPSIM Software Simulator ...................................... 143, 145
MULLW ............................................................................ 129
Multiply Examples
16 x 16 Routine .......................................................... 50
16 x 16 Signed Routine .............................................. 51
8 x 8 Routine .............................................................. 49
8 x 8 Signed Routine .................................................. 49
MULWF ............................................................................ 129
N
NEGW .............................................................................. 130
NOP ................................................................................. 130
O
OERR ................................................................................. 84
Opcode Field Descriptions ............................................... 107
OSC Selection .................................................................... 99
Oscillator
Configuration ............................................................ 100
Crystal ...................................................................... 100
External Clock .......................................................... 101
External Crystal Circuit ............................................ 102
External Parallel Resonant Crystal Circuit ............... 102
External Series Resonant Crystal Circuit ................. 102
RC ............................................................................ 102
RC Frequencies ............................................... 165, 195
Oscillator Start-up Time (Figure) ........................................ 18
Oscillator Start-up Timer (OST) ................................... 15, 99
OST .............................................................................. 15, 99
OV .................................................................................. 9, 36
Overflow (OV) ...................................................................... 9
P
Package Marking Information .......................................... 210
Packaging Information ..................................................... 205
Parameter Measurement Information .............................. 154
PC (Program Counter) ....................................................... 41
PCH .................................................................................... 41
PCL ...................................................................... 34, 41, 108
PCLATH ....................................................................... 34, 41
PD .............................................................................. 37, 105
PEIE ............................................................................. 22, 78
PEIF ................................................................................... 22
Peripheral Bank .................................................................. 42
Peripheral Interrupt Enable ................................................ 23
Peripheral Interrupt Request (PIR) ..................................... 24
PICDEM-1 Low-Cost PIC16/17 Demo Board ........... 143, 144
PICDEM-2 Low-Cost PIC16CXX Demo Board ........ 143, 144
PICDEM-3 Low-Cost PIC16C9XXX Demo Board ............ 144
PICMASTER RT In-Circuit Emulator ............................. 143
PICSTART Low-Cost Development System .................. 143
PIE ............................................................. 19, 34, 92, 96, 98
Pin Compatible Devices ................................................... 221
PIR ............................................................. 19, 34, 92, 96, 98
PM0 ............................................................................ 99, 106
PM1 ............................................................................ 99, 106
POP .............................................................................. 27, 39
POR ............................................................................. 15, 99
PORTA ................................................................... 19, 34, 53
PORTB ................................................................... 19, 34, 55
PORTC ................................................................... 19, 34, 58
DS30412C-page 228
PORTD .................................................................. 19, 34, 60
PORTE .................................................................. 19, 34, 62
Power-down Mode ........................................................... 105
Power-on Reset (POR) ................................................ 15, 99
Power-up Timer (PWRT) ............................................. 15, 99
PR1 .............................................................................. 20, 35
PR2 .............................................................................. 20, 35
PR3/CA1H ......................................................................... 20
PR3/CA1L .......................................................................... 20
PR3H/CA1H ....................................................................... 35
PR3L/CA1L ........................................................................ 35
Prescaler Assignments ...................................................... 69
PRO MATE Universal Programmer ............................... 143
PRODH .............................................................................. 20
PRODL .............................................................................. 20
Program Counter (PC) ....................................................... 41
Program Memory
External Access Waveforms ...................................... 31
External Connection Diagram .................................... 31
Map ............................................................................ 29
Modes
Extended Microcontroller ................................... 29
Microcontroller ................................................... 29
Microprocessor .................................................. 29
Protected Microcontroller ................................... 29
Operation ................................................................... 29
Organization .............................................................. 29
Transfers from Data Memory ..................................... 43
Protected Microcontroller ................................................... 29
PS0 .............................................................................. 38, 67
PS1 .............................................................................. 38, 67
PS2 .............................................................................. 38, 67
PS3 .............................................................................. 38, 67
PUSH ........................................................................... 27, 39
PW1DCH ..................................................................... 20, 35
PW1DCL ...................................................................... 20, 35
PW2DCH ..................................................................... 20, 35
PW2DCL ...................................................................... 20, 35
PWM ............................................................................ 71, 75
Duty Cycle ................................................................. 76
External Clock Source ............................................... 76
Frequency vs. Resolution .......................................... 76
Interrupts ................................................................... 76
Max Resolution/Frequency for External
Clock Input ................................................................. 77
Output ........................................................................ 75
Periods ...................................................................... 76
PWM1 ................................................................................ 72
PWM1ON ..................................................................... 72, 75
PWM2 ................................................................................ 72
PWM2ON ..................................................................... 72, 75
PWRT .......................................................................... 15, 99
R
RA1/T0CKI pin ................................................................... 67
RBIE .................................................................................. 23
RBIF ................................................................................... 24
RBPU ................................................................................. 55
RC Oscillator .................................................................... 102
RC Oscillator Frequencies ....................................... 165, 195
RCIE .................................................................................. 23
RCIF .................................................................................. 24
RCREG ................................................ 19, 34, 91, 92, 96, 97
RCSTA ....................................................... 19, 34, 92, 96, 98
Reading 16-bit Value ......................................................... 69
1996 Microchip Technology Inc.
PIC17C4X
Receive Status and Control Register ................................. 83
Register File Map ............................................................... 33
Registers
ALUSTA ............................................................... 27, 36
BRG ........................................................................... 86
BSR ............................................................................ 27
CPUSTA .................................................................... 37
File Map ..................................................................... 33
FSR0 .......................................................................... 40
FSR1 .......................................................................... 40
INDF0 ......................................................................... 40
INDF1 ......................................................................... 40
INTSTA ...................................................................... 22
PIE ............................................................................. 23
PIR ............................................................................. 24
RCSTA ....................................................................... 84
Special Function Table .............................................. 34
T0STA .................................................................. 38, 67
TCON1 ....................................................................... 71
TCON2 ....................................................................... 72
TMR1 ......................................................................... 81
TMR2 ......................................................................... 81
TMR3 ......................................................................... 81
TXSTA ....................................................................... 83
WREG ........................................................................ 27
Reset
Section ....................................................................... 15
Status Bits and Their Significance ............................. 16
Time-Out in Various Situations .................................. 16
Time-Out Sequence ................................................... 16
RETFIE ............................................................................ 131
RETLW ............................................................................ 131
RETURN .......................................................................... 132
RLCF ................................................................................ 132
RLNCF ............................................................................. 133
RRCF ............................................................................... 133
RRNCF ............................................................................ 134
RX Pin Sampling Scheme .................................................. 91
RX9 .................................................................................... 84
RX9D ................................................................................. 84
S
Sampling ............................................................................ 91
Saving STATUS and WREG in RAM ................................. 27
SETF ................................................................................ 134
SFR .................................................................................. 108
SFR (Special Function Registers) ................................ 29, 32
SFR As Source/Destination ............................................. 108
Signed Math ......................................................................... 9
SLEEP ............................................................... 99, 105, 135
Software Simulator (MPSIM) ........................................... 145
SPBRG ...................................................... 19, 34, 92, 96, 98
Special Features of the CPU ............................................. 99
Special Function Registers ............................ 29, 32, 34, 108
SPEN ................................................................................. 84
SREN ................................................................................. 84
Stack
Operation ................................................................... 39
Pointer ........................................................................ 39
Stack .......................................................................... 29
STKAL ................................................................................ 39
STKAV ............................................................................... 37
SUBLW ............................................................................ 135
SUBWF ............................................................................ 136
SUBWFB .......................................................................... 136
1996 Microchip Technology Inc.
SWAPF .............................................................................137
SYNC ..................................................................................83
Synchronous Master Mode .................................................93
Synchronous Master Reception .........................................95
Synchronous Master Transmission ....................................93
Synchronous Slave Mode ...................................................97
T
T0CKI Pin ...........................................................................26
T0CKIE ...............................................................................22
T0CKIF ...............................................................................22
T0CS ............................................................................38, 67
T0IE ....................................................................................22
T0IF ....................................................................................22
T0SE .............................................................................38, 67
T0STA ..........................................................................34, 38
T16 .....................................................................................71
Table Latch .........................................................................40
Table Pointer ......................................................................40
Table Read
Example ......................................................................48
Section ........................................................................43
Table Reads Section ..................................................48
TABLRD Operation .....................................................44
Timing .........................................................................48
TLRD ..........................................................................48
TLRD Operation .........................................................44
Table Write
Code ...........................................................................46
Interaction ...................................................................45
Section ........................................................................43
TABLWT Operation ....................................................43
Terminating Long Writes ............................................45
Timing .........................................................................46
TLWT Operation .........................................................43
To External Memory ...................................................46
To Internal Memory ....................................................45
TABLRD .............................................................44, 137, 138
TABLWT .............................................................43, 138, 139
TBLATH ..............................................................................40
TBLATL ..............................................................................40
TBLPTRH .....................................................................34, 40
TBLPTRL ......................................................................34, 40
TCLK12 ..............................................................................71
TCLK3 ................................................................................71
TCON1 .........................................................................20, 35
TCON2 .........................................................................20, 35
Terminating Long Writes ....................................................45
Time-Out Sequence ...........................................................16
Timer Resources ................................................................65
Timer0 ................................................................................67
Timer1
16-bit Mode .................................................................74
Clock Source Select ...................................................71
On bit ..........................................................................72
Section ..................................................................71, 73
Timer2
16-bit Mode .................................................................74
Clock Source Select ...................................................71
On bit ..........................................................................72
Section ..................................................................71, 73
Timer3
Clock Source Select ...................................................71
On bit ..........................................................................72
Section ..................................................................71, 77
DS30412C-page 229
PIC17C4X
Timing Diagrams
Asynchronous Master Transmission .......................... 90
Asynchronous Reception ........................................... 92
Back to Back Asynchronous Master Transmission .... 90
Interrupt (INT, TMR0 Pins) ......................................... 26
PIC17C42 Capture ................................................... 159
PIC17C42 CLKOUT and I/O .................................... 156
PIC17C42 Memory Interface Read .......................... 162
PIC17C42 Memory Interface Write .......................... 161
PIC17C42 PWM Timing ........................................... 159
PIC17C42 RESET, Watchdog Timer, Oscillator
Start-up Timer and Power-up Timer ........................ 157
PIC17C42 Timer0 Clock .......................................... 158
PIC17C42 Timer1, Timer2 and Timer3 Clock .......... 158
PIC17C42 USART Module, Synchronous
Receive .................................................................... 160
PIC17C42 USART Module, Synchronous
Transmission ............................................................ 160
PIC17C43/44 Capture Timing .................................. 188
PIC17C43/44 CLKOUT and I/O ............................... 185
PIC17C43/44 External Clock ................................... 184
PIC17C43/44 Memory Interface Read ..................... 191
PIC17C43/44 Memory Interface Write ..................... 190
PIC17C43/44 PWM Timing ...................................... 188
PIC17C43/44 RESET, Watchdog Timer, Oscillator
Start-up Timer and Power-up Timer ........................ 186
PIC17C43/44 Timer0 Clock ..................................... 187
PIC17C43/44 Timer1, Timer2 and Timer3 Clock ..... 187
PIC17C43/44 USART Module Synchronous
Receive .................................................................... 189
PIC17C43/44 USART Module Synchronous
Transmission ............................................................ 189
Synchronous Reception ............................................. 95
Synchronous Transmission ........................................ 94
Table Read ................................................................ 48
Table Write ................................................................. 46
TMR0 ................................................................... 68, 69
TMR0 Read/Write in Timer Mode .............................. 70
TMR1, TMR2, and TMR3 in External Clock Mode ..... 80
TMR1, TMR2, and TMR3 in Timer Mode ................... 81
Wake-Up from SLEEP ............................................. 105
Timing Diagrams and Specifications ................................ 155
Timing Parameter Symbology .......................................... 153
TLRD .......................................................................... 44, 139
TLWT ......................................................................... 43, 140
TMR0
16-bit Read ................................................................ 69
16-bit Write ................................................................. 69
Clock Timing ............................................................ 158
Module ....................................................................... 68
Operation ................................................................... 68
Overview .................................................................... 65
Prescaler Assignments .............................................. 69
Read/Write Considerations ........................................ 69
Read/Write in Timer Mode ......................................... 70
Timing .................................................................. 68, 69
TMR0 STATUS/Control Register (T0STA) ......................... 38
TMR0H ............................................................................... 34
TMR0L ............................................................................... 34
TMR1 ........................................................................... 20, 35
8-bit Mode .................................................................. 73
External Clock Input ................................................... 73
Overview .................................................................... 65
Timer Mode ................................................................ 81
Timing in External Clock Mode .................................. 80
Two 8-bit Timer/Counter Mode .................................. 73
DS30412C-page 230
Using with PWM ........................................................ 75
TMR1CS ............................................................................ 71
TMR1IE .............................................................................. 23
TMR1IF .............................................................................. 24
TMR1ON ............................................................................ 72
TMR2 ........................................................................... 20, 35
8-bit Mode .................................................................. 73
External Clock Input .................................................. 73
In Timer Mode ........................................................... 81
Timing in External Clock Mode .................................. 80
Two 8-bit Timer/Counter Mode .................................. 73
Using with PWM ........................................................ 75
TMR2CS ............................................................................ 71
TMR2IE .............................................................................. 23
TMR2IF .............................................................................. 24
TMR2ON ............................................................................ 72
TMR3
Dual Capture1 Register Mode ................................... 79
Example, Reading From ............................................ 80
Example, Writing To .................................................. 80
External Clock Input .................................................. 80
In Timer Mode ........................................................... 81
One Capture and One Period Register Mode ........... 78
Overview .................................................................... 65
Reading/Writing ......................................................... 80
Timing in External Clock Mode .................................. 80
TMR3CS ...................................................................... 71, 77
TMR3H ........................................................................ 20, 35
TMR3IE .............................................................................. 23
TMR3IF ........................................................................ 24, 77
TMR3L ......................................................................... 20, 35
TMR3ON ...................................................................... 72, 77
TO ...................................................................... 37, 103, 105
Transmit Status and Control Register ................................ 83
TRMT ................................................................................. 83
TSTFSZ ........................................................................... 140
Turning on 16-bit Timer ..................................................... 74
TX9 .................................................................................... 83
TX9d .................................................................................. 83
TXEN ................................................................................. 83
TXIE ................................................................................... 23
TXIF ................................................................................... 24
TXREG ................................................ 19, 34, 89, 93, 97, 98
TXSTA ....................................................... 19, 34, 92, 96, 98
U
Upward Compatibility ........................................................... 5
USART
Asynchronous Master Transmission ......................... 90
Asynchronous Mode .................................................. 89
Asynchronous Receive .............................................. 91
Asynchronous Transmitter ......................................... 89
Baud Rate Generator ................................................ 86
Synchronous Master Mode ........................................ 93
Synchronous Master Reception ................................ 95
Synchronous Master Transmission ........................... 93
Synchronous Slave Mode .......................................... 97
Synchronous Slave Transmit ..................................... 97
W
Wake-up from SLEEP ...................................................... 105
Wake-up from SLEEP Through Interrupt ......................... 105
Watchdog Timer ........................................................ 99, 103
1996 Microchip Technology Inc.
PIC17C4X
WDT ........................................................................... 99, 103
Clearing the WDT .................................................... 103
Normal Timer ........................................................... 103
Period ....................................................................... 103
Programming Considerations .................................. 103
WDTPS0 ............................................................................ 99
WDTPS1 ............................................................................ 99
WREG ................................................................................ 34
X
XORLW ............................................................................ 141
XORWF ............................................................................ 141
Z
Z ..................................................................................... 9, 36
Zero (Z) ................................................................................ 9
LIST OF EXAMPLES
Example 3-1:
Example 3-2:
Example 5-1:
Example 6-1:
Example 7-1:
Example 7-2:
Example 8-1:
Example 8-2:
Example 8-3:
Example 8-4:
Example 9-1:
Example 9-2:
Example 9-3:
Example 9-4:
Example 9-5:
Example 11-1:
Example 11-2:
Example 12-1:
Example 12-2:
Example 12-3:
Example 13-1:
Example F-1:
Signed Math ..................................................9
Instruction Pipeline Flow .............................14
Saving STATUS and WREG in RAM ..........27
Indirect Addressing......................................40
Table Write ..................................................46
Table Read..................................................48
8 x 8 Multiply Routine ..................................49
8 x 8 Signed Multiply Routine......................49
16 x 16 Multiply Routine ..............................50
16 x 16 Signed Multiply Routine..................51
Initializing PORTB .......................................57
Initializing PORTC .......................................58
Initializing PORTD .......................................60
Initializing PORTE .......................................62
Read Modify Write Instructions on an
I/O Port ........................................................64
16-Bit Read .................................................69
16-Bit Write..................................................69
Sequence to Read Capture Registers.........78
Writing to TMR3 ..........................................80
Reading from TMR3 ....................................80
Calculating Baud Rate Error........................86
PIC17C42 to Sleep....................................223
LIST OF FIGURES
Figure 3-1:
Figure 3-2:
Figure 3-3:
Figure 4-1:
Figure 4-2:
Figure 4-3:
Figure 4-4:
Figure 4-5:
Figure 4-6:
Figure 4-7:
Figure 4-8:
Figure 4-9:
Figure 5-1:
Figure 5-2:
Figure 5-3:
Figure 5-4:
Figure 5-5:
Figure 6-1:
Figure 6-2:
Figure 6-3:
Figure 6-4:
Figure 6-5:
Figure 6-6:
Figure 6-7:
Figure 6-8:
Figure 6-9:
Figure 6-10:
Figure 6-11:
1996 Microchip Technology Inc.
PIC17C42 Block Diagram ...........................10
PIC17CR42/42A/43/R43/44 Block
Diagram.......................................................11
Clock/Instruction Cycle................................14
Simplified Block Diagram of On-chip
Reset Circuit................................................15
Time-Out Sequence on Power-Up
(MCLR Tied to VDD) ....................................17
Time-Out Sequence on Power-Up
(MCLR NOT Tied to VDD)............................17
Slow Rise Time (MCLR Tied to VDD) ..........17
Oscillator Start-Up Time ..............................18
Using On-Chip POR ....................................18
Brown-out Protection Circuit 1.....................18
PIC17C42 External Power-On Reset
Circuit (For Slow VDD Power-Up) ................18
Brown-out Protection Circuit 2.....................18
Interrupt Logic .............................................21
INTSTA Register (Address: 07h,
Unbanked)...................................................22
PIE Register (Address: 17h, Bank 1) ..........23
PIR Register (Address: 16h, Bank 1) ..........24
INT Pin / T0CKI Pin Interrupt Timing...........26
Program Memory Map and Stack................29
Memory Map in Different Modes .................30
External Program Memory Access
Waveforms ..................................................31
Typical External Program Memory
Connection Diagram....................................31
PIC17C42 Register File Map.......................33
PIC17CR42/42A/43/R43/44 Register
File Map.......................................................33
ALUSTA Register (Address: 04h,
Unbanked)...................................................36
CPUSTA Register (Address: 06h,
Unbanked)...................................................37
T0STA Register (Address: 05h,
Unbanked)...................................................38
Indirect Addressing......................................39
Program Counter Operation ........................41
DS30412C-page 231
PIC17C4X
Figure 6-12:
Program Counter using The CALL and
GOTO Instructions...................................... 41
Figure 6-13: BSR Operation (PIC17C43/R43/44) ........... 42
Figure 7-1:
TLWT Instruction Operation........................ 43
Figure 7-2:
TABLWT Instruction Operation................... 43
Figure 7-3:
TLRD Instruction Operation ........................ 44
Figure 7-4:
TABLRD Instruction Operation ................... 44
Figure 7-5:
TABLWT Write Timing
(External Memory) ...................................... 46
Figure 7-6:
Consecutive TABLWT Write Timing
(External Memory) ...................................... 47
Figure 7-7:
TABLRD Timing.......................................... 48
Figure 7-8:
TABLRD Timing (Consecutive TABLRD
Instructions) ................................................ 48
Figure 9-1:
RA0 and RA1 Block Diagram ..................... 53
Figure 9-2:
RA2 and RA3 Block Diagram ..................... 54
Figure 9-3:
RA4 and RA5 Block Diagram ..................... 54
Figure 9-4:
Block Diagram of RB<7:4> and RB<1:0>
Port Pins ..................................................... 55
Figure 9-5:
Block Diagram of RB3 and RB2 Port Pins.. 56
Figure 9-6:
Block Diagram of RC<7:0> Port Pins ......... 58
Figure 9-7:
PORTD Block Diagram
(in I/O Port Mode) ....................................... 60
Figure 9-8:
PORTE Block Diagram
(in I/O Port Mode) ....................................... 62
Figure 9-9:
Successive I/O Operation ........................... 64
Figure 11-1: T0STA Register (Address: 05h,
Unbanked) .................................................. 67
Figure 11-2: Timer0 Module Block Diagram ................... 68
Figure 11-3: TMR0 Timing with External Clock
(Increment on Falling Edge) ....................... 68
Figure 11-4: TMR0 Timing: Write High or Low Byte ....... 69
Figure 11-5: TMR0 Read/Write in Timer Mode ............... 70
Figure 12-1: TCON1 Register (Address: 16h, Bank 3) ... 71
Figure 12-2: TCON2 Register (Address: 17h, Bank 3) ... 72
Figure 12-3: Timer1 and Timer2 in Two 8-bit
Timer/Counter Mode................................... 73
Figure 12-4: TMR1 and TMR2 in 16-bit Timer/Counter
Mode........................................................... 74
Figure 12-5: Simplified PWM Block Diagram .................. 75
Figure 12-6: PWM Output ............................................... 75
Figure 12-7: Timer3 with One Capture and One
Period Register Block Diagram................... 78
Figure 12-8: Timer3 with Two Capture Registers
Block Diagram ............................................ 79
Figure 12-9: TMR1, TMR2, and TMR3 Operation in
External Clock Mode................................... 80
Figure 12-10: TMR1, TMR2, and TMR3 Operation in
Timer Mode................................................. 81
Figure 13-1: TXSTA Register (Address: 15h, Bank 0) .... 83
Figure 13-2: RCSTA Register (Address: 13h, Bank 0) ... 84
Figure 13-3: USART Transmit......................................... 85
Figure 13-4: USART Receive.......................................... 85
Figure 13-5: Asynchronous Master Transmission........... 90
Figure 13-6: Asynchronous Master Transmission
(Back to Back) ............................................ 90
Figure 13-7: RX Pin Sampling Scheme .......................... 91
Figure 13-8: Asynchronous Reception............................ 92
Figure 13-9: Synchronous Transmission ........................ 94
Figure 13-10: Synchronous Transmission
(Through TXEN) ......................................... 94
Figure 13-11: Synchronous Reception (Master Mode,
SREN)......................................................... 95
Figure 14-1: Configuration Word..................................... 99
Figure 14-2: Crystal or Ceramic Resonator Operation
(XT or LF OSC Configuration) .................. 100
DS30412C-page 232
Figure 14-3:
Figure 14-4:
Figure 14-5:
Figure 14-6:
Figure 14-7:
Figure 14-8:
Figure 14-9:
Figure 15-1:
Figure 15-2:
Figure 17-1:
Figure 17-2:
Figure 17-3:
Figure 17-4:
Figure 17-5:
Figure 17-6:
Figure 17-7:
Figure 17-8:
Figure 17-9:
Figure 17-10:
Figure 17-11:
Figure 17-12:
Figure 18-1:
Figure 18-2:
Figure 18-3:
Figure 18-4:
Figure 18-5:
Figure 18-6:
Figure 18-7:
Figure 18-8:
Figure 18-9:
Figure 18-10:
Figure 18-11:
Figure 18-12:
Figure 18-13:
Figure 18-14:
Figure 18-15:
Figure 18-16:
Figure 18-17:
Figure 18-18:
Figure 18-19:
Figure 18-20:
Figure 19-1:
Crystal Operation, Overtone Crystals
(XT OSC Configuration) ........................... 101
External Clock Input Operation
(EC OSC Configuration)........................... 101
External Parallel Resonant Crystal
Oscillator Circuit ....................................... 102
External Series Resonant Crystal
Oscillator Circuit ....................................... 102
RC Oscillator Mode .................................. 102
Watchdog Timer Block Diagram............... 104
Wake-up From Sleep Through Interrupt... 105
General Format for Instructions................ 108
Q Cycle Activity ........................................ 109
Parameter Measurement Information....... 154
External Clock Timing .............................. 155
CLKOUT and I/O Timing .......................... 156
Reset, Watchdog Timer,
Oscillator Start-Up Timer and
Power-Up Timer Timing ........................... 157
Timer0 Clock Timings............................... 158
Timer1, Timer2, And Timer3 Clock
Timings..................................................... 158
Capture Timings ....................................... 159
PWM Timings ........................................... 159
USART Module: Synchronous
Transmission (Master/Slave) Timing ........ 160
USART Module: Synchronous Receive
(Master/Slave) Timing .............................. 160
Memory Interface Write Timing ................ 161
Memory Interface Read Timing ................ 162
Typical RC Oscillator Frequency
vs. Temperature ....................................... 163
Typical RC Oscillator Frequency
vs. VDD ..................................................... 164
Typical RC Oscillator Frequency
vs. VDD ..................................................... 164
Typical RC Oscillator Frequency
vs. VDD ..................................................... 165
Transconductance (gm) of LF Oscillator
vs. VDD ..................................................... 166
Transconductance (gm) of XT Oscillator
vs. VDD ..................................................... 166
Typical IDD vs. Frequency (External
Clock 25°C) .............................................. 167
Maximum IDD vs. Frequency (External
Clock 125°C to -40°C) .............................. 167
Typical IPD vs. VDD Watchdog
Disabled 25°C .......................................... 168
Maximum IPD vs. VDD Watchdog
Disabled ................................................... 168
Typical IPD vs. VDD Watchdog
Enabled 25°C ........................................... 169
Maximum IPD vs. VDD Watchdog
Enabled .................................................... 169
WDT Timer Time-Out Period vs. VDD ...... 170
IOH vs. VOH, VDD = 3V.............................. 170
IOH vs. VOH, VDD = 5V.............................. 171
IOL vs. VOL, VDD = 3V............................... 171
IOL vs. VOL, VDD = 5V............................... 172
VTH (Input Threshold Voltage) of
I/O Pins (TTL) VS. VDD ............................. 172
VTH, VIL of I/O Pins (Schmitt Trigger) VS.
VDD ........................................................... 173
VTH (Input Threshold Voltage) of OSC1
Input (In XT and LF Modes) vs. VDD ........ 173
Parameter Measurement Information....... 183
1996 Microchip Technology Inc.
PIC17C4X
Figure 19-2:
Figure 19-3:
Figure 19-4:
Figure 19-5:
Figure 19-6:
Figure 19-7:
Figure 19-8:
Figure 19-9:
Figure 19-10:
Figure 19-11:
Figure 19-12:
Figure 20-1:
Figure 20-2:
Figure 20-3:
Figure 20-4:
Figure 20-5:
Figure 20-6:
Figure 20-7:
Figure 20-8:
Figure 20-9:
Figure 20-10:
Figure 20-11:
Figure 20-12:
Figure 20-13:
Figure 20-14:
Figure 20-15:
Figure 20-16:
Figure 20-17:
Figure 20-18:
Figure 20-19:
Figure 20-20:
External Clock Timing............................... 184
CLKOUT and I/O Timing........................... 185
Reset, Watchdog Timer,
Oscillator Start-Up Timer, and
Power-Up Timer Timing............................ 186
Timer0 Clock Timings ............................... 187
Timer1, Timer2, and Timer3 Clock
Timings ..................................................... 187
Capture Timings ....................................... 188
PWM Timings ........................................... 188
USART Module: Synchronous
Transmission (Master/Slave) Timing ........ 189
USART Module: Synchronous
Receive (Master/Slave) Timing................. 189
Memory Interface Write Timing
(Not Supported in PIC17LC4X Devices)... 190
Memory Interface Read Timing
(Not Supported in PIC17LC4X Devices)... 191
Typical RC Oscillator Frequency vs.
Temperature ............................................. 193
Typical RC Oscillator Frequency
vs. VDD...................................................... 194
Typical RC Oscillator Frequency
vs. VDD...................................................... 194
Typical RC Oscillator Frequency
vs. VDD...................................................... 195
Transconductance (gm) of LF Oscillator
vs. VDD...................................................... 196
Transconductance (gm) of XT Oscillator
vs. VDD...................................................... 196
Typical IDD vs. Frequency (External
Clock 25°C)............................................... 197
Maximum IDD vs. Frequency (External
Clock 125°C to -40°C) .............................. 197
Typical IPD vs. VDD Watchdog
Disabled 25°C........................................... 198
Maximum IPD vs. VDD Watchdog
Disabled.................................................... 198
Typical IPD vs. VDD Watchdog
Enabled 25°C............................................ 199
Maximum IPD vs. VDD Watchdog
Enabled..................................................... 199
WDT Timer Time-Out Period vs. VDD ....... 200
IOH vs. VOH, VDD = 3V .............................. 200
IOH vs. VOH, VDD = 5V .............................. 201
IOL vs. VOL, VDD = 3V ............................... 201
IOL vs. VOL, VDD = 5V ............................... 202
VTH (Input Threshold Voltage) of
I/O Pins (TTL) VS. VDD .............................. 202
VTH, VIL of I/O Pins (Schmitt Trigger)
VS. VDD ..................................................... 203
VTH (Input Threshold Voltage) of OSC1
Input (In XT and LF Modes) vs. VDD........ 203
Table 6-2:
Table 6-3:
Table 7-1:
Table 8-1:
Table 9-1:
Table 9-2:
Table 9-3:
Table 9-4:
Table 9-5:
Table 9-6:
Table 9-7:
Table 9-8:
Table 9-9:
Table 9-10:
Table 11-1:
Table 12-1:
Table 12-2:
Table 12-3:
Table 12-4:
Table 12-5:
Table 12-6:
Table 13-1:
Table 13-2:
Table 13-3:
Table 13-4:
Table 13-5:
Table 13-6:
Table 13-7:
Table 13-8:
Table 13-9:
Table 13-10:
Table 14-1:
Table 14-2:
Table 14-3:
Table 14-4:
Table 15-1:
Table 15-2:
Table 16-1:
Table 17-1:
LIST OF TABLES
Table 1-1:
Table 3-1:
Table 4-1:
Table 4-2:
Table 4-3:
Table 4-4:
Table 5-1:
Table 6-1:
PIC17CXX Family of Devices ....................... 6
Pinout Descriptions..................................... 12
Time-Out in Various Situations ................... 16
STATUS Bits and Their Significance .......... 16
Reset Condition for the Program Counter
and the CPUSTA Register.......................... 16
Initialization Conditions For Special
Function Registers...................................... 19
Interrupt Vectors/Priorities .......................... 25
Mode Memory Access ................................ 30
1996 Microchip Technology Inc.
Table 17-2:
Table 17-3:
Table 17-4:
Table 17-5:
Table 17-6:
Table 17-7:
Table 17-8:
EPROM Memory Access Time
Ordering Suffix ............................................31
Special Function Registers..........................34
Interrupt - Table Write Interaction................45
Performance Comparison ...........................49
PORTA Functions .......................................54
Registers/Bits Associated with PORTA.......54
PORTB Functions .......................................57
Registers/Bits Associated with PORTB.......57
PORTC Functions .......................................59
Registers/Bits Associated with PORTC.......59
PORTD Functions .......................................61
Registers/Bits Associated with PORTD.......61
PORTE Functions .......................................63
Registers/Bits Associated with PORTE.......63
Registers/Bits Associated with Timer0 ........70
Turning On 16-bit Timer ..............................74
Summary of Timer1 and Timer2
Registers .....................................................74
PWM Frequency vs. Resolution at
25 MHz ........................................................76
Registers/Bits Associated with PWM ..........77
Registers Associated with Capture .............79
Summary of TMR1, TMR2, and TMR3
Registers .....................................................81
Baud Rate Formula .....................................86
Registers Associated with Baud Rate
Generator ....................................................86
Baud Rates for Synchronous Mode ............87
Baud Rates for Asynchronous Mode...........88
Registers Associated with Asynchronous
Transmission ...............................................90
Registers Associated with Asynchronous
Reception ....................................................92
Registers Associated with Synchronous
Master Transmission ...................................94
Registers Associated with Synchronous
Master Reception ........................................96
Registers Associated with Synchronous
Slave Transmission .....................................98
Registers Associated with Synchronous
Slave Reception ..........................................98
Configuration Locations.............................100
Capacitor Selection for Ceramic
Resonators ................................................101
Capacitor Selection for Crystal
OscillatoR ..................................................101
Registers/Bits Associated with the
Watchdog Timer ........................................104
Opcode Field Descriptions ........................107
PIC17CXX Instruction Set .........................110
development tools from microchip.............146
Cross Reference of Device Specs for
Oscillator Configurations and Frequencies
of Operation (Commercial Devices) ..........148
External Clock Timing Requirements ........155
CLKOUT and I/O Timing Requirements....156
Reset, Watchdog Timer,
Oscillator Start-Up Timer and
Power-Up Timer Requirements.................157
Timer0 Clock Requirements......................158
Timer1, Timer2, and Timer3 Clock
Requirements ............................................158
Capture Requirements ..............................159
PWM Requirements ..................................159
DS30412C-page 233
PIC17C4X
Table 17-9:
Table 17-10:
Table 17-11:
Table 17-12:
Table 18-1:
Table 18-2:
Table 19-1:
Table 19-2:
Table 19-3:
Table 19-4:
Table 19-5:
Table 19-6:
Table 19-7:
Table 19-8:
Table 19-9:
Table 19-10:
Table 19-11:
Table 19-12:
Table 20-1:
Table 20-2:
Table E-1:
Serial Port Synchronous Transmission
Requirements ........................................... 160
Serial Port Synchronous Receive
Requirements ........................................... 160
Memory Interface Write Requirements ..... 161
Memory Interface Read Requirements..... 162
Pin Capacitance per Package Type ......... 163
RC Oscillator Frequencies........................ 165
Cross Reference of Device Specs for
Oscillator Configurations and Frequencies
of Operation (Commercial Devices).......... 176
External Clock Timing Requirements ....... 184
CLKOUT and I/O Timing Requirements ... 185
Reset, Watchdog Timer,
Oscillator Start-Up Timer and
Power-Up Timer Requirements ................ 186
Timer0 Clock Requirements ..................... 187
Timer1, Timer2, and Timer3 Clock
Requirements ........................................... 187
Capture Requirements.............................. 188
PWM Requirements.................................. 188
Synchronous Transmission
Requirements ........................................... 189
Synchronous Receive Requirements ....... 189
Memory Interface Write Requirements
(Not Supported in PIC17LC4X Devices)... 190
Memory Interface read Requirements
(Not Supported in PIC17LC4X Devices)... 191
Pin Capacitance per Package Type ......... 193
RC Oscillator Frequencies........................ 195
Pin Compatible Devices............................ 221
LIST OF EQUATIONS
Equation 8-1: 16 x 16 Unsigned Multiplication
Algorithm..................................................... 50
Equation 8-2: 16 x 16 Signed Multiplication
Algorithm..................................................... 51
DS30412C-page 234
1996 Microchip Technology Inc.
PIC17C4X
ON-LINE SUPPORT
Microchip provides two methods of on-line support.
These are the Microchip BBS and the Microchip World
Wide Web (WWW) site.
Use Microchip's Bulletin Board Service (BBS) to get
current information and help about Microchip products.
Microchip provides the BBS communication channel for
you to use in extending your technical staff with microcontroller and memory experts.
To provide you with the most responsive service possible,
the Microchip systems team monitors the BBS, posts
the latest component data and software tool updates,
provides technical help and embedded systems
insights, and discusses how Microchip products provide project solutions.
The web site, like the BBS, is used by Microchip as a
means to make files and information easily available to
customers. To view the site, the user must have access
to the Internet and a web browser, such as Netscape or
Microsoft Explorer. Files are also available for FTP
download from our FTP site.
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP service to connect to:
ftp.mchip.com/biz/mchip
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
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available, including listings of Microchip sales offices,
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available for consideration is:
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Questions
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The procedure to connect will vary slightly from country
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service allow multiple users various baud rates
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The following connect procedure applies in most locations.
1. Set your modem to 8-bit, No parity, and One stop
(8N1). This is not the normal CompuServe setting
which is 7E1.
2. Dial your local CompuServe access number.
3. Depress the <Enter> key and a garbage string will
appear because CompuServe is expecting a 7E1
setting.
4. Type +, depress the <Enter> key and “Host Name:”
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5. Type MCHIPBBS, depress the <Enter> key and you
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In the United States, to find the CompuServe phone
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(800) 848-4480 for 300-2400 baud or (800) 331-7166
for 9600-14400 baud connection. After the system
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For voice information (or calling from overseas), you
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Microchip regularly uses the Microchip BBS to distribute
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Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
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Connecting to the Microchip BBS
Connect worldwide to the Microchip BBS using either
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Internet:
You can telnet or ftp to the Microchip BBS at the
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mchipbbs.microchip.com
CompuServe Communications Network:
When using the BBS via the Compuserve Network,
in most cases, a local call is your only expense.
The Microchip BBS connection does not use CompuServe
membership services, therefore you do not need
CompuServe membership to join Microchip's BBS.
There is no charge for connecting to the Microchip BBS.
Trademarks: The Microchip name, logo, PIC, PICSTART,
PICMASTER and PRO MATE are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries. FlexROM, MPLAB and fuzzyLAB, are trademarks and SQTP is a service mark of Microchip in the
U.S.A.
fuzzyTECH is a registered trademark of Inform Software
Corporation. IBM, IBM PC-AT are registered trademarks of
International Business Machines Corp. Pentium is a trademark of Intel Corporation. Windows is a trademark and
MS-DOS, Microsoft Windows are registered trademarks
of Microsoft Corporation. CompuServe is a registered
trademark of CompuServe Incorporated.
All other trademarks mentioned herein are the property of
their respective companies.
1996 Microchip Technology Inc.
DS30412C-page 235
This document was created with FrameMaker 4 0 4
PIC17C4X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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Literature Number: DS30412C
Questions:
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2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30412C-page 236
1996 Microchip Technology Inc.
PIC17C4X
PIC17C4X Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
Examples
PART NO. – XX X /XX XXX
Pattern:
Package:
Temperature
Range:
Frequency
Range:
Device:
QTP, SQTP, ROM Code (factory specified) or
Special Requirements. Blank for OTP and
Windowed devices
P
= PDIP
JW
= Windowed CERDIP
P
= PDIP (600 mil)
PQ
= MQFP
PT
= TQFP
L
= PLCC
–
= 0˚C to +70˚C
I
= –40˚C to +85˚C
08
= 8 MHz
16
= 16 MHz
25
= 25 Mhz
33
= 33 Mhz
PIC17C44
: Standard Vdd range
PIC17C44T : (Tape and Reel)
PIC17LC44 : Extended Vdd range
a)
PIC17C42 – 16/P
Commercial Temp.,
PDIP
package,
16 MHZ,
normal VDD limits
b)
PIC17LC44 – 08/PT
Commercial Temp.,
TQFP
package,
8MHz,
extended VDD limits
c)
PIC17C43 – 25I/P
Industrial
Temp.,
PDIP
package,
25 MHz,
normal VDD limits
Sales and Support
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.Your local Microchip sales office (see below)
2.The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3.The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
1996 Microchip Technology Inc.
DS30412C-page 237
This document was created with FrameMaker 4 0 4
PIC17C4X
NOTES:
DS30412C-page 238
1996 Microchip Technology Inc.
PIC17C4X
NOTES:
DS30412C-page 239
1996 Microchip Technology Inc.
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
Corporate Office
Toronto
Singapore
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-786-7200 Fax: 480-786-7277
Technical Support: 480-786-7627
Web Address: http://www.microchip.com
Microchip Technology Inc.
5925 Airport Road, Suite 200
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Tel: 905-405-6279 Fax: 905-405-6253
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
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Tel: 65-334-8870 Fax: 65-334-8850
Atlanta
Microchip Asia Pacific
Unit 2101, Tower 2
Metroplaza
223 Hing Fong Road
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Tel: 852-2-401-1200 Fax: 852-2-401-3431
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
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Tel: 770-640-0034 Fax: 770-640-0307
Boston
Microchip Technology Inc.
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Chicago
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ASIA/PACIFIC
Hong Kong
ASIA/PACIFIC (continued)
Taiwan, R.O.C
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Italy
11/15/99
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.