PLL620-05/-06/-07/-08/-09 Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) Universal Low Phase Noise IC’s PIN CONFIGURATION (Top View) 16 SEL0^ XIN 2 15 SEL1^ XOUT 3 14 GND SEL3^ 4 13 CLKC SEL2^ 5 12 VDD OE 6 11 CLKT GND 7 10 GND GND 8 9 GND XIN 13 XOUT 14 SEL2^ 15 OE 16 SEL0^ SEL1^ 12 11 10 9 PLL620-0x 1 GND The PLL620-0x family of XO IC’s is specifically designed to work with high frequency fundamental and third overtone crystals. Their low jitter and low phase noise performance make them well suited for high frequency XO requirements. They achieve very low current into the crystal resulting in better overall stability. 2 3 4 GND DESCRIPTION VDD • • 1 PLL 620-0x • VDD GND • 100MHz to 200MHz Fundamental or 3 rd Overtone Crystal. Output range: 100 – 200MHz (no multiplication), 200 – 400MHz (2x multiplier), 400 – 700MHz (4x multiplier), or 800MHz-1GHz(PLL620-09 only, 8x multiplier). CMOS (Standard drive PLL620-07 or Selectable Drive PLL620-06), PECL (Enable low PLL620-08 or Enable high PLL620-05) or LVDS output (PLL620-09). Supports 3.3V-Power Supply. Available in 16-Pin (TSSOP or 3x3mm QFN) Note: PLL620-06 only available in 3x3mm. Note: PLL620-07 only available in TSSOP. DNC/ DRIVSEL* • GND FEATURES 8 GND 7 CLKC 6 VDD 5 CLKT ^: Internal pull-up *: PLL620-06 pin 12 is output drive select (DRIVSEL) (0 for High Drive CMOS, 1 for Standard Drive CMOS) BLOCK DIAGRAM The pin remains ‘Do Not Connect (DNC)’ for PLL620-05/07/08/09. SEL OE X+ Oscillator Amplifier PLL (Phase Locked Loop) XPLL by-pass OUTPUT ENABLE LOGICAL LEVELS Q Part # Q PLL620-08 PLL620-05 PLL620-06 PLL620-07 PLL620-09 OE 0 (Default) 1 0 1 (Default) State Output enabled Tri-state Tri-state Output enabled OE input: Logical states defined by PECL levels for PLL620-08 Logical states defined by CMOS levels for PLL620-05/-06/07/-09 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 1 PLL620-05/-06/-07/-08/-09 Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) Universal Low Phase Noise IC’s PIN DESCRIPTIONS Name TSSOP* Pin number 3x3mm QFN* Pin number Type VDD 1, 12 6,11 P +3.3V power supply. XIN XOUT OE GND 2 3 6 7,8,9, 10, 14 13 14 16 1,2,3,4,8 I I I P DRIVSEL** - 12 I CLKT 11 5 O CLKC 13 7 O Crystal input. See Crystal Specification on page 3. Crystal output. See Crystal Specification on page 3. Output enable. Ground (except pin 12 on PLL620-06: DRIVSEL see below). PLL620-06 only: Drive Select Input. This pin has an internal pull-up that will default DRIVSEL to ‘1’ when not connect to GND. CMOS output of PLL620-06 will be high drive CMOS when DRIVSEL is set to ‘0’, and will be standard CMOS otherwise. The pin remains ‘Do Not Connect (DNC)’ for PLL620-05/07/08/09. True output PECL (PLL620-08) or LVDS (PLL620-09) (N/C for PLL620-07) Complementary output PECL (PLL620-08) or LVDS (PLL62009) (CMOS out for PLL620-07). SEL0 SEL1 SEL2 SEL3 16 15 5 4 10 9 15 Not available I I I I Description Multiplier selector pins. These pins have an internal pull-up that will default SEL to ‘1’ when not connected to GND. * Note: PLL620-06 only available in 3x3mm QFN, PLL620-07 only available in TSSOP. ** Note: DRIVSEL on pin 12 on PLL620-06 only. The pin remains ‘Do Not Connect (DNC)’ for PLL620-05/07/08/09. FREQUENCY SELECTION TABLE SEL3 SEL2 SEL1 SEL0 Selected Multiplier 0 0 1 1 Fin x 8(PLL620-09 only) 1 0 1 1 Fin x 4 1 1 1 0 Fin x 2 1 1 1 1 No multiplication Note: SEL3 is not available (always “1”) in 3x3mm package All pins have internal pull-ups (default value is 1). Connect to GND to set to 0. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 2 PLL620-05/-06/-07/-08/-09 Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) Universal Low Phase Noise IC’s ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. V DD VI VO TS TA TJ -0.5 -0.5 -65 -40 Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model MAX. UNITS 4.6 V DD +0.5 V DD +0.5 150 85 125 260 2 V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Interelectrode Capacitance Recommended ESR SYMBOL CONDITIONS Fundamental or overtone* F XIN C L (xtal) C0 RE 3 rd MIN. TYP. 100 MAX. UNITS 200 MHz 5 pF pF 5 30 AT cut Ω * Note: 3 r d overtone crystals require an external resistor between XIN and XOUT to prevent the fundamental from oscillating. 3. General Electrical Specifications PARAMETERS Supply Current (Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current SYMBOL I DD CONDITIONS MIN. TYP. PECL/LVDS/CMOS V DD @ 50% V DD (CMOS) @ 1.25V (LVDS) @ V DD – 1.3V (PECL) 2.97 45 45 45 50 50 50 ±50 MAX. UNITS 100/80/40 mA 3.63 55 55 55 V % mA 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 3 PLL620-05/-06/-07/-08/-09 Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) Universal Low Phase Noise IC’s 4. Jitter Specifications PARAMETERS CONDITIONS MIN. TYP. At 155.52MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles At 155.52MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. “RJ” measured on Wavecrest SIA 3000 Integrated 12 kHz to 20 MHz At 622.08MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles At 622.08MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. “RJ” measured on Wavecrest SIA 3000 Integrated 12 kHz to 20 MHz Period jitter RMS Period jitter peak-to-peak Accumulated jitter RMS Accumulated jitter peak-to-peak Random Jitter Integrated jitter RMS at 155MHz Period jitter RMS Period jitter peak-to-peak Accumulated jitter RMS Accumulated jitter peak-to-peak Random Jitter Integrated jitter RMS at 622MHz MAX. 2.5 18.5 20 2.5 24 2.5 0.3 27 0.4 11 45 49 11 24 3 1.6 27 1.8 UNITS ps ps ps ps ps ps ps ps 5. Phase Noise Specifications PARAMETERS FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS 155.52MHz 622.08MHz -75 -75 -95 -95 -125 -110 -140 -125 -145 -120 dBc/Hz Phase Noise relative to carrier 6. CMOS Electrical Specifications PARAMETERS Output drive current (High Drive) Output drive current (Standard Drive) Output Clock Rise/Fall Time (Standard Drive) Output Clock Rise/Fall Time (High Drive) SYMBOL I OH I OL I OH I OL CONDITIONS V OH = V DD -0.4V, V DD =3.3V V OL = 0.4V, V DD = 3.3V V OH = V DD -0.4V, V DD =3.3V V OL = 0.4V, V DD = 3.3V MIN. TYP. 30 30 10 10 MAX. UNITS mA mA mA mA 0.3V ~ 3.0V with 15 pF load 2.4 0.3V ~ 3.0V with 15 pF load 1.2 ns * Note: High Drive CMOS is available on PLL620-06 through DRIVSEL selector input on pin 12. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 4 PLL620-05/-06/-07/-08/-09 Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) Universal Low Phase Noise IC’s 7. LVDS Electrical Characteristics PARAMETERS SYMBOL Output Differential Voltage V DD Magnitude Change MIN. TYP. MAX. UNITS V OD 247 355 454 mV ∆V OD -50 50 mV 1.6 V Output High Voltage V OH Output Low Voltage V OL Offset Voltage CONDITIONS 1.4 R L = 100 Ω (see figure) 0.9 1.1 V OS 1.125 1.2 1.375 V Offset Magnitude Change ∆V OS 0 3 25 mV Power-off Leakage I OXD ±1 ±10 uA Output Short Circuit Current I OSD -5.7 -8 mA V out = V DD or GND V DD = 0V V 8. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf R L = 100 Ω C L = 10 pF (see figure) 0.2 0.7 1.0 ns LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50Ω VOD VDIFF VOS RL = 100Ω 50Ω CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 80% 0V 20% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 5 PLL620-05/-06/-07/-08/-09 Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) Universal Low Phase Noise IC’s 9. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. Output High Voltage V OH V DD – 1.025 Output Low Voltage V OL R L = 50 Ω to (V DD – 2V) (see figure) MAX. UNITS V V DD – 1.620 V 19. PECL Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Clock Rise Time tr @20/80% - PECL 0.6 1.5 ns Clock Fall Time tf @80/20% - PECL 0.5 1.5 ns PECL Levels Test Circuit OUT PECL Output Skew OUT VDD 50Ω 2.0V 50% 50Ω OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 6 PLL620-05/-06/-07/-08/-09 Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) Universal Low Phase Noise IC’s PACKAGE INFORMATION 16 PIN TSSOP ( mm ) Symbol A A1 B C D E H L e Min. Max. 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 0.65 BSC E H D A A1 C e B L 3mm x 3mm, QFN 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 7 PLL620-05/-06/-07/-08/-09 Low Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) Universal Low Phase Noise IC’s ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL620-0X X X X X NONE= TUBE R=TAPE AND PART NUMBER NONE=NORMAL PACKAGE L=GREEN PACKAGE PACKAGE TYPE X=SSOP Order Number Marking Package Option TEMPERATURE C=COMMERCIAL I=INDUSTRIAL Order Number Marking Package Option PLL620-05OC P620-05OC TSSOP – Tube PLL620-08OC P620-08OC TSSOP – Tube PLL620-05OC-R P620-05OC TSSOP – Tape & Reel PLL620-08OC-R P620-08OC TSSOP – Tape & Reel PLL620-05OCL P620-05OCL TSSOP – Tube, GREEN PLL620-08OCL P620-08OCL TSSOP – Tube, GREEN PLL620-05OCL-R P620-05OCL TSSOP – Tape & Reel, GREEN PLL620-08OCL-R P620-08OCL TSSOP – Tape & Reel, GREEN PLL620-05QC P620-05QC QFN – Tube PLL620-08QC P620-08QC QFN – Tube PLL620-05QC-R P620-05QC QFN – Tape & Reel PLL620-08QC-R P620-08QC QFN – Tape & Reel PLL620-05QCL P620-05QCL QFN – Tube, GREEN PLL620-08QCL P620-08QCL QFN – Tube, GREEN PLL620-05QCL-R P620-05QCL QFN – Tape & Reel, GREEN PLL620-08QCL-R P620-08QCL QFN – Tape & Reel, GREEN PLL620-06QC P620-06QC QFN – Tube PLL620-09OC P620-09OC TSSOP – Tube PLL620-06QC-R P620-06QC QFN – Tape & Reel PLL620-09OC-R P620-09OC TSSOP – Tape & Reel PLL620-06QCL P620-06QCL QFN – Tube, GREEN PLL620-09OCL P620-09OCL TSSOP – Tube, GREEN PLL620-06QCL-R P620-06QCL QFN – Tape & Reel, GREEN PLL620-09OCL-R P620-09OCL TSSOP – Tape & Reel, GREEN PLL620-07OC P620-07OC TSSOP – Tube PLL620-09QC P620-09QC QFN – Tube PLL620-07OC-R P620-07OC TSSOP – Tape & Reel PLL620-09QC-R P620-09QC QFN – Tape & Reel PLL620-07OCL P620-07OCL TSSOP – Tube, GREEN PLL620-09QCL P620-09QCL QFN – Tube, GREEN PLL620-07OCL-R P620-07OCL TSSOP – Tape & Reel, GREEN PLL620-09QCL-R P620-09QCL QFN – Tape & Reel, GREEN PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/01/05 Page 8