PMC Pm49FL002 / Pm49FL004 2 Mbit / 4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory FEATURES • - Single Power Supply Operation Low voltage range: 3.0 V - 3.6 V • Standard Intel Firmware Hub/LPC Interface Read compatible to Intel® 82802 Firmware Hub devices Conforms to Intel LPC Interface Specification Revision 1.1 - • - • - Memory Configuration Pm49FL002: 256K x 8 (2 Mbit) Pm49FL004: 512K x 8 (4 Mbit) • Cost Effective Sector/Block Architecture Pm49FL002: Sixty-four uniform 4 Kbyte sectors, or sixteen uniform 16 Kbyte blocks (sector group) Pm49FL004: One hundred and twenty-eight uniform 4 Kbyte sectors, or eight uniform 64 Kbyte blocks (sector group) - - - • Address/Address Multiplexed (A/A Mux) - • Top Boot Block - Firmware HUB (FWH)/Low Pin Count (LPC) Mode 33 MHz synchronous operation with PCI bus 5-signal communication interface for insystem read and write operations Standard SDP Command Set Data# Polling and Toggle Bit features Register-based read and write protection for each block (FWH mode only) 4 ID pins for multiple Flash chips selection (FWH mode only) 5 GPI pins for General Purpose Input Register TBL# pin for hardware write protection to Boot Block WP# pin for hardware write protection to whole memory array except Boot Block Pm49FL002: 16 Kbyte top Boot Block Pm49FL004: 64 Kbyte top Boot Block Mode 11-pin multiplexed address and 8-pin data I/O interface Supports fast programming on EPROM programmers - Standard SDP Command Set - Data# Polling and Toggle Bit features • Automatic Erase and Program Operation - Build-in automatic program verification for extended product endurance Typical 25 µs/byte programming time Typical 50 ms sector/block/chip erase time • Lower Power Consumption - • High Product Endurance • Two Configurable Interfaces - - Typical 2 mA active read current Typical 7 mA program/erase current - In-System hardware interface: Auto detection of Firmware Hub (FWH) or Low Pin Count (LPC) memory cycle for in-system read and write operations Address/Address-Multiplexed (A/A Mux) interface for programming on EPROM Programmers during manufacturing - Guarantee 100,000 program/erase cycles per single sector (preliminary) Minimum 20 years data retention • Compatible Pin-out and Packaging - 32-pin (8 mm x 14 mm) VSOP 32-pin PLCC Optional lead-free (Pb-free) package • Hardware Data Protection Programmable Microelectronics Corp. PMC and P-Flash are registered trademark of Programmable Microelectronics Corporation. Intel is a registered trademark of Intel Corporation. 1 Issue Date: December, 2003 Rev:1.4 Pm49FL002 / 004 PMC GENERAL DESCRIPTION The Pm49FL002/004 are 2 Mbit/4 Mbit 3.3 Volt-only Flash Memories used as BIOS in PCs and Notebooks. These devices are designed to use a single low voltage, ranging from 3.0 Volt to 3.6 Volt, power supply to perform insystem or off-system read, erase and program operations. The 12.0 Volt VPP power supply are not required for the program and erase operations of devices. The devices conform to Intel® Low Pin Count (LPC) Interface specification revision 1.1 and also read-compatible with Intel 82802 Firmware Hub (FWH) for most PC and Notebook applications. The Pm49FL002/004 support two configurable interfaces: In-system hardware interface which can automatic detect the FWH or LPC memory cycle for in-system read and write operations, and Address/Address Multiplexed (A/A Mux) interface for fast manufacturing on EPROM Programmers. These devices are designed to work with both Intel Family chipset and Non-Intel Family Chipset platforms, it will provide PC and Notebook manufacturers great flexibility and simplicity for design, procurement, and material inventory. The memory array of Pm49FL002 is divided into uniform 4 Kbyte sectors, or uniform 16 Kbytes blocks (sector group - consists of four adjecent sectors). The memory array of Pm49FL004 is divided into uniform 4 Kbyte sectors, or uniform 64 Kbyte blocks (sector group - consists of sixteen adjecent sectors). The sector or block erase feature allows users to flexibly erase a memory area as small as 4 Kbyte or as large as 64 Kbyte by one single erase operation without affecting the data in others. The chip erase feature allows the whole memory to be erased in one single erase operation. The devices can be programmed on a byte-by-byte basis after performing the erase operation. The program operation of Pm49FL002/004 is executed by issuing the program command code into command register. The internal control logic automatically handles the programming voltage ramp-up and timing. The erase operation of the devices is executed by issuing the sector, block, or chip erase command code into command register. The internal control logic automatically handles the erase voltage ramp-up and timing. The preprogramming on the array which has not been programmed is not required before an erase operation. The devices offer Data# Polling and Toggle Bit functions in FWH/LPC and A/A Mux modes, the progress or completion of program and erase operations can be detected by reading the Data# Polling on I/O7 or Toggle Bit on I/O6. The Pm49FL002 has a 16 Kbyte top boot block which can be used to store user security data and code. The Pm49FL004 has a 64 Kbyte top boot block. The boot block can be write protected by a hardware method controlled by the TBL# pin or a register-based protection turned on/off by the Block Locking Registers (FWH mode only). The rest of blocks except boot block in the devices also can be write protected by WP# pin or Block Locking Registers (FWH mode only). The Pm49FL002/004 are manufactured on PMC’s advanced nonvolatile technology, P-FLASH™. The devices are offered in 32-pin VSOP and PLCC packages with optional environmental friendly lead-free package. Programmable Microelectronics Corp. 2 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC 2 1 32 31 30 GPI4 VCC VCC GPI4 A10 3 CLK R/C# CLK 4 NC VCC A6 NC GPI0 NC GPI0 RST# 5 RST# RST# A7 GPI3 GPI1 GPI3 GPI1 A9 A/A Mux GPI2 LPC GPI2 FWH A8 A/A Mux LPC FWH CONNECTION DIAGRAMS A/A Mux LPC FWH 29 IC IC IC 6 28 GND GND GND NC NC A5 7 27 NC A4 8 26 NC NC NC ID3 RES A3 9 25 VCC VCC VCC ID2 RES A2 10 24 OE# INIT# INIT# ID1 RES A1 11 23 WE# LFRAME# FWH4 ID0 RES A0 12 22 NC NC NC FWH0 LAD0 I/O0 13 21 I/O7 RES RES I/O4 I/O5 I/O6 RES RES RES RES RES 20 RES 19 LAD3 18 FWH3 17 GND LAD2 FWH2 GND I/O1 16 GND A/A Mux LPC LAD1 FWH 15 FWH1 14 I/O3 WP# TBL# I/O2 WP# TBL# 32-PIN PLCC FWH LPC VCC NC NC GND IC GPI4 CLK VCC NC RST# GPI3 GPI2 GPI1 GPI0 WP# TBL# VC C NC NC GND IC GPI4 CLK VC C NC RST# GPI3 GPI2 GPI1 GPI0 WP# TBL# A/A Mux A/A Mux VCC NC NC GND IC A10 R/C# VCC NC RST# A9 A8 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# WE# NC I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 LPC INIT# LFRAME# NC RES RES RES RES LAD3 GND LAD2 LAD1 LAD0 RES RES RES RES FWH INIT# FWH4 NC RES RES RES RES FWH3 GND FWH2 FWH1 FWH0 ID0 ID1 ID2 ID3 32-PIN (8mm x 14mm) VSOP Programmable Microelectronics Corp. 3 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC PRODUCT ORDERING INFORMATION Pm49FL00x T -33 J C E Environmental Attribute E = Lead-free (Pb-free) Package Blank = Standard Package Temperature Range C = Commercial (0°C to +70°C) Package Type J = 32-pin Plastic J-Leaded Chip Carrier (32J) V = 32-pin (8 mm x 14 mm) VSOP (32V) Speed Option Boot Block Location T = Top Boot Block PMC Device Number Pm49FL002 (2 Mbit) Pm49FL004 (4 Mbit) Part Number MHz Boot Block Location P ackag e Temperature R an g e Pm49FL002T-33JCE 32J Pm49FL002T-33JC 33 Commercial (0°C to +70°C) Top Pm49FL002T-33VCE 32V Pm49FL002T-33VC Pm49FL004T-33JCE 32J Pm49FL004T-33JC 33 Commercial (0°C to +70°C) Top Pm49FL004T-33VCE 32V Pm49FL004T-33VC Programmable Microelectronics Corp. 4 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC PIN DESCRIPTIONS SYMB OL TYPE Interface PP FWH D ESC R IPTION LP C A[10:0] I X Address Inputs: For i nputi ng the multi plex addresses and commands i n PP mode. Row and column addresses are latched duri ng a read or wri te cycle controlled by R/C # pi n. R/C # I X Row/C olumn Select: To i ndi cate the row or column address i n PP mode. When thi s pi n goes low, the row address i s latched. When thi s pi n goes hi gh, the column address i s latched. I/O X D ata Inputs/Outputs: Used for A/A Mux mode only, to i nput command/data duri ng wri te operati on and to output data duri ng read operati on. The data pi ns float to tri -state when OE# i s di sabled. WE# I X Wri te Enable: Acti vate the devi ce for wri te operati on. WE# i s acti ve low. OE# I X Output Enable: C ontrol the devi ce's output buffers duri ng a read cycle. OE# i s acti ve low. I/O[7:0] IC I X X X Interface C onfi gurati on Select: Thi s pi n determi nes whi ch mode i s selected. When pulls hi gh, the devi ce enters i nto A/A Mux mode. When pulls low, FWH/LPC mode i s selected. Thi s pi n must be setup duri ng power-up or system reset, and stays no change duri ng operati on. Thi s pi n i s i nternally pulled down wi th a resi stor between 20-100 KΩ. RST# I X X X Reset: To reset the operati on of the devi ce and return to standby mode. INIT# I X X Ini ti ali ze: Thi s i s a second reset pi n for i n-system use. INIT# or RST# pi n pulls low wi ll i ni ti ate a devi ce reset. GPI[4:0] I X X FWH/LPC General Purpose Inputs: Used to set the GPI_REG for system desi gn purpose only. The value of GPI_REG can be read through FWH i nterface. These pi ns should be set at desi red state before the start of the PC I clock cycle for read operati on and should remai n no change unti l the end of the read cycle. Unused GPI pi ns must not be floated. TBL# I X X Top Block Lock: When pulls low, i t enables the hardware wri te protecti on for top boot block. When pulls hi gh, i t di sables the hardware wri te protecti on. WP# I X X Wri te Protect: When pulls low, i t enables the hardware wri te protecti on to the memory array except the top boot block. When pulls hi gh, i t di sables hardware wri te protecti on. I/O X FWH Address and D ata: The major I/O pi ns for transmi tti ng data, addresses and command code i n FWH mode. I X FWH Input: To i ndi cate the start of a FWH memory cycle operati on. Also used to abort a FHW memory cycle i n progress. FWH[3:0] FWH4 I/O X LPC Address and D ata: The major I/O pi ns for transmi tti ng data, addresses and command code i n LPC mode. LFRAME# I X LPC Frame: To i ndi cate the start of a LPC memory cycle operati on. Also used to abort a LPC memory cycle i n progress. C LK I X FWH/LPC C lock: To provi de a synchronous clock for FWH and LPC mode operati ons. LAD [3:0] ID [3:0] X I Identi fi cati on Inputs: These four pi ns are part of the mechani sm that allows multi ple FWH devi ces to be attached to the same bus. The strappi ng of these pi ns i s used to i denti fy the component. The boot devi ce must have ID [3:0] = 0000b and i t i s recommended that all subsequent devi ces should use sequenti al up-count strappi ng. These pi ns are i nternally pulled-down wi th a resi stor between 20-100 KΩ. X V CC X X X D evi ce Power Supply GND X X X Ground NC X X X No C onnecti on X X Reserved: Reserved functi on pi ns for future use. RES Note: I = Input, O = Output Programmable Microelectronics Corp. 5 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC BLOCK DIAGRAM ERASE/PROGRAM VOLTAGE GENERATOR TBL# WP# INIT# FWH[3:0] or LAD[3:0] FWH4 or LFRAME# CLK GPI[4:0] I/O BUFFERS FWH/LPC MODE INTERFACE HIGH VOLTAGE SWITCH A[10:0] I/O[7:0] WE# PP MODE INTERFACE CONTROL LOGIC OE# R/C# DATA LATCH SENSE AMP IC ADDRESS LATCH RST# Y-GATING Y-DECODER X-DECODER MEMORY ARRAY DEVICE OPERATION MODE SELECTION PRODUCT IDENTIFICATION The Pm49FL002/004 can operate in two configurable interfaces: The In-System Hardware interface and Address/Address Multiplexed (A/A Mux) interface controlled by IC pin. If the IC pin is set to logic high (VIH), the devices enter into A/A Mux interface mode. If the IC pin is set logic low (VIL), the devices will be in in-system hardware interface mode. During the in-system hardware interface mode, the devices can automatically detect the Firmware Hub (FWH) or Low Pin Count (LPC) memory cycle sent from host system and response to the command accordingly. The IC pin must be setup during power-up or system reset, and stays no change during device operation. The product identification mode can be used to read the Manufacturer ID and the Device ID by a software Product ID Entry command in both in-system hardware interface and A/A Mux interface modes. The product indentification mode is activated by three-bus-cycle command. Refer to Table 1 for the Manufacturer ID and Device ID of Pm49FL00x and Table 14 for the SDP Command Definition. When working in-system, typically on a PC or Notebook, the Pm49FL002/004 are connected to the host system through a 5-pin communication interface operated based on a 33-MHz synchronous clock. The 5-pin interface is defined as FWH[3:0] and FWH4 pins under FWH mode or as LAD[3:0] and LFRAME# pins under LPC mode for easy understanding as to those existing compatible products. When working off-system, typically on a EPROM Programmer, the devices are operated through 11-pin multiplexed address - A[10:0] and 8-pin data I/O - I/O[7:0] interfaces. The memory addresses of devices are input through two bus cycles as row and column addresses controlled by a R/C# pin. Table 1: Product Identification Programmable Microelectronics Corp. In FWH mode, the product identification can also be read directly at FFBC0000h for Manufacturer ID - “9Dh” and FFBC0001h for Device ID in the 4 GByte system memory map. Description Manufacturer ID Device ID Pm49FL002 Pm49FL004 6 2Mb 4Mb Address Data 00000h 00002h 9D h 7F h 00001h 6D h 6E h Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC DEVICE OPERATION (CONTINUED) SOFTWARE DATA PROTECTION The Pm49FL002/004 provide three levels of data protection for the critical BIOS code of PC and Notebook. It includes memory hardware write protection, hardware data protection and software data protection. The devices feature a software data protection function to protect the device from an unintentional erase or program operation. It is performed by JEDEC standard Software Data Protection (SDP) command sequences. See Table 14 for SDP Command Definition. A program operation is initiated by three memory write cycles of unlock command sequence. A chip (only available in A/A Mux mode), sector or block erase operation is initiated by six memory write cycles of unlock command sequence. During SDP command sequence, any invalid command or sequence will abort the operation and force the device back to standby mode. MEMORY HARDWARE WRITE PROTECTION The Pm49FL002 has a 16 Kbyte top boot block and the Pm49FL004 has a 64 Kbyte top boot block. When working in-system, the memory hardware write protection feature can be activated by two control pins - Top Block Lock (TBL#) and Write Protection (WP#) for both FWH and LPC modes. When TBL# is pulled low (VIL), the boot block is hardware write protected. A sector erase, block erase, or byte program command attempts to erase or program the boot block will be ignored. When WP# is pulled low (VIL), the Block 0 ~ Block 14 of Pm49FL002, or the Block 0 ~ Block 6 of Pm49FL004 (except the boot block) are hardware write protected. Any attemp to erase or program a sector or block within this area will be ignored. BYTE PROGRAMMING In program operation, the data is programmed into the devices (to a logical “0”) on a byte-by-byte basis. In FWH and LPC modes, a program operation is activated by writing the three-byte command sequence and program address/data through four consecutive memory write cycles. In A/A Mux mode, a program operation is activated by writing the three-byte command sequence and program address/data through four consecutive bus cycles. The row address (A10 - A0) is latched on the falling edge of R/C# and the column address (A21 - A11) is latched on the rising edge of R/C#. The data is latched on the rising edge of WE#. Once the program operation is started, the internal control logic automatically handles the internal programming voltages and timing. Both TBL# and WP# pins must be set low (VIL) for protection or high (VIH) for un-protection prior to a program or erase operation. A logic level change on TBL# or WP# pin during a program or erase operation may cause unpredictable results. The TBL# and WP# pins work in combination with the block locking registers. When active, these pins write protect the appropriate blocks regardless of the associated block locking registers setting. A data “0” can not be programmed back to a “1”. Only erase operation can convert “0”s to “1”s. The Data# Polling on I/O7 or Toggle Bit on I/O6 can be used to detect when the programming operation is completed in FWH, LPC, and A/A Mux modes. HARDWARE DATA PROTECTION Hardware data protection protects the devices from unintentional erase or program operation. It is performed by the devices automatically in the following three ways: (a) VCC Detection: if VCC is below 1.8 V (typical), the program and erase functions are inhibited. (b) Write Inhibit Mode: holding any of the signal OE# low, or WE# high inhibits a write cycle (A/A Mux mode only). (c) Noise/Glitch Protection: pulses of less than 5 ns (typical) on the WE# input will not initiate a write cycle (A/A Mux mode only). Programmable Microelectronics Corp. CHIP ERASE The entire memory array can be erased by chip erase operation available under the A/A Mux mode operated by EPROM Programmer only. Pre-programs the device is not required prior to the chip erase operation. Chip erase starts immediately after a six-bus-cycle chip erase command sequence. All commands will be ignored once the chip erase operation has started. The Data# Polling on I/O7 or Toggle Bit on I/O6 can be used to detect the progress or completion of erase operation. The devices will return back to standy mode after the completion of chip erase. 7 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC DEVICE OPERATION (CONTINUED) SECTOR AND BLOCK ERASE I/O6 TOGGLE BIT The Pm49FL002 contains sixty-four uniform 4 Kbyte sectors, or sixteen uniform 16 Kbyte blocks (sector group consists of four adjecent sectors). The Pm49FL004 contains one hundred and twenty-eight uniform 4 Kbyte sectors, or eight uniform 64 Kbyte blocks (sector group consists of sixteen adjecent sectors). A sector erase command is used to erase an individual sector. A block erase command is used to erase an individual block. See Table 12 - 13 for Sector/Block Address Tables. The Pm49FL002/004 also provide a Toggle Bit feature to detect the progress or the completion of a program or erase operation. During a program or erase operation, an attempt to read data from the devices will result in I/ O6 toggling between “1” and “0”. When the program or erase operation is complete, I/O6 will stop toggling and valid data will be read. Toggle bit may be accessed at any time during a program or erase operation. RESET In FWH/LPC mode, an erase operation is activated by writing the six-byte command sequence through six consecutive write memory cycles. In A/A Mux mode, an erase operation is activated by writing the six-byte command in six consecutive bus cycles. Pre-programs the sector or block is not required prior to an erase operation. Any read, program, or erase operation to the devices can be reset by the INIT# or RST# pins. INIT# and RST# pins are internally hard-wired and have same function to the devices. The INIT# pin is only available in FWH and LPC modes. The RST# pin is available in all modes. It is required to drive INIT# or RST# pins low during system reset to ensure proper initialization. I/O7 DATA# POLLING During a memory read operation, pulls low the INIT# or RST# pin will reset the devices back to standby mode and then the FWH[3:0] of FWH interface or the LAD[3:0] of LPC interface will go to high impedance state. During a program or erase operation, pulls low the INIT# or RST# pin will abort the program or erase operation and reset the devices back to standby mode. A reset latency will occur before the devices resume to standby mode when such reset is performed. When a program or erase operation is reset before the completion of such operation, the memory contents of devices may become invalid due to an incomplete program or erase operation. The devices provide a Data# Polling feature to indicate the progress or the completion of a program or erase operation in all modes. During a program operation, an attempt to read the device will result in the complement of the last loaded data on I/O7. Once the program cycle is complete, the true data of the last loaded data is valid on all outputs. During an erase operation, an attempt to read the device will result a “0” on I/O7. After the erase cycle is complete, an attempt to read the device will result a “1” on I/O7. Programmable Microelectronics Corp. 8 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC FWH MODE OPERATION FWH MODE MEMORY READ/WRITE OPERATION FWH ABORT OPERATION In FWH mode, the Pm49FL002/004 are connected through a 5-pin communication interface - FWH[3:0] and FWH4 pins to work with Intel® Family of I/O Controller Hubs (ICH) chipset platforms. The FWH mode also support JEDEC standard Software Data Protection (SDP) product ID entry, byte program, sector erase, and block erase command sequences. The chip erase command sequence is only available in A/A Mux mode. The FWH4 signal indicates the start of a memory cycle or the termination of a cycle in FWH mode. Asserting FWH4 for one or more clock cycle with a valid START value on FWH[3:0] will initiate a memory read or memory write cycle. If the FWH4 is driven low again for one or more clock cycles during this cycle, this cycle will be terminated and the device will wait for the ABORT command “1111b” to release the FWH[3:0] bus. If the abort occurs during the program or erase operation such as checking the operation status with Data# Polling (I/O7) or Toggle Bit (I/O6) pins, the read status cycle will be aborted but the internal program or erase operation will not be affected. Only the reset operation initiated by RST# or INIT# pin can terminate the program or erase operation. The addresses and data are transmitted through the 4bit FWH[3:0] bus synchronized with the input clock on CLK pin during a FWH memory cycle operation. The address or data on FWH[3:0] bus is latched on the rising edge of the clock. The pulse of FWH4 pin inserted for one clock indicates the start of a FWH memory read or memory write cycle. Once the FWH memory cycle is started, asserted by FWH4, a START value “11xxb” is expected by Pm49FL002/004 as a valid command cycle and is used to indicates the type of memory cycle (“1101b” for FWH memory read cycle or “1110b” for FWH memory write cycle). Addresses and data are transferred to and from the device decided by a series of “fields”. Field sequences and contents are strictly defined for FWH memory read and write operations. Refer to Table 2 and 3 for FWH Memory Read Cycle Definition and FWH Memory Write Cycle Definition. There are 7 clock fields in a FWH memory cycle that gives a 28 bit memory address A27 - A0 through FWH[3:0] pins, but only the last five address fields will be decoded by the FWH devices. The Pm49FL002 decodes A17 - A0 with A19 and A18 ignored. The Pm49FL004 decodes A18 - A0 with A19 ignored. The address A22 has the special function of directing reads and writes to the Flash array when A22 = 1 or to the register space with A22 = 0. The A27 - A23 and A21 A20 are don’t care for the devices under FWH mode. The Pm49FL002/004 are mapped within the top 4 Mbyte address range devoted to the FWH devices in the 4 Gbyte system memory space. Please see Table 11 for System Memory Map. Programmable Microelectronics Corp. 9 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC FWH MODE OPERATION (CONTINUED) Table 2: FWH Memory Read Cycle Definition Clock Cycle Field FWH[3: 0] 1 START 1101 IDSEL 0000 to 1111 2 Direction Description IN Start of Cycle: "1101b" to indicate the start of a memory read cycle. IN ID Select Cycle: Indicates which FWH device should respond. If the IDSEL field matches the value set on ID[3:0] pins, then the particular FWH device will respond to subsequent commands. 3-9 IMADDR YYYY IN Address Cycles: This is the 28-bit memory address. The addresses transfer most-significant nibble first and leastsignificant nibble last. (i.e., A27 - 24 on FWH[3:0] first, and A3 - A0 on FWH[3:0] last). 10 IMSIZE 0000 IN Memory Size Cycle: Indicates how many bytes will be or transferred during multi-byte operations. The Pm49FL00x only support "0000b" for one byte operation. 11 TAR0 1111 IN then Float 12 TAR1 1111 (float) 13 RSYNC 0000 (READY) OUT Ready Sync: The FWH device indicates the least-significant nibble of data byte will be ready in next clock cycle. 14-15 DATA YYYY OUT Data Cycles: The 8-bits data transferred with least-significant nibble first and most-significant nibble last. (i.e., I/O3 - I/O0 on LAD[3:0] first, then I/O7 - I/O4 on FWH[3:0] last). 16 TAR0 1111 OUT then Turn -Around Cycle 0: The FWH device has driven the bus Float then float it to all "1"s and then floats the bus. 17 TAR1 1111 (float) Float then Turn-Around Cycle 1: The Intel ICH resumes control of the bus IN during this cycle. Turn-Around Cycle 0: The Intel ICH has driven the bus then float it to all "1"s and then floats the bus. Float then Turn-Around Cycle 1: The device takes control of the bus OUT during this cycle. FWH MEMORY READ CYCLE WAVEFORMS CLK RST# or INIT# FWH4 Memory Read Start FWH[3:0] IDSEL 1101b ID[3:0] 1 Clock 1 Clock Programmable Microelectronics Corp. IMSIZE Address xxxxb x1xxb A[19:16] A[15:12] A[11:8] Load Address in 7 Clocks From Host to Device 10 A[7:4] A[3:0] 0000b TAR 1111b Tri-State 2 Clocks RSYNC Data 0000b D[3:0] D[7:4] 1 Clock Data Out 2 Clocks TAR 1111b Tri-State 2 Clocks Next Start 1101b 1 Clock From Device to Host Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC FWH MODE OPERATION (CONTINUED) Table 3: FWH Memory Write Cycle Definition Clock Cycle Field FWH[3: 0] 1 START 1110 IDSEL 0000 to 1111 2 Direction Description IN Start of Cycle: "1110b" to indicate the start of a memory write cycle. IN ID Select Cycle: Indicates which FWH device should respond. If the IDSEL field matches the value set on ID[3:0] pins, then the particular FWH device will respond to subsequent commands. 3-9 IMADDR YYYY IN Address Cycles: This is the 28-bit memory address. The addresses transfer most-significant nibble first and leastsignificant nibble last. (i.e., A27 - 24 on FWH[3:0] first, and A3 - A0 on FWH[3:0] last). 10 IMSIZE 0000 IN Memory Size Cycle: Indicates how many bytes will be or transferred during multi-byte operations. The Pm49FL00x only support "0000b" for one byte operation. 11-12 DATA YYYY IN Data Cycles: The 8-bits data transferred with least-significant nibble first and most-significant nibble last. (i.e., I/O3 - I/O0 on LAD[3:0] first, then I/O7 - I/O4 on FWH[3:0] last). 13 TAR0 1111 IN then Float 14 TAR1 1111 (float) 15 RSYNC 0000 (READY) 16 TAR0 1111 OUT then Turn-Around Cycle 0: The FWH device has driven the bus Float then float it to all "1"s and then floats the bus. 17 TAR1 1111 (float) Float then Turn-Around Cycle 1: The Intel ICH resumes control of the bus IN during this cycle. Turn-Around Cycle 0: The Intel ICH has driven the bus then float it to all "1"s and then floats the bus. Float then Turn-Around Cycle 1: The device takes control of the bus OUT during this cycle. OUT Ready Sync: The FWH device indicates that it has received the data or command. FWH MEMORY WRITE CYCLE WAVEFORMS CLK RST# or INIT# FWH4 Memory Write Start FWH[3:0] IDSEL 1110b ID[3:0] 1 Clock 1 Clock Programmable Microelectronics Corp. Address xxxxb x1xxb A[19:16] A[15:12] Data IMSIZE A[11:8] A[7:4] Load Address in 7 Clocks From Host to Device 11 A[3:0] 0000b D[3:0] TAR D[7:4] 1 Clock Load Data in 2 Clocks 1111b Tri-State 2 Clocks RSYNC 0000b 1 Clock TAR 1111b Tri-State 2 Clocks Next Start 1110b 1 Clock From Device to Host Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC FWH MODE OPERATION (CONTINUED) FWH BYTE PROGRAM WAVEFORMS CLK RST# or INIT# FWH4 Memory Write Cycle FWH[3:0] Address IDSEL 1110b ID[3:0] 1 Clock 1 Clock xxxxb x1xxb xxxxb 0101b Data IMSIZE 0101b 0101b 0101b 0000b 1010b TAR 1010b 1 Clock Load "AAh" in 2 Clocks Load "5555h" in 7 Clocks 1111b Tri-State 2 Clocks TAR RSYNC 1111b 0000b 1 Clock Host to Device Tri-State 2 Clocks Device to Host CLK RST# or INIT# FWH4 FWH[3:0] 2nd Start IDSEL 1110b ID[3:0] 1 Clock 1 Clock IMSIZE Address xxxxb x1xxb xxxxb 0010b 1010b 1010b 1010b 0000b Data 0101b TAR 0101b 1 Clock Load "55h" in 2 Clocks Load "2AAAh" in 7 Clocks 1111b Tri-State 2 Clocks TAR RSYNC 0000b 1 Clock Host to Device 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# FWH4 FWH[3:0] 3rd Start IDSEL 1110b ID[3:0] 1 Clock 1 Clock IMSIZE Address xxxxb x1xxb xxxxb 0101b 0101b 0101b 0101b 0000b Data 0000b TAR 1010b 1 Clock Load "A0h" in 2 Clocks Load "5555h" in 7 Clocks 1111b Tri-State 2 Clocks TAR RSYNC 0000b 1 Clock Host to Device 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# FWH4 FWH[3:0] 4th Start IDSEL 1110b ID[3:0] 1 Clock 1 Clock IMSIZE Address xxxxb x1xxb A[19:16] A[15:12] A[11:8] A[7:4] 12 0000b Data D[3:0] TAR D[7:4] 1 Clock Load Data in 2 Clocks Load Address in 7 Clocks Host to Device Programmable Microelectronics Corp. A[3:1] 1111b Tri-State 2 Clocks TAR RSYNC 0000b 1 Clock 1111b Tri-State 2 Clocks Device to Host Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC FWH SECTOR ERASE WAVEFORMS CLK RST# or INIT# FWH4 Memory Write Cycle IDSEL FWH[3:0] 1110b ID[3:0] 1 Clock 1 Clock Address xxxxb x1xxb xxxxb 0101b IMSIZE 0101b 0101b 0101b Load "5555h" in 7 Clocks Host to Device 0000b Data 1010b TAR 1010b 1 Clock Load "AAh" in 2 Clocks 1111b Tri-State 2 Clocks RSYNC 1 Clock TAR 1111b 0000b Tri-State 2 Clocks Device to Host CLK RST# or INIT# FWH4 FWH[3:0] 2nd Start IDSEL 1110b ID[3:0] 1 Clock 1 Clock Address xxxxb x1xxb xxxxb 0010b IMSIZE 1010b 1010b 1010b Load "2AAAh" in 7 Clocks Host to Device 0000b Data 0101b TAR 0101b 1 Clock Load "55h" in 2 Clocks 1111b Tri-State 2 Clocks RSYNC 0000b 1 Clock TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# FWH4 FWH[3:0] 3rd Start IDSEL 1110b ID[3:0] 1 Clock 1 Clock Address xxxxb x1xxb xxxxb 0101b IMSIZE 0101b 0101b 0101b Load "5555h" in 7 Clocks Host to Device 0000b Data 0000b TAR 1000b 1 Clock Load "80h" in 2 Clocks 1111b Tri-State 2 Clocks RSYNC 0000b 1 Clock TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# FWH4 FWH[3:0] 4th Start IDSEL 1110b ID[3:0] 1 Clock 1 Clock Address xxxxb x1xxb xxxxb 0101b IMSIZE 0101b Load "5555" in 7 Clocks 0101b 0101b Host to Device 0000b Data 0101b TAR 1010b 1 Clock Load "AAh" in 2 Clocks 1111b Tri-State 2 Clocks RSYNC 1 Clock TAR 1111b 0000b Tri-State 2 Clocks Device to Host CLK RST# or INIT# FWH4 FWH[3:0] 5th Start IDSEL 1110b ID[3:0] 1 Clock 1 Clock Address xxxxb x1xxb xxxxb 0010b IMSIZE 1010b 0010b Load "2AAAh" in 7 Clocks 1010b Host to Device 0000b Data 0101b TAR 0101b 1 Clock Load "55h" in 2 Clocks 1111b Tri-State 2 Clocks RSYNC 0000b 1 Clock TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# FWH4 6th Start FWH[3:0] 1110b ID[3:0] 1 Clock 1 Clock IMSIZE Address IDSEL xxxxb x1xxb xxxxb SA[19:16] SA[15:12] xxxxb xxxxb Load Sector Address in 7 Clocks Host to Device 0000b Data 0000b TAR 0011b 1 Clock Load "30h" in 2 Clocks 1111b Tri-State 2 Clocks RSYNC 0000b 1 Clock TAR 1111b Internal Erase Start Tri-State 2 Clocks Device to Host SA = Sector Address Programmable Microelectronics Corp. 13 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC FWH BLOCK ERASE WAVEFORMS CLK RST# or INIT# FWH4 Memory Write Cycle IDSEL FWH[3:0] 1110b ID[3:0] 1 Clock 1 Clock Address xxxxb x1xxb xxxxb 0101b IMSIZE 0101b 0101b 0101b Load "5555h" in 7 Clocks Host to Device 0000b Data 1010b TAR 1010b 1 Clock Load "AAh" in 2 Clocks 1111b Tri-State 2 Clocks RSYNC 1 Clock TAR 1111b 0000b Tri-State 2 Clocks Device to Host CLK RST# or INIT# FWH4 FWH[3:0] 2nd Start IDSEL 1110b ID[3:0] 1 Clock 1 Clock Address xxxxb x1xxb xxxxb 0010b IMSIZE 1010b 1010b 1010b Load "2AAAh" in 7 Clocks Host to Device 0000b Data 0101b TAR 0101b 1 Clock Load "55h" in 2 Clocks 1111b Tri-State 2 Clocks RSYNC 0000b 1 Clock TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# FWH4 FWH[3:0] 3rd Start IDSEL 1110b ID[3:0] 1 Clock 1 Clock Address xxxxb x1xxb xxxxb 0101b IMSIZE 0101b 0101b 0101b Load "5555h" in 7 Clocks Host to Device 0000b Data 0000b TAR 1000b 1 Clock Load "80h" in 2 Clocks 1111b Tri-State 2 Clocks RSYNC 0000b 1 Clock TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# FWH4 FWH[3:0] 4th Start IDSEL 1110b ID[3:0] 1 Clock 1 Clock Address xxxxb x1xxb xxxxb 0101b IMSIZE 0101b Load "5555" in 7 Clocks 0101b 0101b Host to Device 0000b Data 0101b TAR 1010b 1 Clock Load "AAh" in 2 Clocks 1111b Tri-State 2 Clocks RSYNC 0000b 1 Clock TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# FWH4 FWH[3:0] 5th Start IDSEL 1110b ID[3:0] 1 Clock 1 Clock Address xxxxb x1xxb xxxxb 0010b IMSIZE 0010b Load "2AAAh" in 7 Clocks 1010b 1010b Host to Device 0000b Data 0101b TAR 0101b 1 Clock Load "55h" in 2 Clocks 1111b Tri-State 2 Clocks RSYNC 0000b 1 Clock TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# FWH4 6th Start FWH[3:0] 1110b ID[3:0] 1 Clock 1 Clock IMSIZE Address IDSEL xxxxb x1xxb xxxxb BA[19:16] BA[15:14] + xxb xxxxb xxxxb Load Block Address in 7 Clocks Host to Device 0000b Data 0000b TAR 0101b 1 Clock Load "50h" in 2 Clocks 1111b Tri-State 2 Clocks RSYNC 0000b 1 Clock TAR 1111b Internal Erase Start Tri-State 2 Clocks Device to Host BA = Block Address Programmable Microelectronics Corp. 14 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC FWH MODE OPERATION (CONTINUED) FWH GPI REGISTER READ WAVEFORMS CLK RST# or INIT# FWH4 Memory Read Cycle IDSEL 1101b ID[3:0] 1 Clock 1 Clock FWH[3:0] Address xxxxb x0xxb 1100b 0000b TAR IMSIZE 0001b 0000b 0000b 0000b 1 Clock Load Address "xBC0100h" in 7 Clocks From Host to Device 1111b Tri-State 2 Clocks RSYNC Data 0000b D[3:0] D[7:4] 1 Clock Data Out 2 Clocks TAR 1111b Tri-State 2 Clocks Next Start 1101b 1 Clock From Device to Host FWH BLOCK LOCKING REGISTER READ WAVEFORMS CLK RST# or INIT# FWH4 Memory Read Cycle IDSEL 1101b ID[3:0] 1 Clock 1 Clock FWH[3:0] Programmable Microelectronics Corp. Address xxxxb x0xxb A[19:16] 0000b TAR IMSIZE 0000b 0000b Load Address "xBx0002h" in 7 Clocks From Host to Device 15 0010b 0000b 1 Clock 1111b Tri-State 2 Clocks RSYNC Data 0000b D[3:0] D[7:4] 1 Clock Data Out 2 Clocks TAR 1111b Tri-State 2 Clocks Next Start 1101b 1 Clock From Device to Host Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC LPC MODE OPERATION LPC MODE MEMORY READ/WRITE OPERATION In LPC mode, the Pm49FL002/004 use the 5-pin LPC interface includes 4-bit LAD[3:0] and LFRAME# pins to communicate with the host system. The addresses and data are transmitted through the 4-bit LAD[3:0] bus synchronized with the input clock on CLK pin during a LPC memory cycle operation. The address or data on LAD[3:0] bus is latched on the rising edge of the clock. The pulse of LFRAME# signal inserted for one or more clocks indicates the start of a LPC memory read or write cycle. Once the LPC memory cycle is started, asserted by LFRAME#, a START value “0000b” is expected by the devices as a valid command cycle. Then a CYCTYPE + DIR value (“010xb” for memory read cycle or “011xb” for memory write cycle) is used to indicates the type of memory cycle. Refer to Table 4 and 5 for LPC Memory Read and Write Cycle Definition. There are 8 clock fields in a LPC memory cycle that gives a 32 bit memory address A31 - A0 through LAD[3:0] with the most-significant nibble first. The memory space of Pm49FL002/004 are mapped directly to top of 4 Gbyte system memory space. See Table 11 for System Memory Map. The Pm49FL002 is mapped to the address location of (FFFFFFFFh - FFFC0000h), the A31- A18 must be loaded with “1” to select and activate the device during a LPC memory read or write operation. Only A17 - A0 is used to decode and access the 256 Kbyte memory. The I/O7 - I/O0 data is loaded onto LAD[3:0] in 2 clock cycles with least-significant nibble first and most-significant nibble last. The Pm49FL004 is mapped to the address location of (FFFFFFFFh - FFF80000h), the A31- A19 must be loaded with “1” to select and activate the device during a LPC memory operation. Only A18 - A0 is used to decode and access the 512 Kbyte memory. Programmable Microelectronics Corp. 16 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC LPC MODE OPERATION (CONTINUED) Table 4: LPC Memory Read Cycle Definition Clock Cycle Field LAD[3: 0] 1 START 0000 2 CYCTYPE + DIR Direction Description 010x IN Start of Cycle: "0000b" indicates the start of a LPC memory cycle. IN Cycle Type: Indicates the type of a LPC memory read cycle. CYCTYPE: Bits 3 - 2 must be "01b" for memory cycle. DIR: Bit 1 = "0b" indicates the type of cycle for Read. Bit 0 is reserved. Address Cycles: This is the 32-bit memory address. The addresses transfer most-significant nibble first and leastsignificant nibble last. (i.e., A31 - 28 on LAD[3:0] first, and A3 - A0 on LAD[3:0] last). 3 - 10 AD D R YYYY IN 11 TAR0 1111 IN then Float 12 TAR1 1111 (float) 13 SYNC 0000 OUT Sync: The device indicates the least-significant nibble of data byte will be ready in next clock cycle. 14 - 15 DATA YYYY OUT Data Cycles: The 8-bits data transferred with least-significant nibble first and most-significant nibble last. (i.e., I/O3 - I/O0 on LAD[3:0] first, then I/O7 - I/O4 on LAD[3:0] last). 16 TAR0 1111 OUT then Float 17 TAR1 1111 (float) Float then Turn-Around Cycle 1: The Chipset resumes control of the bus IN during this cycle. Turn-Around Cycle 0: The Chipset has driven the bus to all "1"s and then float the bus. Float then Turn-Around Cycle 1: The device takes control of the bus OUT during this cycle. Turn-Around Cycle 0: The device has driven the bus to all "1"s and then floats the bus. LPC MEMORY READ CYCLE WAVEFORMS CLK RST# or INIT# LFRAME# Start Memory Read Cycle 0000b 010Xb 1 Clock 1 Clock LAD[3:0] Programmable Microelectronics Corp. Address 1111b 1111b 1111b 11b + A[17:16] TAR A[15:12] Load Address in 8 Clocks From Host to Device 17 A[11:8] A[7:4] A[3:0] 1111b Tri-State 2 Clocks SYNC Data 0000b D[3:0] D[7:4] 1 Clock Data Out 2 Clocks TAR 1111b Tri-State 2 Clocks Next Start 0000b 1 Clock From Device to Host Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC LPC MODE OPERATION (CONTINUED) Table 5: LPC Memory Write Cycle Definition Clock Cycle Field LAD[3: 0] 1 START 0000 2 CYCTYPE + DIR Direction Description 011x IN Start of Cycle: "0000b" to indicate the start of a LPC memory cycle. IN Cycle Type: Indicates the type of a LPC memory write cycle. CYCTYPE: Bits 3 - 2 must be "01b" for memory cycle. DIR: Bit 1 = "1b" indicates the type of cycle for Write. Bit 0 is reserved. 3 - 10 AD D R YYYY IN Address Cycles: This is the 32-bit memory address. The addresses transfer most-significant nibble first and leastsignificant nibble last. (i.e., A31 - 28 on LAD[3:0] first, and A3 - A0 on LAD[3:0] last). 11 - 12 DATA YYYY IN Data Cycles: The 8-bits data transferred with least-significant nibble first and most-significant nibble last. (i.e., I/O3 - I/O0 on LAD[3:0] first, then I/O7 - I/O4 on LAD[3:0] last). 13 TAR0 1111 IN then Float 14 TAR1 1111 (float) 15 SYNC 0000 OUT Sync: The device indicates that it has received the data or command. 16 TAR0 1111 OUT then Float Turn-Around Cycle 0: The device has driven the bus to all "1"s and then floats the bus. 17 TAR1 1111 (float) Float then Turn-Around Cycle 1: The Chipset resumes control of the bus IN during this cycle. Turn-Around Cycle 0: The Chipset has driven the bus to all "1"s and then float the bus. Float then Turn-Around Cycle 1: The device takes control of the bus OUT during this cycle. LPC MEMORY WRITE CYCLE WAVEFORMS CLK RST# or INIT# LFRAME# Start Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock LAD[3:0] Programmable Microelectronics Corp. Address 1111b 1111b 1111b A[19:16] Data A[15:12] A[11:8] Load Address in 8 Clocks From Host to Device 18 A[7:4] A[3:0] D[3:0] TAR D[7:4] Load Data in 2 Clocks 1111b Tri-State 2 Clocks SYNC 0000b 1 Clock TAR 1111b Tri-State 2 Clocks Next Start 0000b 1 Clock From Device to Host Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC LPC MODE OPERATION (CONTINUED) LPC BYTE PROGRAM WAVEFORMS CLK RST# or INIT# LFRAME# 1st Start LAD[3:0] Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address 1111b 1111b 1111b 11xxb Data 0101b 0101b 0101b 0101b 1010b TAR 1010b Load "AAh" in 2 Clocks Load "5555h" in 8 Clocks 1111b Tri-State 2 Clocks Sync 0000b 1 Clock Host to Device TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# LFRAME# LAD[3:0] 2nd Start Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address 1111b 1111b 1111b 11xxb Data 0010b 1010b 1010b 1010b 0101b TAR 0101b Load "55h" in 2 Clocks Load "2AAAh" in 8 Clocks 1111b Tri-State 2 Clocks TAR Sync 0000b 1 Clock Host to Device 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# LFRAME# 3rd Start LAD[3:0] Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address 1111b 1111b 1111b 11xxb Data 0101b 0101b 0101b 0101b 0000b TAR 1010b Load "A0h" in 2 Clocks Load "5555h" in 8 Clocks 1111b Tri-State 2 Clocks TAR Sync 0000b 1 Clock Host to Device 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# LFRAME# LAD[3:0] 4th Start Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address 1111b 1111b 1111b A[19:16] Data A[15:12] A[11:8] 19 A[3:1] D[3:0] TAR D[7:4] Load Data in 2 Clocks Load Address in 8 Clocks Host to Device Programmable Microelectronics Corp. A[7:4] 1111b Tri-State 2 Clocks TAR Sync 0000b 1 Clock 1111b Tri-State 2 Clocks Device to Host Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC LPC SECTOR ERASE WAVEFORMS CLK RST# or INIT# LFRAME# 1st Start LAD[3:0] Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address 1111b 1111b 1111b 11xxb Data 0101b 0101b 0101b 0101b 1010b TAR 1010b Load "AAh" in 2 Clocks Load "5555h" in 8 Clocks 1111b Tri-State 2 Clocks Sync 0000b 1 Clock Host to Device TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# LFRAME# LAD[3:0] 2nd Start Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address 1111b 1111b 1111b 11xxb Data 1010b 0010b 1010b 1010b 0101b TAR 0101b Load "55h" in 2 Clocks Load "2AAAh" in 8 Clocks 1111b Tri-State 2 Clocks Sync 0000b 1 Clock Host to Device TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# LFRAME# 3rd Start LAD[3:0] Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address 1111b 1111b 1111b 11xxb Data 0101b 0101b 0101b 0101b 0000b TAR 1000b Load "80h" in 2 Clocks Load "5555h" in 8 Clocks 1111b Tri-State 2 Clocks Sync 0000b 1 Clock Host to Device TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# LFRAME# LAD[3:0] 4th Start Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address 1111b 1111b 1111b 11xxb Data 0101b Load "5555" in 8 Clocks 0101b 0101b 0101b 0101b TAR 1010b Load "AAh" in 2 Clocks Host to Device 1111b Tri-State 2 Clocks Sync 0000b 1 Clock TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# LFRAME# 5th Start LAD[3:0] Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address 1111b 1111b 1111b 11xxb Data 1010b 0010b Load "2AAAh" in 8 Clocks 1010b 1010b 0101b TAR 0101b 1111b Tri-State Load "55h" in 2 Clocks 2 Clocks Data TAR Host to Device Sync 0000b 1 Clock TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# LFRAME# 6th Start LAD[3:0] Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address 1111b 1111b 1111b SA[19:16] SA[15:12] xxxxb xxxxb Load Sector Address in 8 Clocks Host to Device xxxxb 0000b 0011b Load "30h" in 2 Clocks 1111b Tri-State 2 Clocks Sync 0000b 1 Clock TAR 1111b Internal Erase Start Tri-State 2 Clocks Device to Host SA = Sector Address Programmable Microelectronics Corp. 20 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC LPC BLOCK ERASE WAVEFORMS CLK RST# or INIT# LFRAME# 1st Start LAD[3:0] Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address 1111b 1111b 1111b 11xxb Data 0101b 0101b 0101b 0101b 1010b TAR 1010b Load "AAh" in 2 Clocks Load "5555h" in 8 Clocks 1111b Tri-State 2 Clocks Sync 0000b 1 Clock Host to Device TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# LFRAME# LAD[3:0] 2nd Start Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address 1111b 1111b 1111b 11xxb Data 0010b 1010b 1010b 1010b 0101b TAR 0101b Load "55h" in 2 Clocks Load "2AAAh" in 8 Clocks 1111b Tri-State 2 Clocks Sync 0000b 1 Clock Host to Device TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# LFRAME# 3rd Start LAD[3:0] Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address 1111b 1111b 1111b 11xxb Data 0101b 0101b 0101b 0101b 0000b TAR 1000b Load "80h" in 2 Clocks Load "5555h" in 8 Clocks 1111b Tri-State 2 Clocks Sync 0000b 1 Clock Host to Device TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# LFRAME# LAD[3:0] 4th Start Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address 1111b 1111b 1111b 11xxb Data 0101b Load "5555" in 8 Clocks 0101b 0101b 0101b 0101b TAR 1010b Load "AAh" in 2 Clocks Host to Device 1111b Tri-State 2 Clocks Sync 0000b 1 Clock TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# LFRAME# 5th Start LAD[3:0] Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address 1111b 1111b 1111b 11xxb Data 0010b Load "2AAAh" in 8 Clocks 1010b 1010b 1010b 0101b TAR 0101b 1111b Tri-State Load "55h" in 2 Clocks 2 Clocks Data TAR Host to Device Sync 0000b 1 Clock TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# LFRAME# LAD[3:0] 6th Start Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address 1111b 1111b 1111b BA[19:16] BA[15:14] + xxb xxxxb xxxxb Load Block Address in 8 Clocks Host to Device xxxxb 0000b 0101b Load "50h" in 2 Clocks 1111b Tri-State 2 Clocks Sync 0000b 1 Clock TAR 1111b Internal Erase Start Tri-State 2 Clocks Device to Host BA = Block Address Programmable Microelectronics Corp. 21 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC LPC MODE OPERATION (CONTINUED) LPC GPI REGISTER READ WAVEFORMS CLK RST# or INIT# LFRAME# Start Memory Read Cycle 0000b 010Xb 1 Clock 1 Clock LAD[3:0] Programmable Microelectronics Corp. Address 1111b 1111b 1011b 1100b TAR 0000b 0001b Load Address "FFBC0100h" in 8 Clocks From Host to Device 22 0000b 0000b 1111b Tri-State 2 Clocks SYNC Data 0000b D[3:0] D[7:4] 1 Clock Data Out 2 Clocks TAR 1111b Tri-State 2 Clocks Next Start 0000b 1 Clock From Device to Host Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC REGISTERS The Pm49FL002/004 have two registers include the General Purpose Inputs Register (GPI_REG - available in FWH and LPC modes) and the Block Locking Register (BL_REG - available in FWH mode only). The GPI_REG can be read at FFBC0100h in the 4 Gbyte system memory map. And the BL_REG can be read through FFBx0002h where x = F - 0h. See Table 8 and 9 for the address of BL_REG. GENERAL PURPOSE INPUTS REGISTER The Pm49FL002/004 contain an 8-bit General Purpose Inputs Register (GPI_REG) available in FWH and LPC modes. Only Bit 4 to Bit 0 are used in current version and Bit 7 to Bit 5 are reserved for future use. The GPI_REG is a pass-through register with the value set by GPI[4:0] pin during power-up. The GPI_REG is used for system design purpose only, the devices do not use this register. This register is read only and can be read at address location FFBC0100h in the 4 GByte system memory map through a memory read cycle. Refer to Table 6 for General Purpose Input Register Definition. BLOCK LOCKING REGISTERS The devices support block read-lock, write-lock, and lockdown features through a set of Block Locking Registers. Each memory block has an associated 8-bit read/writable block locking register. Only Bit 2 to Bit 0 are used in current version and Bit 7 to Bit 3 are reserved for future use. The default value of BL_REG is “01h” at power up. The definition of BL_REG is listed in Table 7. The FWH Register Configuration Map of Pm49FL002 is shown in Table 8. The FWH Register Configuration Map of Pm49FL004 is shown in Table 9. Unused register will be read as 00h. Table 6. General Purpose Inputs Register Definition Bit Bit Name 7:5 Function 32-PLCC Pin# 32-VSOP Pin# Reserved - - 4 GPI4 GPI_REG Bit 4 30 6 3 GPI3 GPI_REG Bit 3 3 11 2 GPI2 GPI_REG Bit 2 4 12 1 GPI1 GPI_REG Bit 1 5 13 0 GPI0 GPI_REG Bit 0 6 14 Programmable Microelectronics Corp. 23 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC REGISTERS (CONTINUED) Table 7. Block Locking Register Definition Bit 7:3 Function Reserved 2 Read-Lock "1" = Prevents read operations in the block where set. "0" = Normal operation for reads in the block where clear. Default state. 1 Lock-Dow n "1" = Prevents further set or clear operations to the Write-Lock and Read-Lock bits. LockDown only can be set, but not cleared. The block will remain locked-down until reset (with RST# or INIT#), or until the device is power-on reset. "0" = Normal operation for Write-Lock and Read-Lock bit altering in the block where clear. Default state. 0 Write-Lock "1" = Prevents program or erase operations in the block where set. Default state. "0" = Normal operation for programming and erase in the block where clear. Data Bit[7: 3] Bit 2 Bit 1 Bit 0 00h 00000 0 0 0 Full access. 01h 00000 0 0 1 Write locked. Default state at power-up. 02h 00000 0 1 0 Locked open (full access locked down). 03h 00000 0 1 1 Write-locked down. 04h 00000 1 0 0 Read locked. 05h 00000 1 0 1 Read and write locked. 06h 00000 1 1 0 Read-locked down. 07h 00000 1 1 1 Read-locked and write-locked down. Programmable Microelectronics Corp. 24 Resulting Block State Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC REGISTERS (CONTINUED) Table 8. Pm49FL002 Block Locking Register Address Register Block Siz e (Kbytes) Protected Block Address Range Memory Map Address T_BLOCK_LK 16 3C 000h - 3F F F F h F F B F 8002h T_MINUS01_LK 16 16 16 38000h - 3B F F F h 34000h - 37F F F h 30000h - 33F F F h F F B F 0002h T_MINUS02_LK 16 16 2C 000h - 2F F F F h 28000h - 2B F F F h F F B E 8002h T_MINUS03_LK 16 16 24000h - 27F F F h 20000h - 23F F F h F F B E 0002h T_MINUS04_LK 16 16 1C 000h - 1F F F F h 18000h - 1B F F F h F F B D 8002h T_MINUS05_LK 16 16 14000h - 17F F F h 10000h - 13F F F h F F B D 0002h T_MINUS06_LK 16 16 0C 000h - 0F F F F h 08000h - 0B F F F h F F B C 8002h T_MINUS07_LK 16 16 04000h - 07F F F h 00000h - 03F F F h F F B C 0002h Table 9. Pm49FL004 Block Locking Register Address Register Block Siz e (Kbytes) Protected Block Address Range Memory Map Address T_BLOCK_LK 64 70000h - 7F F F F h F F B F 0002h T_MINUS01_LK 64 60000h - 6F F F F h F F B E 0002h T_MINUS02_LK 64 50000h - 5F F F F h F F B D 0002h T_MINUS03_LK 64 40000h - 4F F F F h F F B C 0002h T_MINUS04_LK 64 30000h - 3F F F F h F F B B 0002h T_MINUS05_LK 64 20000h - 2F F F F h F F B A 0002h T_MINUS06_LK 64 10000h - 1F F F F h F F B 90002h T_MINUS07_LK 64 00000h - 0F F F F h F F B 80002h Programmable Microelectronics Corp. 25 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC A/A MUX MODE OPERATION are latched on the falling edge of R/C# pin. The column addresses (internal address A21 - A11) are latched on the rising edge of R/C# pin. The Pm49FL002 uses A17 - A0 internally to decode and access the 256 Kbytes memory space. The Pm49FL004 use A18 - A0 respectively. A/A MUX MODE READ/WRITE OPERATION The Pm49FL002/004 offers a Address/Address Multiplexed (A/A Mux) mode for off-system operation, typically on an EPROM Programmer, similar to a traditional Flash memory except the address input is multiplexed. In the A/A Mux mode, the programmer must drive the OE# pin to low (VIL) for read or WE# pins to low for write operation. The devices have no Chip Enable (CE#) pin for chip selection and activation as traditional Flash memory. The R/C#, OE# and WE# pins are used to activate the device and control the power. The 11 multiplex address pins - A[10:0] and a R/C# pin are used to load the row and column addresses for the target memory location. The row addresses (internal address A10 - A0) During a read operation, the OE# signal is used to control the output of data to the 8 I/O pins - I/O[7:0]. During a write operation, the WE# signal is used to latch the input data from I/O[7:0]. See Table 10 for Bus Operation Modes. Table 10. A/A Mux Mode Bus Operation Modes Mode R S T# OE# WE# Read VIH VIL VIH Write VIH VIH VIL X DIN Standby VIH VIH VIH X High Z Output Disable VIH VIH X X High Z Reset VIL X X X High Z Product Identification VIH VIL VIH Address X (1) A 2 - A 21 = X , A1 = VIL, A0 = VIL and A1 = VIH, A0 = VIH A 2 - A 21 = X , A1 = VIL, A0 = VIH I/O DOUT Manufacturer ID Device ID (2) (2) Notes: 1. X can be VIL or VIH. 2. Refer to Table 1 for the Manufacturer ID and Device ID of devices. Programmable Microelectronics Corp. 26 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC SYSTEM MEMORY MAP System Memory (Top 4 MBytes) FFFFFFFFh Pm49FL002 (2 Mbits) Pm49FL004 (4 Mbits) FFFC0000h Pm49FL008 (8 Mbits) FFF80000h FFF00000h Range for other FWH Devices FFC00000h Table 11. System Memory Map Programmable Microelectronics Corp. 27 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC MEMORY BLOCKS AND ADDRESSES Table 12. Pm49FL002 Sector/Block Address Table Hardw are Protection Block Block Siz e (Kbytes) Sector Sector Siz e (Kbytes) Address Range TBL# Block 15 (Boot Block) 16 " " 3C 000h - 3F F F F h Block 14 16 " " 38000h - 3B F F F h Block 13 16 " " 34000h - 37F F F h Block 12 16 " " 30000h - 33F F F h Block 11 16 " " 2C 000h - 2F F F F h Block 10 16 " " 28000h - 2B F F F h Block 9 16 " " 24000h - 27F F F h Block 8 16 " " 20000h - 23F F F h Block 7 16 " " 1C 000h - 1F F F F h Block 6 16 " " 18000h - 1B F F F h Block 5 16 " " 14000h - 17F F F h Block 4 16 " " 10000h - 13F F F h Block 3 16 " " 0C 000h - 0F F F F h Block 2 16 " " 08000h - 0B F F F h Block 1 16 " " 04000h - 07F F F h Sector 3 4 03000h - 03F F F h Sector 2 4 02000h - 02F F F h Sector 1 4 01000h - 01F F F h Sector 0 4 00000h - 00F F F h WP# Block 0 Programmable Microelectronics Corp. 16 28 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC MEMORY BLOCKS AND ADDRESSES (CONTINUED) Table 13. Pm49FL004 Sector/Block Address Table Hardw are Protection Block Block Siz e (Kbytes) Sector Sector Siz e (Kbytes) Address Range TBL# Block 7 (Boot Block) 64 " " 70000h - 7F F F F h Block 6 64 " " 60000h - 6F F F F h Block 5 64 " " 50000h - 5F F F F h Block 4 64 " " 40000h - 4F F F F h Block 3 64 " " 30000h - 3F F F F h Block 2 64 " " 20000h - 2F F F F h Block 1 64 " " 10000h - 1F F F F h Sector 15 4 0F 000h - 0F F F F h : : : Sector 1 4 01000h - 01F F F h Sector 0 4 00000h - 00F F F h WP# Block 0 Programmable Microelectronics Corp. 64 29 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC COMMAND DEFINITION Table 14. Software Data Protection Command Definition Command S eq u en ce Read B us Cycle 1st B u s Cycle Addr(2) Data 2n d B u s Cycle Addr Data 3rd Bus Cycle Addr Data 4th Bus Cycle Addr Data 5th Bus Cylce Addr Data 6th Bus Cycle Addr Data 1 Addr DOUT 6 5555h A A h 2A A A h 55h 5555h 80h 5555h A A h 2A A A h 55h 5555h 10h Sector Erase 6 5555h A A h 2A A A h 55h 5555h 80h 5555h A A h 2A A A h 55h SA (3) 30h Block Erase 6 5555h A A h 2A A A h 55h 5555h 80h 5555h A A h 2A A A h 55h BA (4) 50h Byte Program 4 5555h A A h 2A A A h 55h 5555h A0h Addr DIN Product ID Entry 3 5555h A A h 2A A A h 55h 5555h 90h Product ID Exit (5) 3 5555h A A h 2A A A h 55h 5555h F 0h Product ID Exit (5) 1 X X X X h F 0h Chip Erase (1) Notes: 1. Chip erase is available in A/A Mux Mode only. 2. Address A[15:0] is used for SDP command decoding internally and A15 must be “0” in FWH/LPC and A/A Mux modes. AMS - A16 = Don’t care where AMS is the most-significant address of Pm49FL00x. 3. SA = Sector address to be erased. 4. BA = Block address to be erased. 5. Either one of the Product ID Exit command can be used. Programmable Microelectronics Corp. 30 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC DEVICE OPERATIONS FLOWCHARTS AUTOMATIC PROGRAMMING Start Load Data AAh to Address 5555h Load Data 55h to Address 2AAAh Load Data A0h to Address 5555h Address Increment Load Program Data to Program Address I/O7 = Data? or I/O6 Stop Toggle? No Yes Last Address? No Yes Programming Completed Chart 1. Automatic Programming Flowchart Programmable Microelectronics Corp. 31 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC DEVICE OPERATIONS FLOWCHARTS (CONTINUED) AUTOMATIC ERASE Start Write Chip, Sector, or Block Erase Command No Data = FFh? or I/O6 Stop Toggle? Yes Erasure Completed CHIP ERASE COMMAND SECTOR ERASE COMMAND Notes: 1. Please see Table 12 to Table 13 for Sector/Block Address Tables. 2. Only erase one sector or one block per erase operation. 3. When the TBL# pin is pulled low (VIL), the boot block will not be erased. BLOCK ERASE COMMAND Load Data AAh to Address 5555h Load Data AAh to Address 5555h Load Data AAh to Address 5555h Load Data 55h to Address 2AAAh Load Data 55h to Address 2AAAh Load Data 55h to Address 2AAAh Load Data 80h to Address 5555h Load Data 80h to Address 5555h Load Data 80h to Address 5555h Load Data AAh to Address 5555h Load Data AAh to Address 5555h Load Data AAh to Address 5555h Load Data 55h to Address 2AAAh Load Data 55h to Address 2AAAh Load Data 55h to Address 2AAAh Load Data 30h to S A (1,2,3) Load Data 50h to (1,2,3) BA Load Data 10h to Address 5555h (3) Chart 2. Automatic Erase Flowchart Programmable Microelectronics Corp. 32 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC DEVICE OPERATIONS FLOWCHARTS (CONTINUED) SOFTWARE PRODUCT IDENTIFICATION ENTRY SOFTWARE PRODUCT IDENTIFICATION EXIT Load Data AAh to Address 5555h Load Data AAh to Address 5555h Load Data 55h to Address 2AAAh Load Data 55h to Address 2AAAh Load Data F0h to Address XXXXh or Load Data 90h to Address 5555h Load Data F0h to Address 5555h Enter Product Identification Mode (1,2) Exit Product Identification Mode (3) Exit Product Identification Mode (3) Notes: 1. After entering Product Identification Mode, the Manufacturer ID and the Device ID of Pm49FL00x can be read. 2. Product Identification Exit command is required to end the Product Identification mode and return to standby mode. 3. Either Product Identification Exit command can be used, the device returns to standby mode. Chart 3. Software Product Identification Entry/Exit Flowchart Programmable Microelectronics Corp. 33 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC ABSOLUTE MAXIMUM RATINGS (1) Temperature Under Bias -55oC to +125oC Storage Temperature -65oC to +150oC Standard Package 240oC 3 Seconds Lead-free Package 260oC 3 Seconds Surface Mount Lead Soldering Temperature Input Voltage with Respect to Ground on All Pins (2) -0.5 V to VCC + 0.5 V All Output Voltage with Respect to Ground -0.5 V to VCC + 0.5 V VCC (2) -0.5 V to +6.0 V Notes: 1. Stresses under those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. The functional operation of the device or any other conditions under those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condition for extended periods may affected device reliability. 2. Maximum DC voltage on input or I/O pins are +6.25 V. During voltage transitioning period, input or I/O pins may overshoot to VCC + 2.0 V for a period of time up to 20 ns. Minimum DC voltage on input or I/O pins are -0.5 V. During voltage transitioning period, input or I/O pins may undershoot GND to -2.0 V for a period of time up to 20 ns. DC AND AC OPERATING RANGE Part Number Pm49FL002 Pm49FL004 Operating Temperature 0oC to 70oC 0oC to 70oC Vcc Power Supply 3.0 V - 3.6 V 3.0 V - 3.6 V Programmable Microelectronics Corp. 34 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC DC CHARACTERISTICS Symbol Parameter Condition Min Typ Max Units II Input Leakage Current for IC, ID[3:0] pins VIN = 0 V to VCC, VCC = VCC max 100 µA ILI Input Leakage Current VIN = 0 V to VCC, VCC = VCC max ±1 µA ILO Output Leakage Current VI/O = 0 V to VCC, VCC = VCC max ±1 µA ISB Standby VCC Current (FWH/LPC Mode) FWH4 or LFRAME# = VIH, f = 33 MHz; VCC = VCC max 500 µA IRY Ready Mode VCC Current (FWH/LPC Mode) FWH4 or LFRAME# = VIL, f = 33 MHz; IOUT = 0 mA, VCC = VCC max 10 mA ICC1 VCC Active Read Current (FWH/LPC Mode) FWH4 or LFRAME# = VIL, f = 33 MHz; IOUT = 0 mA, VCC = VCC max 2 15 mA ICC2 (1) VCC Program/Erase Current 7 20 mA VIL Input Low Voltage -0.5 0.3 VCC V VIH Input High Voltage 0.7 VCC VCC + 0.5 V VOL Output Low Voltage IOL = 2.0 mA, VCC = VCC min 0.1 VCC V VOH Output High Voltage IOH = -100 µA, VCC = VCC min 0.9 VCC V Note: 1. Characterized but not 100% tested. AC CHARACTERISTICS PIN IMPEDANCE (VCC = 3.3 V, f = 1 MHz, T = 25°C ) Typ Max Units Conditions CI/O (1) I/O Pin Capacitance 12 pF VI/O = 0 V CIN (1) Input Capacitance 12 pF VIN = 0 V LPIN (2) Pin Inductance 20 nH Notes: 1. These parameters are characterized but not 100% tested. 2. Refer to PCI specification. Programmable Microelectronics Corp. 35 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC AC CHARACTERISTICS (CONTINUED) FWH/LPC INTERFACE AC INPUT/OUTPUT CHARACTERISTICS Symbol Parameter Condition Min 0 < VOUT < 0.3 VCC IOH (AC) Switching current high 0.3 VCC < VOUT < 0.9 VCC Max -12 VCC mA -17.1 (VCC - VOUT) mA 0.7 VCC < VOUT < VCC (Test point) Equation C VOUT = 0.7 VCC Switching current low (1) -32 VCC VCC > VOUT > 0.6 VCC IOL (AC) Units 0.6 VCC > VOUT > 0.1 VCC mA 16 V C C mA -17.1 (VCC - VOUT) mA 0.18 VCC > VOUT > 0 Equation D (1) (Test point) VOUT = 0.18 VCC 38 V C C mA ICL Low clamp current -3 < VIN < -1 ICH High clamp current VCC + 4 > VIN > VCC + 1 slewr (2) Output rise slew rate 0.2 VCC - 0.6 VCC load 1 4 V/ns slewf (2) Output fall slew rate 0.6 VCC - 0.2 VCC load 1 4 V/ns -25 + (VIN + 1) / 0.015 mA 25 + (VIN - VCC - 1) / 0.015 mA Notes: 1. See PCI specification. 2. PCI specification output load is used. FWH/LPC INTERFACE CLOCK CHARACTERISTICS Symbol Parameter Min Max Units tCYC Clock Cycle Time 30 ns tHIGH Clock High Time 11 ns tLOW Clock Low Time 11 ns Clock Slew Rate 1 INIT# or RST# Slew Rate Programmable Microelectronics Corp. 50 36 4 V/ns mV/ns Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC AC CHARACTERISTICS (CONTINUED) FWH/LPC INTERFACE CLOCK WAVEFORM tC Y C tH I G H tL O W 0.5 V C C 0.6 V C C 0.4 V C C p-to-p (minimum) 0.4 V C C 0.3 V C C 0.2 V C C FWH/LPC INTERFACE MEASUREMENT CONDITION PARAMETERS Symbol Value Units VTH1 0.6 VCC V VTL1 0.2 VCC V VTEST 0.4 VCC V VMAX1 0.4 VCC V Input Signal Edge Rate 1 V/ns Note: 1. The input test environment is done with 0.1 VCC of overdrive over VIH and VIL. Timing parameters must be met with no more overdrive that this. VMAX specifies the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may use different voltage values, but must correlate results back to these parameter. FWH/LPC MEMORY READ/WRITE OPERATIONS CHARACTERISTICS Symbol Parameter Min TCYC Clock Cycle Time 30 ns TSU Input Set Up Time 7 ns TH Input Hold Time 0 ns TVAL Clock to Data Out 2 TON Clock to Active Time (float to active delay) 2 TOFF Clock to Inactive Time (active to float delay) Programmable Microelectronics Corp. 37 Max 11 Units ns ns 28 ns Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC AC CHARACTERISTICS (CONTINUED) FWH/LPC INPUT TIMING PARAMETERS V TH CLK V TEST tS U FWH[3:0] or LAD[3:0] tH V TL V MAX INPUT VALID (Valid Input Data) FWH/LPC OUTPUT TIMING PARAMETERS V TH CLK V TEST V TL tV A L FWH[3:0] or LAD[3:0] (Valid Output Data) tO F F FWH[3:0] or LAD[3:0] (Float Output Data) tO N Programmable Microelectronics Corp. 38 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC AC CHARACTERISTICS (CONTINUED) FWH/LPC RESET OPERATION CHARACTERISTICS Symbol Parameter Min Max Units 1 ms Reset Active Time to Clock Stable 100 µs TRSTP Reset Pulse Width 100 ns TRSTF Reset Active to Output Float Delay TPRST Reset Active Time to VCC Stable TKRST TRST (1) 50 Reset Inactive Time to Input Active 1 ns µs Note: 1. There will be a 10 µs reset latency if a reset procedure is performed during a programming or erase operation. FWH/LPC RESET AC WAVEFORMS TPRST VCC CLK TKRST TRSTP RST#/INIT# TRST T RSTF FWH[3:0] or LAD[3:0] FWH4 or LFRAME# A/A MUX MODE INPUT TEST MEASUREMENT CONDITION PARAMETERS 3.0 V Input AC Measurement Level 1.5 V 0.0 V A/A MUX MODE TEST LOAD CONDITION TO TESTER TO DUT CL 30 pF Programmable Microelectronics Corp. 39 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC AC CHARACTERISTICS (CONTINUED) A/A MUX MODE READ OPERATIONS CHARACTERISTICS Symbol Parameter Min tRC Read Cycle Time tACC Address to Output Delay tRST RST# High to Row Address Set-up Time tAS Max 270 Units ns 120 ns 1 ms R/C# Address Set-up Time 45 ns tAH R/C# Address Hold Time 45 ns tOE OE# to Output Delay tDF OE# to Output High Z 0 tOH Output Hold from OE# or Address, whichever occured first 0 ns tVCS VCC Set-up Time 50 µs 50 ns 30 ns A/A MUX MODE READ OPERATIONS AC WAVEFORMS RST# tR C tR S T ADDRESS ROW ADDRESS tA S tA H COLUMN ADDRESS tA S tA H R/C# tA C C OE# tO E tD F WE# tO H HIGH Z OUTPUT OUTPUT VALID tV C S V CC Programmable Microelectronics Corp. 40 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC AC CHARACTERISTICS (CONTINUED) A/A MUX MODE WRITE (PROGRAM/ERASE) OPERATIONS CHARACTERISTICS Symbol Parameter Min tRST RST# High to Row Address Set-up Time tAS Max Units 1 ms R/C# Address Set-up Time 50 ns tAH R/C# Address Hold Time 50 ns tCWH R/C# to WE# High Time 50 ns tOES OE# High Set-up Time 20 ns tOEH OE# High Hold Time 20 ns tDS Data Set-up Time 50 ns tDH Data Hold Time 5 ns tWP Write Pulse Width 100 ns tWPH Write Pulse Width High 100 ns tBP Byte Programming Time 40 µs tEC Chip, Sector or Block Erase Cycle Time 80 ms tVCS VCC Set-up Time 50 µs A/A MUX MODE WRITE OPERATIONS AC WAVEFORMS RST# tR C tR S T ADDRESS ROW ADDRESS tA S tA H COLUMN ADDRESS tA S tA H R/C# tC W H tV C S tO E H OE# tO E S WE# OUTPUT tD S HIGH Z tD H INPUT DATA V CC Programmable Microelectronics Corp. 41 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC AC CHARACTERISTICS (CONTINUED) A/A MUX MODE BYTE PROGRAM OPERATIONS AC WAVEFORMS 4-Byte Program Command ADDRESS 5555 2AAA tC W H tW P 5555 BYTE ADDRESS R/C# tW P H tB P WE# OE# tD H tD S DATA AA INPUT DATA A0 55 VALID DATA A/A MUX MODE CHIP ERASE OPERATIONS AC WAVEFORMS 6-Byte Chip Erase Command ADDRESS 2AAA 5555 5555 2AAA 5555 5555 R/C# tC W H tW P tW P H tD S tD H tE C WE# OE# DATA IN AA Programmable Microelectronics Corp. 55 80 42 AA 55 10 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC AC CHARACTERISTICS (CONTINUED) A/A MUX MODE SECTOR/BLOCK ERASE OPERATIONS AC WAVEFORMS 6-Byte Block Erase Command ADDRESS 2AAA 5555 5555 2AAA 5555 SECTOR OR BLOCK ADDRESS R/C# tC W H tW P tW P H tD S tD H tE C WE# OE# DATA IN AA 80 55 AA 55 30/50 A/A MUX MODE TOGGLE BIT AC WAVEFORMS ADDRESS ROW COLUMN R/C# WE# tO E H OE# tO E I/O6 Note: D D 1. Toggling OE# will operate Toggle Bit. 2. I/O6 may start and end from “1” or “0” in random. Programmable Microelectronics Corp. 43 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC AC CHARACTERISTICS (CONTINUED) A/A MUX MODE DATA# POLLING AC WAVEFORMS ROW ADDRESS COLUMN R/C# WE# tO E H OE# tO E I/O7 Note: D D# D# D# D Toggling OE# will operate Data# Polling. PROGRAM/ERASE PERFORMANCE Parameter Unit Typ Max Remarks Sector/Block Erase Time ms 50 80 From writing erase command to erase completion Chip Erase Time ms 50 80 From writing erase command to erase completion Byte Programming Time µs 25 40 Excludes the time of four-cycle program command execution Note: These parameters are characterized but not 100% tested. RELIABILITY CHARACTERISTICS (1) Parameter Endurance Data Retention ESD - Human Body Model ESD - Machine Model Latch-Up Min 100,000 Typ (2) 20 Unit Test Method Cycles JEDEC Standard A117 Years JEDEC Standard A103 2,000 >4,000 Volts JEDEC Standard A114 200 >400 Volts JEDEC Standard A115 mA 100 + ICC1 JEDEC Standard 78 Notes: 1. These parameters are characterized but not 100% tested. 2. Preliminary specification only and will be formalized after cycling qualification test. Programmable Microelectronics Corp. 44 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC PACKAGE TYPE INFORMATION 32V 32-Pin Thin Small Outline Package (VSOP - 8 mm x 14 mm)( measure in millimeters) 1.05 0.95 Pin 1 I.D. 0.27 0.17 8.10 7.90 0.50 BSC 0.15 0.05 12.50 12.30 14.20 13.80 1.20 MAX 0.20 0.10 0° 5° 0.25 0.70 0.50 32J 32-Pin Plastic Leaded Chip Carrier (measured in millimeters) 12.57 12.32 11.51 11.35 0.74X30° 15.11 14.86 3.56 3.18 Pin 1 I.D. 2.41 1.93 14.05 13.89 SEATING PLANE 13.46 12.45 0.53 0.33 1.27 Typ. 0.81 0.66 TOP VIEW Programmable Microelectronics Corp. SIDE VIEW 45 Issue Date: December, 2003 Rev: 1.4 Pm49FL002 / 004 PMC REVISION HISTORY Date Revision No. Description of Changes P ag e N o . June, 2002 1.0 Preliminary publication All July, 2002 1.1 Formal publication All Revised program and erase time specification January, 2003 November, 2003 1.2 1.3 Corrected typo on the part number for Block Locking Register 23 Removed Pm49FL008 information All Removed inch measurement for package type information 45 Changed product ordering information for lead-free package option December, 2003 1, 4, 34 1.4 Upgraded guranteed program/erase cycles from 50,000 to 100,000 (preliminary) Programmable Microelectronics Corp. 1, 41, 44 46 1, 44 Issue Date: December, 2003 Rev: 1.4