W39V040FB Data Sheet 512K × 8 CMOS FLASH MEMORY WITH FWH INTERFACE Table of Contents1. GENERAL DESCRIPTION ......................................................................................................... 3 2. FEATURES ................................................................................................................................. 3 3. PIN CONFIGURATIONS ............................................................................................................ 4 4. BLOCK DIAGRAM ...................................................................................................................... 4 5. PIN DESCRIPTION..................................................................................................................... 4 6. FUNCTIONAL DESCRIPTION ................................................................................................... 5 7. 8. 9. 6.1 Interface Mode Selection and Description..................................................................... 5 6.2 Read (Write) Mode ........................................................................................................ 5 6.3 Reset Operation............................................................................................................. 5 6.4 Boot Block Operation and Hardware Protection at Initial- #TBL & #WP ....................... 5 6.5 Sector Erase Command ................................................................................................ 6 6.6 Program Operation ........................................................................................................ 6 6.7 Hardware Data Protection ............................................................................................. 6 6.8 WRITE OPERATION STATUS...................................................................................... 6 REGISTER FOR FWH MODE .................................................................................................... 8 7.1 General Purpose Inputs Register for FWH Mode.......................................................... 8 7.2 Product Identification Registers..................................................................................... 8 7.3 Block Locking Registers ................................................................................................ 8 7.4 Register Based Block Locking Value Definitions Table ................................................ 9 7.5 Read Lock.................................................................................................................... 10 7.6 Write Lock .................................................................................................................... 10 7.7 Lock Down ................................................................................................................... 10 7.8 Product Identification Registers................................................................................... 10 TABLE OF OPERATING MODES ............................................................................................ 11 8.1 Operating Mode Selection - Programmer Mode.......................................................... 11 8.2 Operating Mode Selection - FWH Mode ..................................................................... 11 8.3 FWH Cycle Definition................................................................................................... 11 TABLE OF COMMAND DEFINITION ....................................................................................... 12 9.1 Embedded Programming Algorithm ............................................................................ 13 9.2 Embedded Erase Algorithm......................................................................................... 14 9.3 Embedded #Data Polling Algorithm............................................................................. 15 9.4 Embedded Toggle Bit Algorithm.................................................................................. 16 9.5 Software Product Identification and Boot Block Lockout Detection Acquisition Flow . 17 -1- Publication Release Date: December 12, 2005 Revision A4 W39V040FB 10. 11. 12. 13. ELECTRICAL CHARACTERISTICS......................................................................................... 18 10.1 Absolute Maximum Ratings ......................................................................................... 18 10.2 Programmer interface Mode DC Operating Characteristics........................................ 18 10.3 FWH Interface Mode DC Operating Characteristics ................................................... 19 10.4 Power-up Timing.......................................................................................................... 19 10.5 Capacitance................................................................................................................. 19 10.6 Programmer Interface Mode AC Characteristics......................................................... 20 10.7 Read Cycle Timing Parameters................................................................................... 21 10.8 Write Cycle Timing Parameters................................................................................... 21 10.9 Data Polling and Toggle Bit Timing Parameters ......................................................... 21 TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE ....................................... 22 11.1 Read Cycle Timing Diagram........................................................................................ 22 11.2 Write Cycle Timing Diagram........................................................................................ 22 11.3 Program Cycle Timing Diagram .................................................................................. 23 11.4 #DATA Polling Timing Diagram................................................................................... 23 11.5 Toggle Bit Timing Diagram .......................................................................................... 24 11.6 Sector Erase Timing Diagram ..................................................................................... 24 FWH INTERFACE MODE AC CHARACTERISTICS ............................................................... 25 12.1 AC Test Conditions...................................................................................................... 25 12.2 Read/Write Cycle Timing Parameters ......................................................................... 25 12.3 Reset Timing Parameters ............................................................................................ 25 TIMING WAVEFORMS FOR FWH INTERFACE MODE.......................................................... 26 13.1 Read Cycle Timing Diagram........................................................................................ 26 13.2 Write Cycle Timing Diagram........................................................................................ 26 13.3 Program Cycle Timing Diagram .................................................................................. 27 13.4 #DATA Polling Timing Diagram................................................................................... 28 13.5 Toggle Bit Timing Diagram .......................................................................................... 29 13.6 FGPI Register/Product ID Readout Timing Diagram................................................... 31 13.7 Reset Timing Diagram ................................................................................................. 31 14. ORDERING INFORMATION .................................................................................................... 32 15. HOW TO READ THE TOP MARKING...................................................................................... 32 16. PACKAGE DIMENSIONS ......................................................................................................... 33 17. 16.1 32L PLCC .................................................................................................................... 33 16.2 32L STSOP.................................................................................................................. 33 VERSION HISTORY ................................................................................................................. 34 -2- W39V040FB 1. GENERAL DESCRIPTION The W39V040FB is a 4-megabit, 3.3-volt only CMOS flash memory organized as 512K × 8 bits. For flexible erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes. The device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is required for accelerated program. The unique cell architecture of the W39V040FB results in fast program/erase operations with extremely low current consumption. This device can operate at two modes, Programmer bus interface mode, Firmware Hub (FWH) bus interface mode. As in the Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs. But in the FWH interface mode, this device complies with the Intel FWH specification. The device can also be programmed and erased using standard EPROM programmers. 2. FEATURES • Single 3.3-volt operations: • − 3.3-volt Read − 3.3-volt Erase − 3.3-volt Program • − #TBL supports 64-Kbyte Boot Block hardware protection − #WP supports the whole chip except Boot Block hardware protection Fast Program operation: − Byte-by-Byte programming: 9 μS (typ.) (VPP = 12V) − Byte-by-Byte programming: 12 μS (typ.) (VPP = Vcc) Hardware protection: • Low power consumption − Active current: 15 mA (typ. for FWH read mode) • Automatic program and erase timing with internal VPP generation • End of program or erase detection − Toggle bit − Data polling • Fast Erase operation: − Sector erase 0.6 Sec. (typ.) • Fast Read access time: Tkq 11 nS • Endurance: 10K cycles (typ.) • Latched address and data • Twenty-year data retention • TTL compatible I/O • 8 Even sectors with 64K bytes • Available packages: 32L PLCC, 32L STSOP • Any individual sector can be erased 32L PLCC Lead free, 32L STSOP Lead free -3- Publication Release Date: December 12, 2005 Revision A4 W39V040FB 3. PIN CONFIGURATIONS 4. BLOCK DIAGRAM #WP #TBL CLK FWH[3:0] FWH4 64K BYTES BLOCK 7 FWH Interface 64K BYTES BLOCK 6 IC #INIT #RESET Firmware Hub (FWH) Mode 64K BYTES BLOCK 5 64K BYTES BLOCK 4 64K BYTES BLOCK 3 R/#C A[10:0] DQ[7:0] #OE #WE RY/#BY NC NC NC VSS IC A10(FGPI4) R/#C(CLK) V DD Vpp #RESET A9(FGPI3) A8(FGPI2) A7(FGPI1) A6(FGPI0) A5(#WP) A4(#TBL) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32L STSOP A 8 ^ F G P I 2 v A 9 ^ F G P I 3 v # R E S E T 4 3 2 V P P 1 V D D R / # C ^ C L K v 32 31 #OE(#INIT) #WE(FWH4) RY/#BY(RSV) DQ7(RSV) DQ6(RSV) DQ5(RSV) DQ4(RSV) DQ3(FWH3) VSS DQ2(FWH2) DQ1(FWH1) DQ0(FWH0) A0(ID0) A1(ID1) A2(ID2) A3(ID3) 29 IC A6(FGPI0) 6 28 V SS A5(#WP) 7 27 NC A4(#TBL) 8 26 NC 32L PLCC A3(ID3) 9 25 V DD A2(ID2) 10 24 #OE(#INIT) A1(ID1) 11 23 #WE(FWH4) A0(ID0) 12 22 RY/#BY(RSV) 13 21 DQ7(RSV) DQ0(FWH0) SYM. 14 15 16 17 18 19 20 D Q 1 ^ F W H 1 v D Q 2 ^ F W H 2 v V S S D Q 3 ^ F W H 3 v D Q 4 ^ R S V v D Q 5 ^ R S V v D Q 6 ^ R S V v Interface 64K BYTES BLOCK 1 64K BYTES BLOCK 0 20000 1FFFF 10000 0FFFF 00000 -4- INTERFACE PIN NAME PGM FWH * * * * * * * * * Interface Mode Selection Reset Initialize Top Boot Block Lock Write Protect CLK Input General Purpose Inputs ID[3:0] * Identification Inputs They Are Internal Pull Down to Vss FWH[3:0] FWH4 R/#C A[10:0] DQ[7:0] #OE #WE RY/#BY VDD VSS * * * * * * * * * * * * VPP * * Accelerate Program Power Supply RSV NC * * * * Reserved Pins No Connection IC #RESET #INIT #TBL #WP CLK FGPI[4:0] 30 5 64K BYTES BLOCK 2 5. PIN DESCRIPTION A 1 0 ^ F G P I 4 v A7(FGPI1) Programmer 7FFFF 70000 6FFFF 60000 5FFFF 50000 4FFFF 40000 3FFFF 30000 2FFFF Address/Data Inputs FWH Cycle Initial Row/Column Select Address Inputs Data Inputs/Outputs Output Enable Write Enable Ready/ Busy Power Supply Ground W39V040FB 6. FUNCTIONAL DESCRIPTION 6.1 Interface Mode Selection and Description This device can operate in two interface modes, one is Programmer interface mode, and the other is FWH interface mode. The IC (Mode) pin of the device provides the control between these two interface modes. These interface modes need to be configured before power up or return from #RESET. When IC (Mode) pin is set to VDD, the device will be in the Programmer mode; while the IC (Mode) pin is set to low state (or leaved no connection), it will be in the FWH mode. In Programmer mode, this device just behaves like traditional flash parts with 8 data lines. But the row and column address inputs are multiplexed. The row address are mapped to the higher internal address A[18:11]. And the column address are mapped to the lower internal address A[10:0]. For FWH mode, it complies with the FWH Interface Specification, through the FWH[3:0] to communicate with the system chipset . 6.2 Read (Write) Mode In Programmer interface mode, the read (write) operation of the W39V040FB is controlled by #OE (#WE). The #OE (#WE) is held low for the host to obtain (write) data from (to) the outputs (inputs). #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when #OE is high. As for in the FWH interface mode, the read or write is determined by the "bit 0 & bit 1 of START CYCLE ". Refer to the FWH cycle definition and timing waveforms for further details. 6.3 Reset Operation The #RESET input pin can be used in some application. When #RESET pin is at high state, the device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to read or standby mode, it depends on the control signals. 6.4 Boot Block Operation and Hardware Protection at Initial- #TBL & #WP There is a hardware method to protect the top boot block and other sectors. Before power on programmer, tie the #TBL pin to low state and then the top boot block will not be programmed/erased. If #WP pin is tied to low state before power on, the other sectors will not be programmed/erased. In order to detect whether the boot block feature is set on or not, users can perform software command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address 7FFF2(hex). You can check the DQ2/DQ3 at the address 7FFF2 to see whether the #TBL/#WP pin is in low or high state. If the DQ2 is “0”, it means the #TBL pin is tied to high state. In such condition, whether boot block can be programmed/erased or not will depend on software setting. On the other hand, if the DQ2 is “1”, it means the #TBL pin is tied to low state, then boot block is locked no matter how the software is set. Like the DQ2, the DQ3 inversely mirrors the #WP state. If the DQ3 is “0”, it means the #WP pin is in high state, then all the sectors except the boot block can be programmed/erased. On the other hand, if the DQ3 is “1”, then all the sectors except the boot block are programmed/erased inhibited. -5- Publication Release Date: December 12, 2005 Revision A4 W39V040FB To return to normal operation, perform a three-byte command sequence (or an alternate single-byte command) to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection. 6.5 Sector Erase Command Sector erase is a six-bus cycles operation. There are two "unlock" write cycles, followed by writing the "set-up" command. Two more "unlock" write cycles then follows by the Sector erase command. The Sector address (any address location within the desired Sector) is latched on the rising edge of R/#C in programmer mode, while the command (30H) is latched on the rising edge of #WE. Sector erase does not require the user to program the device prior to erase. When erasing a Sector, the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The automatic Sector erase begins after the erase command is completed, right from the rising edge of the #WE pulse for the last Sector erase command pulse and terminates when the data on DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be performed at an address within any of the sectors being erased. Refer to the Erase Command flow Chart using typical command strings and bus operations. 6.6 Program Operation The W39V040FB is programmed on a byte-by-byte basis. Program operation can only change logical data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or boot block from "0" to "1", is needed before programming. The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte Programming). The device will internally enter the program operation immediately after the byteprogram command is entered. The internal program timer will automatically time-out (12μS typ. - TBP) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle. 6.7 Hardware Data Protection The integrity of the data stored in the W39V040FB is also hardware protected in the following ways: (1) Noise/Glitch Protection: A #WE pulse of less than 5 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming and read operation are inhibited when VDD is less than 2.0V typical. (3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. 6.8 WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ5, DQ6, and DQ7. Each of DQ7 and DQ6 provides a method for determining whether a program or erase operation is complete or in progress. The device also offers a hardware-based output signal, RY/#BY in programmer mode, to determine whether an Embedded Program or Erase operation is in progress or has been completed. -6- W39V040FB DQ7: #Data Polling The #Data Polling bit, DQ7, indicates whether an Embedded Program or Erase algorithm is in progress or completed. Data Polling is valid after the rising edge of the final #WE pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 and the complement of the data programmed to DQ7. Once the Embedded Program algorithm has completed, the device outputs the data programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, #Data Polling on DQ7 is active for about 1μS, and then the device returns to the read mode. During the Embedded Erase algorithm, #Data Polling produces “0” on DQ7. Once the Embedded Erase algorithm has completed, #Data Polling produces “1” on DQ7. An address within any of the sectors selected for erasure must be provided to read valid status information on DQ7. Just before the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (#OE) is set to low. That is, the device may change from providing status information to valid data on DQ7. Depending on when it samples the DQ7 output, the system may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still invalid. Valid data on DQ7-DQ0 will appear on successive read cycles. RY/#BY: Ready/#Busy The RY/#BY is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/#BY status is valid after the rising edge of the final #WE pulse in the command sequence. Since RY/#BY is an open-drain output, several RY/#BY pins can be tied together in parallel with a pull-up resistor to VDD. When the output is low (Busy), the device is actively erasing or programming. When the output is high (Ready), the device is in the read mode or standby mode. DQ6: Toggle Bit Toggle Bit on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete. Toggle Bit I may be read at any address, and is valid after the rising edge of the final #WE pulse in the command sequence (before the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either #OE or #CE to control the read cycles. Once the operation has completed, DQ6 stops toggling. The system can use DQ6 to determine whether a sector is actively erasing. If the device is actively erasing (i.e., the Embedded Erase algorithm is in progress), DQ6 toggles. If a program address falls within a protected sector, DQ6 toggles for about 1 μs after the program command sequence is written, and then returns to reading array data. DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. DQ5 produces “1” under these conditions which indicates that the program or erase cycle was not successfully completed. -7- Publication Release Date: December 12, 2005 Revision A4 W39V040FB The device may output “1” on DQ5 if the system tries to program “1” to a location that was previously programmed to “0.” Only the erase operation can change “0” back to “1.” Under this condition, the device stops the operation, and while the timing limit has been exceeded, DQ5 produces “1.” Under both these conditions, the system must hardware reset to return to the read mode. 7. REGISTER FOR FWH MODE There are three kinds of registers on this device, the General Purpose Input Registers, the Block Lock Control Registers and Product Identification Registers. Users can access these registers through respective address in the 4Gbytes memory map. There are detail descriptions in the sections below. 7.1 General Purpose Inputs Register for FWH Mode This register reads the FGPI[4:0] pins on the W39V040FB.This is a pass-through register which can read via memory address FFBC0100(hex). Since it is pass-through register, there is no default value. GPI Register Table BIT FUNCTION 7−5 Reserved 4 Read FGPI4 pin status 3 Read FGPI3 pin status 2 Read FGPI2 pin status 1 Read FGPI1 pin status 0 Read FGPI0 pin status 7.2 Product Identification Registers In the FWH interface mode, a read from FFBC, 0000(hex) can output the manufacturer code, DA(hex). A read from FFBC, 0001(hex) can output the device code 54(hex). There is an alternative software method to read out the Product Identification in both the Programmer interface mode and the FWH interface mode. Thus, the programming equipment can automatically matches the device with its proper erase and programming algorithms. In the software access mode, a or JEDEC 3-byte command sequence can be used to access the product ID for programmer interface mode. A read from address 0000(hex) outputs the manufacturer code, DA(hex). A read from address 0001(hex) outputs the device code, 54(hex). The product ID operation can be terminated by a three-byte command sequence or an alternate one-byte command sequence (see Command Definition table for detail). 7.3 Block Locking Registers This part provides 8 even 64Kbytes blocks, and each block can be locked by register control. These control registers can be set or clear through memory address. Below is the detail description. Please note that this feature is only can be applied on FWH mode. -8- W39V040FB Block Locking Registers type and access memory map Table REGISTERS REGISTERS TYPE CONTROL BLOCK DEVICE PHYSICAL ADDRESS 4GBYTES SYSTEM MEMORY ADDRESS BLR7 R/W 7 7FFFFh – 70000h FFBF0002h BLR6 R/W 6 6FFFFh – 60000h FFBE0002h BLR5 R/W 5 5FFFFh – 50000h FFBD0002h BLR4 R/W 4 4FFFFh – 40000h FFBC0002h BLR3 R/W 3 3FFFFh – 30000h FFBB0002h BLR2 R/W 2 2FFFFh – 20000h FFBA0002h BLR1 R/W 1 1FFFFh – 10000h FFB90002h BLR0 R/W 0 0FFFFh – 00000h FFB80002h Block Locking Register Bits Function Table BIT FUNCTION 7–3 Reserved Read Lock 1: Prohibit to read in the block where set 0: Normal read operation in the block where clear. This is default state. Lock Down 1: Prohibit further to set or clear the Read Lock or Write Lock bits. This Lock Down Bit can only be set not clear. Only the device is reset or re-powered, the Lock Down Bit is cleared. 0: Normal operation for Read Lock or Write Lock. This is the default state. Write Lock 1: Prohibited to write in the block where set. This is default state. 0: Normal programming/erase operation in the block where clear. 2 1 0 7.4 Register Based Block Locking Value Definitions Table BIT [7:3] BIT 2 BIT 1 BIT 0 RESULT 00000 0 0 0 Full Access. 00000 0 0 1 Write Lock. Default State. 00000 0 1 0 Locked Open (Full Access, Lock Down). 00000 0 1 1 Write Locked, Locked Down. 00000 1 0 0 Read Locked. 00000 1 0 1 Read & Write Locked. 00000 1 1 0 Read Locked, Locked Down. 00000 1 1 1 Read & Write Locked, Locked Down. -9- Publication Release Date: December 12, 2005 Revision A4 W39V040FB 7.5 Read Lock Any attempt to read the data of read locked block will result in “00H.” The default state of any block is unlocked upon power up. User can clear or set the write lock bit anytime as long as the lock down bit is not set. 7.6 Write Lock This is the default state of blocks upon power up. Before any program or erase to the specified block, user should clear the write lock bit first. User can clear or set the write lock bit anytime as long as the lock down bit is not set. The write lock function is in conjunction with the hardware protect pins, #WP & TBL. When hardware protect pins are enabled, it will override the register block locking functions and write lock the blocks no matter how the status of the register bits. Reading the register bit will not reflect the status of the #WP or #TBL pins. 7.7 Lock Down The default state of lock down bit for any block is unlocked. This bit can be set only once; any further attempt to set or clear is ignored. Only the reset from #RESET or #INIT can clear the lock down bit. Once the lock down bit is set for a block, then the write lock bit & read lock bit of that block will not be set or cleared, and keep its current state. 7.8 Product Identification Registers In the FWH interface mode, a read from FFBC, 0000(hex) can output the manufacturer code, DA(hex). A read from FFBC,0001(hex) can output the device code 54(hex). There is an alternative software method (six commands bytes) to read out the Product Identification in both the Programmer interface mode and the FWH interface mode. Thus, the programming equipment can automatically matches the device with its proper erase and programming algorithms. In the software access mode, a six-byte (or JEDEC 3-byte) command sequence can be used to access the product ID for programmer interface mode. A read from address 0000(hex) outputs the manufacturer code, DA(hex). A read from address 0001(hex) outputs the device code, 54(hex). The product ID operation can be terminated by a three-byte command sequence or an alternate one-byte command sequence (see Command Definition table for detail). - 10 - W39V040FB 8. TABLE OF OPERATING MODES 8.1 Operating Mode Selection - Programmer Mode PINS MODE #OE #WE #RESET ADDRESS DQ. Read VIL VIH VIH AIN Dout Write VIH VIL VIH AIN Din X X VIL X High Z VIL X VIH X High Z/DOUT X VIH VIH X High Z/DOUT VIH X VIH X High Z Standby Write Inhibit Output Disable 8.2 Operating Mode Selection - FWH Mode Operation modes in FWH interface mode are determined by "START Cycle" when it is selected. When it is not selected, its outputs (FWH[3:0]) will be disable. Please reference to the "FWH Cycle Definition". 8.3 FWH Cycle Definition FIELD NO. OF CLOCKS DESCRIPTION START 1 "1101b" indicates FWH Memory Read cycle; while "1110b" indicates FWH Memory Write cycle. 0000b" appears on FWH bus to indicate the initial IDSEL 1 This one clock field indicates which FWH component is being selected. MSIZE 1 Memory Size. There is always show “0000b” for single byte access. TAR 2 Turned Around Time ADDR 7 Address Phase for Memory Cycle. FWH supports the 28 bits address protocol. The addresses transfer most significant nibble first and least significant nibble last. (i.e. Address[27:24] on FWH[3:0] first, and Address[3:0] on FWH[3:0] last.) SYNC N Synchronous to add wait state. "0000b" means Ready, "0101b" means Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b" means error, and other values are reserved. DATA 2 Data Phase for Memory Cycle. The data transfer least significant nibble first and most significant nibble last. (i.e. DQ[3:0] on FWH[3:0] first, then DQ[7:4] on FWH[3:0] last.) - 11 - Publication Release Date: December 12, 2005 Revision A4 W39V040FB 9. TABLE OF COMMAND DEFINITION COMMAND DESCRIPTION Read Sector Erase Byte Program Product ID Entry (4) Product ID Exit (4) Product ID Exit NO. OF Cycles (1) 1 6 4 3 3 1 1ST CYCLE Addr. Data AIN DOUT 5555 AA 5555 AA 5555 AA 5555 AA XXXX F0 2ND CYCLE Addr. Data 2AAA 2AAA 2AAA 2AAA 55 55 55 55 3RD CYCLE Addr. Data 5555 5555 5555 5555 80 A0 90 F0 4TH CYCLE Addr. Data 5TH CYCLE Addr. Data 5555 AA AIN DIN 2AAA 55 6TH CYCLE Addr. Data SA (5) Notes: 1. The cycle means the write command cycle not the FWH clock cycle. 2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[7:0] are mapped to the internal A[18:11] 3. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex) 4. Either one of the two Product ID Exit commands can be used. 5. SA: Sector Address SA = 7XXXXh for Unique Sector7 (Boot Sector) SA = 3XXXXh for Unique Sector3 SA = 6XXXXh for Unique Sector6 SA = 2XXXXh for Unique Sector2 SA = 5XXXXh for Unique Sector5 SA = 1XXXXh for Unique Sector1 SA = 4XXXXh for Unique Sector4 SA = 0XXXXh for Unique Sector0 - 12 - 30 W39V040FB 9.1 Embedded Programming Algorithm Start Write Program Command Sequence (see below) #Data Polling/ Toggle bit Programming Completed Program Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data - 13 - Publication Release Date: December 12, 2005 Revision A4 W39V040FB 9.2 Embedded Erase Algorithm Start Write Erase Command Sequence (see below) #Data Polling or Toggle Bit Erasure Completed Individual Sector Erase Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/80H 5555H/AAH 2AAAH/55H Sector Address/30H - 14 - W39V040FB 9.3 Embedded #Data Polling Algorithm Start Read Byte (DQ0 - DQ7) Address = SA Yes DQ7 = Data ? No No DQ5 = 1 Yes Read Byte (DQ0 - DQ7) Address = SA Yes DQ7 = Data No Fail Pass Note: SA = Valid address for programming .During a sector erase operation, a valid address is an address within any sector selected for erasure. - 15 - Publication Release Date: December 12, 2005 Revision A4 W39V040FB 9.4 Embedded Toggle Bit Algorithm Start Read Byte (DQ0-DQ7) Read Byte (DQ0-DQ7) No Toggle Bit =Toggle ? Yes No DQ5 = 1 ? Yes Read Byte (DQ0-DQ7) Twin No Toggle Bit =Toggle ? Fail Pass Note: Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. - 16 - W39V040FB 9.5 Software Product Identification and Boot Block Lockout Detection Acquisition Flow Product Identification Entry (1) Load data AA to address 5555 Product Product Identification Exit(6) Identification and Boot Block Lockout Detection Mode (3) Load data AA to address 5555 (2) Load data 55 to address 2AAA Read address = 00000 data = DA Load data 90 to address 5555 Read address = 00001 data = 54 Pause 10 μS Read address = 7FFF2 Check DQ[3:0] of data outputs (2) Load data 55 to address 2AAA Load data F0 to address 5555 (4) Pause 10 μS (5) Normal Mode Notes for software product identification/boot block lockout detection: (1) Data Format: DQ7−DQ0 (Hex); Address Format: A14−A0 (Hex) (2) A1−A18 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) The DQ[3:2] to indicate the sectors protect status as below: 0 1 DQ2 64Kbytes Boot Block Unlocked by #TBL hardware trapping 64Kbytes Boot Block Locked by #TBL hardware trapping DQ3 Whole Chip Unlocked by #WP hardware trapping Except Boot Block Whole Chip Locked by #WP hardware trapping Except Boot Block (5) The device returns to standard operation mode. (6) Optional 1-write cycle (write F0 (hex.) at XXXX address) can be used to exit the product identification/boot block lockout detection. - 17 - Publication Release Date: December 12, 2005 Revision A4 W39V040FB 10. ELECTRICAL CHARACTERISTICS 10.1 Absolute Maximum Ratings PARAMETER RATING UNIT 0 to +70 °C Storage Temperature -65 to +150 °C Power Supply Voltage to VSS Potential -0.5 to +4.0 V -0.5 to VDD +0.5 V -0.5 to +13 V -1.0 to VDD +0.5 V Operating Temperature D.C. Voltage on Any Pin to Ground Potential VPP Voltage Transient Voltage (<20 nS) on Any Pin to Ground Potential Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings May adversely affect the life and reliability of the device. 10.2 Programmer interface Mode DC Operating Characteristics (VDD = 3.3V ± 0.3V, VSS= 0V, TA = 0 to 70° C) PARAMETER SYM. LIMITS TEST CONDITIONS MIN. TYP. Power Supply Current ICC Input Leakage Current ILI Output Leakage Current ILO Input Low Voltage VIL Input High Voltage VIH Output Low Voltage VOL Output High Voltage VOH In Read or Write mode, all DQs open UNIT MAX. mA - 15 30 VIN = VSS to VDD - - 90 μA VOUT = VSS to VDD - - 90 μA - -0.5 - 0.8 V - 2.0 - VDD +0.5 V IOL = 2.1 mA - - 0.45 V IOH = -0.1mA 2.4 - - V Address inputs = 3.0V/0V, at f = 3 MHz - 18 - W39V040FB 10.3 FWH Interface Mode DC Operating Characteristics (VDD = 3.3V ± 0.3V, VSS= 0V, TA = 0 to 70° C) PARAMETER Power Supply Current Read Power Supply Current Program/Erase SYM. LIMITS TEST CONDITIONS UNIT MIN. TYP. MAX. ICC All Iout = 0A, CLK = 33 MHz, in FWH mode operation. - 15 25 mA ICC CLK = 33 MHz, in FWH mode operation. - 18 30 mA - 20 50 uA - 3 10 mA FWH4 = 0.9 VDD, CLK = 33 MHz, Standby Current 1 Isb1 all inputs = 0.9 VDD / 0.1 VDD no internal operation FWH4 = 0.1 VDD, CLK = 33 MHz, Standby Current 2 Isb2 Input Low Voltage VIL - -0.5 - 0.3 VDD V Input Low Voltage of #INIT VILI - -0.5 - 0.2 VDD V Input High Voltage VIH - 0.5 VDD - VDD +0.5 V Input High Voltage of #INIT Pin VIHI - 1.35 V - VDD +0.5 V Output Low Voltage VOL IOL = 1.5 mA - - 0.1 VDD V Output High Voltage VOH IOH = -0.5 mA 0.9 VDD - - V all inputs = 0.9 VDD /0.1 VDD no internal operation. 10.4 Power-up Timing PARAMETER SYMBOL TYPICAL UNIT Power-up to Read Operation TPU. READ 100 μS Power-up to Write Operation TPU. WRITE 5 mS MAX. UNIT 10.5 Capacitance (VDD = 3.3V, TA = 25° C, f = 1 MHz) PARAMETER SYMBOL CONDITIONS I/O Pin Capacitance CI/O VI/O = 0V 12 pf Input Capacitance CIN VIN = 0V 6 pf - 19 - Publication Release Date: December 12, 2005 Revision A4 W39V040FB 10.6 Programmer Interface Mode AC Characteristics AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0V to 0.9 VDD Input Rise/Fall Time < 5 nS Input/Output Timing Level 1.5V/1.5V Output Load 1 TTL Gate and CL = 30 pF AC Test Load and Waveform +3.3V 1.8KΩ DOUT Input 30 pF (Including Jig and Scope) Output 0.9VDD 1.3K Ω 1.5V 1.5V 0V Test Point - 20 - Test Point W39V040FB Programmer Interface Mode AC Characteristics, continued 10.7 Read Cycle Timing Parameters (VDD = 3.3V ± 0.3V, VSS = 0V, TA = 0 to 70° C) PARAMETER Read Cycle Time Row / Column Address Set Up Time Row / Column Address Hold Time Address Access Time Output Enable Access Time #OE Low to Active Output #OE High to High-Z Output Output Hold from Address Change SYMBOL TRC TAS TAH TAA TOE TOLZ TOHZ TOH W39V040FB MIN. MAX. 350 50 50 0 0 UNIT 150 75 35 - nS nS nS nS nS nS nS nS 10.8 Write Cycle Timing Parameters PARAMETER Reset Time Address Setup Time Address Hold Time R/#C to Write Enable High Time #WE Pulse Width #WE High Width Data Setup Time Data Hold Time #OE Hold Time Byte programming Time Sector Erase Cycle Time (Note 2) Program/Erase Valid to RY/#BY Delay SYMBOL MIN. TYP. MAX. UNIT TRST TAS TAH TCWH TWP TWPH TDS TDH TOEH TBP TPEC TBUSY 1 50 50 50 100 100 50 50 0 90 12 0.6 - 200 6 - μS nS nS nS nS nS nS nS nS μS S nS Notes: 1. All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is input high and (b) low level signal's reference level is input low. Ref. to the AC testing condition. 2. Exclude 00H pre-program prior to erasure. (In the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00H before erasure 10.9 Data Polling and Toggle Bit Timing Parameters PARAMETER #OE to Data Polling Output Delay #OE to Toggle Bit Output Delay Toggle or Polling interval SYMBOL TOEP TOET - - 21 - W39V040FB MIN. MAX. 50 350 350 - UNIT nS nS mS Publication Release Date: December 12, 2005 Revision A4 W39V040FB 11. TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE 11.1 Read Cycle Timing Diagram #RESET TRST TRC TAS Column Address Row Address Column Address A[10:0] TAH Row Address TAH TAS R/#C VIH #WE TAA #OE TOH TOE T OHZ TOLZ High-Z High-Z DQ[7:0] Data Valid 11.2 Write Cycle Timing Diagram TRST #RESET A[10:0] Column Address TAS TAH Row Address TAS TAH R/ #C TCWH TOEH #OE TWP TWPH #WE TDS DQ[7:0] Data Valid - 22 - TDH W39V040FB Timing Waveforms for Programmer Interface Mode, continued 11.3 Program Cycle Timing Diagram Byte Program Cycle A[10:0] 2AAA 5555 (Internal A[18:0]) DQ[7:0] 5555 55 AA Programmed Address A0 Data-In R/#C #OE T WPH TBP TWP #WE Byte 1 Byte 0 Byte 2 Byte 3 Internal Write Start RY/#BY T BUSY Note: The internal address A[18:0] are converted from external Column/Row address. Column/Row Address are mapped to the Low/High order internal address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[7:0] are mapped to the internal A[18:11]. 11.4 #DATA Polling Timing Diagram A[10:0] (Internal A[18:0]) An An An An R/ #C #WE #OE TOEP DQ7 X X X X TBP RY/#BY TBUSY - 23 - Publication Release Date: December 12, 2005 Revision A4 W39V040FB Timing Waveforms for Programmer Interface Mode, continued 11.5 Toggle Bit Timing Diagram A[10:0] R/ #C #WE #OE TOET DQ6 TBP RY/#BY 11.6 Sector Erase Timing Diagram Six-byte code for 3.3V-only Sector Erase A[10:0] (Internal A[18:0]) DQ[7:0] 5555 2AAA 5555 AA 55 80 5555 AA 2AAA 55 SA 30 R/ #C #OE TWP TPEC #WE TWPH Internal Erase starts SB0 SB1 SB2 SB3 SB4 SB5 RY/#BY Note: The internal address A[18:0] are converted from external Column/Row addres Column/Row Address are mapped to the Low/High order internal address i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[7:0] are mapped to the internal A[18:11]. SA = Sector Address, Please ref. to the "Table of Command Definition" - 24 - TBUSY W39V040FB 12. FWH INTERFACE MODE AC CHARACTERISTICS 12.1 AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0.6 VDD to 0.2 VDD Input Rise/Fall Slew Rate 1 V/nS Input/Output Timing Level 0.4VDD / 0.4VDD Output Load 1 TTL Gate and CL = 10 pF 12.2 Read/Write Cycle Timing Parameters (VDD = 3.3V ± 0.3V, VSS = 0V, TA = 0 to 70° C) PARAMETER SYMBOL W39V040FB UNIT MIN. MAX. Clock Cycle Time TCYC 30 - nS Input Set Up Time TSU 7 - nS Input Hold Time THD 0 - nS Clock to Data Valid TKQ 2 11 nS Note: Minimum and Maximum time have different load. Please refer to PCI specification. 12.3 Reset Timing Parameters PARAMETER SYMBOL MIN. TYP. MAX. UNIT VDD stable to Reset Active TPRST 1 - - mS Clock Stable to Reset Active TKRST 100 - - μS Reset Pulse Width TRSTP 100 - - nS Reset Active to Output Float TRSTF - - 50 nS Reset Inactive to Input Active TRST 10 - - μS Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is input high and (b) low level signal's reference level is input low. Please refer to the AC testing condition. - 25 - Publication Release Date: December 12, 2005 Revision A4 W39V040FB 13. TIMING WAVEFORMS FOR FWH INTERFACE MODE 13.1 Read Cycle Timing Diagram TCYC CLK #RESET TSU THD FWH4 TSU THD Start FWH Read FWH[3:0] Address IDSEL 1101b 0000b 1 Clock 1 Clock TKQ M Size XXXXb XA[22]XXb A[18:16] A[15:12] A[11:8] A[7:4] A[3:0] TAR 0000b 1111b Load Address in 7 Clocks Sync Tri-State 0000b 2 Clocks TAR Data D[3:0] D[7:4] 1111b 1 Clock Data out 2 Clocks Next Start 0000b Tri-State 2 Clocks 1 Clock Note: When A22 = high, the host will read the BIOS code from the FWH device. While A22 = low, the host will read the GPI (Add = FFBC0100) or Product ID (Add = FFBC0000/FFBC0001) from the FWH device 13.2 Write Cycle Timing Diagram TCYC CLK #RESET TSU THD FWH4 Start FWH Write FWH[3:0] IDSEL 1110b 0000b 1 Clock1 Clock Address XXXXb XXXXb A[18:16] A[15:12] A[11:8] M Size A[7:4] A[3:0] 0000b Data D[3:0] D[7:4] TAR Load Data in 2 Clocks 2 Clocks Load Address in 7 Clocks - 26 - Sync 1111b Tri-State 0000b 1 Clock TAR Next Start 1111b Tri-State 0000b 2 Clocks 1 Clock W39V040FB Timing Waveforms for FWH Interface Mode, continued 13.3 Program Cycle Timing Diagram CLK #RESET FWH4 FWH[3:0 1110b ] 1 Clock Address IDSEL 1st Start 0000b XXXXb XXXXb XXXXb X101b 0101b 0101b 0101b 0000b TAR 1010b 1111b 1010b Load Data "AA" in 2 Clocks Load Address "5555" in 7 Clocks 1 Clock Data M Size Tri-State 2 Clocks Sync 0000b Start next command TAR 1111b 1 Clock Tri-State 2 Clocks 1 Clock Write the 1st command to the device in FWH mode. CLK #RESET FWH4 2nd Start FWH[3:0 ] 1110b 1 Clock Address IDSEL 0000b XXXXb XXXXb XXXXb X010b Data M Size 1010b 1010b 1010b 0000b 0101b 1111b 0101b Load Data "55" in 2 Clocks Load Address "2AAA" in 7 Clocks 1 Clock TAR Tri-State 2 Clocks 0000b Start next command TAR Sync 1111b 1 Clock Tri-State 2 Clocks 1 Clock Write the 2nd command to the device in FWH mode. CLK #RESET FWH4 3rd Start ] FWH[3:0 1110b 1 Clock Address IDSEL 0000b XXXXb XXXXb XXXXb X101b 0101b 0101b 0101b 0000b 0000b TAR 1010b 1111b Load Data "A0" in 2 Clocks Load Address "5555" in 7 Clocks 1 Clock Data M Size Tri-State 2 Clocks 0000b Start next command TAR Sync 1111b 1 Clock Tri-State 2 Clocks 1 Clock Write the 3rd command to the device in FWH mode. CLK #RESET Internal program start FWH4 4th Start FWH[3:0 ] 1110b Address IDSEL 0000b XXXXb XXXXb A[18:16] A[15:12] A[11:8] A[7:4] A[3:0] 0000b TAR Data M Size D[3:0] D[7:4] 1111b TAR Sync Tri-State 0000b 1111b Tri-State Internal program start 1 Clock 1 Clock Load Din in 2 Clocks Load Ain in 7 Clocks 2 Clocks 1 Clock 2 Clocks Write the 4th command(target location to be programmed) to the device in FWH mode. - 27 - Publication Release Date: December 12, 2005 Revision A4 W39V040FB Timing Waveforms for FWH Interface Mode, continued 13.4 #DATA Polling Timing Diagram CLK #RESET FWH4 Start FWH[3:0] 1110b Address IDSEL 0000b XXXXb XXXXb 1 Clock 1 Clock An[18:16] An[15:12] M Size An[11:8] An[7:4] An[3:0] 0000b Data Dn[3:0] Dn[7:4] Load Data "Dn" in 2 Clocks Load Address "An" in 7 Clocks TAR 1111b Sync 0000b Tri-State 2 Clocks 1 Clock TAR 1111b Next Start Tri-State 2 Clocks 1 Clock Write the last command(program or erase) to the device in FWH mode. CLK #RESET XXXXb FWH4 FWH[3:0] Start IDSEL 1101b 0000b Address XXXXb XXXXb 1 Clock 1 Clock An[18:16] An[15:12] TAR M Size An[11:8] An[7:4] An[3:0] 0000b 1111b Tri-State 2 Clocks Load Address in 7 Clocks Sync 0000b Data XXXXb Dn7,xxx 1 Clock Data out 2 Clocks TAR 1111b Next Start Tri-State 2 Clocks 1 Clock Read the DQ7 to see if the internal write complete or not. CLK #RESET FWH4 FWH[3:0] Start IDSEL 1101b 0000b 1 Clock 1 Clock Address XXXXb XXXXb An[18:16] An[15:12] TAR M Size An[11:8] An[7:4] An[3:0] Load Address in 7 Clocks 0000b 1111b Tri-State 2 Clocks When internal write complete, the DQ7 will equal to Dn7. - 28 - Sync 0000b Data XXXXb Dn7,xxx 1 Clock Data out 2 Clocks TAR 1111b Next Start Tri-State 2 Clocks 1 Clock W39V040FB Timing Waveforms for FWH Interface Mode, continued 13.5 Toggle Bit Timing Diagram CLK #RESET FWH4 Start FWH[3:0] Address IDSEL 1110b 0000b XXXXb XXXXb 1 Clock 1 Clock A[18:16] A[15:12] Data M Size A[11:8] A[7:4] A[3:0] 0000b D[3:0] D[7:4] Load Data "Dn" in 2 Clocks Load Address "An" in 7 Clocks TAR 1111b Sync 0000b Tri-State 2 Clocks 1 Clock TAR 1111b Next Start Tri-State 2 Clocks 1 Clock Write the last command(program or erase) to the device in FWH mode. CLK #RESET FWH4 Start FWH[3:0] 1101b Address IDSEL 0000b XXXXb XXXXb 1 Clock 1 Clock XXXXb XXXXb TAR M Size XXXXb XXXXb XXXXb 0000b 1111b Tri-State 2 Clocks Load Address in 7 Clocks Sync 0000b Data XXXXb X,D6,XXb 1 Clock Data out 2 Clocks TAR 1111b Next Start Tri-State 2 Clocks 1 Clock Read the DQ6 to see if the internal write complete or not. CLK #RESET FWH4 Start FWH[3:0] Address IDSEL 1101b 0000b 1 Clock 1 Clock XXXXb XXXXb XXXXb XXXXb TAR M Size XXXXb XXXXb XXXXb 0000b 1111b Tri-State 2 Clocks Load Address in 7 Clocks Sync 0000b Data XXXXb X,D6,XXb 1 Clock Data out 2 Clocks TAR 1111b Next Start Tri-State 2 Clocks 1 Clock When internal write complete, the DQ6 will stop toggle. - 29 - Publication Release Date: December 12, 2005 Revision A4 W39V040FB Timing Waveforms for FWH Interface Mode, continued Sector Erase Timing Diagram CLK #RESET FWH4 1110b 0000b XXXXb XXXXb XXXXb X101b 0101b 0101b 0101b 0000b 1010b TAR 1010b Load Data "AA" in 2 Clocks Load Address "5555" in 7 Clocks 1 Clock 1 Clock Data M Size Address 1st Start IDSEL FWH[3:0] 1111b Tri-State 2 Clocks 1 Clock Start next command TAR Sync 0000b 1111b Tri-State 2 Clocks 1 Clock Write the 1st command to the device in FWH mode. CLK #RESET FWH4 Address 2nd Start IDSEL FWH[3:0] 1110b 0000b XXXXb XXXXb XXXXb X010b 1010b 1010b 0000b 0101b TAR 0101b Load Data "55" in 2 Clocks Load Address "2AAA" in 7 Clocks 1 Clock 1 Clock Data M Size 1010b 1111b Tri-State 2 Clocks 1 Clock Start next command TAR Sync 0000b 1111b Tri-State 2 Clocks 1 Clock Write the 2nd command to the device in FWH mode. CLK #RESET FWH4 1110b 0000b M Size Address 3rd Start IDSEL FWH[3:0] XXXXb XXXXb XXXXb X101b 0101b 0101b 0101b 0000b TAR 1000b Load Data "80" in 2 Clocks Load Address "5555" in 7 Clocks 1 Clocks1 Clocks Data 0000b 1111b Sync Tri-State 2 Clocks 0000b 1 Clocks Start next command TAR Tri-State 1111b 2 Clocks 1 Clocks TAR Start next command Write the 3rd command to the device in FWH mode. CLK #RESET FWH4 FWH[3:0] Address 4th Start IDSEL 1110b 0000b XXXXb XXXXb 1 Clock 1 Clock XXXXb X101b M Size 0101b 0101b 0101b 0000b Data 1010b TAR 1010b Load Data "AA" in 2 Clocks Load Address "5555" in 7 Clocks Tri-State 1111b 2 Clocks Sync 0000b 1 Clock 1111b Tri-State 2 Clocks 1 Clock Write the 4th command to the device in FWH mode. CLK #RESET FWH4 1110b 0000b M Size Address 5th Start IDSEL FWH[3:0] XXXXb XXXXb XXXXb X010b 1010b 1010b 1010b 0000b TAR 0101b Load Data "55" in 2 Clocks Load Address "2AAA" in 7 Clocks 1 Clock 1 Clock Data 0101b 1111b Tri-State 2 Clocks Sync 0000b 1 Clock Start next command TAR 1111b Tri-State 2 Clocks 1 Clock Write the 5th command to the device in FWH mode. CLK #RESET FWH4 Internal erase start 6th Start Address IDSEL M Size Data TAR Sync FWH[3:0] 1110b 0000b 1 Clock 1 Clock XXXXb XXXXb A[18:16] XXXXb XXXXb XXXXb XXXXb Load Sector Address in 7 Clocks 0000b 0000b 0011b Load Din in 2 Clocks 1111b Tri-State 2 Clocks 0000b 1 Clock Write the 6th command(target sector to be erased) to the device in FWH mode. - 30 - TAR 1111b Tri-State Internal erase start 2 Clocks W39V040FB Timing Waveforms for FWH Interface Mode, continued 13.6 FGPI Register/Product ID Readout Timing Diagram CLK #RESET FWH4 Start IDSEL 1101b 0000b 1 Clock 1 Clock M Size Address FWH[3:0] A[27:24] A[23:20] A[19:16] 0000b 0001b /0000b 0000b 0000b /0001b 0000b Load Address "FFBC0100(hex)" in 7 Clocks for GPI Register & "FFBC0000(hex)/FFBC0001(hex) for Product ID TAR Tri-State 1111b 2 Clocks TAR Data Sync 0000b D[3:0] D[7:4] 1 Clock Data out 2 Clocks Tri-State Next Sta 1111b 2 Clocks 1 Clock Note: During the GPI read out mode, the DQ[4:0] will capture the states(High or Low) of the FGPI[4:0] input pins. The DQ[7:5] are reserved pins 13.7 Reset Timing Diagram VDD TPRST CLK TKRST TRSTP #RESET TRST T RSTF FWH[3:0] FWH4 - 31 - Publication Release Date: December 12, 2005 Revision A4 W39V040FB 14. ORDERING INFORMATION ACCESS TIME POWER SUPPLY CURRENT MAX. STANDBY VDD CURRENT MAX. (nS) (mA) (mA) W39V040FBP 11 30 10 32L PLCC W39V040FBQ 11 30 10 32L STSOP W39V040FBPZ 11 30 10 32L PLCC Lead free W39V040FBQZ 11 30 10 32L STSOP Lead free PART NO. PACKAGE Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 15. HOW TO READ THE TOP MARKING Example: The top marking of 32-pin STSOP W39V040FBQ W39V040FBQ 2138977A-A12 345OBFA 1st line: Winbond logo 2nd line: the part number: W39V040FBQ 3rd line: the lot number 4th line: the tracking code: 345 O B FA 149: Packages made in ’03, week 45 O: Assembly house ID: A means ASE, O means OSE, ...etc. B: IC revision; A means version A, B means version B, ...etc. FA: Process code - 32 - W39V040FB 16. PACKAGE DIMENSIONS 16.1 32L PLCC Symbol HE A A1 A2 b1 b c D E e GD GE HD HE L y θ E 4 1 32 30 5 29 GD D HD Dimension in Inches Dimension in mm Min. Nom. Max. Min. Nom. Max. 3.56 0.140 0.50 0.020 0.105 0.110 0.115 2.67 2.80 2.93 0.026 0.028 0.032 0.66 0.71 0.81 0.016 0.018 0.022 0.41 0.46 0.008 0.56 0.010 0.014 0.20 0.25 0.35 0.547 0.550 0.553 13.89 13.97 14.05 0.447 0.450 0.453 11.35 11.43 11.51 0.044 0.050 0.056 1.12 1.27 1.42 0.490 0.510 0.530 12.45 12.95 13.46 0.390 0.410 0.430 9.91 10.41 10.92 0.585 0.590 0.595 14.86 14.99 15.11 0.485 0.490 0.495 12.32 12.45 12.57 0.075 0.090 0.095 1.91 2.29 2.41 0.004 0 10 0.10 0 10 21 13 Notes: 14 1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusio 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection sepc. c 20 L A2 θ e A1 b b1 Seating Plane A y GE 16.2 32L STSOP HD D c Dimension in Inches Dimension in mm Symbol Min. Nom. Max. e E b θ A1 A2 A L L1 - 33 - Y A A1 A2 b c D E HD e L L1 Y θ Min. Nom. Max. 0.047 0.002 1.20 0.006 0.05 0.15 0.035 0.040 0.041 0.95 1.00 0.007 0.009 0.010 0.17 0.22 0.27 0.004 ----- 0.008 0.10 ----- 0.21 0.488 12.40 0.315 8.00 0.551 14.00 0.020 0.020 0.024 0.50 0.028 0.50 0.031 0.000 0 3 1.05 0.60 0.70 0.80 0.004 0.00 5 0 0.10 3 5 Publication Release Date: December 12, 2005 Revision A4 W39V040FB 17. VERSION HISTORY VERSION DATE PAGE A1 August 19, 2004 - DESCRIPTION Initial Issued Modify Isb1, Tbp, Tpec, Icc (read) A2 October 4, 2004 3, 17, 18, 20 Add Icc (program/erase) and Toggle or polling interval Power supply voltage to Vss potential A3 April 14, 2005 33 A4 Dec. 12, 2005 7, 16 Add important notice Revise DQ5: Exceeded Timing Limits description, Embedded Toggle Bit Algorithm Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 34 -