SC2463
High Performance Quad Output
Switching Regulator
POWER MANAGEMENT
Description
Features
The SC2463 is a high performance controller for multioutput converters that can be configured for a wide variety of applications. The SC2463 utilizes PWM synchronous buck topologies where efficiency is most important.
It also provides two dedicated programmable positive
linear regulators using external transistors. Each of the
four outputs is adjustable down to 0.5V. The two PWM
switchers are synchronized 180° out of phase reducing
input ripple, allowing for fewer input capacitors. Power
up sequencing prevents converter latch-up.
Two synchronized converters for low noise
Power up sequencing to prevent latch-up
Out of phase operation for low input ripple
Over current protection
Wide input range, 4.5 to 30V
Programmable frequency up to 700kHz
Low shutdown current 100uA
Two synchronous bucks for high efficiency at high
current
Two programmable positive linear regulators
Output voltage as low as 0.5V
Small package TSSOP-28. This product is fully
WEEE and RoHS compliant
The SC2463 can be synchronized to other converters to
prevent beat frequencies. The wide range programmable
operating frequency allows users to optimize a converter
design. The PWM switchers sense the voltage across the
low-side MOSFETs on-resistance to efficiently provide
adjustable current-limit, eliminating costly current-sense
resistors. A POK signal is issued when soft-start is complete on both PWM switchers and their outputs are within
10% of the set point.
Applications
DSL applications with multiple input voltage
requirements
Mixed-Signal applications requiring 4 positive
output voltages
Cable modem power management
Base station power management
Typical Application Circuit
+4.5-30V
C2
R1
Q1
C1
C3
R3
9
R4
+3.3V
7
8
28
27
VIN
SS/SHDN
OSC
BST2
GD2H
SY NC
PH2
POK
GD2L
FB2
R7
C10
4
Q4
+2.5V
BD4
EO2
SC2463
BST1
5
R9
FB4
GD1H
R10
C14
PH1
11
BD3
GD1L
ILIM1
R16
C18
C16
EO1
C7
17
Q2
18
+3.3V
L1
19
Q3
20
C8
R5
(as low as 0.5V)
13
C12
26
25
R6
C11
R8
12
Q5
C13
+1.5V
L2
24
Q6
23
(as low as 0.5V)
C15
2
R12
3
C19
C20
1
ILIM2
14
15
+1.2V
FB3
PGND
R11
21
10
Q7
AGND
FB1
C17
D2
D1
BDI
PVCC
6
AVCC
C6
22
U1
16
C4
R15
R13
R17
R14
R18
Revision: May 16, 2007
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SC2463
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device
reliability.
Parameter
Symbol
Maximum
Units
VIN, BDI
VIN, VBDI
-0.3 to 30
V
Power Dissipation at TA = 25°C (1)
Pd
1.3
W
Operating Ambient Temperature Range
TA
-40 < TA < 105
°C
Operating Junction Temperature Range
TJ
-40 < TJ < 150
°C
Storage Temperature Range
TSTG
-60 < TSTG < 150
°C
Thermal Resistance, Junction to Case (1)
θJC
13
°C/W
Thermal Resistance, Junction to Ambient (1)
θJA
96
°C/W
Lead Temperature (Soldering) 10 Sec.
TSOLDER
260
°C
Peak Reflow Soldering Temperature
TREFLOW
235
°C
BST1, BST2 to PGND
-0.3 to 35
V
PVCC, AVCC, GD1L, GD2L, BD3, BD4 to PGND
-0.3 to 7
V
EO1, EO2, FB1, FB2, FB3, FB4, ILIM1, ILIM2, OSC,
SYNC, POK, SS/SHDN to AGND
-0.3 to 7
V
GD1H to PH1, GD2H to PH2
-0.3 to 7
V
+/-0.3
V
-6 to 0.3
V
1
A
PGND to AGND
PH1 to BST1, PH2 to BST2
GD1H, GD1L, GD2H, GD2L peak source/sink current
Note: (1) 1 x 1 inch 1 oz copper ground plane.
Electrical Characteristics
Unless specified: V = 12V, PVCC = AVCC = 5V, fs = 600KHz, SS/SHDN = 5V, SYNC = 0V, TA = T = -40°C to 105°C
IN
Parameter
J
Test Conditions
Min
Typ
Max
Unit
SS/SHDN = 0V
100
200
µA
No load
10
14
mA
Pow er Supply using BDI Regulator
Shutdown Current ISUPPLY
Operating Current
AVCC
VIN > 5.5V
4.6
5
5.4
V
PVC C
VIN > 5.5V
4.6
5
5.4
V
3.90
4.20
4.45
V
Undervoltage Lockout
Start Threshold
UVLO Hysteresis
2007 Semtech Corp.
200
2
mV
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SC2463
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: V = 12V, PVCC = AVCC = 5V, fs = 600KHz, SS/SHDN = 5V, SYNC = 0V, TA = T = -40°C to 105°C
IN
Parameter
J
Test Conditions
Min
Typ
Max
Unit
PWM Comparator
Delay to Output
70
nS
Positive Linear Regulator w ith PNP Transistor
Feedback Voltage on FB4
0.48
Feedback Input Leakage Current
Internal FET On-Resistance
0.5
0.52
150
ISINK=5mA
V
nA
40
80
Ω
0.5
0.52
mV
Positive Linear Regulator w ith NPN Transistor
Feedback Voltage on FB3
0.48
Feedback Input Leakage Current
Internal FET On-Resistance
150
ISOURCE = 5mA
nA
70
140
Ω
0.5
0.51
V
PWM Error Amplifiers
Feedback Voltage on FB1, FB2
TJ = 25°C
0.49
0.488
Input Bias Current
0.512
200
nA
90
Open Loop Gain (1)
dB
Unity Gain Bandwidth
3
MHz
Output Sink Current
2
mA
Output Source Current
2
mA
Slew Rate
1
V/µS
Oscillator
Frequency Range
Frequency
100
RT = 12.5K
540
600
700
KHz
660
KHz
Ramp Peak Voltage
3.8
V
Ramp Valley Voltage
0.75
V
SYNC Input High Pulse Width
100
nS
SYNC Rise/Fall Time
SYNC Frequency Range
FOSC
SYNC High/Low Threshold
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1.5
3
50
nS
FOSC
+10%
kHz
V
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SC2463
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: V = 12V, PVCC = AVCC = 5V, fs = 600KHz, SS/SHDN = 5V, SYNC = 0V, TA = T = -40°C to 105°C
IN
Parameter
J
Test Conditions
Min
Typ
Max
Units
Duty Cycle
PWM 1 Maximum Duty Cycle
PWM 2 Maximum Duty Cycle
PWM 1 & 2 Minimum On Time
80
fs = 100kHz to 700kHz
%
80
fs = 100kHz to 700kHz
50
nS
Current Limit
CH1& 2 ILIM Set Voltage
TJ = 25°C
1.8
Temperature Coefficient
of ILIM Set Voltage
2
2.2
1.7
V
mV/°C
Soft Start/Shut Dow n
Charge Current
5
Discharge Current
10
15
1
µA
mA
Disable Switching Threshold
Voltage
0.45
0.5
Disable BDI Regulator Threshold
Voltage
0.28
0.34
V
50
µS
Disable Low to Shut Down
0.6
V
Output
Gate Drive On-Resistance(H)
ISOURCE=15mA
2
5
Ω
Gate Drive On-Resistance(L)
ISINK=15mA
2
5
Ω
Rise Time(H)
COUT = 1000pF
15
nS
Fall Time(H)
COUT = 1000pF
25
nS
Rise Time(L)
COUT = 1000pF
15
nS
Fall Time(L)
COUT = 1000pF
15
nS
10
%
1
%
-10
%
1
%
Pow er Good
FB1 & FB2 Trip Level above FB
Hysteresis
FB1 & FB2 Trip Level below FB
Hysteresis
PWR OK Output Low Level
Pullup resistor = 10K
PWR OK Output High Leakage
Pullup resistor = 10K
2007 Semtech Corp.
4
0.4
0.7
V
30
µA
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SC2463
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: V = 12V, PVCC = AVCC = 5V, fs = 600KHz, SS/SHDN = 5V, SYNC = 0V, TA = T = -40°C to 105°C
IN
Parameter
J
Test Conditions
Min
Typ
Max
Units
Thermal Protection
Thermal Shutdown Temperature
150
°C
Thermal Shutdown Hysteresis
15
°C
Notes:
(1) Guaranteed by design.
(2) This device is ESD sensitive. Use of standard ESD handling precautions is required.
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SC2463
POWER MANAGEMENT
Pin Configuration
Ordering Information
Top View
Part Number(2)
Package(1)
Temp. Range (TJ)
SC2463TSTRT
TSSOP-28
-40°C to +105°C
Notes:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(2) Lead free product. This product is fully WEEE and
RoHS compliant
(28 Pin TSSOP)
Marking Information
TOP
SC2463 TS
yyww
xxxxxx
nnnn = Part Number (Example: 1406)
yyww = Date Code (Example: 0012)
xxxxx = Semtech Lot No. (Example: P94A01)
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SC2463
POWER MANAGEMENT
Pin Descriptions
Pin #
Pin N ame
1
ILIM1
Adjustable current-li mi t pi n set for the PWM swi tcher1. C onnect a resi stor from thi s pi n to
AGND .
2
FB 1
Voltage mode PWM swi tcher1 feedback i nput. C onnect to a resi stor-di vi der from output to
FB1 to AGND to adjust the output voltage between 0.5V and 0.8 x VIN. The feedback set poi nt
i s 0.5V.
3
EO1
The PWM swi tcher1 loop compensati on pi n. C onnect a compensati on network to compensate
the control loop. Type 3 compensati on network i s usually used.
4
BD 4
Open-drai n output PNP transi stor dri ver. Internally connected to the drai n of an N-channel
MOSFET. Thi s pi n connects to the base of an external PNP pass transi stor to form a posi ti ve
li near regulator.
5
FB 4
PNP transi stor posi ti ve li near regulator feedback i nput. C onnect to a resi stor-di vi der between
the posi ti ve li near regulator and AGND to adjust the output voltage. The feedback set poi nt i s
0.5V.
6
SS/SHDN
The pi n provi des a soft-start functi on for the PWM swi tchers and posi ti ve li near regulators.
When the pi n reaches 0.5V, the regulated 10uA pull-up current source charges the capaci tor
connected from thi s pi n to AGND . The error ampli fi er reference voltage of swi tcher1, swi tcher2
and the two posi ti ve li near regulators ramps from 0.7V to 2V respecti vely followi ng the
sequence. If the pi n i s pulled down below 0.5V, the SC 2463 i s di sabled. If the SS/SHD N pi n i s
pulled down below 0.34V, the bi as PNP transi stor for SC 2463 i s di sabled and the supply
current i s only 100uA.
7
SYNC
The pi n can be used to synchroni ze two or more controllers. Thi s pi n requi res a 10K resi stor to
AGND when i t i s not used.
8
POK
Open-drai n power-good output. POK i s low when the output voltage i s more than 10% below
or above the regulati on poi nt. POK i s hi gh i mpedance when the output i s i n regulati on.
C onnect a resi stor between the pi n and PVC C .
9
OSC
Osci llator frequency adjustable i nput. C onnect a resi stor between the pi n and AGND to set the
PWM frequency.
10
FB 3
NPN transi stor posi ti ve li near regulator feedback i nput. C onnect to a resi stor-di vi der between
the posi ti ve li near regulator and AGND to adjust the output voltage. The feedback set poi nt i s
0.5V.
11
BD 3
Open-drai n output NPN transi stor dri ver. Internally connected to the drai n of a P-channel
MOSFET. Thi s pi n connects to the base of an external NPN pass transi stor to form a posi ti ve
li near regulator.
12
EO2
The PWM swi tcher2 loop compensati on pi n. C onnect a compensati on network to compensate
the control loop. Type 3 compensati on network i s usually used.
13
FB 2
Voltage mode PWM swi tcher2 feedback i nput. C onnect to a resi stor-di vi der from output to
FB2 to AGND to adjust the output voltage between 0.5V and 0.8 x V IN. The feedback set poi nt
i s 0.5V.
14
ILIM2
Adjustable current-li mi t pi n set for the PWM swi tcher2. C onnect a resi stor from thi s pi n to
AGND .
15
AGND
Thi s i s small si gnal ground and must be routed separately from the hi gh current ground PGND .
All voltage levels are measured wi th respect to thi s pi n. A cerami c capaci tor should be
connected ri ght to thi s pi n for noi se decoupli ng.
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Pin Function
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SC2463
POWER MANAGEMENT
Pin Descriptions (Cont.)
Pin #
Pin Name
Pin Function
16
AVCC
This pin is connected to the output of the external linear regulator to supply the IC. The IC may
be powered directly from a single 5V (±10%) supply at this pin but low-shutdown-current is lost.
The pin must be always decoupled to AGND with a minimum of 1uF ceramic capacitor, place
very close to the pin.
17
BST2
The pin powers the upper MOSFET driver of PWM switcher2. Connect this pin to the junction
of the bootstrap capacitor and cathode of the bootstrap diode. The anode of the bootstrap
diode is connected to the PVCC.
18
GD2H
Switcher2 upper MOSFET gate driver output. It swings between BST2 and PH2.
19
PH2
20
GD2L
Switcher2 lower MOSFET gate driver output. It swings between PVCC and PGND.
21
PGND
The pin provides the power ground for the lower gate drivers for both PWM switchers. It should
be connected to the sources of the lower MOSFETs and the negative terminal of the input
capacitors.
22
PVC C
This pin is connected to the output of the external linear regulator to supply the internal lower
gate drivers for both PWM switchers. It may be powered directly from a single 5V (±10%)
supply at this pin but low-shutdown-current is lost. The pin must be always decoupled to PGND
with a minimum of 10uF ceramic capacitor, place very close to the pin.
23
GD1L
Switcher1 lower MOSFET gate driver output. It swings between PVCC and PGND.
24
PH1
25
GD1H
Switcher1 upper MOSFET gate driver output. It swings between BST1 and PH1.
26
BST1
The pin powers the upper MOSFET driver of PWM switcher1. Connect this pin to the junction
of the bootstrap capacitor and cathode of the bootstrap diode. The anode of the bootstrap
diode is connected to the PVCC.
27
VIN
The pin is internally connected to the pull-up resistor of an N-channel MOSFET to regulate the
bias for the IC.
28
BD I
The external bias pass PNP transistor driver. Internally connected to the drain of an N-channel
MOSFET.
2007 Semtech Corp.
The pin is connected to the junction of the upper MOSFET's source, output inductor and lower
MOSFET's drain.
The pin is connected to the junction of the upper MOSFETs source, output inductor and lower
MOSFETs drain.
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SC2463
POWER MANAGEMENT
Block Diagram
SS/SHDN
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SC2463
POWER MANAGEMENT
Applications Information
Frequency Setting and Synchronization
The SC2463 is designed to control and drive two N-Channel MOSFET PWM synchronous buck switchers and two
positive linear regulators. The two PWM switchers are
synchronized 180° out of phase for low input ripple and
noise. The switching frequency is programmable to optimize design. The SC2463 PWM switchers feature lossless
current sensing and programmable over current limit. The
two positive linear regulators output voltages are adjustable.
The internal oscillator free-running frequency of the
SC2463 is set by an external resistor using the following
formula:
R freq =
7.9 x 10 9
fs − 12 x 10 3
When it is synchronized externally, the applied clock frequency should be equal or greater than the free-running
frequency.
Pow er Supplies
Setting Current Limit
Supplies VIN, PVCC and AVCC from the input source are
used to power the SC2463. An external PNP transistor
linear regulator supplies AVCC and PVCC. The AVCC supply provides the bias for the oscillator, the switchers, the
linear regulator controllers and the POK circuitry. PVCC is
used to drive the low side MOSFET gate. In low shutdown current mode, the PNP transistor is turned off, disabling AVCC and PVCC.
SC2463 monitors the voltage drop in the lower MOSFETs
Rdson voltage to sense an over current condition. This
method of current sensing minimizes any unnecessary
losses due to external sense resistance.
The SC2463 utilizes an internal current source and an
external resistor connected from the ILIM pins to the
AGND pin to program a current limit level. This limit is
programmable by choosing the resistor relative to the
level required. The value of the resistor can be selected
by the following formula:
Soft-start, Sequencing and Disabling
A 10µA current source pulls up on the SS/SHDN pin.
When the SS/SHDN pin reaches 0.5V, the first switcher
is activated and the reference input of the error amplifier is ramped up with the soft-start voltage. When the
SS/SHDN pin reaches 2V, the SS/SHDN pin is pulled
down to approximately 0.7V and the second switcher
begins to soft-start in an identical fashion to the first
switcher. When the SS/SHDN pin reaches 2V for the
second time, the SS/SHDN pin is pulled down to approximately 0.7V again, and then the positive linear regulators ramp up with the SS/SHDN pin voltage. The SS/
SHDN pin is eventually pulled up to the supply AVCC. The
soft-start time is controlled by the value of the capacitor
connected to the SS/SHDN pin.
Ri lim = 2000 /(IIim * Rdson)
Rilim should be between 10K and 100K.
An internal comparator with a reference from the level
set by the external resistor monitors the voltage drop
across the lower MOSFET. Once the Vdson of the MOSFET
exceeds this level, the low side gate is turned on and the
upper MOSFET is turned off in the next switching cycle.
Gate Drives
The low side gate driver is supplied from PVCC and provides a peak source/sink current of 1A. The high side
gate drive is also capable of sourcing and sinking peak
currents of 1A. The high side MOSFET gate drive can be
provided by an external 12V supply that is connected
from BST to GND. The actual gate to source voltage of
the upper MOSFET will approximately equal 7V (12V-VCC).
If the external 12V supply is not available, a classical
bootstrap technique can be implemented from the PVCC
supply. A bootstrap capacitor is connected from BST to
Phase while PVCC is connected through a diode (Schottky
or other fast low VF diode) to the BST. This will provide a
gate to source voltage approximately equal to the
VCC-Vdiode drop.
If the SS/SHDN pin is pulled down below 0.5V, the
SC2463 is disabled. If the SS/SHDN pin is pulled down
below 0.34V, the bias PNP transistor for SC2463 is disabled and the supply current is only 100uA.
The power-ok circuitry monitors the FB inputs of the
error amplifiers of the switchers. If the voltage on
these inputs goes above 0.55V or below 0.45V then
the POK pin is pulled low. The POK pin is held low until
the end of the start-up sequence.
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SC2463
POWER MANAGEMENT
Applications Information (Cont.)
Operating Frequency (f s )
Shoot through control circuitry provides a 30ns dead time
to ensure both the upper and lower MOSFET will not turn
on simultaneously and cause a shoot through condition.
The switching frequency in the SC2463 is userprogrammable. The advantages of using constant
frequency operation are simple passive component
selection and ease of feedback compensation. Before
setting the operating frequency, the following trade-offs
should be considered:
Error Amplifier and PWM Controller
In closed loop operation, the internal oscillator ramp
ranges from 0.75V to 3.8V. The error amplifier output
ranges determines duty-ratio of a converter. The synchronous continuous-conduction mode of operation allows
the SC2463 to regulate the output irrespective of the
direction of the load current.
1)
2)
3)
4)
5)
The SC2463 uses voltage-mode control for good noise
immunity and ease of compensation. The low-side
MOSFET of each channel is turned off at the falling-edge
of the phase timing clock. After a brief non-overlapping
time interval of 30ns, the high-side MOSFET is turned
on. The phase inductor current ramps up. When the internal ramp reaches the threshold determined by the
error amplifier output, the high-side MOSFET is turned
off. As long as phase voltage collapses below 1.5V, the
low-side MOSFET is turned on.
For a given output power, the sizes of the passive
components are inversely proportional to the switching
frequency, whereas MOSFET/Diode switching losses are
proportional to the operating frequency. Other issues
such as heat dissipation, packaging and the cost issues
are also to be considered. The frequency bands for
signal transmission should be avoided because of EM
interference.
Minimum Switc
h On Time Consideration
Switch
Buck Converter
In the SC2463, the falling edge of the clock turns on
the top MOSFET. The inductor current and the sensed
voltage ramp up. After the internal ramp voltage crosses
a threshold determined by the error amplifier output,
the top MOSFET is turned off. The propagation delay
time from the turn-on of the controlling FET to its turnoff is the minimum switch on time. The SC2463 has a
minimum on time of about 50ns at room temperature.
This is the shortest on interval of the controlling FET.
The controller either does not turn on the top MOSFET
at all or turns it on for at least 50ns.
Buck converter design includes the following specifications:
Input voltage range: Vin ∈ [ Vin,min , Vin,max ]
Input voltage ripple (peak-to-peak): ∆Vin
Output voltage: Vo
Output voltage accuracy: ε
Output voltage ripple (peak-to-peak): ∆Vo
Nominal output (load) current: Io
Maximum output current limit: Io,max
Output (load) current transient slew rate: dIo (A/s)
Circuit efficiency: η
For a synchronous step-down converter, the operating
duty cycle is VO/VIN. So the required on time for the top
MOSFET is VO/(VINfs). If the frequency is set such that
the required pulse width is less than 50ns, then the
converter will start skipping cycles. Due to minimum on
time limitation, simultaneously operating at very high
switching frequency and very short duty cycle is not
practical. If the voltage conversion ratio VO/V IN and
hence the required duty cycle is higher, the switching
frequency can be increased to reduce the size of passive
components.
Selection criteria and design procedures for the
following are described:
1) output inductor (L) type and value
2) output capacitor (Co) type and value
3) input capacitor (Cin) type and value
4) power MOSFETs
5) current sensing and limiting circuit
6) voltage sensing circuit
7) loop compensation network
2007 Semtech Corp.
Passive component size
Circuitry efficiency
EMI condition
Minimum switch on time and
Maximum duty ratio
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SC2463
POWER MANAGEMENT
Applications Information (Cont.)
c) Current rating: The saturation current of the inductor
should be at least 1.5 times of the peak inductor current
under all conditions.
There will not be enough modulation headroom if the on
time is simply made equal to the minimum on time of the
SC2463. For ease of control, we recommend the required
pulse width to be at least 1.5 times the minimum on
time.
Output Capacit
or (C o) and V out Ripple
Capacitor
The output capacitor provides output current filtering in
steady state and serves as a reservoir during load
transient. The output capacitor can be modeled as an
ideal capacitor in series with its parasitic ESR (Resr) and
ESL (Lesl) (Figure 1).
I nductor (L) and Ripple Current
Both step-down controllers in the SC2463 operate in
synchronous continuous-conduction mode (CCM)
regardless of the output load. The output inductor
selection/design is based on the output DC and transient
requirements. Both output current and voltage ripples
are reduced with larger inductors but it takes longer to
change the inductor current during load transients.
Conversely smaller inductors results in lower DC copper
losses but the AC core losses (flux swing) and the winding
AC resistance losses are higher. A compromise is to
choose the inductance such that peak-to-peak inductor
ripple-current is 20% to 30% of the rated output load
current.
Assuming that the inductor current ripple (peak-to-peak)
value is δ*Io, the inductance value will then be
L=
Co
Lesl
Resr
Figure 1. An equivalent circuit of Co
If the current through the branch is ib(t), the voltage
across the terminals will then be
Vo (1 − D)
.
δIo fs
t
v o ( t ) = Vo +
The peak current in the inductor becomes (1+δ/2)*Io
and the RMS current is
IL,rms = Io 1 +
di ( t )
1
ib ( t )dt + L esl b + R esr ib ( t ).
Co 0
dt
∫
This basic equation illustrates the effect of ESR, ESL
and Co on the output voltage.
δ2
.
12
The first term is the DC voltage across Co at time t=0.
The second term is the voltage variation caused by the
charge balance between the load and the converter
output. The third term is voltage ripple due to ESL and
the fourth term is the voltage ripple due to ESR. The
total output voltage ripple is then a vector sum of the
last three terms.
The followings are to be considered when choosing
inductors:
a) Inductor core material: For high efficiency applications
above 350KHz, ferrite, Kool-Mu and polypermalloy
materials should be used. Low-cost powdered iron cores
can be used for cost sensitive-applications below 350KHz
but with attendant higher core losses.
Since the inductor current is a triangular waveform
with peak-to-peak value δ*Io, the ripple-voltage caused
by inductor current ripples is
b) Select inductance value: Sometimes the calculated
inductance value is not available off-the-shelf. The
designer can choose the adjacent (larger) standard
inductance value. The inductance varies with
temperature and DC current. It is a good engineering
practice to re-evaluate the resultant current ripple at
the rated DC output current.
∆v C ≈
δIo
,
8C o fs
the ripple-voltage due to ESL is
∆v ESL = L esl fs
δIo
,
D
and the ESR ripple-voltage is
2007 Semtech Corp.
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SC2463
POWER MANAGEMENT
Applications Information (Cont.)
Remark 1: High frequency ceramic capacitors may not
carry most of the ripple current. It also depends on the
capacitor value. Only when the capacitor value is set
properly, the effect of ceramic capacitor low ESR starts
to be significant.
For example, if a 10µF, 4mΩ ceramic capacitor is
connected in parallel with 2x1500µF, 90mΩ electrolytic
capacitors, the ripple current in the ceramic capacitor is
only about 42% of the current in the electrolytic
capacitors at the ripple frequency. If a 100µF, 2mΩ
ceramic capacitor is used, the ripple current in the
ceramic capacitor will be about 4.2 times of that in the
electrolytic capacitors. When two 100µF, 2mΩ ceramic
capacitors are used, the current ratio increases to 8.3.
In this case most of the ripple current flows in the
ceramic decoupling capacitor. The ESR of the ceramic
capacitors will then determine the output ripple-voltage.
∆v ESR = R esr δIo .
Aluminum capacitors (e.g. electrolytic, solid OS-CON,
POSCAP, tantalum) have high capacitances and low
ESL’s. The ESR has the dominant effect on the output
ripple voltage. It is therefore very important to minimize
the ESR.
When determining the ESR value, both the steady state
ripple-voltage and the dynamic load transient need to be
considered. To keep the steady state output ripple-voltage
< ∆Vo, the ESR should satisfy
R esr1 <
∆Vo
.
δIo
To limit the dynamic output voltage overshoot/
undershoot within α (say 3%) of the steady state output
voltage) from no load to full load, the ESR value should
satisfy
R esr 2 <
Remark 2: The total equivalent capacitance of the filter
bank is not simply the sum of all the paralleled capacitors.
The total equivalent ESR is not simply the parallel
combination of all the individual ESR’s either. Instead
they should be calculated using the following formulae.
αVo
.
Io
Then, the required ESR value of the output capacitors
should be
Resr = min{Resr1,Resr2 }.
2
C eq (ω) :=
The voltage rating of aluminum capacitors should be at
least 1.5Vo. The RMS current ripple rating should also
be greater than
δIo
2 3
2
2
(R1a C1a + R1b C1b )ω2 C1a C1b + (C1a + C1b )
2
R eq (ω) :=
.
Usually it is necessary to have several capacitors of the
same type in parallel to satisfy the ESR requirement.
The voltage ripple cause by the capacitor charge/
discharge should be an order of magnitude smaller than
the voltage ripple caused by the ESR. To guarantee this,
the capacitance should satisfy
Co >
2
(R1a + R1b )2 ω2C1a C1b + (C1a + C1b )2
2
2
2
R1aR1b (R1a + R1b )ω2C1a C1b + (R1b C1b + R1a C1a )
2
2
(R1a + R1b )2 ω2 C1a C1b + (C1a + C1b )2
where R 1a and C 1a are the ESR and capacitance of
electrolytic capacitors, and R1b and C1b are the ESR and
capacitance of the ceramic capacitors respectively.
(Figure 2)
10
.
2πfsR esr
C1a
In many applications, several low ESR ceramic capacitors
are added in parallel with the aluminum capacitors in
order to further reduce ESR and improve high frequency
decoupling. Because the values of capacitance and ESR
are usually different in ceramic and aluminum capacitors,
the following remarks are made to clarify some practical
issues.
R1a
C1b
R1b
Ceq
Req
Figure 2. Equivalent RC branch.
Req and Ceq are both functions of frequency. For rigorous
2007 Semtech Corp.
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SC2463
POWER MANAGEMENT
Applications Information (Cont.)
It can be seen that the current in the input capacitor
pulses with high di/dt. Capacitors with low ESL should be
used. It is also important to place the input capacitor
close to the MOSFET’s on the PC board to reduce trace
inductances around the pulse current loop.
design, the equivalent ESR should be evaluated at the
ripple frequency for voltage ripple calculation when both
ceramic and electrolytic capacitors are used. If R1a = R1b
= R1 and C1a = C1b = C1, then Req and Ceq will be frequencyindependent and
The RMS value of the capacitor current is approximately
Req = 1/2 R1 and Ceq = 2C1.
ICin = Io D[(1 +
Input Capacitor (C in)
δ2
D
D
)(1 − )2 + 2 (1 − D) ].
η
12
η
The power dissipated in the input capacitors is then
The input supply to the converter usually comes from a
pre-regulator. Since the input supply is not ideal, input
capacitors are needed to filter the current pulses at the
switching frequency. A simple buck converter is shown in
Figure 3.
PCin = ICin2Resr.
For reliable operation, the maximum power dissipation
in the capacitors should not result in more than 10oC of
temperature rise. Many manufacturers specify the
maximum allowable ripple current (ARMS) rating of the
capacitor at a given ripple frequency and ambient
temperature. The input capacitance should be high
enough to handle the ripple current. For higher power
applications, multiple capacitors are placed in parallel to
increase the ripple current handling capability.
Sometimes meeting tight input voltage ripple
specifications may require the use of larger input
capacitance. At full load, the peak-to-peak input voltage
ripple due to the ESR is
Figure 3. A simple model for the converter input
δ
∆v ESR = R esr (1 + )Io .
2
In Figure 3 the DC input voltage source has an internal
impedance Rin and the input capacitor Cin has an ESR of
Resr. MOSFET and input capacitor current waveforms, ESR
voltage ripple and input voltage ripple are shown in Figure
4.
The peak-to-peak input voltage ripple due to the capacitor
is
∆v C ≈
DIo
,
Cin fs
From these two expressions, CIN can be found to meet
the input voltage ripple specification. In a multi-phase
converter, channel interleaving can be used to reduce
ripple. The two step-down channels of the SC2463
operate at 180 degrees from each other. If both stepdown channels in the SC2463 are connected in parallel,
both the input and the output RMS currents will be
reduced.
Ripple cancellation effect of interleaving allows the use
of smaller input capacitors. When converter outputs are
connected in parallel and interleaved, smaller inductors
and capacitors can be used for each channel. The total
output ripple-voltage remains unchanged. Smaller
inductors speeds up output load transient.
Figure 4. Typical waveforms at converter input
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SC2463
POWER MANAGEMENT
Applications Information (Cont.)
When two channels with a common input are interleaved,
the total DC input current is simply the sum of the
individual DC input currents. The combined input current
waveform depends on duty ratio and the output current
waveform. Assuming that the output current ripple is
small, the following formula can be used to estimate the
RMS value of the ripple current in the input capacitor.
Gate Charge (nC)
50
Let the duty ratio and output current of Channel 1 and
Channel 2 be D1, D2 and Io1, Io2, respectively.
Cg( 200 , Rds)
Cg( 500 , Rds)
20
1
0
0
5
15
20
1
Rds
On-resistance (mOhm)
10
20
FOM:100*10^{-12}
FOM:200*10^{-12}
FOM:500*10^{-12}
If D1<0.5 and D2<0.5, then
2
40
Cg( 100 , Rds)
Figure 5. Figure of Merit curves
2
ICin ≈ D1Io1 + D 2Io2 .
MOSFET selection also depends on applications. In many
applications, either switching loss or conduction loss
dominates for a particular MOSFET. For synchronous buck
converters with high input to output voltage ratios, the
top MOSFET is hard switched but conducts with very low
duty cycle. The bottom switch conducts at high duty cycle
but switches at near zero voltage. For such applications,
MOSFETs with low Cg are used for the top switch and
MOSFETs with low Rds(on) are used for the bottom switch.
If D1>0.5 and (D1-0.5) < D2<0.5, then
2
2
ICin ≈ 0.5Io1 + (D1 − 0.5)(Io1 + Io 2 )2 + (D 2 − D1 + 0.5)Io 2 .
If D1>0.5 and D2 < (D1-0.5) < 0.5, then
2
2
ICin ≈ 0.5Io1 + D 2 (Io1 + Io 2 )2 + (D1 − D 2 − 0.5)Io 2 .
If D1>0.5 and D2 > 0.5, then
2
MOSFET power dissipation consists of
a) conduction loss due to the channel resistance Rds(on),
b) switching loss due to the switch rise time tr and fall
time tf, and
c) the gate loss due to the gate resistance RG.
2
ICin ≈ (D1 + D 2 − 1)(Io1 + Io 2 )2 + (1 − D 2 )Io1 + (1 − D1 )Io2 .
Choosing P
o w er MOSFET
s
Po
MOSFETs
Top Switch:
The RMS value of the top switch current is calculated as
Main considerations in selecting the MOSFETs are power
dissipation, cost and packaging. Switching losses and
conduction losses of the MOSFETs are directly related to
the total gate charge (Cg) and channel on-resistance
(Rds(on)). In order to judge the performance of MOSFETs,
the product of the total gate charge and on-resistance is
used as a figure of merit (FOM). Transistors with the same
FOM follow the same curve in Figure 5.
IQ1,rms = Io D(1 +
δ2
12
).
The conduction losses are then
Ptc = IQ1,rms2 Rds(on).
Rds(on) varies with temperature and gate-source voltage.
Curves showing R ds(on) variations can be found in
manufacturers’ data sheet. From the Si4860
datasheet, Rds(on) is less than 8mW when Vgs is greater
than 10V. However R ds(on) increases by 50% as the
junction temperature increases from 25oC to 110oC.
The closer the curve is to the origin, the lower is the FOM.
This means lower switching loss or lower conduction loss
or both. It may be difficult to find MOSFETs with both low
Cg and low Rds(on. Usually a trade-off between Rds(on and
Cg has to be made.
The switching losses can be estimated using the simple
formula
2007 Semtech Corp.
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SC2463
POWER MANAGEMENT
Applications Information (Cont.)
in the MOSFET package. Here Qg is the total gate charge
specified in the datasheet. The power dissipated within
the MOSFET package is
Pts = 21 ( t r + t f )(1 + 2δ )Io Vin f s .
where tr is the rise time and tf is the fall time of the
switching process. Different manufactures have different
definitions and test conditions for t and t . To clarify
r
f
these, we sketch the typical MOSFET switching
characteristics under clamped inductive mode in Figure
6.
Ptg =
Rg
R gt
Q g Vcc fs .
The total power loss of the top switch is then
Pt = Ptc+Pts+Ptg.
If the input supply of the power converter varies
over a wide range, then it will be necessary to weigh
the relative importance of conduction and switching
losses. This is because conduction losses are inversely
proportional to the input voltage. Switching loss however increases with the input voltage. The total power
loss of MOSFET should be calculated and compared for
high-line and low-line cases. The worst case is then
used for thermal design.
Bottom Switch:
The RMS current in bottom switch can be shown to be
Figure 6. MOSFET switching characteristics
IQ 2,rms = Io (1 − D)(1 +
Where,
Qgs1 is the gate charge needed to bring the gate-to-source
voltage Vgs to the threshold voltage Vgs_th,
Qgs2 is the additional gate charge required for the switch
current to reach its full-scale value Ids and
.
Qgd is the charge needed to charge gate-to-drain (Miller)
capacitance when Vds is falling.
Switching losses occur during the time interval [t1, t3].
Defining tr = t3-t1 and tr can be approximated as
tr =
(Q gs 2 + Q gd )R gt
Vcc − Vgsp
Pbc=IQ2,rms2 Rds(on).
where Rds(on) is the channel resistance of bottom MOSFET.
If the input voltage to output voltage ratio is high (e.g.
Vin=12V, Vo=1.5V), the duty ratio D will be small. Since
the bottom switch conducts with duty ratio (1-D), the
corresponding conduction losses can be quite high.
Due to non-overlapping conduction between the top and
the bottom MOSFET’s, the internal body diode or the
external Schottky diode across the drain and source
terminals always conducts prior to the turn on of the
bottom MOSFET. The bottom MOSFET switches on with
only a diode voltage between its drain and source
terminals. The switching loss
.
Pbs = 21 ( t r + t f )(1 + 2δ )Io Vd fs
Rgt = Rgi+Rge+Rg.
is negligible due to near zero-voltage switching.
Vgsp is the Miller plateau voltage shown in Figure 11.
Similarly an approximate expression for tf is
The gate losses are estimated as
Pbg =
(Q gs 2 + Q gd )R gt
Vgsp
Rg
R gt
Q g Vcc fs .
The total bottom switch losses are then
.
Pb=Pbc+Pbs+Pbg.
Only a portion of the total losses Pg = QgVccfs is dissipated
2007 Semtech Corp.
).
The conduction losses are then
where Rgt is the total resistance from the driver supply
rail to the gate of the MOSFET. It includes the gate driver
internal impedance Rgi, external resistance Rge and the
gate resistance Rg within the MOSFET i.e.
tf =
δ2
12
16
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SC2463
POWER MANAGEMENT
Applications Information (Cont.)
Once the power losses Ploss for the top (Pt) and
bottom (Pb) MOSFET’s are known, thermal and package
design at component and system level should be done
to verify that the maximum die junction temperature
(Tj,max, usually 125oC) is not exceeded under the worstcase condition. The equivalent thermal impedance from
junction to ambient (θja) should satisfy
θ ja ≤
Tj,max − Ta,max
Ploss
.
0.6
0.9
1.2
1.5
1.8
2.5
3.3
(1- h)/h
0.2
0.8
1.4
2
2.6
4
5.6
Ro1 (Ohm) 200
806
1.4K
2K
2.61K 4.02K 5.62K
Ro2 (Ohm) 1K
1K
1K
1K
1K
Setting the Output V
olt
age
Volt
oltage
The non-inverting input of the channel-one error amplifier is internally tied the 0.5V voltage reference output. A
simple voltage divider (Ro1 at top and Ro2 at bottom) sets
the converter output voltage. The voltage feedback gain
h=0.5/Vo is related to the divider resistors value as
1K
Valley Current Sensing for Current-Limit
The valley current sensing for current limiting is a unique
scheme which could sense the voltage across the bottom switch MOSFET when it is on. The scheme is robust
with good noise immunity due to reference to ground.
h
Ro1.
1− h
The current sensing point is at a delay time tdv before
the beginning of a switching cycle. Therefore, the actual
valley current is
Once either R o1 or R o2 is chosen, the other can be
calculated for the desired output voltage Vo. Since the
number of standard resistance values is limited, the
calculated resistance may not be available as a standard
value resistor. As a result, there will be a set error in the
converter output voltage. This non-random error is
caused by the feedback voltage divider ratio. It cannot
be corrected by the feedback loop.
The following table lists a few standard resistor combinations for realizing some commonly used output
voltages.
IV = −
Vo
RDS (ON ) _ B + RL
(1 − e
−
t dv
τ2
) + I VS e
−
t dv
τ2
where, IVS is the preset valley current limiting threshold.
If a sensed current exceeds the threshold, the top switch
will keep off in the next cycle until the current goes back
below the threshold. In steady state, since the output
voltage is out of regulation in over current condition, the
control loop will try to make maximum duty cycle for the
top switch as it is on, which is usually greater than 80%.
Therefore, as the current falls back below the threshold, it is on in the next almost full cycle. The peak current is not controlled and only depends upon circuit parameters and operating condition in this cycle. The peak
current IP is
Only the voltages in boldface can be precisely set with
standard 1% resistors.
From this table, one may also observe that when the
value
1 − h Vo − 0 . 5
=
h
0 .5
T
IP =
2007 Semtech Corp.
1K
and its multiples fall into the standard resistor value
chart (1%, 5% or so), it is possible to use standard value
resistors to exactly set up the required output voltage
value.
The input bias current of the error amplifier also causes
an error in setting the output voltage. The maximum
inverting input bias currents of error amplifiers 1 or 2 is
200nA. Since the non-inverting input is biased to 0.5V,
the percentage error in the second output voltage will be
100%•(0.2uA) R •R /[0.5 • (R +R ) ].
01 o2
o1 o2
θ ja depends on the die to substrate bonding,
packaging material, the thermal contact surface, thermal
compound property, the available effective heat sink
area and the air flow condition (free or forced convection).
Actual temperature measurement of the prototype should
be carried out to verify the thermal design.
Ro 2 =
Vo (V)
17
T
−
−
Vin − Vo
(1 − e τ1 ) + I V e τ1
R DS (ON ) _ T + RL
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SC2463
POWER MANAGEMENT
Applications Information (Cont.)
L - Output inductance
C - Output capacitance
RC - Output capacitor ESR
VIN - Input voltage
Where, T is switching cycle period.
Because the inductor current ramps up according to Vin
–Vo, and down with Vo, a falling output voltage in over
current condition moves the inductor “ramp up” current up faster and the peak current IP larger but the
“ramp down” current slower. As long as the current is
still larger than the current limiting threshold, the top
switch is held off. The switching frequency is folded back
lower but average current is still relatively high.
The transfer function of the error amplifier with external
compensation network is as follows:
s
)(1 +
ω
ωZ1
GCOMP (s ) = I ⋅
s
s
(1 +
)(1 +
ωP1
(1 +
An example is shown in Typical Characteristics section
with input voltage 12V and output voltage 5V with output current 3.5A.
s
)
ωZ 2
s
)
ωP 2
referring to Fig. 7, where,
ω Z1 =
The preset valley current limit is 5A, which has to be
greater than full load current 3.5A. When the output is
shorted, the inductor peak current and the load current,
both are a function of the input voltage and the output
inductance, would be higher than the current limit. Therefore, proper thermal management and inductor saturation current rating have to be considered at the worst
conditions.
ωI =
1
1
, ωZ 2 =
R 2 C1
(R1 + R 3 )C 2
1
1
, ωP1 =
, ωP 2 =
R 1 ( C1 + C 3 )
R3C2
1
C1C 3
R2
C1 + C 3
C3
C2
Loop Compensation
R3
R2
C1
R1
SC2463 is a voltage mode buck controller with high gain
bandwidth error amplifier utilizing external network compensation to regulate output voltage.
+
Vref
For a DC/DC converter, it is usually required that the
converter has a loop gain of a high crossover frequency
for fast load response, high DC and low frequency gain
for low steady state error, and enough phase margin for
its operating stability. Often one can not have all these
properties at the same time. The purpose of the loop
compensation is to arrange the poles and zeros of the
compensation network to meet the requirements for a
specific application.
Figure 7. Voltage Mode Buck Converter Compensation
Network
With the compensation, the converter total loop gain is
as follows:
s
1+
1
s
s
1
⋅ ωI ⋅ VI 1 +
1+
RC ⋅ C 4
ωZ1
ωZ 2
VM
⋅
⋅
⋅
T(s) = GPWM ⋅ GCOMP (s) ⋅ G VD (s) =
L
s
s
s
⋅1+
1+
1 + s 1 + s 2L1C
ωP1
ωP 2
R
The power stage of a buck converter control-to-output
transfer function is as shown below:
G VD ( s ) = VIN
Where:
GPWM = PWM gain
VM = 3.0V, ramp peak to valley voltage of SC2463
1 + sR CC
L
1 + s + s 2LC
R
The design guidelines are as follows:
1. Set the loop gain crossover frequency ωC less than
1/5th the switching frequency.
2. Place an integrator in the origin to increase DC and
low frequency gains.
where,
ωO =
1
LC
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SC2463
POWER MANAGEMENT
Applications Information (Cont.)
The maximum voltage to drive an NPN transistor is AVCC
minus the voltage drop across the internal P-MOSFET
which is the product of On-Resistance and sourcing current. The maximum driving voltage with 5mA sourcing
current is minimum AVCC (4.5V) minus 5mA times maximum On-Resistance 140Ω, i.e. 3.8V.
3. Select ωZ1 and ωZ2 such that they are placed near ωO
to dampen peaking; the loop gain has –20dB rate
to go across the 0dB line for obtaining a wide bandwidth.
4. Cancel ωESR with compensation pole ωP1 (ωP1 = ωESR ).
5. Place a high frequency compensation pole ωP2 at the
half switching frequency to get the maximum attenuation of the switching ripple and the high frequency
noise with the adequate phase lag at ωC.
Layout Guidelines
In order to achieve optimal electrical, thermal and noise
performance for high frequency converters, attention
must be paid to the PCB layouts. The goal of layout optimization is to place components properly and identify
the high di/dt loops to minimize them. The following guidelines should be used to ensure proper functions of the
converters:
The compensated loop gain will be as given in Figure 8:
T (s)
ωz1
Lo op ga in T (s)
ωo
ωz2
G vd
-2 0d B /de c
ωc
0d B
1. A ground plane is recommended to minimize noises
and copper losses, and maximize heat dissipation.
2. Start the PCB layout by placing the power components first. Arrange the power circuit to achieve a
clean power flow route. Put all the connections on
one side of the PCB with wide copper filled areas if
possible.
3. The PVCC and AVCC bypass capacitors should be
placed next to the PVCC, AVCC and PGND, AGND pins
respectively.
4. Separate the power ground from the signal ground.
In SC2463, the power ground PGND should be tied
to the source terminal of lower MOSFETs. The signal
ground AGND should be tied to the negative terminal of the output capacitor.
5. The trace connecting the feedback resistors to the
output should be short, direct and far away from the
noise sources such as switching node and switching
components. Minimize the traces between DRXH/
DRXL and the gates of the MOSFETs to reduce their
impedance to drive the MOSFETs.
7. Minimize the loop including input capacitors, top/bottom MOSFETs. This loop passes high di/dt current.
Make sure the trace width is wide enough to reduce
copper losses in this loop.
8. Maximize the trace width of the loop connecting the
inductor, bottom MOSFET and the output capacitors.
9. Connect the ground of the feedback divider and the
compensation components directly to the GND pin
of the SC2463 by using a separate ground trace.
Then connect this pin to the ground of the output
capacitor as close as possible.
ωp 1
ωp 2
P o w e r sta ge
G V D (s)
ωE S R
-4 0d B /de c
Figure 8. Asymptotic diagram of buck power stage and
its compensated loop gain
Dual Positive LDOs Controller
The SC2463 provides two positive adjustable linear regulator controllers. The first positive linear regulator uses a
PNP transistor to regulate output voltage. This is set by
a voltage divider connected from the output to FB to
AGND. Referring to the front page Application Circuit,
select R10 in the 5KΩ to 20KΩ range. Calculate R9 with
the following equation:
V
R 9 = R10 OUT − 1
0.5
The second positive linear regulator uses a NPN transistor to regulate output voltage. This is set by a voltage
divider connected from the output to FB to AGND. Referring to the front page Application Circuit, select R18
in the 5KΩ to 20KΩ range. Calculate R14 with the
following equation:
V
R14 = R18 OUT − 1
0
.
5
2007 Semtech Corp.
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GND
2.5V/1A
+3.3V/2A
10uF
C22
C17
100uF
R11
20K
1K
R8
C12 Open
GND
1.2V/0.5A
100uF
C23
R17
1K
R13
4.99K
TP7
R51
10K
C31
2.2nF
R1
10K
Q7
FZT649
C52 100pF
Q4
FZT749
C13
10uF
GND
SS/SD
SYNC
POK
R24
10K
R20
14K
100pF
C53
0
R15
C18 Open
C21
Open
TP10
f s=250KHz
R3 30K
C8 0.1uF
10
11
5
4
8
7
9
6
C6
1uF
GND
FB3
BD3
FB4
BD4
POK
SYNC
OSC
SS/SD
15
R2
10
C50
1uF
10uF
C5
SC2463
PVCC
PGND
16
AVCC
AGND
22
Q1
FZT749
R22
51K
14
20
21
28
BDI
ILIM2
R50
20K
27
VIN
EO1
FB1
GD1L
PH1
GD1H
BST1
EO2
FB2
GD2L
PH2
GD2H
TP13
3
2
23
24
25
26
12
13
20
19
18
17
R9 20K
0
R6
TP3
5.6nF
C14
TP6
C9
0.1uF
C25
4.7nF
680pF
C24
0
R14
R21
20K
C15 390pF
C16
0.1uF R12 2
2
R4
TP1
D2
SL04
C2
10uF/16V
D1
SL04
C1
10uF/16V
C32
22uF
BST2
R52
0
R23
51K
ILIM1
2007 Semtech Corp.
1
12V
TP11
TP8
L1 10uH
TP14
TP12
Q6
SUD50N03-10CP
R19
2.0K
R16
18K
TP9
R10
2.05K
R5
11.5K
TP4
C28
Open
TP16
C27
Open
TP15
C4
10uF/16V
Q5
SUD50N03-10CP L2 10uH
Q3
SUD50N03-10CP
TP5
Q2
SUD50N03-10CP
C3
10uF/16V
C33
Open
R18
150
C19
3.3nF
R7
180
C10
6.8nF
C20
470uF/6.3V
C11
680uF/4V
+3.3V/2A
C29
Open
22uF
C51
22uF
C30
GND
5V/2A
GND
3.3V/2A
SC2463
POWER MANAGEMENT
Evaluation Board Schematic
www.semtech.com
SC2463
POWER MANAGEMENT
Bill of Materia l - Evaluation Board
Item
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Quantity
4
1
2
1
2
1
1
8
2
2
1
1
1
1
1
1
3
1
1
2
2
2
4
1
4
1
1
2
1
3
1
2
3
1
1
1
1
1
1
2
1
2007 Semtech Corp.
Reference
C1, C2, C3, C4
C5
C6, C50
C8
C9, C16
C10
C11
C12,C18,C21,C52
C27,C28,C29,C33
C13,C22
C17,C23
C14
C15
C19
C20
C24
C25
C30,C32, C51
C31
C53
D1, D2
L1,L2
Q1,Q4
Q2,Q3,Q5,Q6
Q7
R1,R13,R24,R51
R2
R3
R4,R12
R5
R6,R14,R15
R7
R8,R17
R9,R21,R50
R10
R11
R16
R18
R19
R20
R22,R23
U1
Value
10uF/16V
10uF
1uF
0.1uF
0.1uF
6.8nF
680uF/4V
Manufacturer
TDK
Part #
C3216X5R1C106MT
Sanyo
4TPB680M
TDK
TDK
C3216X5R1C106MT
C4532X5R0J107MT
Sanyo
6TPB470M
Vishay
Coilcraft
Zetex
Vishay
Zetex
SL04
DO5022P-103
FZT749TA
SUD50N03-10CP
FZT649
Semtech Corp.
SC2463
Open
10uF
100uF
5.6nF
390pF
3.3nF
470uF/6.3V
680pF
4.7nF
22uF
2.2nF
100pF
SL04
10uH
10K
10
30K
2
11.5K
0
180
1K
20K
2.05K
40.2K
18K
150
2.0K
14K
51K
21
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SC2463
POWER MANAGEMENT
Typical Characteristics
ST
ARTUP SEQUENCE(1)
STARTUP
ST
ARTUP SEQUENCE(2)
STARTUP
20MS/DIV
A: SS/SHDN PIN VOLTAGE, 5V/DIV
B: CH1 OUTPUT VOLTAGE, 5V/DIV
C: CH2 OUTPUT VOLTAGE, 5V/DIV
D: CH3 OUTPUT VOLTAGE, 2V/DIV
10MS/DIV
A: CH1 OUTPUT VOLTAGE, 5V/DIV
B: CH2 OUTPUT VOLTAGE, 2V/DIV
C: CH3 OUTPUT VOLTAGE, 1V/DIV
D: CH4 OUTPUT VOLTAGE, 2V/DIV
STEAD
Y ST
ATE OPERA
TION
STEADY
STA
OPERATION
SWITCHER1 LOAD TRANSIENT
500NS/DIV
A: CH1 OUTPUT VOLTAGE, 10V/DIV
B: CH2 OUTPUT VOLTAGE, 10V/DIV
200US/DIV
A: CH1 LOAD CURRENT, 0.25A/US, 0.5A/DIV
C: CH2 OUTPUT VOLTAGE, 50MV/DIV
LDO CH3 LOAD TRANSIENT
OVERCURRENT PROTECTION
200US/DIV
A: CH1 LOAD CURRENT, 0.25A/US, 0.5A/DIV
C: CH3 OUTPUT VOLTAGE, 20MV/DIV
10US/DIV
A: CH1 PH1 VOLTAGE, 10V/DIV
B: CH1 INDUCTOR CURRENT, 2A/DIV
2007 Semtech Corp.
22
www.semtech.com
SC2463
POWER MANAGEMENT
Outline Drawing - TSSOP-28
A
DIM
D
e
N
A
A1
A2
b
c
D
E1
E
e
L
L1
N
01
aaa
bbb
ccc
2X E/2
E1
E
PIN 1
INDICATOR
ccc C
2X N/2 TIPS
1 23
e/2
B
aaa C
SEATING
PLANE
D
DIMENSIONS
MILLIMETERS
INCHES
MIN NOM MAX MIN NOM MAX
.047
.006
.002
.042
.031
.007
.012
.003
.007
.378 .382 .386
.169 .173 .177
.252 BSC
.026 BSC
.018 .024 .030
(.039)
28
8°
0°
.004
.004
.008
1.20
0.15
0.05
1.05
0.80
0.19
0.30
0.20
0.09
9.60 9.70 9.80
4.30 4.40 4.50
6.40 BSC
0.65 BSC
0.45 0.60 0.75
(1.0)
28
0°
8°
0.10
0.10
0.20
A2 A
C
bxN
bbb
H
A1
C A-B D
c
GAGE
PLANE
0.25
SEE DETAIL
SIDE VIEW
L
(L1)
A
DETAIL
01
A
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
3.
DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4.
REFERENCE JEDEC STD MO-153, VARIATION AE.
Land Pattern - TSSOP-28
X
DIM
(C)
G
C
G
P
X
Y
Z
Z
Y
DIMENSIONS
INCHES
MILLIMETERS
(.222)
.161
.026
.016
.061
.283
(5.65)
4.10
0.65
0.40
1.55
7.20
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
2007 Semtech Corp.
23
www.semtech.com