R1LV1616R Series 16Mb Advanced LPSRAM (1M wordx16bit / 2M wordx8bit) REJ03C0101-0400Z Rev.4.00 2007.09.12 Description The R1LV1616R Series is a family of low voltage 16-Mbit static RAMs organized as 1048576-words by 16-bit, fabricated by Renesas's high-performance 0.15um CMOS and TFT technologies. The R1LV1616R Series is suitable for memory applications where a simple interfacing , battery operating and battery backup are the important design objectives. The R1LV1616R Series is packaged in a 52pin micro thin small outline mount device[µTSOP / 10.79mm x 10.49mm with the pin-pitch of 0.4mm], a 48pin thin small outline mount device[TSOP / 12mm x 20mm with the pinpitch of 0.5mm] or a 48balls fine pitch ball grid array [f-BGA / 7.5mmx8.5mm with the ball-pitch of 0.75mm and 6x8 array] . It gives the best solution for a compaction of mounting area as well as flexibility of wiring pattern of printed circuit boards. Features • Single 2.7-3.6V power supply • Small stand-by current:2µA (3.0V, typ.) • Data retention supply voltage =2.0V • No clocks, No refresh • All inputs and outputs are TTL compatible • Easy memory expansion by CS1#, CS2, LB# and UB# • Common Data I/O • Three-state outputs: OR-tie capability • OE# prevents data contention on the I/O bus • Process technology: 0.15um CMOS REJ03C0101-0400Z Rev.4.00 2007.09.12 page 1 of 15 R1LV1616R Series Ordering Information Type No. Access time Package R1LV1616RSD-5S% 55 ns (Note0) R1LV1616RSD-7S% 70 ns R1LV1616RSD-8S% 85 ns R1LV1616RBG-5S% 55 ns (Note0) R1LV1616RBG-7S% 70 ns R1LV1616RBG-8S% 85 ns R1LV1616RSA-5S% 55 ns (Note0) R1LV1616RSA-7S% 70 ns R1LV1616RSA-8S% 85 ns 350-mil 52-pin plastic µ - TSOP(II) (normal-bend type) (52PTG) 7.5mmx8.5mm f-BGA 0.75mm pitch 48ball 12mm x 20mm plastic TSOP(I) (normal-bend type) (48P3R) Note0. 55ns parts can be supported under the condition of the input timing limitation toward SRAM on customer’s system. Please contact our sales office in your region, in case of the inquiry for 55ns parts. % - Temperature version; see table below % Temperature Range R 0 ~ +70 ºC I -40 ~ +85 ºC REJ03C0101-0400Z Rev.4.00 2007.09.12 page 2 of 15 R1LV1616R Series Pin Arrangement 52-pin µTSOP 48-pin fBGA A15 1 52 A16 A14 2 51 BYTE# A13 3 50 UB# A12 4 49 A11 5 48 Vss LB# A10 6 47 DQ15/A-1 A9 7 46 DQ7 A8 8 45 DQ14 A19 9 44 DQ6 CS1# 10 43 DQ13 WE# 11 42 DQ5 NC 12 41 DQ12 NC 13 40 DQ4 Vcc 14 39 NC CS2 15 38 DQ11 NC 16 37 DQ3 NC 17 36 DQ10 A18 18 35 DQ2 A17 19 34 A7 20 33 DQ9 DQ1 A6 21 32 DQ8 A5 22 31 DQ0 A4 23 30 OE# A3 24 29 A2 25 28 Vss NC 26 27 A0 A1 1 2 3 4 5 6 A LB# OE# A0 A1 A2 CS2 B DQ15 UB# A3 A4 CS1# DQ0 C DQ13 DQ14 A5 A6 DQ1 DQ2 D Vss DQ12 A17 A7 DQ3 Vcc E Vcc DQ11 Vss or NC A16 DQ4 Vss F DQ10 DQ9 A14 A15 DQ6 DQ5 G DQ8 A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 N.C. 48-pin TSOP A15 1 A14 2 A13 3 A12 4 A11 5 A10 6 A9 7 A8 8 A19 9 NC 10 WE# 11 CS2 12 NC 13 UB# 14 LB# 15 A18 16 A17 17 A7 18 A6 19 A5 20 A4 21 A3 22 A2 23 A1 24 REJ03C0101-0400Z Rev.4.00 2007.09.12 page 3 of 15 48 A16 47 BYTE# 46 Vss 45 DQ15/A-1 44 DQ7 43 DQ14 42 DQ6 41 DQ13 40 DQ5 39 DQ12 38 DQ4 37 Vcc 36 DQ11 35 DQ3 34 DQ10 33 DQ2 32 DQ9 31 DQ1 30 DQ8 29 DQ0 28 OE# 27 26 Vss CS1# 25 A0 R1LV1616R Series Pin Description Pin name Function A0 to A19 Address input DQ 0 to DQ15 Data input/output CS1# &CS2 Chip select WE# Write enable OE# Output enable LB# Lower byte select UB# Upper byte select Vcc Power supply Vss Ground BYTE# Byte (x8 mode) enable input NC Non connection LB# UB# x8/x16 SWITCHING CIRCUIT BYTE# WE# OE# Note. BYTE# pin supported by only TSOP and uTSOP types. REJ03C0101-0400Z Rev.4.00 2007.09.12 page 4 of 15 OUTPUT BUFFER OUTPUT BUFFER SENSE Amp. DATA SELECTOR DQ8 DATA INPUT BUFFER CS1# DQ7 DATA INPUT BUFFER CLOCK GENERATOR DQ0 DATA SELECTOR CS2 1048576 Words x 16BITS OR 2097152 Words x 8BITS SENSE Amp. A19 Memory Array DECODER A0 ADDRESS BUFFER Block Diagram DQ15 / A-1 Vcc Vss R1LV1616R Series Operating Table CS1# CS2 BYTE# LB# UB# WE# OE# DQ0-7 DQ8-14 DQ15 Operation H X X X X X X High-Z High-Z High-Z Stand by X L X X X X X High-Z High-Z High-Z Stand by X X H H H X X High-Z High-Z High-Z Stand by L H H L H L X Din High-Z High-Z Write in lower byte L H H L H H L Dout High-Z High-Z Read from lower byte L H X X X H H High-Z High-Z High-Z Output disable L H H H L L X High-Z Din Din Write in upper byte L H H H L H L High-Z Dout Dout Read from upper byte L H H L L L X Din Din Din Write L H H L L H L Dout Dout Dout Read L H L L L L X Din High-Z A-1 Write L H L L L H L Dout High-Z A-1 Read Note 1. H:VIH L:VIL X: VIH or VIL 2. BYTE# pin supported by only TSOP and uTSOP types. When apply BYTE# =“L” , please assign LB#=UB#=“L”. Absolute Maximum Ratings Parameter Symbol Value Unit Power supply voltage relative to Vss Vcc -0.5 to +4.6 V Terminal voltage on any pin relation toVss VT -0.5*1 to Vcc+0.3*2 V Power dissipation PT 0.7 W Operation temperature Storage temperature Tstg Storage temperature range under bias Tbias Note 1. -2.0V in case of AC (Pulse width ≤ 30ns) 2. Maximum voltage is +4.6V REJ03C0101-0400Z Rev.4.00 2007.09.12 page 5 of 15 R ver. 0 to +70 ºC I ver. -40 to +85 ºC Topr -65 to +150 ºC R ver. 0 to +70 ºC I ver. -40 to +85 ºC R1LV1616R Series Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Unit Vcc 2.7 3.0 3.6 V Vss 0 0 0 V Input high voltage VIH 2.4 - Vcc+0.2 V Input low voltage VIL -0.2 - 0.4 V 1 0 - +70 ºC 2 -40 - +85 ºC 2 Supply voltage Ambient temperature range R ver. I ver. Ta Note Note 1. –2.0V in case of AC (Pulse width ≤ 30ns) 2. Ambient temperature range depends on R/I-version. Please see table on page 2. DC Characteristics Test conditions*2 Symbol Min. Typ.*1 Max. Unit Input leakage current |ILI| - - 1 µA Vin=Vss to Vcc Output leakage current |ILo| - - 1 µA CS1# =VIH or CS2=VIL or OE# = VIH or WE# =VIL or LB# =UB# =VIH,VI/O=Vss to Vcc Icc1 - 25 40 mA Min. cycle, duty =100% I I/O = 0 mA, CS1# =VIL, CS2=VIH Others = VIH / VIL Parameter Average operating current Standby current Standby current Icc2 - 2 5 mA Cycle time = 1 µs, I I/O = 0 mA, CS1#≤ 0.2V, CS2 ≥ VCC-0.2V VIH ≥ VCC-0.2V , VIL ≤ 0.2V, duty=100% ISB - 0.1 0.3 mA CS2=VIL - 2 6 µA ~+25ºC - 4 12 µA ~+40ºC - - 25 µA ~+70ºC - - 40 µA ~+85ºC ISB1 V in ≥ 0V (1) 0V≤CS2≤0.2V or (2) CS2≥Vcc-0.2V, CS1# ≥Vcc-0.2V or (3)LB# =UB# ≥Vcc-0.2V, CS2≥Vcc-0.2V, CS1# ≤0.2V Average value Output hige voltage VOH 2.4 - - V IOH = -1mA Output Low voltage VOL - - 0.4 V IOL = 2mA Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested. 2. BYTE# pin supported by only TSOP and uTSOP types. BYTE# ≥ Vcc-0.2V or BYTE# ≤ 0.2V REJ03C0101-0400Z Rev.4.00 2007.09.12 page 6 of 15 R1LV1616R Series Capacitance (Ta = +25ºC, f =1MHz) Parameter Symbol Min. Typ. Max. Unit Test conditions Note Input capacitance C in - - 10 pF V in = 0V 1 Input / output capacitance C I/O - - 10 pF V I/O = 0V 1 Note 1:This parameter is sampled and not 100% tested. AC Characteristics Test Conditions (Vcc=2.7~3.6V, Ta = 0~+70ºC / -40~+85ºC *) • Input pulse levels: VIL= 0.4V,VIH=2.4V • Input rise and fall time : 5ns • Input and output timing reference levels : 1.4V • Output load : See figures (Including scope and jig) 1.4V RL=500Ω DQ CL=30pF Note: Temperature range depends on R/I-version. Please see table on page 2. REJ03C0101-0400Z Rev.4.00 2007.09.12 page 7 of 15 R1LV1616R Series Read Cycle Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change LB#,UB# access time Chip select to output in low-Z LB#,UB# enable to low-Z Output enable to output in low-Z Chip deselect to output in high-Z LB#,UB# disable to high-Z Output disable to output in high-Z Symbol R1LV1616R**5S (Note0) R1LV1616R**7S R1LV1616R**8S Unit Notes Min. Max. Min. Max. Min. Max. tRC tAA 55 - 70 - 85 - ns - 70 - 70 - 85 ns tACS1 tACS2 tOE tOH tBA tCLZ tBLZ tOLZ tCHZ1 tCHZ2 tBHZ tOHZ - 55 - 70 - 85 ns - 55 - 70 - 85 ns - 35 - 35 - 45 ns 10 - 10 - 10 - ns - 55 - 70 - 85 ns 10 - 10 - 10 - ns 2,3 5 - 5 - 5 - ns 2,3 5 - 5 - 5 - ns 2,3 0 20 0 25 0 30 ns 1,2,3 0 20 0 25 0 30 ns 1,2,3 0 20 0 25 0 30 ns 1,2,3 0 20 0 25 0 30 ns 1,2,3 REJ03C0101-0400Z Rev.4.00 2007.09.12 page 8 of 15 R1LV1616R Series Write Cycle Parameter Write cycle time Address valid to end of write Chip selection to end of write Write pulse width LB#,UB# valid to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Output active from end of write Output disable to output in high-Z Write to output in high-Z Symbol tWC tAW tCW tWP tBW tAS tWR tDW tDH tOW tOHZ tWHZ R1LV1616R**5S (Note0) R1LV1616R**7S R1LV1616R**8S Unit Notes Min. Max. Min. Max. Min. Max. 55 - 70 - 85 - ns 50 - 65 - 70 - ns 55 - 65 - 70 - ns 5 40 - 55 - 60 - ns 4 50 - 65 - 70 - ns 0 - 0 - 0 - ns 6 0 - 0 - 0 - ns 7 25 - 35 - 40 - ns 0 - 0 - 0 - ns 5 - 5 - 5 - ns 2 0 20 0 25 0 30 ns 1,2 0 20 0 25 0 30 ns 1,2 Note0. 55ns parts can be supported under the condition of the input timing limitation toward SRAM on customer’s system. Please contact our sales office in your region, in case of the inquiry for 55ns parts. In case of tAA =70ns, tRC =70ns. 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. AT any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and form device to device. 4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going low or UB# going low . A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1# going low or CS2 going high to end of write. 6. tAS is measured the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle. REJ03C0101-0400Z Rev.4.00 2007.09.12 page 9 of 15 R1LV1616R Series Byte enable (supported by only 48-pin TSOP and 52-pin µTSOP ) Parameter Byte setup time Byte recovery time Symbol tBS tBR R1LV1616R**-5S Max. Min. R1LV1616R**-7S Min. Max. R1LV1616R**-8S Min. Max. Unit 5 - 5 - 5 - ms 5 - 5 - 5 - ms BYTE# Timing Waveform CS2 CS1# tBS BYTE# REJ03C0101-0400Z Rev.4.00 2007.09.12 page 10 of 15 tBR Notes R1LV1616R Series Timing Waveform Read Cycle tRC A 0~19 (Word Mode) A -1~19 (Byte Mode) Valid address tAA tBA tOH LB#,UB# tBHZ tACS1 CS1# tCHZ1 tACS2 CS2 tCHZ2 tOE OE# WE# = "H" level DQ0~15 (Word Mode) DQ0~7 (Byte Mode) REJ03C0101-0400Z Rev.4.00 2007.09.12 page 11 of 15 tOLZ tCLZ tBLZ tOHZ Valid data R1LV1616R Series Write Cycle (1) (WE# Clock) tWC A 0~19 (Word Mode) Valid address A -1~19 (Byte Mode) tBW LB#,UB# tCW CS1# tCW CS2 tAW tAS tWR tWP tWHZ WE# tOW tDW DQ0~15 (Word Mode) DQ0~7 (Byte Mode) REJ03C0101-0400Z Rev.4.00 2007.09.12 page 12 of 15 tDH Valid data R1LV1616R Series Write Cycle (2) (CS1# ,CS2 Clock, OE#=VIH) tWC A 0~19 (Word Mode) Valid address A -1~19 (Byte Mode) tBW LB#,UB# CS1# tAS CS2 WE# DQ0~15 tCW tWR tCW tWP tDW tDH (Word Mode) DQ0~7 (Byte Mode) REJ03C0101-0400Z Rev.4.00 2007.09.12 page 13 of 15 Valid data R1LV1616R Series Write Cycle (3) ( LB#,UB# Clock, OE#=VIH) tWC A 0~19 (Word Mode) Valid address A -1~19 (Byte Mode) tAS tBW tWR LB#,UB# CS1# tCW tCW CS2 WE# DQ0~15 tWP tDW tDH (Word Mode) DQ0~7 (Byte Mode) REJ03C0101-0400Z Rev.4.00 2007.09.12 page 14 of 15 Valid data R1LV1616R Series Data Retention Characteristics Parameter Symbol VDR Vcc for data retention MIn. Typ.*1 Max. Test conditions*2,3 Unit 2.0 - 3.6 V - 2 6 µA V in ≥ 0V (1) 0V ≤ CS2 ≤ 0.2V or (2) CS2 ≥ Vcc-0.2V, CS1# ≥ Vcc-0.2V or (3) LB# =UB# ≥ Vcc-0.2V, CS2 ≥ Vcc-0.2V, CS1# ≤ 0.2V ~+25ºC Vcc=3.0V,Vin≥0V - 4 12 µA ~+40ºC - - 25 µA ~+70ºC - - 40 µA ~+85ºC 0 - - ns 5 - - ms IccDR Data retention current Chip deselect to data retention time Operation recovery time tCDR tR (1) 0V ≤ CS2 ≤ 0.2V or (2) CS2 ≥ Vcc-0.2V, CS1# ≥ Vcc-0.2V or (3) LB# =UB# ≥Vcc-0.2V, CS2 ≥ Vcc-0.2V, CS1# ≤ 0.2V Average value See retention waveform Note 1. Typical parameter of IccDR indicates the value for the center of distribution at Vcc=3.0V and not 100% tested. 2. BYTE# pin supported only by TSOP and uTSOP types. BYTE# ≥ Vcc-0.2V or BYTE# ≤ 0.2V 3. Also CS2 controls address buffer, WE# buffer ,CS1# buffer ,OE# buffer ,LB# ,UB# buffer and Din buffer .If CS2 controls data retention mode,Vin levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ Vcc-0.2V or 0V ≤ CS2 ≤ 0.2V. The other input levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high impedance state. Data Retention timing Waveform (1) (LB#,UB# Controlled) Vcc tCDR 2.70V tR 2.4V 2.4V LB# =UB# ≥ Vcc-0.2V LB# UB# Data Retention timing Waveform (2) (CS1# Controlled) Vcc tCDR 2.70V tR 2.4V 2.4V CS1# ≥ Vcc-0.2V CS1# Data Retention timing Waveform (3) (CS2 Controlled) Vcc tCDR CS2 2.70V 0.2V 0.2V 0V ≤ CS2 ≤ 0.2V REJ03C0101-0400Z Rev.4.00 2007.09.12 page 15 of 15 tR Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. 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