HM62V16100I Series Wide Temperature Range Version 16 M SRAM (1-Mword × 16-bit) REJ03C0060-0200Z Rev. 2.00 Oct.06.2003 Description The HM62V16100I Series is 16-Mbit static RAM organized 1-Mword × 16-bit. HM62V16100I Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It has the package variations of 48-bump chip size package with 0.75 mm bump pitch and 48-pin plastic TSOPI for high density surface mounting. Features • Single 3.0 V supply: 2.7 V to 3.6 V • Fast access time: 45/55 ns (max) • Power dissipation: Active: 9 mW/MHz (typ) Standby: 1.5 µW (typ) • Completely static memory. No clock or timing strobe required • Equal access and cycle times • Common data input and output. Three state output • Battery backup operation. 2 chip selection for battery backup • Temperature range: −40 to +85°C Rev.2.00, Oct.06.2003, page 1 of 23 HM62V16100I Series Ordering Information Type No. Access time Package HM62V16100LTI-4 45 ns 48-pin plastic TSOPI (normal-bend type) (TFP-48DA) HM62V16100LTI-4SL 45 ns HM62V16100LTI-5SL 55 ns HM62V16100LBPI-4 45 ns HM62V16100LBPI-4SL 45 ns HM62V16100LBPI-5SL 55 ns Rev.2.00, Oct.06.2003, page 2 of 23 48-bump CSP with 0.75 mm bump pitch (TBP-48F) HM62V16100I Series Pin Arrangement 48-pin TSOP A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE CS2 NU UB LB A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 (Top view) Rev.2.00, Oct.06.2003, page 3 of 23 A16 BYTE VSS I/O15/A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE VSS CS1 A0 HM62V16100I Series Pin Description (TSOP) Pin name Function A0 to A19 Address input (word mode) A-1 to A19 Address input (byte mode) I/O0 to I/O15 Data input/output CS1 Chip select 1 CS2 Chip select 2 WE Write enable OE Output enable LB Lower byte select UB Upper byte select BYTE Byte enable VCC Power supply VSS Ground NC No connection 1 NU* Not used (test mode pin) Note: 1. This pin should be connected to a ground (VSS), or not be connected (open). Rev.2.00, Oct.06.2003, page 4 of 23 HM62V16100I Series 48-bumps CSP 1 2 3 4 5 6 A LB OE A0 A1 A2 CS2 B I/O8 UB A3 A4 CS1 I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D VSS I/O11 A17 A7 I/O3 VCC E VCC I/O12 VSS A16 I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 A19 A12 A13 WE I/O7 H A18 A8 A9 A10 A11 NU (Top view) Pin Description (CSP) Pin name Function A0 to A19 Address input I/O0 to I/O15 Data input/output CS1 Chip select 1 CS2 Chip select 2 WE Write enable OE Output enable LB Lower byte select UB Upper byte select VCC Power supply VSS Ground 1 NU* Not used (test mode pin) Note: 1. This pin should be connected to a ground (VSS), or not be connected (open). Rev.2.00, Oct.06.2003, page 5 of 23 HM62V16100I Series Block Diagram (TSOP) LSB A15 A14 V CC A13 V SS A12 A11 A10 A9 A8 Memory matrix 8,192 x 128 x 16 • • • • • Row decoder A18 8,192 x 256 x 8 A16 A19 A4 MSB A5 I/O0 Column I/O • • Input data control Column decoder I/O15 MSBA17 A7A6 A3 A2 A1A0 A-1 LSB • • BYTE CS2 CS1 LB UB WE OE Rev.2.00, Oct.06.2003, page 6 of 23 Control logic • • HM62V16100I Series Block Diagram (CSP) LSB A19 A8 A9 A10 A11 A12 A13 A14 A16 A18 A15 A3 MSB A6 V CC V SS • • • • • Row decoder I/O0 Memory matrix 8,192 x 128 x 16 Column I/O • • Input data control Column decoder I/O15 MSB A17 A7 A5 A4 A2 A1 A0 LSB • • CS2 CS1 LB UB WE OE Rev.2.00, Oct.06.2003, page 7 of 23 Control logic • • HM62V16100I Series Operation Table (TSOP) Byte mode CS1 CS2 WE OE UB LB BYTE I/O0 to I/O7 I/O8 to I/O14 I/O15 Operation H × × × × × L High-Z High-Z High-Z Standby × L × × × × L High-Z High-Z High-Z Standby L H H L × × L Dout High-Z A-1 Read L H L × × × L Din High-Z A-1 Write L H H H × × L High-Z High-Z High-Z Output disable Note: H: VIH, L: VIL, ×: VIH or VIL Word mode CS1 CS2 WE OE UB LB BYTE I/O0 to I/O7 I/O8 to I/O14 I/O15 Operation H × × × × × H High-Z High-Z High-Z Standby × L × × × × H High-Z High-Z High-Z Standby × × × × H H H High-Z High-Z High-Z Standby L H H L L L H Dout Dout Dout Read L H H L H L H Dout High-Z High-Z Lower byte read L H H L L H H High-Z Dout Dout Upper byte read L H L × L L H Din Din Din Write L H L × H L H Din High-Z High-Z Lower byte write L H L × L H H High-Z Din Din Upper byte write L H H H × × H High-Z High-Z High-Z Output disable Note: H: VIH, L: VIL, ×: VIH or VIL Rev.2.00, Oct.06.2003, page 8 of 23 HM62V16100I Series Operation Table (CSP) CS1 CS2 WE OE UB LB I/O0 to I/O7 I/O8 to I/O15 Operation H × × × × × High-Z High-Z Standby × L × × × × High-Z High-Z Standby × × × × H H High-Z High-Z Standby L H H L L L Dout Dout Read L H H L H L Dout High-Z Lower byte read L H H L L H High-Z Dout Upper byte read L H L × L L Din Din Write L H L × H L Din High-Z Lower byte write L H L × L H High-Z Din Upper byte write L H H H × × High-Z High-Z Output disable Note: H: VIH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Symbol Value Unit Power supply voltage relative to VSS VCC −0.5 to +4.6 Terminal voltage on any pin relative to VSS VT −0.5* to VCC + 0.3* Power dissipation PT 1.0 W Storage temperature range Tstg −55 to +125 °C Storage temperature range under bias Tbias −40 to +85 °C 1 V 2 V Notes: 1. VT min: −2.0 V for pulse half-width ≤ 10 ns. 2. Maximum voltage is +4.6 V. DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage VCC 2.7 3.0 3.6 V VSS 0 0 0 V Input high voltage VIH 2.2 VCC + 0.3 V Input low voltage VIL −0.3 0.6 V Ambient temperature range Ta −40 +85 °C Note: 1. VIL min: −2.0 V for pulse half-width ≤ 10 ns. Rev.2.00, Oct.06.2003, page 9 of 23 Note 1 HM62V16100I Series DC Characteristics Parameter Symbol Min Typ* 1 Max Unit Test conditions* 2 Input leakage current |ILI| 1 µA Vin = VSS to VCC Output leakage current |ILO| 1 µA CS1 = VIH or CS2 = VIL or OE = VIH or WE = VIL or LB = UB = VIH, VI/O = VSS to VCC Operating current ICC 20 mA CS1 = VIL, CS2 = VIH, Others = VIH/ VIL, II/O = 0 mA Average operating current ICC1 (READ) 22 35 mA Min. cycle, duty = 100%, II/O = 0 mA, CS1 = VIL, CS2 = VIH, WE = VIH, Others = VIH/VIL ICC1 30 50 mA Min. cycle, duty = 100%, II/O = 0 mA, CS1 = VIL, CS2 = VIH, Others = VIH/VIL 3 8 mA Cycle time = 70 ns, duty = 100%, II/O = 0 mA, CS1 = VIL, CS2 = VIH, WE = VIH, Others = VIH/VIL Address increment scan or decrement scan ICC2 20 30 mA Cycle time = 70 ns, duty = 100%, II/O = 0 mA, CS1 = VIL, CS2 = VIH, Others = VIH/VIL Address increment scan or decrement scan ICC3 3 8 mA Cycle time = 1 µs, duty = 100%, II/O = 0 mA, CS1 ≤ 0.2 V, CS2 ≥ VCC − 0.2 V VIH ≥ VCC − 0.2 V, VIL ≤ 0.2 V 5 ICC2* (READ) *5 Standby current Standby current Output high voltage Output low voltage 0.1 0.5 mA CS2 = VIL ISB1* 3 0.5 25 µA 0 V ≤ Vin (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS1 ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V or (3) LB = UB ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V, CS1 ≤ 0.2 V Average value ISB1* 4 0.5 8 µA VOH 2.4 V IOH = −1 mA VOH VCC − 0.2 V IOH = −100 µA VOL 0.4 V IOL = 2 mA VOL 0.2 V IOL = 100 µA ISB Rev.2.00, Oct.06.2003, page 10 of 23 HM62V16100I Series Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and not guaranteed. 2. BYTE pin supported by only TSOP type. BYTE ≥ VCC − 0.2 V or BYTE ≤ 0.2 V 3. This characteristic is guaranteed only for L-version. 4. This characteristic is guaranteed only for L-SL version. 5. ICC2 is the value measured while the valid address is increasing or decreasing by one bit. Word mode: LSB (least significant bit) is A0. Byte mode: LSB (least significant bit) is A-1. Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Symbol Min Typ Max Unit Test conditions Note Input capacitance Cin 8 pF Vin = 0 V 1 Input/output capacitance CI/O 10 pF VI/O = 0 V 1 Note: 1. This parameter is sampled and not 100% tested. Rev.2.00, Oct.06.2003, page 11 of 23 HM62V16100I Series AC Characteristics (Ta = −40 to +85°C, VCC = 2.7 V to 3.6 V, unless otherwise noted.) Test Conditions • Input pulse levels: VIL = 0.4 V, VIH = 2.4 V • Input rise and fall time: 5 ns • Input and output timing reference levels: 1.4 V • Output load: See figures (Including scope and jig) 1.4 V RL=500 Ω Dout 50pF Rev.2.00, Oct.06.2003, page 12 of 23 HM62V16100I Series Read Cycle HM62V16100I -4 -5 Parameter Symbol Min Max Min Max Unit Read cycle time tRC 45 55 ns Address access time tAA 45 55 ns Chip select access time tACS1 45 55 ns tACS2 45 55 ns Notes Output enable to output valid tOE 30 35 ns Output hold from address change tOH 10 10 ns LB, UB access time tBA 45 55 ns Chip select to output in low-Z tCLZ1 10 10 ns 2, 3 tCLZ2 10 10 ns 2, 3 LB, UB enable to low-Z tBLZ 5 5 ns 2, 3 Output enable to output in low-Z tOLZ 5 5 ns 2, 3 Chip deselect to output in high-Z tCHZ1 0 20 0 20 ns 1, 2, 3 tCHZ2 0 20 0 20 ns 1, 2, 3 LB, UB disable to high-Z tBHZ 0 15 0 20 ns 1, 2, 3 Output disable to output in high-Z tOHZ 0 15 0 20 ns 1, 2, 3 Notes Write Cycle HM62V16100I -4 -5 Parameter Symbol Min Max Min Max Unit Write cycle time tWC 45 55 ns Address valid to end of write tAW 45 50 ns Chip selection to end of write tCW 45 50 ns 5 Write pulse width tWP 35 40 ns 4 LB, UB valid to end of write tBW 45 50 ns Address setup time tAS 0 0 ns 6 Write recovery time tWR 0 0 ns 7 Data to write time overlap tDW 25 25 ns Data hold from write time tDH 0 0 ns Output active from end of write tOW 5 5 ns 2 Output disable to output in high-Z tOHZ 0 15 0 20 ns 1, 2 Write to output in high-Z tWHZ 0 15 0 20 ns 1, 2 Rev.2.00, Oct.06.2003, page 13 of 23 HM62V16100I Series Byte Control HM62V16100I -4 Parameter -5 Symbol Min Max Min Max Unit Notes BYTE setup time tBS 5 5 ms 8 BYTE recovery time tBR 5 5 ms 8 Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap of a low CS1, a high CS2, a low WE and a low LB or a low UB. A write begins at the latest transition among CS1 going low, CS2 going high, WE going low and LB going low or UB going low. A write ends at the earliest transition among CS1 going high, CS2 going low, WE going high and LB going high or UB going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1 going low or CS2 going high to the end of write. 6. tAS is measured from the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write cycle. 8. Byte control supported by only TSOP type. Rev.2.00, Oct.06.2003, page 14 of 23 HM62V16100I Series Timing Waveform Read Cycle* 1 t RC Address*2 Valid address tAA tACS1 CS1 tCLZ1 CS2 tCHZ1 tACS2 tCLZ2 tCHZ2 tBHZ tBA LB, UB tBLZ tOHZ tOE OE tOLZ Dout*3 High impedance Notes: 1. Only for TSOP type. BYTE > VCC – 0.2 V or BYTE < 0.2 V 2. Word mode: A0 to A19 Byte mode: A-1 to A19 3. Word mode: I/O0 to I/O15 Byte mode: I/O0 to I/O7 Rev.2.00, Oct.06.2003, page 15 of 23 tOH Valid data HM62V16100I Series 1 Write Cycle (1)* (WE Clock) tWC Valid address Address*2 tWR tCW CS1 tCW CS2 tBW LB, UB tAW tWP WE tAS tDW tDH Valid data Din*3 tWHZ tOW High impedance Dout*3 Notes: 1. Only for TSOP type. BYTE > VCC – 0.2 V or BYTE < 0.2 V 2. Word mode: A0 to A19 Byte mode: A-1 to A19 3. Word mode: I/O0 to I/O15 Byte mode: I/O0 to I/O7 Rev.2.00, Oct.06.2003, page 16 of 23 HM62V16100I Series Write Cycle (2)* (CS1, CS2 Clock, OE = VIH) 1 tWC Valid address Address*2 tAW tAS tCW tAS tCW tWR CS1 CS2 tBW LB, UB tWP WE tDW Din*3 Dout*3 Notes: 1. Only for TSOP type. BYTE > VCC – 0.2 V or BYTE < 0.2 V 2. Word mode: A0 to A19 Byte mode: A-1 to A19 3. Word mode: I/O0 to I/O15 Byte mode: I/O0 to I/O7 Rev.2.00, Oct.06.2003, page 17 of 23 Valid data High impedance tDH HM62V16100I Series Write Cycle (3)* (LB, UB Clock, OE = VIH) 1 tWC Valid address Address tAW tCW tWR CS1 tCW CS2 tAS tBW UB (LB) tBW LB (UB) tWP WE tDW Din-UB (Din-LB) Din-LB (Din-UB) Dout Note: 1. Only for TSOP type. BYTE > V CC – 0.2 V Rev.2.00, Oct.06.2003, page 18 of 23 tDH Valid data tDW Valid data High impedance tDH HM62V16100I Series Byte Control (TSOP) CS2 CS1 tBS BYTE Rev.2.00, Oct.06.2003, page 19 of 23 tBR HM62V16100I Series Low VCC Data Retention Characteristics (Ta = −40 to +85°C) Parameter Symbol Min Typ* VCC for data retention VDR 1.5 Data retention current ICCDR* 1 2 5 3, 4 Max Unit Test conditions* 3.6 V Vin ≥ 0 V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ VCC − 0.2 V, CS1 ≥ VCC − 0.2 V or (3) LB = UB ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V, CS1 ≤ 0.2 V 0.5 25 µA VCC = 3.0 V, Vin ≥ 0 V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ VCC − 0.2 V, CS1 ≥ VCC − 0.2 V or (3) LB = UB ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V, CS1 ≤ 0.2 V Average value ICCDR* 0.5 8 µA Chip deselect to data retention time tCDR 0 ns Operation recovery time tR 5 ms See retention waveforms Notes: 1. This characteristic is guaranteed only for L-version. 2. This characteristic is guaranteed only for L-SL version. 3. BYTE pin supported by only TSOP type. BYTE ≥ VCC − 0.2 V or BYTE ≤ 0.2 V 4. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, LB, UB buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE, OE, CS1, LB, UB, I/O) can be in the high impedance state. If CS1 controls data retention mode, CS2 must be CS2 ≥ VCC − 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The other input levels (address, WE, OE, LB, UB, I/O) can be in the high impedance state. 5. Typical values are at VCC = 3.0 V, Ta = +25°C and not guaranteed. Rev.2.00, Oct.06.2003, page 20 of 23 HM62V16100I Series Low VCC Data Retention Timing Waveform (1) (CS1 Controlled) t CDR Data retention mode tR V CC 2.7 V 2.2 V V DR CS1 CS1 ≥ VCC – 0.2 V 0V Low VCC Data Retention Timing Waveform (2) (CS2 Controlled) t CDR Data retention mode tR V CC 2.7 V CS2 V DR 0.6 V 0 V < CS2 < 0.2 V 0V Low VCC Data Retention Timing Waveform (3) (LB, UB Controlled) t CDR Data retention mode V CC 2.7 V 2.2 V V DR LB, UB 0V Rev.2.00, Oct.06.2003, page 21 of 23 LB, UB ≥ VCC – 0.2 V tR HM62V16100I Series Package Dimensions HM62V16100LTI Series (TFP-48DA) 12.00 12.40 Max Unit: mm 25 18.40 48 As of January, 2003 24 1.20 Max *0.22 ± 0.08 0.08 M 0.20 ± 0.06 0.45 Max 0.10 *Dimension including the plating thickness Base material dimension Rev.2.00, Oct.06.2003, page 22 of 23 0.80 20.00 ± 0.20 0˚ – 8˚ 0.05 ± 0.05 0.50 *0.17 ± 0.05 0.125 ± 0.04 1 0.50 ± 0.10 Package Code JEDEC JEITA Mass (reference value) TFP-48DA Conforms Conforms 0.52 g HM62V16100I Series HM62V16100LBPI Series (TBP-48F) As of January, 2003 8.00 0.20 S A 2.125 0.20 S B Unit: mm A INDEX MARK A 6 5 4 3 2 1 Pin#1 INDEX A B 9.50 C D E F 0.75 G 4× 0.75 0.15 0.2 S 2.125 48 × φ0.35 ± 0.05 φ0.08 M S A B 1.2 Max 0.25 ± 0.05 S 0.10 S H Details of the part A Package Code JEDEC JEITA Mass (reference value) Rev.2.00, Oct.06.2003, page 23 of 23 TBP-48F – – 0.15 g B Revision History Rev. Date HM62V16100I Series Data Sheet Contents of Modification Page Description Sep. 21, 2001 Initial issue 1.00 Jun.19, 2003 Deletion of Preliminary 2.00 Oct.06, 2003 Deletion of HM62V16100LTI-5, HM62V16100LBPI-5 0.0 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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