RENESAS R5F212BCSNLG

To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1.
2.
3.
4.
5.
6.
7.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights
of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.
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of Renesas Electronics or others.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by
you or third parties arising from the use of these circuits, software, or information.
When exporting the products or technology described in this document, you should comply with the applicable export control
laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas
Electronics products or the technology described in this document for any purpose relating to military applications or use by
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under any applicable domestic or foreign laws or regulations.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and
“Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as
indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular
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application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written
consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise
expressly specified in a Renesas Electronics data sheets or data books, etc.
“Standard”:
8.
9.
10.
11.
12.
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support.
“Specific”:
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or
systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a
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control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because
the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system
manufactured by you.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental
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(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
R8C/2A Group, R8C/2B Group
RENESAS MCU
1.
REJ03B0182-0210
Rev.2.10
Nov 26, 2007
Overview
1.1
Features
The R8C/2A Group and R8C/2B Group of single-chip MCUs incorporates the R8C/Tiny Series CPU core,
employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable
of executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation
processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs also
use an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
Furthermore, the R8C/2B Group has on-chip data flash (1 KB × 2 blocks).
The difference between the R8C/2A Group and R8C/2B Group is only the presence or absence of data flash. Their
peripheral functions are the same.
1.1.1
Applications
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 1 of 60
R8C/2A Group, R8C/2B Group
1.1.2
1. Overview
Specifications
Tables 1.1 and 1.2 outlines the Specifications for R8C/2A Group and Tables 1.3 and 1.4 outlines the
Specifications for R8C/2B Group.
Table 1.1
Item
CPU
Specifications for R8C/2A Group (1)
Function
Central processing
unit
Memory
Power Supply
Voltage
Detection
I/O Ports
ROM, RAM
Voltage detection
circuit
Clock
Clock generation
circuits
Programmable I/O
ports
Interrupts
Watchdog Timer
Timer
Timer RA
Timer RB
Timer RC
Timer RD
Timer RE
Timer RF
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Specification
R8C/Tiny series core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to Table 1.5 Product List for R8C/2A Group.
• Power-on reset
• Voltage detection 2
• Input-only: 2 pins
• CMOS I/O ports: 55, selectable pull-up resistor
• High current drive ports: 8
3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),
On-chip oscillator (high-speed, low-speed)
(high-speed on-chip oscillator has a frequency adjustment function),
XCIN clock oscillation circuit (32 kHz)
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, low-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode
Real-time clock (timer RE)
• External: 5 sources, Internal: 23 sources, Software: 4 sources
• Priority levels: 7 levels
15 bits × 1 (with prescaler), reset start selectable
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait oneshot generation mode
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
16 bits × 2 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 6 pins), reset synchronous PWM mode (output three-phase
waveforms (6 pins), sawtooth wave modulation), complementary PWM mode
(output three-phase waveforms (6 pins), triangular wave modulation), PWM3
mode (PWM output 2 pins with fixed period)
8 bits × 1
Real-time clock mode (count seconds, minutes, hours, days of week), output
compare mode
16 bits × 1 (with capture/compare register pin and compare register pin)
Input capture mode, output compare mode
Page 2 of 60
R8C/2A Group, R8C/2B Group
Table 1.2
1. Overview
Specifications for R8C/2A Group (2)
Item
Function
Serial
UART0, UART1,
Interface
UART2
Clock Synchronous Serial I/O with
Chip Select (SSU)
I2C bus(1)
LIN Module
A/D Converter
D/A Converter
Flash Memory
Operating Frequency/Supply
Voltage
Current consumption
Operating Ambient Temperature
Package
Specification
Clock synchronous serial I/O/UART × 3
1 (shared with I2C-bus)
1 (shared with SSU)
Hardware LIN: 1 (timer RA, UART0)
10-bit resolution × 12 channels, includes sample and hold function
8-bit resolution × 2 circuits
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 100 times
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V)
f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V)
f(XIN) = 5 MHz (VCC = 2.2 to 5.5 V)
12 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
5.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
2.1 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))
0.65 µA (VCC = 3.0 V, stop mode)
-20 to 85°C (N version)
-40 to 85°C (D version)(2)
-20 to 105°C (Y version)(3)
64-pin LQFP
• Package code: PLQP0064KB-A (previous code: 64P6Q-A)
• Package code: PLQP0064GA-A (previous code: 64P6U-A)
64-pin FLGA
• Package code: PTLG0064JA-A (previous code: 64F0G)
NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D version if D version functions are to be used.
3. Please contact Renesas Technology sales offices for the Y version.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 3 of 60
R8C/2A Group, R8C/2B Group
Table 1.3
Item
CPU
1. Overview
Specifications for R8C/2B Group (1)
Function
Central processing
unit
Memory
Power Supply
Voltage
Detection
I/O Ports
ROM, RAM
Voltage detection
circuit
Clock
Clock generation
circuits
Programmable I/O
ports
Interrupts
Watchdog Timer
Timer
Timer RA
Timer RB
Timer RC
Timer RD
Timer RE
Timer RF
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Specification
R8C/Tiny series core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to Table 1.6 Product List for R8C/2B Group.
• Power-on reset
• Voltage detection 2
• Input-only: 2 pins
• CMOS I/O ports: 55, selectable pull-up resistor
• High current drive ports: 8
3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),
On-chip oscillator (high-speed, low-speed)
(high-speed on-chip oscillator has a frequency adjustment function),
XCIN clock oscillation circuit (32 kHz)
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, low-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode
Real-time clock (timer RE)
• External: 5 sources, Internal: 23 sources, Software: 4 sources
• Priority levels: 7 levels
15 bits × 1 (with prescaler), reset start selectable
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait oneshot generation mode
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
16 bits × 2 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 6 pins), reset synchronous PWM mode (output three-phase
waveforms (6 pins), sawtooth wave modulation), complementary PWM mode
(output three-phase waveforms (6 pins), triangular wave modulation), PWM3
mode (PWM output 2 pins with fixed period)
8 bits × 1
Real-time clock mode (count seconds, minutes, hours, days of week), output
compare mode
16 bits × 1 (with capture/compare register pin and compare register pin)
Input capture mode, output compare mode
Page 4 of 60
R8C/2A Group, R8C/2B Group
Table 1.4
1. Overview
Specifications for R8C/2B Group (2)
Item
Function
Serial
UART0, UART1,
Interface
UART2
Clock Synchronous Serial I/O with
Chip Select (SSU)
I2C bus(1)
LIN Module
A/D Converter
D/A Converter
Flash Memory
Operating Frequency/Supply
Voltage
Current consumption
Operating Ambient Temperature
Package
Specification
Clock synchronous serial I/O/UART × 3
1 (shared with I2C-bus)
1 (shared with SSU)
Hardware LIN: 1 (timer RA, UART0)
10-bit resolution × 12 channels, includes sample and hold function
8-bit resolution × 2 circuits
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V)
f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V)
f(XIN) = 5 MHz (VCC = 2.2 to 5.5 V)
12 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
5.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
2.1 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))
0.65 µA (VCC = 3.0 V, stop mode)
-20 to 85°C (N version)
-40 to 85°C (D version)(2)
-20 to 105°C (Y version)(3)
64-pin LQFP
• Package code: PLQP0064KB-A (previous code: 64P6Q-A)
• Package code: PLQP0064GA-A (previous code: 64P6U-A)
64-pin FLGA
• Package code: PTLG0064JA-A (previous code: 64F0G)
NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D version if D version functions are to be used.
3. Please contact Renesas Technology sales offices for the Y version.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 5 of 60
R8C/2A Group, R8C/2B Group
1.2
1. Overview
Product List
Table 1.5 lists Product List for R8C/2A Group, Figure 1.1 shows a Part Number, Memory Size, and Package of
R8C/2A Group, Table 1.6 lists Product List for R8C/2B Group, and Figure 1.2 shows a Part Number, Memory Size,
and Package of R8C/2B Group.
Table 1.5
Product List for R8C/2A Group
Part No.
R5F212A7SNFP
R5F212A7SNFA
R5F212A7SNLG
R5F212A8SNFP
R5F212A8SNFA
R5F212A8SNLG
R5F212AASNFP
R5F212AASNFA
R5F212AASNLG
R5F212ACSNFP
R5F212ACSNFA
R5F212ACSNLG
R5F212A7SDFP
R5F212A7SDFA
R5F212A8SDFP
R5F212A8SDFA
R5F212AASDFP
R5F212AASDFA
R5F212ACSDFP
R5F212ACSDFA
R5F212A7SNXXXFP
R5F212A7SNXXXFA
R5F212A7SNXXXLG
R5F212A8SNXXXFP
R5F212A8SNXXXFA
R5F212A8SNXXXLG
R5F212AASNXXXFP
R5F212AASNXXXFA
R5F212AASNXXXLG
R5F212ACSNXXXFP
R5F212ACSNXXXFA
R5F212ACSNXXXLG
R5F212A7SDXXXFP
R5F212A7SDXXXFA
R5F212A8SDXXXFP
R5F212A8SDXXXFA
R5F212AASDXXXFP
R5F212AASDXXXFA
R5F212ACSDXXXFP
R5F212ACSDXXXFA
ROM Capacity
48 Kbytes
48 Kbytes
48 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
96 Kbytes
128 Kbytes
128 Kbytes
128 Kbytes
48 Kbytes
48 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
128 Kbytes
128 Kbytes
48 Kbytes
48 Kbytes
48 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
96 Kbytes
128 Kbytes
128 Kbytes
128 Kbytes
48 Kbytes
48 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
128 Kbytes
128 Kbytes
RAM Capacity
2.5 Kbytes
2.5 Kbytes
2.5 Kbytes
3 Kbytes
3 Kbytes
3 Kbytes
7 Kbytes
7 Kbytes
7 Kbytes
7.5 Kbytes
7.5 Kbytes
7.5 Kbytes
2.5 Kbytes
2.5 Kbytes
3 Kbytes
3 Kbytes
7 Kbytes
7 Kbytes
7.5 Kbytes
7.5 Kbytes
2.5 Kbytes
2.5 Kbytes
2.5 Kbytes
3 Kbytes
3 Kbytes
3 Kbytes
7 Kbytes
7 Kbytes
7 Kbytes
7.5 Kbytes
7.5 Kbytes
7.5 Kbytes
2.5 Kbytes
2.5 Kbytes
3 Kbytes
3 Kbytes
7 Kbytes
7 Kbytes
7.5 Kbytes
7.5 Kbytes
NOTE:
1. The user ROM is programmed before shipment.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 6 of 60
Current of Nov. 2007
Package Type
PLQP0064KB-A
PLQP0064GA-A
PTLG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PLTG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PLTG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PLTG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PTLG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PLTG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PLTG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PLTG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
Remarks
N version
D version
N version
D version
Factory
programming
product(1)
R8C/2A Group, R8C/2B Group
Part No.
1. Overview
R 5 F 21 2A 7 S N XXX FP
Package type:
FP: PLQP0064KB-A (0.5 mm pin-pitch, 10 mm square body)
FA: PLQP0064GA-A (0.8 mm pin-pitch, 14 mm square body)
LG: PTLG0064JA-A (0.65 mm pin-pitch, 6 mm square body)
ROM number
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
Y: Operating ambient temperature -20°C to 105°C (1)
S: Low-voltage version
ROM capacity
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/2A Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
NOTE:
1: Please contact Renesas Technology sales offices for the Y version.
Figure 1.1
Part Number, Memory Size, and Package of R8C/2A Group
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 7 of 60
R8C/2A Group, R8C/2B Group
Table 1.6
1. Overview
Product List for R8C/2B Group
Part No.
R5F212B7SNFP
R5F212B7SNFA
R5F212B7SNLG
R5F212B8SNFP
R5F212B8SNFA
R5F212B8SNLG
R5F212BASNFP
R5F212BASNFA
R5F212BASNLG
R5F212BCSNFP
R5F212BCSNFA
R5F212BCSNLG
R5F212B7SDFP
R5F212B7SDFA
R5F212B8SDFP
R5F212B8SDFA
R5F212BASDFP
R5F212BASDFA
R5F212BCSDFP
R5F212BCSDFA
R5F212B7SNXXXFP
R5F212B7SNXXXFA
R5F212B7SNXXXLG
R5F212B8SNXXXFP
R5F212B8SNXXXFA
R5F212B8SNXXXLG
R5F212BASNXXXFP
R5F212BASNXXXFA
R5F212BASNXXXLG
R5F212BCSNXXXFP
R5F212BCSNXXXFA
R5F212BCSNXXXLG
R5F212B7SDXXXFP
R5F212B7SDXXXFA
R5F212B8SDXXXFP
R5F212B8SDXXXFA
R5F212BASDXXXFP
R5F212BASDXXXFA
R5F212BCSDXXXFP
R5F212BCSDXXXFA
ROM Capacity
Program ROM Data flash
48 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
96 Kbytes
1 Kbyte × 2
96 Kbytes
1 Kbyte × 2
96 Kbytes
1 Kbyte × 2
128 Kbytes
1 Kbyte × 2
128 Kbytes
1 Kbyte × 2
128 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
96 Kbytes
1 Kbyte × 2
96 Kbytes
1 Kbyte × 2
128 Kbytes
1 Kbyte × 2
128 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
96 Kbytes
1 Kbyte × 2
96 Kbytes
1 Kbyte × 2
96 Kbytes
1 Kbyte × 2
128 Kbytes
1 Kbyte × 2
128 Kbytes
1 Kbyte × 2
128 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
96 Kbytes
1 Kbyte × 2
96 Kbytes
1 Kbyte × 2
128 Kbytes
1 Kbyte × 2
128 Kbytes
1 Kbyte × 2
NOTE:
1. The user ROM is programmed before shipment.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 8 of 60
Current of Nov. 2007
RAM
Capacity
Package Type
2.5 Kbytes
2.5 Kbytes
2.5 Kbytes
3 Kbytes
3 Kbytes
3 Kbytes
7 Kbytes
7 Kbytes
7 Kbytes
7.5 Kbytes
7.5 Kbytes
7.5 Kbytes
2.5 Kbytes
2.5 Kbytes
3 Kbytes
3 Kbytes
7 Kbytes
7 Kbytes
7.5 Kbytes
7.5 Kbytes
2.5 Kbytes
2.5 Kbytes
2.5 Kbytes
3 Kbytes
3 Kbytes
3 Kbytes
7 Kbytes
7 Kbytes
7 Kbytes
7.5 Kbytes
7.5 Kbytes
7.5 Kbytes
2.5 Kbytes
2.5 Kbytes
3 Kbytes
3 Kbytes
7 Kbytes
7 Kbytes
7.5 Kbytes
7.5 Kbytes
PLQP0064KB-A
PLQP0064GA-A
PTLG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PTLG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PTLG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PTLG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PTLG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PTLG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PTLG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PTLG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
Remarks
N version
D version
N version
D version
Factory
programming
product(1)
R8C/2A Group, R8C/2B Group
Part No.
1. Overview
R 5 F 21 2B 7 S N XXX FP
Package type:
FP: PLQP0064KB-A (0.5 mm pin-pitch, 10 mm square body)
FA: PLQP0064GA-A (0.8 mm pin-pitch, 14 mm square body)
LG: PTLG0064JA-A (0.65 mm pin-pitch, 6 mm square body)
ROM number
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
Y: Operating ambient temperature -20°C to 105°C (1)
S: Low-voltage version
ROM capacity
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/2B Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
NOTE:
1: Please contact Renesas Technology sales offices for the Y version.
Figure 1.2
Part Number, Memory Size, and Package of R8C/2B Group
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 9 of 60
R8C/2A Group, R8C/2B Group
1.3
1. Overview
Block Diagram
Figure 1.3 shows a Block Diagram.
I/O ports
8
8
8
8
Port P0
Port P1
Port P2
Port P3
3
2
5
Port P4
Port P5
LIN module
Watchdog timer
(15 bits)
A/D converter
(10 bits × 12 channels)
D/A converter
(8 bits × 2)
R8C/Tiny Series CPU core
R0H
R1H
R0L
R1L
R2
R3
SB
ROM(1)
USP
ISP
INTB
A0
A1
FB
Memory
RAM(2)
PC
FLG
Multiplier
NOTES:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
Figure 1.3
Block Diagram
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 10 of 60
7
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
I2C bus or SSU
(8 bits × 1)
Port P8
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RD (16 bits × 2)
Timer RE (8 bits × 1)
Timer RF (16 bits × 1)
System clock
generation circuit
8
UART or
clock synchronous serial I/O
(8 bits × 3)
Timers
Port P6
Peripheral functions
R8C/2A Group, R8C/2B Group
1.4
1. Overview
Pin Assignment
P8_1/TRFO01
P8_0/TRFO00
P6_0/TREO
P4_5/INT0
P6_6/INT2/TXD1
P6_7/INT3/RXD1
P6_5/(CLK1)/CLK2 (2)
P6_4/RXD2
P6_3/TXD2
P3_1/TRBO
P3_0/TRAO
P3_6/(INT1)(2)
P3_2/(INT2)(2)
P1_3/Kl3/AN11
P1_2/Kl2/AN10
P1_1/Kl1/AN9
Figure 1.4 shows 64-pin LQFP Package Pin Assignment (Top View). Figure 1.5 shows 64-pin FLGA Package Pin
Assignment (Top Perspective View). Tables 1.7 and 1.8 outlines the Pin Name Information by Pin Number.
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
32
50
31
51
30
52
29
53
28
54
27
55
26
R8C/2A Group
R8C/2B Group
56
57
25
24
23
58
59
22
PLQP0064KB-A(64P6Q-A)
PLQP0064GA-A(64P6U-A)
(top view)
60
61
62
21
20
19
7
8
9
10 11 12 13 14 15 16
P4_4/XCOUT
RESET
P4_7/XOUT (1)
VSS/AVSS
P4_6/XIN
VCC/AVCC
P8_2/TRFO02
P8_3/TRFO10/TRFI
P8_4/TRFO11
P8_5/TRFO12
P8_6
P1_4/TXD0
P1_5/RXD0/(TRAIO)/(INT1)(2)
P1_6/CLK0
P1_7/TRAIO/INT1
P2_0/TRDIOA0/TRDCLK
P2_1/TRDIOB0
P2_2/TRDIOC0
P2_3/TRDIOD0
P2_4/TRDIOA1
P2_5/TRDIOB1
P2_6/TRDIOC1
P2_7/TRDIOD1
6
P5_0/TRCCLK
5
P5_1/TRCIOA/TRCTRG
4
P5_2/TRCIOB
3
P5_3/TRCIOC
2
P5_4/TRCIOD
1
P4_3/XCIN
17
MODE
18
64
P3_3/SSI
63
P3_4/SDA/SCS
P1_0/Kl0/AN8
P0_0/AN7
P0_1/AN6
P0_2/AN5
P0_3/AN4
P0_4/AN3
P6_2
P6_1
P0_5/AN2/CLK1
P0_6/AN1/DA0
VSS/AVSS
P0_7/AN0/DA1
VREF
VCC/AVCC
P3_7/SSO
P3_5/SCL/SSCK
NOTES:
1. P4_7/XOUT are an input-only port.
2. Can be assigned to the pin in parentheses by a program.
3. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.4
64-pin LQFP Package Pin Assignment (Top View)
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 11 of 60
R8C/2A Group, R8C/2B Group
A
8
7
6
5
2
B
C
D
E
F
G
H
P3_3/SSI
P0_1/AN6
P5_0/
TRCCLK
P0_6/AN1/ P6_0/TREO
DA0
P3_4/SDA/
SCS
P0_0/AN7
P5_2/
TRCIOB
P0_7/AN0/
DA1
VREF
P3_0/TRAO P6_5/CLK2/
(CLK1)(2)
P5_3/
TRCIOC
MODE
P3_7/SSO
P0_4/AN3
P6_1
P0_5/AN2/
CLK1
P3_6/
(INT1)(2)
P3_1/TRBO
P4_3/XCIN
P3_5/SCL/
SSCK
P6_2
P3_2/
(INT2)(2)
P6_3/TXD2
P1_3/KI3/
AN11
VCC/AVCC
P4_7/
XOUT(1)
RESET P8_3/
P6_4/RXD2
TRFO10/TRFI
P1_2/KI2/
AN10
P4_4/XCOUT P2_5/
TRDIOB1
4
3
1. Overview
P5_4/
TRCIOD
VSS/AVSS
VCC/AVCC
VSS/AVSS
P5_1/TRCIOA/ P4_6/XIN
TRCTRG
1
P2_7/
TRDIOD1
A
B
P2_3/
P1_7/TRAIO/ P1_6/CLK0
TRDIOD0 INT
C
D
P0_2/AN5
P8_4/
TRFO11
P1_0/KI0/
AN8
P1_1/KI1/
AN9
P8_2/
TRFO02
P8_1/
TRFO01
P1_4/TXD0
P6_6/INT2/
TXD1
P8_0/
TRFO00
P8_5/
TRFO12
P4_5/INT0
P6_7/INT3/
RXD1
G
H
P1_5/RXD0/
P2_4/
P2_1/
TRDIOA1 TRDIOB0 (TRAIO)/(INT1)(2)
P2_2/
P2_0/TRDIOA0/ P8_6
TRDIOC0 TRDCLK
P2_6/
TRDIOC1
P0_3/AN4
E
F
Package: PTLG0064JA-A (64F0G)
NOTES:
1. P4_7 is an input-only port.
2. Can be assigned to the pin in parentheses by a
program.
R5F212A7
SNLG
JAPAN
Pin assignments (top view)
Figure 1.5
64-pin FLGA Package Pin Assignment (Top Perspective View)
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 12 of 60
8
7
6
5
4
3
2
1
R8C/2A Group, R8C/2B Group
Table 1.7
Pin Name Information by Pin Number (1)
Pin
Control Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1. Overview
Port
Interrupt
P3_3
P3_4
MODE
XCIN
XCOUT
RESET
XOUT
VSS/AVSS
XIN
VCC/AVCC
I/O Pin Functions for of Peripheral Modules
Serial
Timer
SSU
I2C bus
Interface
SSI
SCS
SDA
P4_3
P4_4
P4_7
P4_6
P5_4
P5_3
P5_2
P5_1
P5_0
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P1_7
INT1
TRCIOD
TRCIOC
TRCIOB
TRCIOA/TRCTRG
TRCCLK
TRDIOD1
TRDIOC1
TRDIOB1
TRDIOA1
TRDIOD0
TRDIOC0
TRDIOB0
TRDIOA0/TRDCLK
TRAIO
25
26
P1_6
P1_5
(INT1)(1)
(TRAIO)(1)
27
28
29
30
31
32
33
34
35
36
37
38
P1_4
P8_6
P8_5
P8_4
P8_3
P8_2
P8_1
P8_0
P6_0
P4_5
P6_6
P6_7
39
P6_5
40
41
42
43
44
P6_4
P6_3
P3_1
P3_0
P3_6
(INT1)(1)
45
P3_2
(INT2)(1)
TXD0
INT0
INT2
INT3
TRFO12
TRFO11
TRFO10/TRFI
TRFO02
TRFO01
TRFO00
TREO
INT0
TXD1
RXD1
(CLK1)(1)/
CLK2
RXD2
TXD2
TRBO
TRAO
NOTE:
1. Can be assigned to the pin in parentheses by a program.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
CLK0
RXD0
Page 13 of 60
A/D Converter,
D/A Converter
R8C/2A Group, R8C/2B Group
Table 1.8
Pin Name Information by Pin Number (2)
Pin
Control Pin
Number
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1. Overview
Port
P1_3
P1_2
P1_1
P1_0
P0_0
P0_1
P0_2
P0_3
P0_4
P6_2
P6_1
P0_5
P0_6
Interrupt
I/O Pin Functions for of Peripheral Modules
Serial
Timer
SSU
I2C bus
Interface
Kl3
KI2
KI1
KI0
CLK1
A/D Converter,
D/A Converter
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1/DA0
VSS/AVSS
P0_7
AN0/DA1
VREF
VCC/AVCC
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
P3_7
P3_5
Page 14 of 60
SSO
SSCK
SCL
R8C/2A Group, R8C/2B Group
1.5
1. Overview
Pin Functions
Tables 1.9 and 1.10 list Pin Functions.
Table 1.9
Pin Functions (1)
Item
Pin Name
I/O Type
Description
Power supply input
VCC, VSS
−
Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.
Analog power
supply input
AVCC, AVSS
−
Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
Reset input
RESET
I
Input “L” on this pin resets the MCU.
MODE
MODE
I
Connect this pin to VCC via a resistor.
XIN clock input
XIN
I
XIN clock output
XOUT
O
These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic resonator or a crystal oscillator between
the XIN and XOUT pins(1). To use an external clock, input it to
the XIN pin and leave the XOUT pin open.
XCIN clock input
XCIN
I
XCIN clock output
XCOUT
O
INT interrupt input
INT0 to INT3
I
INT interrupt input pins.
INT0 is timer RD input pin. INT1 is timer RA input pin.
Key input interrupt
KI0 to KI3
I
Key input interrupt input pins
Timer RA
TRAIO
TRAO
O
Timer RA output pin
Timer RB
TRBO
O
Timer RB output pin
Timer RC
TRCCLK
I
External clock input pin
TRCTRG
I
External trigger input pin
I/O
These pins are provided for XCIN clock generation circuit I/O.
Connect a crystal oscillator between the XCIN and XCOUT
pins(1). To use an external clock, input it to the XCIN pin and
leave the XCOUT pin open.
Timer RA I/O pin
TRCIOA, TRCIOB,
TRCIOC, TRCIOD
I/O
Timer RC I/O pins
Timer RD
TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1
I/O
Timer RD I/O pins
TRDCLK
I
External clock input pin
Timer RE
TREO
O
Divided clock output pin
Timer RF
TRFI
I
Timer RF input pin
TRFO00 to TRFO02,
TRFO10 to TRFO12
O
Timer RF output pins
CLK0, CLK1, CLK2
I/O
RXD0, RXD1, RXD2
I
Serial data input pins
Serial interface
I2C bus
SSU
Reference voltage
input
Transfer clock I/O pins
TXD0, TXD1, TXD2
O
Serial data output pins
SCL
I/O
Clock I/O pin
SDA
I/O
Data I/O pin
SSI
I/O
Data I/O pin
SCS
I/O
Chip-select signal I/O pin
SSCK
I/O
Clock I/O pin
SSO
I/O
Data I/O pin
VREF
I
Reference voltage input pin to A/D converter and D/A
converter
I: Input
O: Output
I/O: Input and output
NOTE:
1. Refer to the oscillator manufacturer for oscillation characteristics.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 15 of 60
R8C/2A Group, R8C/2B Group
Table 1.10
1. Overview
Pin Functions (2)
Item
Pin Name
I/O Type
Description
A/D converter
AN0 to AN11
I
Analog input pins to A/D converter
D/A converter
DA0 to DA1
O
D/A converter output pins
I/O port
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_3 to P4_5,
P5_0 to P5_4,
P6_0 to P6_7,
P8_0 to P8_6
I/O
CMOS I/O ports. Each port has an I/O select direction
register, allowing each pin in the port to be directed for input
or output individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
P2_0 to P2_7 also function as LED drive ports.
Input port
P4_6, P4_7
I: Input
O: Output
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
I
I/O: Input and output
Page 16 of 60
Input-only ports
R8C/2A Group, R8C/2B Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
b31
b15
R2
R3
b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
Data registers(1)
R2
R3
A0
A1
FB
b19
b15
Address registers(1)
Frame base register(1)
b0
Interrupt table register
INTBL
INTBH
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
b19
b0
Program counter
PC
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
b7
Flag register
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
NOTE:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 17 of 60
R8C/2A Group, R8C/2B Group
2.1
2. Central Processing Unit (CPU)
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 18 of 60
R8C/2A Group, R8C/2B Group
2.8.7
2. Central Processing Unit (CPU)
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 19 of 60
R8C/2A Group, R8C/2B Group
3.
3. Memory
Memory
3.1
R8C/2A Group
Figure 3.1 is a Memory Map of R8C/2A Group. The R8C/2A group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal
ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte internal
RAM area is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for storing data but also
for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special
Function Registers
(SFRs))
002FFh
00400h
Internal RAM
0XXXXh
03000h
0FFDCh
Internal RAM
Undefined instruction
Overflow
BRK instruction
Address match
Single step
0WWWWh
Watchdog timer, oscillation stop detection, voltage monitor
0YYYYh
(Reserved)
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
Expanded area
FFFFFh
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Internal ROM
Internal RAM
Size
Address 0YYYYh
Address ZZZZZh
Size
Address 0XXXXh
Address 0WWWWh
48 Kbytes
04000h
−
2.5 Kbytes
00DFFh
−
64 Kbytes
96 Kbytes
04000h
04000h
13FFFh
1BFFFh
3 Kbytes
7 Kbytes
00FFFh
011FFh
−
03DFFh
128 Kbytes
04000h
23FFFh
7.5 Kbytes
011FFh
03FFFh
Figure 3.1
Memory Map of R8C/2A Group
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 20 of 60
R8C/2A Group, R8C/2B Group
3.2
3. Memory
R8C/2B Group
Figure 3.2 is a Memory Map of R8C/2B Group. The R8C/2B group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a
48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.
The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte
internal RAM is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for storing data but
also for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special
Function Registers
(SFRs))
002FFh
00400h
Internal RAM
0XXXXh
02400h
Internal ROM
(data flash)(1)
02BFFh
0FFDCh
Undefined instruction
Overflow
BRK instruction
Address match
Single step
03000h
Internal RAM
0WWWWh
Watchdog timer, oscillation stop detection, voltage monitor
0YYYYh
(Reserved)
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
Expanded area
FFFFFh
NOTES:
1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown.
2. The blank regions are reserved. Do not access locations in these regions.
Internal ROM
Internal RAM
Size
Address 0YYYYh
Address ZZZZZh
Size
Address 0XXXXh
Address 0WWWWh
48 Kbytes
04000h
−
2.5 Kbytes
00DFFh
−
64 Kbytes
04000h
13FFFh
3 Kbytes
00FFFh
−
96 Kbytes
04000h
1BFFFh
7 Kbytes
011FFh
03DFFh
128 Kbytes
04000h
23FFFh
7.5 Kbytes
011FFh
03FFFh
Figure 3.2
Memory Map of R8C/2B Group
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 21 of 60
R8C/2A Group, R8C/2B Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the special
function registers.
Table 4.1
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
SFR Information (1)(1)
Register
Symbol
After reset
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Module Operation Enable Register
PM0
PM1
CM0
CM1
MSTCR
00h
00h
01101000b
00100000b
00h
Protect Register
PRCR
00h
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
Address Match Interrupt Register 0
OCD
WDTR
WDTS
WDC
RMAD0
Address Match Interrupt Enable Register
Address Match Interrupt Register 1
AIER
RMAD1
00000100b
XXh
XXh
00X11111b
00h
00h
00h
00h
00h
00h
00h
Count Source Protection Mode Register
CSPR
00h
10000000b(6)
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Control Register 1
High-Speed On-Chip Oscillator Control Register 2
FRA0
FRA1
FRA2
00h
When shipping
00h
Clock Prescaler Reset Flag
CPSRF
00h
High-Speed On-Chip Oscillator Control Register 6
High-Speed On-Chip Oscillator Control Register 7
FRA6
FRA7
When Shipping
When Shipping
0030h
0031h
0032h
Voltage Detection Register 1(2)
Voltage Detection Register 2(2)
VCA1
VCA2
00001000b
00h(3)
00100000b(4)
0033h
0034h
0035h
0036h
0037h
0038h
Voltage Monitor 1 Circuit Control Register(5)
Voltage Monitor 2 Circuit Control Register(5)
Voltage Monitor 0 Circuit Control Register(2)
VW1C
VW2C
VW0C
00001000b
00h
0000X000b(3)
0100X001b(4)
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
0039h
003Ah
003Eh
003Fh
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register.
3. The LVD0ON bit in the OFS register is set to 1 and hardware reset.
4. Power-on reset, voltage monitor 0 reset, or the LVD0ON bit in the OFS register is set to 0 and hardware reset.
5. Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3.
6. The CSPROINI bit in the OFS register is set to 0.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 22 of 60
R8C/2A Group, R8C/2B Group
Table 4.2
Address
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
4. Special Function Registers (SFRs)
SFR Information (2)(1)
Register
Symbol
After reset
Timer RC Interrupt Control Register
Timer RD0 Interrupt Control Register
Timer RD1 Interrupt Control Register
Timer RE Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
Key Input Interrupt Control Register
TRCIC
TRD0IC
TRD1IC
TREIC
S2TIC
S2RIC
KUPIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
SSU/IIC Interrupt Control Register(2)
Compare 1 Interrupt Control Register
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
INT2 Interrupt Control Register
Timer RA Interrupt Control Register
SSUIC / IICIC
CMP1IC
S0TIC
S0RIC
S1TIC
S1RIC
INT2IC
TRAIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XXXXX000b
Timer RB Interrupt Control Register
INT1 Interrupt Control Register
INT3 Interrupt Control Register
Timer RF Interrupt Control Register
Compare 0 Interrupt Control Register
INT0 Interrupt Control Register
A/D Conversion Interrupt Control Register
Capture Interrupt Control Register
TRBIC
INT1IC
INT3IC
TRFIC
CMP0IC
INT0IC
ADIC
CAPIC
XXXXX000b
XX00X000b
XX00X000b
XXXXX000b
XXXXX000b
XX00X000b
XXXXX000b
XXXXX000b
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Selected by the IICSEL bit in the PMR register.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 23 of 60
R8C/2A Group, R8C/2B Group
Table 4.3
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
4. Special Function Registers (SFRs)
SFR Information (3)(1)
Register
Symbol
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
UART1 Transmit Buffer Register
U1MR
U1BRG
U1TB
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
U1C0
U1C1
U1RB
SS Control Register H / IIC bus Control Register 1(2)
SS Control Register L / IIC bus Control Register 2(2)
SS Mode Register / IIC bus Mode Register(2)
SS Enable Register / IIC bus Interrupt Enable Register(2)
SS Status Register / IIC bus Status Register(2)
SS Mode Register 2 / Slave Address Register(2)
SS Transmit Data Register / IIC bus Transmit Data Register(2)
SS Receive Data Register / IIC bus Receive Data Register(2)
SSCRH / ICCR1
SSCRL / ICCR2
SSMR / ICMR
SSER / ICIER
SSSR / ICSR
SSMR2 / SAR
SSTDR / ICDRT
SSRDR / ICDRR
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Selected by the IICSEL bit in the PMR register.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 24 of 60
After reset
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
01111101b
00011000b
00h
00h / 0000X000b
00h
FFh
FFh
R8C/2A Group, R8C/2B Group
Table 4.4
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
4. Special Function Registers (SFRs)
SFR Information (4)(1)
Register
Symbol
After reset
D/A Register 0
DA0
00h
D/A Register 1
DA1
00h
D/A Control Register
DACON
00h
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
Port P5 Register
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
Port P6 Direction Register
PD6
00h
Port P2 Drive Capacity Control Register
UART1 Function Select Register
P2DRR
U1SR
00h
000000XXb
Port Mode Register
External Input Enable Register
INT Input Filter Select Register
Key Input Enable Register
Pull-Up Control Register 0
Pull-Up Control Register 1
PMR
INTEN
INTF
KIEN
PUR0
PUR1
00h
00h
00h
00h
00h
XX000000b
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 25 of 60
R8C/2A Group, R8C/2B Group
Table 4.5
Address
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
NOTE:
1.
4. Special Function Registers (SFRs)
SFR Information (5)(1)
Timer RA Control Register
Timer RA I/O Control Register
Timer RA Mode Register
Timer RA Prescaler Register
Timer RA Register
LIN Control Register 2
LIN Control Register
LIN Status Register
Timer RB Control Register
Timer RB One-Shot Control Register
Timer RB I/O Control Register
Timer RB Mode Register
Timer RB Prescaler Register
Timer RB Secondary Register
Timer RB Primary Register
Register
Symbol
TRACR
TRAIOC
TRAMR
TRAPRE
TRA
LINCR2
LINCR
LINST
TRBCR
TRBOCR
TRBIOC
TRBMR
TRBPRE
TRBSC
TRBPR
00h
00h
00h
FFh
FFh
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
Timer RE Second Data Register / Counter Data Register
Timer RE Minute Data Register / Compare Data Register
Timer RE Hour Data Register
Timer RE Day of Week Data Register
Timer RE Control Register 1
Timer RE Control Register 2
Timer RE Clock Source Select Register
TRESEC
TREMIN
TREHR
TREWK
TRECR1
TRECR2
TRECSR
00h
00h
00h
00h
00h
00h
00001000b
Timer RC Mode Register
Timer RC Control Register 1
Timer RC Interrupt Enable Register
Timer RC Status Register
Timer RC I/O Control Register 0
Timer RC I/O Control Register 1
Timer RC Counter
TRCMR
TRCCR1
TRCIER
TRCSR
TRCIOR0
TRCIOR1
TRC
Timer RC General Register A
TRCGRA
Timer RC General Register B
TRCGRB
Timer RC General Register C
TRCGRC
Timer RC General Register D
TRCGRD
Timer RC Control Register 2
Timer RC Digital Filter Function Select Register
Timer RC Output Master Enable Register
TRCCR2
TRCDF
TRCOER
01001000b
00h
01110000b
01110000b
10001000b
10001000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00011111b
00h
01111111b
Timer RD Start Register
Timer RD Mode Register
Timer RD PWM Mode Register
Timer RD Function Control Register
Timer RD Output Master Enable Register 1
Timer RD Output Master Enable Register 2
Timer RD Output Control Register
Timer RD Digital Filter Function Select Register 0
Timer RD Digital Filter Function Select Register 1
TRDSTR
TRDMR
TRDPMR
TRDFCR
TRDOER1
TRDOER2
TRDOCR
TRDDF0
TRDDF1
11111100b
00001110b
10001000b
10000000b
FFh
01111111b
00h
00h
00h
The blank regions are reserved. Do not access locations in these regions
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 26 of 60
After reset
R8C/2A Group, R8C/2B Group
Table 4.6
Address
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
4. Special Function Registers (SFRs)
SFR Information (6)(1)
Register
Timer RD Control Register 0
Timer RD I/O Control Register A0
Timer RD I/O Control Register C0
Timer RD Status Register 0
Timer RD Interrupt Enable Register 0
Timer RD PWM Mode Output Level Control Register 0
Timer RD Counter 0
Symbol
TRDCR0
TRDIORA0
TRDIORC0
TRDSR0
TRDIER0
TRDPOCR0
TRD0
Timer RD General Register A0
TRDGRA0
Timer RD General Register B0
TRDGRB0
Timer RD General Register C0
TRDGRC0
Timer RD General Register D0
TRDGRD0
Timer RD Control Register 1
Timer RD I/O Control Register A1
Timer RD I/O Control Register C1
Timer RD Status Register 1
Timer RD Interrupt Enable Register 1
Timer RD PWM Mode Output Level Control Register 1
Timer RD Counter 1
TRDCR1
TRDIORA1
TRDIORC1
TRDSR1
TRDIER1
TRDPOCR1
TRD1
Timer RD General Register A1
TRDGRA1
Timer RD General Register B1
TRDGRB1
Timer RD General Register C1
TRDGRC1
Timer RD General Register D1
TRDGRD1
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
UART2 Transmit Buffer Register
U2MR
U2BRG
U2TB
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
U2C0
U2C1
U2RB
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 27 of 60
After reset
00h
10001000b
10001000b
11000000b
11100000b
11111000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00h
10001000b
10001000b
11000000b
11100000b
11111000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
R8C/2A Group, R8C/2B Group
Table 4.7
Address
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
4. Special Function Registers (SFRs)
SFR Information (7)(1)
Register
Symbol
After reset
Flash Memory Control Register 4
FMR4
01000000b
Flash Memory Control Register 1
FMR1
1000000Xb
Flash Memory Control Register 0
FMR0
00000001b
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 28 of 60
R8C/2A Group, R8C/2B Group
Table 4.8
SFR Information (8)(1)
Address
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
NOTE:
1.
4. Special Function Registers (SFRs)
Register
The blank regions are reserved. Do not access locations in these regions.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 29 of 60
Symbol
After reset
R8C/2A Group, R8C/2B Group
Table 4.9
SFR Information (9)(1)
Address
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
NOTE:
1.
4. Special Function Registers (SFRs)
Register
The blank regions are reserved. Do not access locations in these regions.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 30 of 60
Symbol
After reset
R8C/2A Group, R8C/2B Group
Table 4.10
SFR Information (10)(1)
Address
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
0270h
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
NOTE:
1.
4. Special Function Registers (SFRs)
Register
The blank regions are reserved. Do not access locations in these regions.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 31 of 60
Symbol
After reset
R8C/2A Group, R8C/2B Group
Table 4.11
Address
0280h
0281h
0282h
0283h
0284h
0285h
0286h
0287h
0288h
0289h
028Ah
028Bh
028Ch
028Dh
028Eh
028Fh
0290h
0291h
0292h
0293h
0294h
0295h
0296h
0297h
0298h
0299h
029Ah
029Bh
029Ch
029Dh
029Eh
029Fh
02A0h
02A1h
02A2h
02A3h
02A4h
02A5h
02A6h
02A7h
02A8h
02A9h
02AAh
02ABh
02ACh
02ADh
02AEh
02AFh
02B0h
02B1h
02B2h
02B3h
02B4h
02B5h
02B6h
02B7h
02B8h
02B9h
02BAh
02BBh
02BCh
02BDh
02BEh
02BFh
4. Special Function Registers (SFRs)
SFR Information (11)(1)
Register
Symbol
After reset
Timer RF Register
TRF
00h
00h
Timer RF Control Register 0
Timer RF Control Register 1
Capture / Compare 0 Register
TRFCR0
TRFCR1
TRFM0
Compare 1 Register
TRFM1
00h
00h
0000h(2)
FFFFh(3)
FFh
FFh
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. After input capture mode.
3. After output compare mode.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 32 of 60
R8C/2A Group, R8C/2B Group
Table 4.12
Address
02C0h
02C1h
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
02D0h
02D1h
02D2h
02D3h
02D4h
02D5h
02D6h
02D7h
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
02E0h
02E1h
02E2h
02E3h
02E4h
02E5h
02E6h
02E7h
02E8h
02E9h
02EAh
02EBh
02ECh
02EDh
02EEh
02EFh
02F0h
02F1h
02F2h
02F3h
02F4h
02F5h
02F6h
02F7h
02F8h
02F9h
02FAh
02FBh
02FCh
02FDh
02FEh
02FFh
FFFFh
4. Special Function Registers (SFRs)
SFR Information (12)(1)
Register
Symbol
After reset
A/D Register 0
AD0
XXh
XXh
A/D Control Register 2
ADCON2
00001000b
A/D Control Register 0
A/D Control Register 1
ADCON0
ADCON1
00000011b
00h
Port P8 Direction Register
PD8
00h
Port P8 Register
P8
XXh
Pull-Up Control Register 2
PUR2
XXX00000b
Timer RF Output Control Register
TRFOUT
00h
Option Function Select Register
OFS
(Note 2)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. The OFS register cannot be changed by a program. Use a flash programmer to write to it.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 33 of 60
R8C/2A Group, R8C/2B Group
5.
5. Electrical Characteristics
Electrical Characteristics
The electrical characteristics of N version (Topr = –20°C to 85°C) and D version (Topr = –40°C to 85°C) are
listed below.
Please contact Renesas Technology sales offices for the electrical characteristics in the Y version (Topr =
–20°C to 105°C).
Table 5.1
Absolute Maximum Ratings
Symbol
Parameter
Rated Value
Unit
-0.3 to 6.5
V
Input voltage
-0.3 to VCC + 0.3
V
VO
Output voltage
-0.3 to VCC + 0.3
V
Pd
Power dissipation
700
mW
Topr
Operating ambient temperature
-20 to 85 (N version) /
-40 to 85 (D version)
°C
Tstg
Storage temperature
-65 to 150
°C
VCC/AVCC
Supply voltage
VI
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 34 of 60
Condition
Topr = 25°C
R8C/2A Group, R8C/2B Group
Table 5.2
5. Electrical Characteristics
Recommended Operating Conditions
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
VCC/AVCC
Supply voltage
2.2
−
5.5
V
VSS/AVSS
Supply voltage
−
0
−
V
VIH
Input “H” voltage
0.8 VCC
−
VCC
V
VIL
Input “L” voltage
0
−
0.2 VCC
V
IOH(sum)
Peak sum output
“H” current
Sum of all pins IOH(peak)
−
−
−240
mA
IOH(sum)
Average sum
output “H” current
Sum of all pins IOH(avg)
−
−
−120
mA
IOH(peak)
Peak output “H”
current
Except P2_0 to P2_7
−
−
-10
mA
P2_0 to P2_7
−
−
-40
mA
Average output
“H” current
Except P2_0 to P2_7
−
−
-5
mA
P2_0 to P2_7
−
−
-20
mA
IOL(sum)
Peak sum output
“L” current
Sum of all pins IOL(peak)
−
−
240
mA
IOL(sum)
Average sum
output “L” current
Sum of all pins IOL(avg)
−
−
120
mA
IOL(peak)
Peak output “L”
current
Except P2_0 to P2_7
−
−
10
mA
P2_0 to P2_7
−
−
40
mA
IOL(avg)
Average output
“L” current
Except P2_0 to P2_7
−
−
5
mA
f(XIN)
XIN clock input oscillation frequency
IOH(avg)
−
−
20
mA
3.0 V ≤ VCC ≤ 5.5 V
0
−
20
MHz
P2_0 to P2_7
2.7 V ≤ VCC < 3.0 V
0
−
10
MHz
2.2 V ≤ VCC < 2.7 V
0
−
5
MHz
f(XCIN)
XCIN clock input oscillation frequency
2.2 V ≤ VCC ≤ 5.5 V
0
−
70
kHz
−
System clock
3.0 V ≤ VCC ≤ 5.5 V
0
−
20
MHz
2.7 V ≤ VCC < 3.0 V
0
−
10
MHz
2.2 V ≤ VCC < 2.7 V
0
−
5
MHz
FRA01 = 0
Low-speed on-chip
oscillator clock selected
−
125
−
kHz
FRA01 = 1
High-speed on-chip
oscillator clock selected
3.0 V ≤ VCC ≤ 5.5 V
−
−
20
MHz
FRA01 = 1
High-speed on-chip
oscillator clock selected
2.7 V ≤ VCC ≤ 5.5 V
−
−
10
MHz
FRA01 = 1
High-speed on-chip
oscillator clock selected
2.2 V ≤ VCC ≤ 5.5 V
−
−
5
MHz
OCD2 = 0
XlN clock selected
OCD2 = 1
On-chip oscillator clock
selected
NOTES:
1. VCC = 2.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
P0
P1
P2
P3
P4
P5
P6
P8
Figure 5.1
30pF
Ports P0 to P6, P8 Timing Measurement Circuit
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 35 of 60
R8C/2A Group, R8C/2B Group
Table 5.3
5. Electrical Characteristics
A/D Converter Characteristics(1)
Symbol
Parameter
−
Resolution
−
Absolute
accuracy
Conditions
Standard
Min.
Typ.
Max.
Unit
Vref = AVCC
−
−
10
Bit
10-bit mode
φAD = 10 MHz, Vref = AVCC = 5.0 V
−
−
±3
LSB
8-bit mode
φAD = 10 MHz, Vref = AVCC = 5.0 V
−
−
±2
LSB
10-bit mode
φAD = 10 MHz, Vref = AVCC = 3.3 V
−
−
±5
LSB
8-bit mode
φAD = 10 MHz, Vref = AVCC = 3.3 V
−
−
±2
LSB
10-bit mode
φAD = 5 MHz, Vref = AVCC = 2.2 V
−
−
±5
LSB
8-bit mode
φAD = 5 MHz, Vref = AVCC = 2.2 V
−
−
±2
LSB
Rladder
Resistor ladder
Vref = AVCC
10
−
40
kΩ
tconv
Conversion time 10-bit mode
φAD = 10 MHz, Vref = AVCC = 5.0 V
3.3
−
−
µs
φAD = 10 MHz, Vref = AVCC = 5.0 V
2.8
−
−
µs
2.2
−
AVCC
V
0
−
AVCC
V
0.25
−
10
MHz
8-bit mode
Vref
Reference voltage
VIA
Analog input voltage(2)
−
A/D operating
clock frequency
Without sample and hold
Vref = AVCC = 2.7 to 5.5 V
With sample and hold
Vref = AVCC = 2.7 to 5.5 V
1
−
10
MHz
Without sample and hold
Vref = AVCC = 2.2 to 5.5 V
0.25
−
5
MHz
With sample and hold
Vref = AVCC = 2.2 to 5.5 V
1
−
5
MHz
NOTES:
1. VCC/AVCC = Vref = 2.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
Table 5.4
D/A Converter Characteristics(1)
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
−
Resolution
−
−
8
−
Absolute accuracy
−
−
1.0
%
tsu
Setup time
−
−
3
µs
RO
Output resistor
4
10
20
kΩ
IVref
Reference power input current
−
−
1.5
mA
(NOTE 2)
Bit
NOTES:
1. VCC/AVCC = Vref = 2.7 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. This applies when one D/A converter is used and the value of the DAi register (i = 0 or 1) for the unused D/A converter is 00h.
The resistor ladder of the A/D converter is not included. Also, even if the VCUT bit in the ADCON1 register is set to 0 (VREF
not connected), IVref flows into the D/A converters.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 36 of 60
R8C/2A Group, R8C/2B Group
Table 5.5
Flash Memory (Program ROM) Electrical Characteristics
Symbol
−
5. Electrical Characteristics
Parameter
Program/erase endurance(2)
Conditions
Standard
Unit
Min.
Typ.
Max.
R8C/2A Group
100(3)
−
−
times
R8C/2B Group
1,000(3)
−
−
times
µs
−
Byte program time
−
50
400
−
Block erase time
−
0.4
9
s
td(SR-SUS)
Time delay from suspend request until
suspend
−
−
97+CPU clock
× 6 cycles
µs
−
Interval from erase start/restart until
following suspend request
650
−
−
µs
−
Interval from program start/restart until
following suspend request
0
−
−
ns
−
Time from suspend until program/erase
restart
−
−
3+CPU clock
× 4 cycles
µs
−
Program, erase voltage
2.7
−
5.5
V
−
Read voltage
2.2
−
5.5
V
−
Program, erase temperature
0
−
60
°C
−
Data hold time(7)
20
−
−
year
Ambient temperature = 55°C
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 37 of 60
R8C/2A Group, R8C/2B Group
Table 5.6
5. Electrical Characteristics
Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
10,000(3)
−
−
times
Byte program time
(program/erase endurance ≤ 1,000 times)
−
50
400
µs
−
Byte program time
(program/erase endurance > 1,000 times)
−
65
−
µs
−
Block erase time
(program/erase endurance ≤ 1,000 times)
−
0.2
9
s
−
Block erase time
(program/erase endurance > 1,000 times)
−
0.3
−
s
td(SR-SUS)
Time delay from suspend request until
suspend
−
−
97+CPU clock
× 6 cycles
µs
−
Interval from erase start/restart until
following suspend request
650
−
−
µs
−
Interval from program start/restart until
following suspend request
0
−
−
ns
−
Time from suspend until program/erase
restart
−
−
3+CPU clock
× 4 cycles
µs
−
Program, erase voltage
2.7
−
5.5
V
−
Read voltage
2.2
−
5.5
V
−
Program, erase temperature
-20(8)
−
85
°C
−
Data hold time(9)
20
−
−
year
−
Program/erase endurance(2)
−
Ambient temperature = 55 °C
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times
is the same as that in program ROM.
5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
8. -40°C for D version.
9. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 38 of 60
R8C/2A Group, R8C/2B Group
5. Electrical Characteristics
Suspend request
(maskable interrupt request)
FMR46
Clock-dependent
time
Fixed time
Access restart
td(SR-SUS)
Figure 5.2
Table 5.7
Time delay until Suspend
Voltage Detection 0 Circuit Electrical Characteristics
Symbol
Parameter
Condition
Vdet0
Voltage detection level
−
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit operation
starts(2)
Vccmin
MCU operating voltage minimum value
VCA25 = 1, VCC = 5.0 V
Standard
Unit
Min.
Typ.
Max.
2.2
2.3
2.4
V
−
0.9
−
µA
−
−
300
µs
2.2
−
−
V
NOTES:
1. The measurement condition is VCC = 2.2 V to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
Table 5.8
Voltage Detection 1 Circuit Electrical Characteristics
Symbol
Parameter
Condition
Vdet1
Voltage detection level
−
Voltage monitor 1 interrupt request generation time(2)
−
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit operation
starts(3)
VCA26 = 1, VCC = 5.0 V
Standard
Unit
Min.
Typ.
Max.
2.70
2.85
3.00
V
−
40
−
µs
−
0.6
−
µA
−
−
100
µs
NOTES:
1. The measurement condition is VCC = 2.2 V to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).
2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
Table 5.9
Voltage Detection 2 Circuit Electrical Characteristics
Symbol
Vdet2
−
Parameter
Condition
Voltage detection level
Voltage monitor 2 interrupt request generation
time(2)
−
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit operation
starts(3)
VCA27 = 1, VCC = 5.0 V
Standard
Unit
Min.
Typ.
Max.
3.3
3.6
3.9
V
−
40
−
µs
−
0.6
−
µA
−
−
100
µs
NOTES:
1. The measurement condition is VCC = 2.2 V to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 39 of 60
R8C/2A Group, R8C/2B Group
Table 5.10
5. Electrical Characteristics
Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3)
Symbol
Parameter
Condition
Standard
Min.
Typ.
Unit
Max.
Vpor1
Power-on reset valid voltage(4)
−
−
0.1
V
Vpor2
Power-on reset or voltage monitor 0 reset valid
voltage
0
−
Vdet0
V
trth
External power VCC rise gradient(2)
20
−
−
mV/msec
NOTES:
1. The measurement condition is Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. This condition (external power VCC rise gradient) does not apply if VCC ≥ 1.0 V.
3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the
VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1.
4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on
reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if −20°C ≤ Topr ≤ 85°C, maintain tw(por1) for
3,000 s or more if −40°C ≤ Topr < −20°C.
Vdet0(3)
Vdet0(3)
2.2V
trth
trth
External
Power VCC
Vpor2
Vpor1
Sampling time(1, 2)
tw(por1)
Internal
reset signal
(“L” valid)
1
× 32
fOCO-S
1
× 32
fOCO-S
NOTES:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage
range (2.2 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details.
3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit of Hardware Manual for details.
Figure 5.3
Power-on Reset Circuit Electrical Characteristics
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 40 of 60
R8C/2A Group, R8C/2B Group
Table 5.11
High-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
fOCO40M
5. Electrical Characteristics
Parameter
High-speed on-chip oscillator frequency
temperature • supply voltage dependence
High-speed on-chip oscillator frequency when
correction value in FRA7 register is written to
FRA1 register
−
Value in FRA1 register after reset
−
Oscillation frequency adjustment unit of highspeed on-chip oscillator
−
−
Condition
Standard
Unit
Min.
Typ.
Max.
VCC = 2.7 V to 5.5 V
−20°C ≤ Topr ≤ 85°C(2)
39.2
40
40.8
MHz
VCC = 2.7 V to 5.5 V
−40°C ≤ Topr ≤ 85°C(2)
39.0
40
41.0
MHz
VCC = 2.2 V to 5.5 V
−20°C ≤ Topr ≤ 85°C(3)
35.2
40
44.8
MHz
VCC = 2.2 V to 5.5 V
−40°C ≤ Topr ≤ 85°C(3)
34.0
40
46.0
MHz
−
36.864
−
MHz
−3%
−
3%
%
VCC = 5.0 V, Topr = 25°C
VCC = 2.7 V to 5.5 V
−20°C ≤ Topr ≤ 85°C
08h
−
F7h
−
Adjust FRA1 register
(value after reset) to -1
−
+0.3
−
MHz
Oscillation stability time
VCC = 5.0 V, Topr = 25°C
−
10
100
µs
Self power consumption at oscillation
VCC = 5.0 V, Topr = 25°C
−
550
−
µA
NOTES:
1. VCC = 2.2 to 5.5 V, Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. These standard values show when the FRA1 register value after reset is assumed.
3. These standard values show when the correction value in the FRA6 register is written to the FRA1 register.
Table 5.12
Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
fOCO-S
Low-speed on-chip oscillator frequency
30
125
250
−
Oscillation stability time
VCC = 5.0 V, Topr = 25°C
−
10
100
kHz
µs
−
Self power consumption at oscillation
VCC = 5.0 V, Topr = 25°C
−
15
−
µA
NOTE:
1. VCC = 2.2 to 5.5 V, Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
Table 5.13
Power Supply Circuit Timing Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
td(P-R)
Time for internal power supply stabilization during
power-on(2)
1
−
2000
µs
td(R-S)
STOP exit time(3)
−
−
150
µs
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25°C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 41 of 60
R8C/2A Group, R8C/2B Group
Table 5.14
Symbol
5. Electrical Characteristics
Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1)
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
tSUCYC
SSCK clock cycle time
4
−
−
tCYC(2)
tHI
SSCK clock “H” width
0.4
−
0.6
tSUCYC
tLO
SSCK clock “L” width
0.4
−
0.6
tSUCYC
tRISE
SSCK clock rising
time
Master
−
−
1
tCYC(2)
Slave
−
−
1
µs
tFALL
SSCK clock falling
time
Master
−
−
1
tCYC(2)
−
−
1
µs
tSU
SSO, SSI data input setup time
100
−
−
ns
tH
SSO, SSI data input hold time
1
−
−
tCYC(2)
tLEAD
Slave
SCS setup time
Slave
1tCYC + 50
−
−
ns
tLAG
SCS hold time
Slave
1tCYC + 50
−
−
ns
tOD
SSO, SSI data output delay time
tSA
SSI slave access time
tOR
SSI slave out open time
−
−
1
tCYC(2)
2.7 V ≤ VCC ≤ 5.5 V
−
−
1.5tCYC + 100
ns
2.2 V ≤ VCC < 2.7 V
−
−
1.5tCYC + 200
ns
2.7 V ≤ VCC ≤ 5.5 V
−
−
1.5tCYC + 100
ns
2.2 V ≤ VCC < 2.7 V
−
−
1.5tCYC + 200
ns
NOTES:
1. VCC = 2.2 to 5.5 V, VSS = 0 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 42 of 60
R8C/2A Group, R8C/2B Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIH or VOH
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIH or VOH
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
CPHS, CPOS: Bits in SSMR register
Figure 5.4
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 43 of 60
R8C/2A Group, R8C/2B Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIH or VOH
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0
VIH or VOH
SCS (input)
VIH or VOH
tHI
tLEAD
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
CPHS, CPOS: Bits in SSMR register
Figure 5.5
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 44 of 60
R8C/2A Group, R8C/2B Group
5. Electrical Characteristics
tHI
VIH or VOH
SSCK
VIH or VOH
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
Figure 5.6
tH
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous
Communication Mode)
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 45 of 60
R8C/2A Group, R8C/2B Group
Table 5.15
5. Electrical Characteristics
Timing Requirements of I2C bus Interface (1)
Symbol
Parameter
Condition
tSCL
SCL input cycle time
tSCLH
SCL input “H” width
tSCLL
SCL input “L” width
tsf
tSP
SCL, SDA input fall time
SCL, SDA input spike pulse rejection time
tBUF
Standard
Typ.
(2)
−
12tCYC + 600
(2)
−
3tCYC + 300
Min.
Max.
−
−
Unit
ns
ns
5tCYC + 500(2)
−
−
−
−
ns
−
300
−
SDA input bus-free time
5tCYC(2)
−
1tCYC(2)
−
ns
ns
tSTAH
Start condition input hold time
3tCYC(2)
−
−
ns
tSTAS
Retransmit start condition input setup time
3tCYC(2)
−
−
ns
tSTOP
Stop condition input setup time
3tCYC(2)
−
−
ns
tSDAS
Data input setup time
−
−
ns
tSDAH
Data input hold time
1tCYC + 20(2)
0
−
−
ns
NOTES:
1. VCC = 2.2 to 5.5 V, VSS = 0 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
VIH
SDA
VIL
tBUF
tSTAH
tSCLH
tSTAS
tSP
tSTOP
SCL
P(2)
S(1)
tsf
Sr(3)
tSCLL
tsr
tSCL
NOTES:
1. Start condition
2. Stop condition
3. Retransmit start condition
Figure 5.7
I/O Timing of I2C bus Interface
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 46 of 60
P(2)
tSDAS
tSDAH
ns
R8C/2A Group, R8C/2B Group
Table 5.16
Electrical Characteristics (1) [VCC = 5 V]
Symbol
VOH
Parameter
Output “H” voltage
Except P2_0 to P2_7,
XOUT
P2_0 to P2_7
XOUT
VOL
5. Electrical Characteristics
Output “L” voltage
Except P2_0 to P2_7,
XOUT
P2_0 to P2_7
XOUT
VT+-VT-
Hysteresis
IIH
IIL
RPULLUP
RfXIN
Input “H” current
Input “L” current
Pull-up resistance
Feedback
resistance
Feedback
resistance
RAM hold voltage
Condition
IOH = -5 mA
IOH = -200 µA
Drive capacity HIGH
Drive capacity LOW
Drive capacity HIGH
Drive capacity LOW
IOL = 5 mA
IOL = 200 µA
Drive capacity HIGH
Drive capacity LOW
Drive capacity HIGH
Drive capacity LOW
INT0, INT1, INT2,
INT3, KI0, KI1, KI2,
KI3, TRAIO, TRFI,
RXD0, RXD1, CLK0,
CLK1, CLK2, SSI,
SCL, SDA, SSO
VRAM
IOL = 20 mA
IOL = 5 mA
IOL = 1 mA
IOL = 500 µA
Max.
VCC
VCC
VCC
VCC
VCC
VCC
2.0
0.45
2.0
2.0
2.0
2.0
−
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
0.1
1.0
−
V
−
−
µA
XIN
−
30
−
−
50
1.0
5.0
-5.0
167
−
µA
kΩ
MΩ
XCIN
−
18
−
MΩ
1.8
−
−
V
RESET
RfXCIN
IOH = -20 mA
IOH = -5 mA
IOH = -1 mA
IOH = -500 µA
Standard
Min.
Typ.
VCC − 2.0
−
VCC − 0.5
−
VCC − 2.0
−
VCC − 2.0
−
VCC − 2.0
−
VCC − 2.0
−
−
−
−
−
−
−
−
−
−
−
−
−
0.1
0.5
VI = 5 V
VI = 0 V
VI = 0 V
During stop mode
NOTE:
1. VCC = 4.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 20 MHz, unless otherwise specified.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 47 of 60
R8C/2A Group, R8C/2B Group
Table 5.17
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (2) [Vcc = 5 V]
(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply
High-speed
current
clock mode
(VCC = 3.3 to 5.5 V)
Single-chip mode,
output pins are
open, other pins
are VSS
High-speed
on-chip
oscillator mode
Low-speed
on-chip
oscillator mode
Low-speed
clock mode
Wait mode
Stop mode
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 48 of 60
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Min.
−
Standard
Typ.
Max.
12
20
Unit
mA
−
10
16
mA
−
7
−
mA
−
5.5
−
mA
−
4.5
−
mA
−
3
−
mA
−
6
12
mA
−
2.5
−
mA
−
150
400
µA
−
150
400
µA
−
35
−
µA
−
30
90
µA
−
18
55
µA
−
3.5
−
µA
−
2.3
−
µA
−
0.7
3.0
µA
−
1.7
−
µA
R8C/2A Group, R8C/2B Group
5. Electrical Characteristics
Timing Requirements
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]
Table 5.18
XIN Input, XCIN Input
Symbol
tc(XIN)
tWH(XIN)
tWL(XIN)
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
Standard
Min.
Max.
50
−
25
−
25
−
14
−
7
−
7
−
Parameter
XIN input cycle time
XIN input “H” width
XIN input “L” width
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
Unit
ns
ns
ns
µs
µs
µs
VCC = 5 V
tC(XIN)
tWH(XIN)
XIN input
tWL(XIN)
Figure 5.8
Table 5.19
XIN Input and XCIN Input Timing Diagram when VCC = 5 V
TRAIO Input, INT1 Input
Symbol
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
Standard
Min.
Max.
100
−
40
−
40
−
Parameter
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
tC(TRAIO)
Unit
ns
ns
ns
VCC = 5 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.9
Table 5.20
TRAIO Input and INT1 Input Timing Diagram when VCC = 5 V
TRFI Input
tc(TRFI)
TRFI input cycle time
Standard
Min.
Max.
−
400(1)
tWH(TRFI)
TRFI input “H” width
200(2)
−
ns
tWL(TRFI)
TRFI input “L” width
200(2)
−
ns
Symbol
Parameter
Unit
ns
NOTES:
1. When using timer RF input capture mode, adjust the cycle time to (1/timer RF count source frequency × 3) or above.
2. When using timer RF input capture mode, adjust the pulse width to (1/timer RF count source frequency × 1.5) or above.
VCC = 5 V
tc(TRFI)
tWH(TRFI)
TRFI input
tWL(TRFI)
Figure 5.10
TRFI Input Timing Diagram when VCC = 5 V
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 49 of 60
R8C/2A Group, R8C/2B Group
Table 5.21
5. Electrical Characteristics
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
200
−
100
−
100
−
−
50
0
−
50
−
90
−
Parameter
CLKi input cycle time
CLKi input “H” width
CLKi input “L” width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Unit
ns
ns
ns
ns
ns
ns
ns
i = 0 to 2
VCC = 5 V
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 to 2
Figure 5.11
Table 5.22
Serial Interface Timing Diagram when VCC = 5 V
External Interrupt INTi (i = 0, 2, 3) Input
INT0 input “H” width
Standard
Min.
Max.
−
250(1)
INT0 input “L” width
250(2)
Symbol
tW(INH)
tW(INL)
Parameter
−
Unit
ns
ns
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 5 V
tW(INL)
INTi input
tW(INH)
i = 0, 2, 3
Figure 5.12
External Interrupt INTi Input Timing Diagram when VCC = 5 V
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 50 of 60
R8C/2A Group, R8C/2B Group
Table 5.23
Electrical Characteristics (3) [VCC = 3 V]
Symbol
VOH
5. Electrical Characteristics
Parameter
Output “H” voltage
Except P2_0 to P2_7,
XOUT
P2_0 to P2_7
XOUT
VOL
Output “L” voltage
Except P2_0 to P2_7,
XOUT
P2_0 to P2_7
XOUT
VT+-VT-
Hysteresis
IIH
IIL
RPULLUP
RfXIN
RfXCIN
VRAM
Input “H” current
Input “L” current
Pull-up resistance
Feedback resistance
Feedback resistance
RAM hold voltage
Condition
IOH = -1 mA
Standard
Min.
Typ.
VCC − 0.5
−
Max.
VCC
Unit
V
Drive capacity
HIGH
Drive capacity
LOW
Drive capacity
HIGH
Drive capacity
LOW
IOL = 1 mA
IOH = -5 mA
VCC − 0.5
−
VCC
V
IOH = -1 mA
VCC − 0.5
−
VCC
V
IOH = -0.1 mA
VCC − 0.5
−
VCC
V
IOH = -50 µA
VCC − 0.5
−
VCC
V
−
−
0.5
V
Drive capacity
HIGH
Drive capacity
LOW
Drive capacity
HIGH
Drive capacity
LOW
IOL = 5 mA
−
−
0.5
V
IOL = 1 mA
−
−
0.5
V
IOL = 0.1 mA
−
−
0.5
V
IOL = 50 µA
−
−
0.5
V
0.1
0.3
−
V
0.1
0.4
−
V
−
−
µA
−
66
−
−
1.8
−
160
3.0
18
−
4.0
-4.0
500
−
−
−
INT0, INT1, INT2,
INT3, KI0, KI1, KI2,
KI3, TRAIO, TRFI,
RXD0, RXD1, CLK0,
CLK1, CLK2, SSI,
SCL, SDA, SSO
RESET
VI = 3 V
VI = 0 V
VI = 0 V
XIN
XCIN
During stop mode
µA
kΩ
MΩ
MΩ
V
NOTE:
1. VCC =2.7 to 3.3 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 10 MHz, unless otherwise specified.
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 51 of 60
R8C/2A Group, R8C/2B Group
Table 5.24
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (4) [Vcc = 3 V]
(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply current High-speed
(VCC = 2.7 to 3.3 V)
clock mode
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
on-chip
oscillator
mode
Low-speed
on-chip
oscillator
mode
Low-speed
clock mode
Wait mode
Stop mode
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 52 of 60
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Min.
−
Standard
Typ.
Max.
5.5
−
Unit
mA
−
2
−
mA
−
5.5
11
mA
−
2.2
−
mA
−
145
400
µA
−
145
400
µA
−
30
−
µA
−
28
85
µA
−
17
50
µA
−
3.3
−
µA
−
2.1
−
µA
−
0.65
3.0
µA
−
1.65
−
µA
R8C/2A Group, R8C/2B Group
5. Electrical Characteristics
Timing requirements
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V]
Table 5.25
XIN Input, XCIN Input
Symbol
tc(XIN)
tWH(XIN)
tWL(XIN)
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
Standard
Min.
Max.
100
−
40
−
40
−
14
−
7
−
7
−
Parameter
XIN input cycle time
XIN input “H” width
XIN input “L” width
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
Unit
ns
ns
ns
µs
µs
µs
VCC = 3 V
tC(XIN)
tWH(XIN)
XIN input
tWL(XIN)
XIN Input and XCIN Input Timing Diagram when VCC = 3 V
Figure 5.13
Table 5.26
TRAIO Input, INT1 Input
Symbol
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
Standard
Min.
Max.
300
−
120
−
120
−
Parameter
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
Unit
ns
ns
ns
VCC = 3 V
tC(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.14
Table 5.27
TRAIO Input and INT1 Input Timing Diagram when VCC = 3 V
TRFI Input
tc(TRFI)
TRFI input cycle time
Standard
Min.
Max.
−
1200(1)
tWH(TRFI)
TRFI input “H” width
600(2)
−
ns
tWL(TRFI)
TRFI input “L” width
600(2)
−
ns
Symbol
Parameter
Unit
ns
NOTES:
1. When using timer RF input capture mode, adjust the cycle time to (1/timer RF count source frequency × 3) or above.
2. When using timer RF input capture mode, adjust the pulse width to (1/timer RF count source frequency × 1.5) or above.
VCC = 3 V
tc(TRFI)
tWH(TRFI)
TRFI input
tWL(TRFI)
Figure 5.15
TRFI Input Timing Diagram when VCC = 3 V
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 53 of 60
R8C/2A Group, R8C/2B Group
Table 5.28
5. Electrical Characteristics
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
300
−
150
−
150
−
−
80
0
−
70
−
90
−
Parameter
CLKi input cycle time
CLKi input “H” width
CLKi Input “L” width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Unit
ns
ns
ns
ns
ns
ns
ns
i = 0 to 2
VCC = 3 V
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 to 2
Figure 5.16
Table 5.29
Serial Interface Timing Diagram when VCC = 3 V
External Interrupt INTi (i = 0, 2, 3) Input
INT0 input “H” width
Standard
Min.
Max.
−
380(1)
INT0 input “L” width
380(2)
Symbol
tW(INH)
tW(INL)
Parameter
Unit
−
ns
ns
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 3 V
tW(INL)
INTi input
tW(INH)
i = 0, 2, 3
Figure 5.17
External Interrupt INTi Input Timing Diagram when VCC = 3 V
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 54 of 60
R8C/2A Group, R8C/2B Group
Table 5.30
Electrical Characteristics (5) [VCC = 2.2 V]
Symbol
VOH
5. Electrical Characteristics
Parameter
Output “H” voltage
Except P2_0 to P2_7,
XOUT
P2_0 to P2_7
XOUT
VOL
Output “L” voltage
Except P2_0 to P2_7,
XOUT
P2_0 to P2_7
XOUT
VT+-VT-
Hysteresis
IIH
IIL
RPULLUP
RfXIN
RfXCIN
VRAM
Input “H” current
Input “L” current
Pull-up resistance
Feedback resistance
Feedback resistance
RAM hold voltage
Condition
IOH = -1 mA
Min.
VCC - 0.5
Standard
Typ.
−
Max.
VCC
IOH = -2 mA
VCC - 0.5
−
VCC
V
IOH = -1 mA
VCC - 0.5
−
VCC
V
IOH = -0.1 mA
VCC - 0.5
−
VCC
V
IOH = -50 µA
VCC - 0.5
−
VCC
V
−
−
0.5
V
Drive capacity
HIGH
Drive capacity
LOW
Drive capacity
HIGH
Drive capacity
LOW
IOL = 2 mA
−
−
0.5
V
IOL = 1 mA
−
−
0.5
V
IOL = 0.1 mA
−
−
0.5
V
IOL = 50 µA
−
−
0.5
V
0.05
0.3
−
V
0.05
0.15
−
V
−
−
µA
−
100
−
−
1.8
−
200
5
35
−
4.0
-4.0
600
−
−
−
INT0, INT1, INT2,
INT3, KI0, KI1, KI2,
KI3, TRAIO, TRFI,
RXD0, RXD1, CLK0,
CLK1, CLK2, SSI,
SCL, SDA, SSO
VI = 2.2 V
VI = 0 V
VI = 0 V
XIN
XCIN
During stop mode
NOTE:
1. VCC = 2.2 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 5 MHz, unless otherwise specified.
Page 55 of 60
V
Drive capacity
HIGH
Drive capacity
LOW
Drive capacity
HIGH
Drive capacity
LOW
IOL = 1 mA
RESET
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Unit
µA
kΩ
MΩ
MΩ
V
R8C/2A Group, R8C/2B Group
Table 5.31
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (6) [Vcc = 2.2 V]
(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply current High-speed
(VCC = 2.2 to 2.7 V)
clock mode
Single-chip mode,
output pins are open,
other pins are VSS
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
High-speed
XIN clock off
High-speed on-chip oscillator on fOCO = 5 MHz
on-chip
Low-speed on-chip oscillator on = 125 kHz
oscillator
No division
mode
XIN clock off
High-speed on-chip oscillator on fOCO = 5 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
Low-speed on- XIN clock off
chip oscillator High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
mode
Divide-by-8, FMR47 = 1
Low-speed
XIN clock off
High-speed on-chip oscillator off
clock mode
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1
Wait mode
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
Stop mode
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Page 56 of 60
Min.
−
Standard
Typ.
Max.
2.5
−
Unit
mA
−
1
−
mA
−
4
−
mA
−
1.7
−
mA
−
110
300
µA
−
125
350
µA
−
27
−
µA
−
20
60
µA
−
12
40
µA
−
2.8
−
µA
−
1.9
−
µA
−
0.6
3.0
µA
−
1.60
−
µA
R8C/2A Group, R8C/2B Group
5. Electrical Characteristics
Timing requirements
(Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25°C) [VCC = 2.2 V]
XIN Input, XCIN Input
Table 5.32
Symbol
tc(XIN)
tWH(XIN)
tWL(XIN)
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
Standard
Min.
Max.
200
−
90
−
90
−
14
−
7
−
7
−
Parameter
XIN input cycle time
XIN input “H” width
XIN input “L” width
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
Unit
ns
ns
ns
µs
µs
µs
VCC = 2.2 V
tC(XIN)
tWH(XIN)
XIN input
tWL(XIN)
Figure 5.18
XIN Input and XCIN Input Timing Diagram when VCC = 2.2 V
Table 5.33
TRAIO Input, INT1 Input
Symbol
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
Standard
Min.
Max.
TBD
−
TBD
−
TBD
−
Parameter
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
Unit
ns
ns
ns
VCC = 2.2 V
tC(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.19
Table 5.34
TRAIO Input and INT1 Input Timing Diagram when VCC = 2.2 V
TRFI Input
tc(TRFI)
TRFI input cycle time
Standard
Min.
Max.
−
2000(1)
tWH(TRFI)
TRFI input “H” width
1000(2)
−
ns
tWL(TRFI)
TRFI input “L” width
1000(2)
−
ns
Symbol
Parameter
Unit
ns
NOTES:
1. When using timer RF input capture mode, adjust the cycle time to (1/timer RF count source frequency × 3) or above.
2. When using timer RF input capture mode, adjust the pulse width to (1/timer RF count source frequency × 1.5) or above.
VCC = 2.2 V
tc(TRFI)
tWH(TRFI)
TRFI input
tWL(TRFI)
Figure 5.20
TRFI Input Timing Diagram when VCC = 2.2 V
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 57 of 60
R8C/2A Group, R8C/2B Group
Table 5.35
5. Electrical Characteristics
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
800
−
400
−
400
−
−
200
0
−
150
−
90
−
Parameter
CLKi input cycle time
CLKi input “H” width
CLKi input “L” width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Unit
ns
ns
ns
ns
ns
ns
ns
i = 0 to 2
VCC = 2.2 V
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 to 2
Figure 5.21
Table 5.36
Serial Interface Timing Diagram when VCC = 2.2 V
External Interrupt INTi (i = 0, 2, 3) Input
INT0 input “H” width
Standard
Min.
Max.
−
1000(1)
INT0 input “L” width
1000(2)
Symbol
tW(INH)
tW(INL)
Parameter
−
Unit
ns
ns
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 2.2 V
tW(INL)
INTi input
tW(INH)
i = 0, 2, 3
Figure 5.22
External Interrupt INTi Input Timing Diagram when VCC = 2.2 V
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 58 of 60
R8C/2A Group, R8C/2B Group
Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Technology website.
JEITA Package Code
P-LQFP64-10x10-0.50
RENESAS Code
PLQP0064KB-A
Previous Code
64P6Q-A / FP-64K / FP-64KV
MASS[Typ.]
0.3g
HD
*1
D
48
33
49
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
32
bp
64
1
c
Reference
Symbol
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
Terminal cross section
ZE
17
c1
*2
E
HE
b1
16
Index mark
ZD
c
A
*3
A1
y
e
A2
F
bp
e
x
y
ZD
ZE
L
L1
L
x
L1
Detail F
JEITA Package Code
P-LQFP64-14x14-0.80
RENESAS Code
PLQP0064GA-A
Previous Code
64P6U-A
Dimension in Millimeters
Min Nom Max
9.9 10.0 10.1
9.9 10.0 10.1
1.4
11.8 12.0 12.2
11.8 12.0 12.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
1.25
1.25
0.35 0.5 0.65
1.0
MASS[Typ.]
0.7g
HD
*1
D
33
48
49
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
32
bp
c
Reference
Symbol
*2
E
HE
c1
b1
ZE
Terminal cross section
64
17
c
Index mark
A2
16
ZD
A
1
A1
F
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
L1
y
e
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
*3
Detail F
bp
x
Page 59 of 60
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.1 0.2
0
0.32 0.37 0.42
0.35
0.09 0.145 0.20
0.125
0°
8°
0.8
0.20
0.10
1.0
1.0
0.3 0.5 0.7
1.0
R8C/2A Group, R8C/2B Group
JEITA Package Code
P-TFLGA64-6x6-0.65
Package Dimensions
RENESAS Code
PTLG0064JA-A
Previous Code
64F0G
MASS[Typ.]
0.07g
w S B
b1
S
AB
b
D
S
w S A
AB
e
A
e
H
G
F
E
E
D
C
B
A
y S
x4
v
Index mark
(Laser mark)
Rev.2.10 Nov 26, 2007
REJ03B0182-0210
Page 60 of 60
1
2
3
Index mark
4
5
6
7
8
Reference
Symbol
D
E
v
w
A
e
b
b1
x
y
Dimension in Millimeters
Min
Nom Max
6.0
6.0
0.15
0.20
1.05
0.65
0.31 0.35 0.39
0.39 0.43 0.47
0.08
0.10
REVISION HISTORY
REVISION HISTORY
Rev.
Date
0.01
Apr 03, 2006
0.10
Jun 26, 2006
0.20
Sep 15, 2006
0.30
Dec 22, 2006
R8C/2A Group, R8C/2B Group Datasheet
R8C/2A Group, R8C/2B Group Datasheet
Description
Page
−
Summary
First Edition issued
All pages Pin name revised
CMP0_0 → TRFO00, CMP0_1 → TRFO01, CMP0_2 → TRFO02,
CMP1_0 → TRFO10, CMP1_1 → TRFO11, CMP1_2 → TRFO12,
TRFIN → TRFI
2, 4
Table 1.1 Specifications for R8C/2A Group (1) and Table 1.3
Specifications for R8C/2B Group (1);
I/O Ports: • Input-only: 3 pins → 2 pins revised
Interrupts: • Internal: 17 sources → 23 sources revised
3, 5
Table 1.2 Specifications for R8C/2A Group (2) and Table 1.4
Specifications for R8C/2B Group (2);
ROM Correction Function deleted
8
Figure 1.3 Block Diagram revised
9
Figure 1.4 Pin Assignment (Top View) revised
10, 11
Table 1.7 Pin Name Information by Pin Number (1) and Table 1.8 Pin
Name Information by Pin Number (2) revised
12, 13
Table 1.9 Pin Functions (1) and Table 1.10 Pin Functions (2) revised
19
Table 4.1 SFR Information (1);
• 0008h: Module Standby Control Register, MSTCR, 00h added
• 001Ch: “00h” → “00h, 10000000b” revised
• NOTE6 added
20
Table 4.2 SFR Information (2);
• 005Fh: Capture Interrupt Control Register, CAPIC, XXXXX000b added
22
Table 4.4 SFR Information (4);
• 00DCh: “00DDh” → “00DCh” revised
• 00F5h: “XXXX00XXb” → “00h” revised
23
Table 4.5 SFR Information (5);
• 0105h: LIN Special Function Register, LINCR2, 00h added
30
Table 4.12 SFR Information (12);
• 02C2h, 02C3h: A/D Register 1, AD1, XXh deleted
• 02C4h, 02C5h: A/D Register 2, AD2, XXh deleted
• 02C6h, 02C7h: A/D Register 3, AD3, XXh deleted
31
Package Dimensions;
“Diagrams showing the latest package dimensions... in the “Packages”
section of the Renesas Technology website.” added
31 to 54 5. Electrical Characteristics added
6
Table 1.5 and Figure 1.1 revised
7
Table 1.6 and Figure 1.2 revised
17
Figure 3.1 revised
18
Figure 3.2 revised
A-1
REVISION HISTORY
Rev.
Date
0.30
Dec 22, 2006
1.00
2.00
Feb 09, 2007
Oct 17, 2007
R8C/2A Group, R8C/2B Group Datasheet
Description
Page
Summary
19
Table 4.1;
• 000Ah: “00XXX000b” → “00h” revised
• 0008h: “Module Standby Control Register” → “Module Operation Enable Register” revised
• 000Fh: “00011111b” → “00X11111b” revised
37
Table 5.11 revised
All pages “Preliminary” deleted
3
Table 1.2 revised
5
Table 1.4 revised
6
Table 1.5 and Figure 1.1 revised
7
Table 1.6 and Figure 1.2 revised
17
Figure 3.1 revised
18
Figure 3.2 revised
19
Table 4.1;
• 0008h: “Module Standby Control Register” → “Module Operation Enable Register” revised
• 000Ah: “00XXX000b” → “00h” revised
• 000Fh: “00011111b” → “00X11111b” revised
• 002Bh: “High-Speed On-Chip Oscillator Control Register 6” added
23
Table 4.5;
0105h: “LIN Control Register 2” register name revised
31
Table 5.2 revised
32
Table 5.3 and Table 5.4; NOTE1 revised
37
Table 5.11 revised
44
Table 5.17 revised
46
Table 5.21 and Figure 5.11; “i = 0 to 2” revised
48
Table 5.24 revised
50
Table 5.28 revised, Figure 5.16 “i = 0 to 2” revised
52
Table 5.31 revised
53
Table 5.34 revised
54
Table 5.35 and Figure 5.21; “i = 0 to 2” revised
All pages “PTLG0064JA-A (64F0G) package” added
3, 5
Table 1.2 and Table 1.4;
• Operating Ambient Temperature: Y version added
• Package: 64-pin FLGA added
6 to 7
Table 1.5 and Figure 1.1 revised
8
Table 1.6 and Figure 1.2 revised
10
Figure 1.4 “64-pin LQFP Package” added
11
Figure 1.5 added
19 to 20 Figure 3.1 and Figure 3.2 revised
24
Table 4.4;
00F5h: “00h” → “000000XXb” revised
A-2
REVISION HISTORY
Rev.
Date
2.00
Oct 17, 2007
2.10
Nov 26, 2007
R8C/2A Group, R8C/2B Group Datasheet
Description
Page
Summary
33
Table 5.1;
Pd: Rated Value “TBD” → “700” revised, “NOTE1” added
59
Package Dimensions “PTLG0064JA-A (64F0G) package” added
2, 4
Table 1.1, Table 1.3 Clock: “Real-time clock (timer RE)” added
6, 7
Table 1.5 and Figure 1.1 revised
8, 9
Table 1.6 and Figure 1.2 revised
20, 21
Figure 3.1 and Figure 3.2 revised
22
Table 4.1 002Ch: High-Speed On-Chip Oscillator Control Register 7
added
35
Table 5.2 NOTE2 revised
41
Table 5.11 revised
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A-3
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
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warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
http://www.renesas.com
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2377-3473
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
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