RT9641A/B Triple Linear Regulator Controller Support ACPI Control Interface General Description The RT9641A/B, paired with either the RT9230 or powered through two external MOS transistors. In RT9231 simplifies the implementation of ACPI- sleep states, a PMOS (or PNP) transistor conducts compliant designs in microprocessor and computer the current from the ATX 5VSB output, while in active applications. The IC integrates two linear controllers states, current flow is transferred to a NMOS and a low-current pass transistor, as well as the transistor connected to the ATX 5V output. Similar to monitoring and control functions into a 16-pin SOIC the 3.3VDUAL output, the operation of the 5VDUAL output is dictated not only by the status of the S3 and package. One linear controller generates the 3.3VDUAL voltage plane from an ATX power supply's 5VSB output during sleep states (S3,S4/S5), powering the PCI slots through an external pass transistor, as instructed by the status of the 3.3VDUAL S5 pins, but that of the EN5VDL pin as well. Features z − 5V Active/Sleep(5VDUAL) enable pin. An additional pass transistor is used to switch in the ATX 3.3V output for PCI operation Provides 3 ACPI-Controlled Voltages z 3.3V Active/Sleep(3.3VDUAL) during S0 and S1 (active) operating states. The − 2.5V/3.3V Active/Sleep(VMEM) with RT9641A second linear controller supplies the computer − 2.6V/3.43V Active and 2.5V/3.3V Sleep(VMEM) with RT9641B system's 2.5V/3.3V memory power through an external pass transistor in active states. During S3 z − No Compensation Required state, an integrated pass transistor supplies the 2.5V/3.3V sleep-state power. A third controller z − 2.5V/3.3V (2.6V/3.43V) Output： ： ±2.0%； ； Both Operational States 5V output in active states, or the ATX 5VSB in sleep states. RT9641A/B's operating mode (active-state outputs or sleep-state outputs) is selectable through two control pins: S3 and S5. Further control of the logic governing activation of different power modes is offered through two enabling pins: EN3VDL and z z supply, while incurring minimal losses. In sleep state, the 3.3VDUAL output is supplied from the ATX 5VSB through a NPN transistor, also external to the Small Size − Small External Component Count z Selectable 2.5V/3.3V (2.6/3.43) VMEM Output Voltage via FAULT/MSEL Pin − 2.5V/2.6V for RDRAM Memory regulator uses an external N-channel pass MOSFET input supplied by an ATX (or equivalent) power Fixed Output Voltages Require No Precision External Resistors EN5VDL. In active states, the 3.3VDUAL linear to connect the output (VOUT1) directly to the 3.3V Excellent Output Voltage Accuracy − 3.3VDUALOutput： ： ±2.0%； ； Sleep States Only powers up a 5VDUAL plane by switching in the ATX The Simple Control Design − 3.3V/3.43V for SDRAM Memory z Under-voltage Monitoring of All Outputs with Centralized FAULT Reporting z Adjustable Soft-start Function Eliminates 5VSB Perturbations controller. Active state power delivery for the 2.5V/3.3V or 2.6V/3.43V VMEM output is done through an external NPN or a NMOS transistor. In sleep states, conduction on this output is transferred to an internal pass transistor. The 5VDUAL output is DS9641A/B-03 March 2002 www.richtek-ic.com.tw 1 RT9641A/B Ordering Information Pin Configurations RT9641A/B Part Number Package type S2 : SOP-16 Pin Configurations TOP VIEW RT9641ACS2 (Plastic SOP-16) Operating temperature range C: Commercial standard VMEM voltage RT9641BCS2 A : 2.5V/3.3V (Plastic SOP-16) B : 2.6V/3.43V 5VSB EN3VDL 1 16 VSEN2 2 15 3V3DLSB 3V3DL 3 14 DRV2 12V 4 13 SS EN5VDL S3 5 12 6 11 S5 GND 7 8 5VDL 5VDLSB 10 DLA 9 FAULT/MSEL Function Block Diagram 12V 3V3DLSB 3V3DL 5VSB TO 12V EA4 _ DLA + 12V BIAS 12V MONITOR 10.5V/9.5V 5VSB POR 5VDLSB UV DETECTOR MONITOR AND CONTROL + TEMPERATURE MONITOR (TMON) + + MEM VOLTAGE SELECT COMP _ _ 1.265V DRV2 UA COMPARTOR 5VDL VSEN2 _ + + _ 3.75V 5µA SS www.richtek-ic.com.tw 2 + EA2 TO UV DEECTOR _ 0.2V _ 40µA EN3VDL S3 S5 EN5VDL GND DS9641A/B-03 March 2002 RT9641A/B Absolute Maximum Ratings z Supply Voltage (V5VSB) +7.0V z 12V GND−0.3V to +14.5V z DLA, DRV2 GND−0.3V to V12V+0.3V z All Other Pins GND−0.3V to 5VSB+0.3V z Package Thermal Resistance SOP-16, θJA 100°C/W z Maximum Junction Temperature 150°C z Maximum Storage Temperature Range -65°C to 150°C z Maximum Lead Temperature (Soldering, 10 sec.) 300°C Recommended Operating Conditions +5V ± 5% z Supply Voltage (V5VSB) z Secondary Bias Voltage (V12V) +12V ± 10% z Digital Inputs (VS3, VS5, VEN3VDL, VEN5VDL) 0 to + 5.5V z Junction Temperature Range 0°C to 125°C z Ambient Temperature Range 0°C to 70°C CAUTION: Stresses beyond the ratings specified in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Characteristics (VCC (12VIN) = 12V, GND = 0V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Units -- 7 20 mA -- 2 10 mA Rising 5VSB POR Threshold -- 2.5 -- V Rising 12V Threshold -- 10.5 11 V -- 6.5 -- µA -- 0.8 VCC Supply Current Operating Supply Current I5VSB Shutdown Supply Current I5VSB(OFF) VSS = 0V, S3 = 0, S5 =0 Power-on Reset, Soft-start, and 12V Monitor Soft-start Current Shutdown Soft-start Voltage DS9641A/B-03 March 2002 ISS -V To be continued www.richtek-ic.com.tw 3 RT9641A/B Parameter Symbol Test Conditions Min Typ Max Units -- -- 2.0 % 2.5V/3.3V (2.6V/3.43V) Linear Regulator (VOUT2) Regulation VSEN2 Nominal Voltage Level VVSEN RSEL = 1KΩ -- 2.5/2. -- V VSEN2 Nominal Voltage Level VVSEN2 RSEL = 1KΩ -- 3.3/3. -- V VSEN2 Under-voltage Falling Threshold -- 68 -- % VSEN2 Under-voltage Hysteresis -- 7 -- % VSEN2 Output Current IVSEN2 5VSB = 5V 200 300 -- mA DRV2 Output Drive Current IDRV2 5VSB = 5V, RSEL = 1KΩ 20 30 -- mA RSEL = 10KΩ -- 200 -- Ω -- -- 2.0 % -- 3.3 -- V 3V3DL Under-voltage Falling Threshold -- 2.24 -- V 3V3DL Under-voltage Hysteresis -- 230 -- mV 5.0 10 -- mA -- 90 -- Ω 5VDL Under-voltage Falling Threshold -- 3.40 -- V 5VDL Under-voltage Hysteresis -- 350 -- mV -40 -- -- mA -- 10 -- µS 50 -- mS DRV2 Output Impedance 3.3V Dual Linear Regulator (VOUT1) Sleep-mode Regulation 3V3DL Nominal Voltage Level 3V3DLSB Output Drive Current V3V3DL I3V3DLS 5VSB = 5V DLA Output Impedance 5V Dual Switch Controller (VOUT3) 5VDLSB Output Drive Current I5VDLSB 5VDLSB = 4V Timing Intervals Active to Sleep, Input to Switching Delay Sleep to Active, Input to Switching Delay Td1 Td2 CSS = 0.1µF (1) (1) -- Control I/O (S3, S5, EN3VDL, EN5VDL, FAULT) High Level Threshold 2.0 -- -- V Low Level Threshold -- -- 0.8 V S3, S5 Internal Pull-up Impedance to 5VSB -- 50 -- KΩ -- 100 -- Ω -- 145 -- °C -- 155 -- °C FAULT Output Impedance FAULT = high Temperature Monitor Fault-level Threshold Shutdown-level Threshold Note: (1) = 50mS with 0.1µF Soft-start capacitor. The delay time is adjustable with td2 = 500xCSS (mS). www.richtek-ic.com.tw 4 TDS DS9641A/B-03 March 2002 RT9641A/B Simplified Power System Diagram 5VIN 12VIN 5VSB 3.3VIN Linear Controller Q2 3.3VDUAL FAULT Q3 Linear Controller Q1 VMEM RT9641A/B Control Logic Q4 Q5 5VDUAL SHUTDOWN S3 S5 EN5VDL EN3VDL DS9641A/B-03 March 2002 www.richtek-ic.com.tw 5 RT9641A/B Functional Pin Description 5VSB (Pin 1) FAULT/MSEL (Pin 9) Provide a 5V bias supply for the IC to this pin by This is a multiplexed function pin allowing the setting connecting it to the ATX 5VSB output. This pin also of the memory output voltage to either 2.5V(2.6V) or provides the base bias current for all the external 3.3V(3.43V) NPN transistors controlled by the IC. The voltage at systems). The memory voltage setting is latched-in this when SS pin voltage goes up to 0.8V (typically 5mS pin monitored for power-on reset (POR) purposes. EN3VDL and EN5VDL (Pin 2 and 5) These pins control the logic governing the output (for RDRAM or SDRAM memory after POR). In case of an under-voltage on any of the outputs or an over temperature event, this pin is used to report the fault condition by being pulled to 5VSB. behavior in response to S3 and S4/S5 requests. DLA (Pin 10) These are digital inputs whose status can only be Connect this pin to the gates of suitable N-MOSFETs, changed during active states operation or during chip which in active states, are used to switch in the ATX shutdown (SS pin grounded by external open-drain 3.3V and 5V outputs into the 3.3VDUAL and 5VDUAL device). The input information is latched-in when outputs, respectively. entering a sleep state, as well as following 5VSB POR release or exit from shutdown. 5VDLSB (Pin 11) Connect this pin to the gate of a suitable P-MOSFET 3V3DLSB (Pin 3) or bipolar PNP. In sleep states, this transistor is Connect this pin to the base of a suitable NPN switched on, connecting the ATX 5VSB output to the transistor. In sleep states, this transistor is used to 5VDUAL regulator output. When PNP is used, it is regulate the voltage at 3V3DL pin to 3.3V. recommanded to use a 100Ω base resistor for base 3V3DL (Pin 4) current limiting. Connect this pin to the 3.3V dual output (VOUT1). In 5VDL (Pin 12) sleep states, the voltage at this pin is regulated to Connect this pin to the 5VDUAL output (VOUT3). In 3.3V; in active states, ATX 3.3V output is delivered to either operating state, the voltage at this pin is this node through a fully on N-MOS transistor. During provided through a fully on MOS transistor. This pin all operating states, this pin is monitored for under- is also monitored for under-voltage events. voltage events. SS (Pin 13) S3 and S5 (Pin 6 and 7) Connect These pins switch the IC’s operating state from active recommended) from this pin to GND. The internal (S0, S1) to S3 and S4/S5 sleep states. Connect S3 Soft-start (SS) current source along with the external to SLP_S3 and S5 to SLP_S5. These are digital capacitor creates a voltage ramp used to control the inputs featuring internal 50kΩ (typical) resistor pull-up ramp-up of the output voltages. Pulling this pin low to 5VSB. Internal circuitry de-glitches the S3 pin for with an open-drain device shuts down all the output disturbances. GND (Pin 8) Signal ground for the IC. All voltage levels are a small ceramic capacitor (0.1µF as well as forces the FAULT pin low. The CSS capacitor is also used to provide a controlled S4/S5 to active transition delay time. measured with respect to this pin. www.richtek-ic.com.tw 6 DS9641A/B-03 March 2002 RT9641A/B 12V (Pin 14) VSEN2 (Pin 16) Connect this pin to the ATX (or equivalent) 12V Connect this pin to the memory output (VOUT2). In output. This pin is used to monitor the status of the sleep states, this pin is regulated to 2.5V(2.6V) or power supply as well as provide bias for the NMOS- 3.3V(3.43V) (based on RSEL) through an internal compatible output drivers. 12V presence at the chip pass in the absence of bias voltage, or severe 12V (Typically). The active-state voltage at this pin is brownout during active states (S0, S1) operation can regulated through an external NPN or NMOS lead transistor connected at the DRV2 pin for both to chip misbehavior. RT9641A/B refuses entering active state before 12V power ready. DRV2 (Pin 15) For the 2.5V RDRAM systems, connect this pin to the transistor capable of delivering 300mA 2.5V(2.6V) and 3.3V(3.43V) setting. During all operating states, the voltage at this pin is monitored for under-voltage events. base of a suitable NPN transistor. This pass transistor regulates the 2.5V(2.6V) output from the ATX 3.3V during active states operation. For 3.3V SDRAM systems connect this pin to the gate of a suitable N-MOS transistor or the base of a suitable NPN transistor. Description Operation Operational Truth Tables The RT9641A/B controls 3 output voltages. It is The EN3VDL and EN5VDL pins offer a host of choices designed for microprocessor computer applications in terms of the overall system architecture and with 3.3V, 5V, 5VSB, and 12V outputs from an ATX supported features. Tables 1~3 describe the truth power supply. The IC is composed of two linear combinations pertaining to each of the three outputs. controllers supplying the PCI slots' 3.3VAUX power (3.3VDUAL, VOUT1) and the 2.5V RDRAM or 3.3V SDRAM memory power (2.5V/3.3V(2.6V/3.43V) VMEM, VOUT2), and a dual switch controller supplying the Table 1. 3.3VDUAL Output (VOUT1) Truth Table EN3VDL S5 S3 3V3D Comments 0 1 1 3.3V S0, S1 States (Active) 0 1 0 3.3V S3 0 0 1 Note Maintains Previous State 0 0 0 3.3V S4/S5 The RT9641A/B automatically initializes upon receipt 1 1 1 3.3V S0, S1 States (Active) of input power. The Power-On Reset (POR) function 1 1 0 3.3V S3 continually monitors the 5VSB input supply voltage, 1 0 1 Note Maintains Previous State initiating soft-start operation after it exceeds its POR 1 0 0 0V S4/S5 5VDUAL voltage (VOUT3). In addition, all the control and monitoring functions necessary for complete ACPI implementation are integrated into the RT9641A/B. Initialization threshold (in S4/S5 states). The 5VSB POR trip event is also used to lock in the memory voltage setting based on RSEL. The RT9641A/B forces the operation mode to start from S4/S5 states at POR releasing. DS9641A/B-03 March 2002 Note: Combination not allowed. As seen in Table 1, EN3VDL simply controls whether the 3.3VDUAL plane remains powered up during S4/S5 sleep state. www.richtek-ic.com.tw 7 RT9641A/B Table 2. 5VDUAL Output (VOUT3) Truth Table EN5VDL S5 S3 5VDL state. Exceeding the maximum current rating of this Comments output in a sleep state can lead to output voltage 0 1 1 5V S0, S1 States(Active) drooping. If excessive, this droop can ultimately trip the 0 1 0 0V S3 under-voltage detector and send a FAULT signal to the 0 0 1 Note Maintains Previous State 0 0 0 0V S4/S5 1 1 1 5V S0, S1 States(Active) the circuit is desired, this can be achieved by externally 1 1 0 5V S3 pulling or latching the SS pin low. Pulling the SS pin 1 0 1 Note Maintains Previous State 1 0 0 5V S4/S5 computer system. However, a FAULT condition will only set off the FAULT flag, and it will not shut off or latch off any part of the circuit. If shutdown or latch off low will also force the FAULT pin to go low. Under-voltage sensing is disabled on all disabled Note: Combination not allowed. outputs and during soft-start ramp-up intervals. Very similarly, Table 2 details the fact that EN5VDL Another condition that could set off the FAULT flag is status controls whether the 5VDUAL plane supports chip over-temperature. If the RT9641A/B reaches an sleeps states. internal temperature of 145°C (typical), the FAULT flag is set (FAULT/MSEL pulled high), but the chip Table 3. 2.5V/3.3V(2.6V/3.43V) VMEM Output (VOUT2) Truth Table RSEL S5 S3 continues to operate until the temperature reaches 155°C (typical), when unconditional shutdown of all 2.5V/3.3V Comments outputs takes place. The thermal shutdown can be released with a re-soft-start when the chip cools down. 1KΩ 1 1 2.5V/2.6V S0, S1 States(Active) 1KΩ 1 0 2.5V S3 1KΩ 0 1 Note Maintains Previous State 1KΩ 0 0 0V S4/S5 10KΩ 1 1 3.3V/3.43V S0, S1 States(Active) 10KΩ 1 0 3.3V S3 drain or open collector device capable of sinking a 10KΩ 0 1 Note Maintains Previous State minimum of 2mA. Pulling the SS pin low effectively 10KΩ 0 0 0V S4/S5 shuts down all the pass elements. Upon release of the Shutdown computer system, or at any other time, the RT9641A/B output is maintained in S3 (Suspend-To-RAM), but not state. The specified shutdown level (typically 0.8V) with an open cycle and resumes normal operation in accordance to As seen in Table 3, 2.5V/3.3V(2.6V/3.43V) VMEM S4/S5 can be shut down by pulling the SS pin below the SS pin, the RT9641A/B undergoes a new soft-start Note: Combination not allowed. in In case of a FAULT condition that might endanger the dual-voltage support accommodates both SDRAM as well as RDRAM type memories. the ATX supply and control pins status. Layout Considerations The typical application employing a RT9641A/B is a fairly straight-forward implementation. Similar to any other linear regulators, attention has to be paid to a Fault Protection few potentially sensitive small signal components, such All the outputs are monitored against under-voltage as those connected to high-impedance nodes or those events. A serve over-current caused by a failed load supplying critical by-pass currents. on any of the outputs, would, in turn, cause that specific output to suddenly drop. If any of the output voltages drop below 68% of their set value, such event is reported by having the FAULT/MSEL pin pulled to 5V. Additionally, the 2.5V/3.3V(2.6V/3.43V) memory regulator is internally current limited while in a sleep www.richtek-ic.com.tw 8 DS9641A/B-03 March 2002 RT9641A/B The power components (pass transistors) and the controller IC should be placed first. The controller capacitor placement, but having these capacitors close to the load they serve is preferable. should be placed in a central position on the The only critical small signal component is the soft- motherboard, closer to the memory load if possible. start capacitor, CSS. Locate the component close to SS Ensure the VSEN2 connection is properly sized to pin of the control IC and connect to ground though a carry 300mA without significant resistive losses. The vias placed close to the capacitor’s ground pad. pass transistors should be placed on pads capable of Minimize any leakage current paths from SS node, heatsinking, matching the device’s power dissipation. since the internal current source is only 5µA. Where applicable, multiple via corrections to a large internal plane can significantly lower localized device temperature rise. A multi-layer printed circuit board is recommended. Fig.1 shows the connections of most of the components to the converter. Note that each individual capacitor could represent numerous physical capacitors. Dedicate one solid layer for a ground plane +12VIN and make all critical component ground connections +5VSB through vias placed as close to the component as C12V C5VSB possible. Dedicate another solid layer as a power CI N plane and break this plane into smaller islands of Q2 VOUT1 5VDLSB VOUT3 3V3DLSB 5VDL RT9641A/B DLA CBULK3 CBULK1 VSEN2 Q5 VOUT2 +5V IN GND DRV2 circuit layers to create power islands connecting the filtering components (output capacitors) and the loads. Use the remaining printed circuit layers for small signal CHF2 CBULK2 Q3 support both the input power and output power nodes. Use copper filled polygons on the top and bottom CHF3 3V3DL LOAD Q4 LOAD CSS common voltage levels. Ideally, the power plane should 5VSB LOAD CHF1 12V SS Q1 wiring. Component Selection Guidelines Output Capacitors Selection +3.3VI N The output capacitors for all outputs should be ISLAND ON POWER PLANE LAYER selected to allow the output voltage to meet the ISLAND ON CIRCUIT/POWER PLANE LAYER dynamic regulation requirements of active state VIA CONNECTION TO GROUND PLANE operation (S0, S1). The load transient for the various microprocessor system’s components may require high Fig.1 Printed Circuit Board Islands quality capacitors to supply the high slew rate (di/dt) current demands. Thus, it is recommended that Placement of the decoupling and bulk capacitors should follow a placement reflecting their purpose. As capacitors COUT1 and COUT2 should be selected for transient load regulation. such, the high-frequency decoupling capacitors (CHF) should be placed as close as possible to the load they Also, during the transition between active and sleep are decoupling; the ones decoupling the controller none of the power pass elements are conducting- (C12V, C5VSB) close to the controller pins, the one during this time the output capacitors have to supply all decoupling the load close to the load connector or the the output current. The output voltage drop during this load itself (if embedded). The bulk capacitance brief period of time can be approximated with the (aluminum following formula: electrolytic or tantalum capacitors) placement is not as critical as the high-frequency DS9641A/B-03 March 2002 states, there is a short interval of time during which ∆VOUT = IOUT x (ESROUT + tt / COUT), where www.richtek-ic.com.tw 9 RT9641A/B ∆VOUT : criteria for the selection of this transistor is output output voltage drop IOUT: output current during transition voltage budgeting. The maximum RDS(ON) allowed at highest junction temperature can be expressed with COUT: output capacitor bank capacitance the following equation: ESROUT: output capacitor bank ESR tt: active-to-sleep or sleep-to-active transition time (5µS typical) RDS(ON) MAX = (VIN MIN−VOUT MIN)/ IOUT MAX, where VIN MIN: minimum input voltage Since the output voltage drop is heavily dependent on the ESR (equivalent series resistance) of the output VOUT MIN: minimum output voltage allowed. IOUT MAX: maximum output current capacitor bank, the capacitors should be chosen to The maintain the output voltage above the lowest allowable approximately 6V, so the logic level MOSFET is regulation level. gate bias available for this MOEFET is prefered. The 3.3V(3.43V) VMEM power also can be regulated from ATX 5V in order to have high quality Input Capacitors Selection The input capacitors for an RT9641A/B application must have sufficiently low ESR so that the input voltage does not dip excessively when energy is transferred to the output capacitors. VMEM, in such a configuration, either MOSFET or NPN transistors can be used. While the heat dissipation should be carefully handled. Q4 Transistor Selection/Considerations If a P-chanel MOSFET is used to switch the 5VSB output of the ATX supply into the 5VDUAL output during The RT9641A/B typically requires one P-channel or S3 and S4/S5 states (as dictated by EN5VDL status), PNP transistor and two N-channel power MOSFETs then, similar to the situation where Q1 is a MOSFET, and two bipolar NPN transistors. the selection criteria of this device is also proper One general requirement for selection of transistors for voltage budgeting. The maximum rDS (ON), however, has to be achieved with only 4.5V of VGS, so a logic all the linear regulators/switching elements is package selection for efficient removal of heat. The power dissipated in a linear regulator/switching element is: PLINEAR = IO x (VIN – VOUT) level MOSFET needs to be selected. If a PNP device is chosen to perform this function, it has to have a low saturation voltage while providing the maximum sleepstate current and have current gain sufficiently high to Select a package and heatsink that maintains the be saturated using the minimum drive current (typically junction temperature below the rating 20mA). A 100Ω~200Ω resistor is recommended to be with the maximum expected ambient temperature. Q1 inserted between the 5VDLSB pin and Base node of the PNP transistor for limiting the base current. The active element on the 2.5V/3.3V (2.6V/3.43V) Q3, Q5 VMEM output has different requirements for each the The two N-channel MOSFETs are used to switch the two voltage settings. In 2.5V systems utilizing RDRAM 3.3V and 5V inputs provided by the ATX supply into the (or voltage-compatible) memory, Q1 had better to be a 3.3VDUAL and 5VDUAL outputs, respectively, while in bipolar NPN capable of conducting the maximum required output current and it must have a minimum active (S0, S1) state. Similar RDS(ON) criteria apply in these cases as well, unlike the PMOS, however, these current gain (hfe) of 100~150 at this current and 0.7V NMOS transistors get the benefit of an increased VGS VCE. In such systems, the 2.5V(2.6V) output is drive (approximately 8V and 7V respectively). regulated from the ATX 3.3V output while in an active Q2 state. In 3.3V systems (SDRAM or compatible) Q1 is The NPN transistor used as sleep-state pass element suggested to use an N-channel MOSFET, then the on the 3.3VDUAL output must have a minimum current MOSFET serves like a switch when it is connected to ATX3.3V during active states (S0, S1). The main www.richtek-ic.com.tw 10 gain of 100 at VCE = 1.5V and ICE = 500mA throughout the in-circuit operating temperature range. DS9641A/B-03 March 2002 RT9641A/B Typical Application Circuit +5VIN +12VIN +3.3VIN + C1 10µF +5VSB C2 1µF + C14 C4 1µF 5VSB 12V Q2 2SD1802 470µF + C3 220µF C5 1µF ER800D 3V3DLSB CEB603AL VOUT1 3.3VDUAL Q3 1/2 UF76113DK8 C6 1µF DRV2 + C7 200µF 3V3DL VSEN2 FAULT/MSEL R1 1K Q1 2SD1802 RT9641A/B 5VDLSB C8,9 + 2X150µF S5 EN5VDL 5VDL EN3VDL EN3VDL SHUTDOWN (From Open-drain N-MOS) SS 1µF VOUT2 2.5VMEM C10 1µF Q4 MMBT2907A R2 Q5 1/2 HUF76113DK8 S3 S5 EN5VDL 2X150µF 100 DLA S3 + VOUT2 3.3V/3.43 VMEM + C11 150µF C12 1µF VOUT3 5VDUAL GND C13 0.1µF DS9641A/B-03 March 2002 www.richtek-ic.com.tw 11 RT9641A/B Package Information H M B B J A C F Symbol www.richtek-ic.com.tw 12 D I Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 9.804 10.008 0.386 0.394 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.178 0.254 0.007 0.010 I 0.102 0.254 0.004 0.010 J 5.791 6.198 0.228 0.244 M 0.406 1.270 0.016 0.050 DS9641A/B-03 March 2002 RT9641A/B DS9641A/B-03 March 2002 www.richtek-ic.com.tw 13 RT9641A/B RICHTEK TECHNOLOGY CORP. RICHTEK TECHNOLOGY CORP. Headquarter Taipei Office (Marketing) 6F, No. 35, Hsintai Road, Chupei City 8F-1, No. 137, Lane 235, Paochiao Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5510047 Fax: (8863)5537749 Tel: (8862)89191466 Fax: (8862)89191465 Email: [email protected] www.richtek-ic.com.tw 14 DS9641A/B-03 March 2002