SAMSUNG S6A0075

S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
June. 2000.
Ver. 0.0
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
written permission of LCD Driver IC Team.
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
INTRODUCTION
S6A0075 is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology. It can
display 1, 2, or 4 lines with 5 x 8 or 6 x 8 dots format.
FUNCTIONS
•
Character type dot matrix LCD driver & controller
•
Internal driver: 34 common and 100 segment signal output
•
Easy interface with 4-bit or 8-bit MPU
•
Clock synchronized serial interface
•
5 x 8 dot matrix / 6 x 8 dot matrix possible
•
Bi-directional shift function
•
All character reverse display
•
Display shift per line
•
Voltage converter for LCD drive voltage: 13V max. (2 times/3 times)
•
Various instruction functions
•
Automatic power on reset
FEATURES
•
Internal memory
- Character Generator ROM (CGROM): 9,600 bits (240 characters x 5 x 8 dot)
- Character Generator RAM (CGRAM): 64 x 8 bits (8 characters x 5 x 8 dot)
- Segment Icon RAM (SEGRAM): 16 x 8 bits (96 icons max.)
- Display Data RAM (DDRAM): 80 x 8 bits (80 characters max.)
•
Low power operation
- Power supply voltage range: 2.7 - 5.5V (VDD)
- LCD Drive voltage range: 3.0 - 13.0V (VDD - V5)
•
CMOS process
•
Programmable duty cycle: 1/17, 1/33
•
Internal oscillator with an external resistor
•
Bare chip available
2
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
PROGRAMMABLE DUTY CYCLES
5-dot Font Width
Display Line
Numbers
Duty Ratio
Single-chip Operation
Displayable Characters
Possible Icons
1
1/17
1 line of 40 characters
80
2
1/33
2 lines of 40 characters
80
4
1/33
4 line of 20 characters
80
6-dot Font Width
Display Line
Numbers
Duty Ratio
Single-chip Operation
Displayable Characters
Possible Icons
1
1/17
1 line of 32 characters
96
2
1/33
2 lines of 32 characters
96
4
1/33
4 line of 16 characters
96
3
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
BLOCK DIAGRAM
IE
OSC1 OSC2
Oscillator
Power on Reset
(POR)
Timing Generator
RESET
IM
RS/CS
E/SCLK
RW/SID
System
Interface
Serial
4-bit
8-bit
8
Instruction
Register
(IR)
7
Instruction
Decoder
34-bit
Shift
Register
Display Data
RAM (DDRAM)
96 x 8-bit
Address
Counter
COM0Common COM33
Driver
7
7
8
8
DB4-DB7
Data
Register
(DR)
Input/
Output
Buffer
DB3-DB1
8
COM1100-bit 100-bit
Segment COM100
Shift
Latch
Driver
Register Circuit
8
Busy Flag
DB0-SOD
3
Segment
RAM
(SEGRAM)
16 bytes
Vci
C1
7
8
Character
Generator
RAM
(CGRAM)
64 bytes
LCD Driver
Voltage Selector
8
Character
Generator
ROM
(CGROM)
9600 bits
Cursor and
Blink
Controller
Voltage Converter
C2
5
V5OUT2
V5OUT3
VDD
GND(VSS)
4
5/6
Parallel/Serial Converter and
Smooth Scroll Circuit
V1 - V5
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
PAD CONFIGURATION
(0, 0)
Y
X
Chip size: 7450 x 5340
PAD size: 100 × 100
Unit: µ m
S6A0075
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD
OSC2
OSC1
RESET
IM
IE
VSS1
RS/CS
RW/SID
E/SCLK
DB0/SOD
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VCI
C2
C1
VSS2
V5OUT2
V5OUT3
V5
V4
V3
V2
V1
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
5
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
PAD CENTER COORDINATES
Table 1. Pad Location
Pad
No.
Pad
Name
1
Coordinate
X
Y
Pad
No.
SEG68
-2975
-2504
33
2
SEG69
-2850
-2504
3
SEG70
-2725
4
SEG71
5
Pad
Name
Coordinate
X
Y
Pad
No.
SEG100
1024
-2504
65
34
COM9
1262
-2504
-2504
35
COM10
1387
-2600
-2504
36
COM11
SEG72
-2475
-2504
37
6
SEG73
-2350
-2504
7
SEG74
-2225
8
SEG75
9
Coordinate
X
Y
DB4
3559
0
66
DB5
3559
125
-2504
67
DB6
3559
250
1512
-2504
68
DB7
3559
375
COM12
1637
-2504
69
VCI
3559
500
38
COM13
1762
-2504
70
C2
3559
625
-2504
39
COM14
1887
-2504
71
C1
3559
750
-2100
-2504
40
COM15
2012
-2504
72
VSS2
3559
875
SEG76
-1975
-2504
41
COM16
2137
-2504
73
V5OUT2
3559
1000
10
SEG77
-1850
-2504
42
COM25
2262
-2504
74
V5OUT3
3559
1125
11
SEG78
-1725
-2504
43
COM26
2387
-2504
75
V5
3559
1250
12
SEG79
-1600
-2504
44
COM27
2512
-2504
76
V4
3559
1375
13
SEG80
-1475
-2504
45
COM28
2637
-2504
77
V3
3559
1500
14
SEG81
-1350
-2504
46
COM29
2762
-2504
78
V2
3559
1625
15
SEG82
-1225
-2504
47
COM30
2887
-2504
79
V1
3559
1750
16
SEG83
-1100
-2504
48
COM31
3012
-2504
80
COM24
3262
2504
17
SEG84
-975
-2504
49
COM32
3137
-2504
81
COM23
3137
2504
18
SEG85
-850
-2504
50
COM33
3262
-2504
82
COM22
3012
2504
19
SEG86
-725
-2504
51
VDD
3559
-1750
83
COM21
2887
2504
20
SEG87
-600
-2504
52
OSCC
3559
-1625
84
COM20
2762
2504
21
SEG88
-475
-2504
53
OSC1
3559
-1500
85
COM19
2637
2504
22
SEG89
-350
-2504
54
RESET
3559
-1375
86
COM18
2512
2504
23
SEG90
-225
-2504
55
IM
3559
-1250
87
COM17
2387
2504
24
SEG91
-100
-2504
56
IE
3559
-1125
88
COM8
2262
2504
25
SEG92
24
-2504
57
VSS1
3559
-1000
89
COM7
2137
2504
26
SEG93
149
-2504
58
RS/CS
3559
-875
90
COM6
2012
2504
27
SEG94
274
-2504
59
RW/SID
3559
-750
91
COM5
1887
2504
28
SEG95
399
-2504
60
E/SCLK
3559
-625
92
COM4
1762
2504
29
SEG96
524
-2504
61
DB0/SOD
3559
-500
93
COM3
1637
2504
30
SEG97
649
-2504
62
DB1
3559
-375
94
COM2
1512
2504
31
SEG98
774
-2504
63
DB2
3559
-250
95
COM1
1387
2504
32
SEG99
899
-2504
64
DB3
3559
-125
96
COM0
1262
2504
Table 1. Pad Location (Continued)
6
Pad
Name
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Pad
No.
Pad
Name
97
Coordinate
X
Y
Pad
No.
SEG1
1024
2504
131
98
SEG2
899
2504
99
SEG3
774
100
SEG4
101
Pad
Name
S6A0075
Coordinate
X
Y
SEG35
-3559
1937
132
SEG36
-3559
1812
2504
133
SEG37
-3559
1687
649
2504
134
SEG38
-3559
1562
SEG5
524
2504
135
SEG39
-3559
1437
102
SEG6
399
2504
136
SEG40
-3559
1312
103
SEG7
274
2504
137
SEG41
-3559
1187
104
SEG8
149
2504
138
SEG42
-3559
1062
105
SEG9
24
2504
139
SEG43
-3559
937
106
SEG10
-100
2504
140
SEG44
-3559
812
107
SEG11
-225
2504
141
SEG45
-3559
687
108
SEG12
-350
2504
142
SEG46
-3559
562
109
SEG13
-475
2504
143
SEG47
-3559
437
110
SEG14
-600
2504
144
SEG48
-3559
312
111
SEG15
-725
2504
145
SEG49
-3559
187
112
SEG16
-850
2504
146
SEG50
-3559
62
113
SEG17
-975
2504
147
SEG51
-3559
-62
114
SEG18
-1100
2504
148
SEG52
-3559
-187
115
SEG19
-1225
2504
149
SEG53
-3559
-312
116
SEG20
-1350
2504
150
SEG54
-3559
-437
117
SEG21
-1475
2504
151
SEG55
-3559
-562
118
SEG22
-1600
2504
152
SEG56
-3559
-687
119
SEG23
-1725
2504
153
SEG57
-3559
-812
120
SEG24
-1850
2504
154
SEG58
-3559
-937
121
SEG25
-1975
2504
155
SEG59
-3559
-1062
122
SEG26
-2100
2504
156
SEG60
-3559
-1187
123
SEG27
-2225
2504
157
SEG61
-3559
-1312
124
SEG28
-2350
2504
158
SEG62
-3559
-1437
125
SEG29
-2475
2504
159
SEG63
-3559
-1562
126
SEG30
-2600
2504
160
SEG64
-3559
-1687
127
SEG31
-2725
2504
161
SEG65
-3559
-1812
128
SEG32
-2850
2504
162
SEG66
-3559
-1937
129
SEG33
-2975
2504
163
SEG67
-3559
-2062
130
SEG34
-3559
2062
Pad
No.
Pad
Name
Coordinate
X
Y
7
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
PAD DESCRIPTION
Table 2. Pad Description
Pad (No)
Input/
Output
Name
VDD (51)
VSS1, VSS2
(57,72)
-
0V (GND)
Power supply
Power supply
Bias voltage level for LCD driving.
Input voltage to the voltage converter to
generate LCD drive voltage
(Vci = 2.5 - 4.5V).
Input
SEG1 - SEG100
(97- 33)
Output
Segment output
Segment signal output for LCD drive.
LCD
COM0 - COM33
(80 - 96, 34 - 50)
Output
Common output
Common signal output for LCD drive.
LCD
Oscillator
When use internal oscillator, connect
external Rf resistor.
If external clock is used, connect it to
OSC1.
External
resistor/oscillator
(OSC1)
OSC1, OSC2
(53, 52)
Input
(OSC1),
Output
(OSC2)
C1, C2
(71, 70)
Input
External
capacitance
input
To use the voltage converter (2 times /3
times), these pins must be connected to
the external capacitance.
RESET (54)
Input
Reset pin
Initialized to low
-
IE (56)
Input
Select pin of
instruction set
When IE = "High", Instruction set is
selected as Table 6. When IE = "Low",
Instruction set is selected as Table 10.
-
Two times
converter output
The value of Vci is converted two times.
To use three times converter, the same
capacitance as that of C1-C2 should be
connected here.
Three times
converter output
The value of Vci is converted three
times.
Interface mode
selection
Select Interface mode with the MPU.
When IM = "Low": Serial mode,
When IM = "High": 4-bit/8-bit bus mode.
V5OUT2 (73)
Output
V5OUT3 (74)
IM (55)
8
Interface
for logical circuit (+3V, +5V)
V1 - V5
(79 - 75)
Vci (69)
Description
Input
External
capacitance
V5 capacitance
V5
-
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
Table 2. Pad Description (Continued)
Pad (No)
RS/CS (58)
Input/
Output
Input
Name
When bus mode, used as register
selection input.
When RS/CS = "High", data register is
selected.
When RS/CS = "Low", instruction
Register select/
register is selected.
chip select
When serial mode, used as chip
selection input.
When RS/CS = "Low", selected.
When RS/CS = "High", not elected.
(low access enable)
Read/Write/
RW/SID (59)
E/SCLK (60)
DB0/SOD (61)
Input
Input
Read/Write
Enable/Serial
clock
Data bus 1-7
Input.Output
DB4 - DB7
(65 - 68)
Serial input
data
Data bus 0
Input.Output/
bit/serial output
Output
data
DB1 - DB3
(62 - 64)
Description
Interface
MPU
When bus mode, used as read/write
selection input.
When RW/SID = "High", read operation.
When RW/SID = "Low", write operation.
When serial mode, used for data input
pin.
MPU
When bus mode, used as read/write
enable signal.
When serial mode, used as serial clock
input pin.
MPU
When 8-bit bus mode, used as lowest bidirectional data bit. During 4-bit bus
mode, open this pin.
When serial mode, used as serial data
output pin. If not in read operation, open
this pin.
MPU
When 8-bit bus mode, used as low order
bi-directional data bus.
During 4-bit bus mode or serial mode,
open these pins.
MPU
When 8-bit bus mode, used as high
order bi-directional data bus. In case of
4-bit bus mode, used as both high and
low order. DB7 used for busy flag output.
During serial mode, open these pins.
MPU
9
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
FUNCTION DESCRIPTION
SYSTEM INTERFACE
This chip has all three kinds interface type with MPU: serial, 4-bit bus and 8-bit bus. Serial and bus (4-bit/8-bit) is
selected by IM input, and 4-bit bus and 8-bit bus is selected by DL bit in the instruction register. During read or
write operation, two 8-bit registers are used. one is data register (DR), the other is instruction register (IR). The
data register (DR) is used as temporary data storage place for being written into or read from
DDRAM/CGRAM/SEGRAM, target RAM is selected by RAM address setting instruction. Each internal operation,
reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the data in the
next DDRAM/CGRAM/SEGRAM address is transferred into DR automatically. Also after MPU writes data to DR,
the data in DR is transferred into DDRAM/CGRAM/SEGRAM automatically. The Instruction register (IR) is used
only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select
register, use RS/CS input pin in 4-bit/8-bit bus mode (IM = "High") or RS bit in serial mode (IM = "Low").
10
RS
R/W
Operation
0
0
Instruction write operation (MPU writes Instruction code into IR)
0
1
Read busy flag (DB7) and address counter (DB0 - DB6)
1
0
Data write operation (MPU writes data into DR)
1
1
Data read operation (MPU reads data from DR)
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
BUSY FLAG (BF)
When BF = "High", it indicates that the internal operation is being processed. So during this time the next
instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation),
through DB7. Before executing the next instruction, be sure that BF is not high.
DISPLAY DATA RAM (DDRAM)
DDRAM stores display data of maximum 80 x 8 bits (80 characters). DDRAM address is set in the address
counter (AC) as a hexadecimal number. (refer to Figure 1.)
MSB
LSB
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Figure 1. DDRAM Address
Display of 5-Dot Font Width Character
5-dot 1-line Display
In case of 1-line display with 5-dot font, the address range of DDRAM is 00H-4FH. (refer to Figure 2)
COM1
COM8
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13
SEG1
SEG100
S6A0075
Display Position
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27
SEG1
DDRAM Address
COM9
COM16
SEG100
S6A0075
COM1
COM8
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 1F 10 11 12 13 14
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28
COM9
COM16
(After Shift Left)
1
COM1
COM8
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
4F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 1F 10 11 12
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26
COM9
COM16
(After Shift Right)
Figure 2. 1-line x 40ch. Display
11
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
5-dot 2-line Display
In case of 2-line display with 5-dot font, the address range of DDRAM is 00H-27H, 40H-67H (refer to Figure 3).
1
COM1
COM8
COM17
COM24
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53
SEG100
SEG1
S6A0075
Display Position
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27
54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67
SEG1
DDRAM Address
COM9
COM16
COM25
COM32
SEG100
S6A0075
1
COM1
COM8
COM17
COM24
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14
41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 00
55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 40
COM9
COM16
COM25
COM32
(After Shift Left)
1
COM1
COM8
COM17
COM24
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12
67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26
53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66
(After Shift Right)
Figure 3. 2-line x 40ch. Display (5-dot Font Width)
12
COM9
COM16
COM25
COM32
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
5-dot 4-line Display
In case of 4-line display with 5-dot font, the address range of DDARM is 00H-13H, 20H-33H, 40H -53H, 60H-73H
(refer to Figure 4).
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
1
2
3
4
5
6
7
8
10 11 12 13 14 15 16 17 18 19 20
Display Position
DDRAM Address
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53
60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73
SEG1
1
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
9
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13
2
S6A0075
3
4
5
6
7
8
9
SEG100
10 11 12 13 14 15 16 17 18 19 20
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 00
21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 20
41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 40
61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 60
(After Shift Left)
1
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
13 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12
33 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32
53 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52
73 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72
(After Shift Right)
Figure 4. 4-line x 20ch. Display (5-dot Font Width)
13
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
DISPLAY OF 6-DOT FONT WIDTH CHARACTER
When this device is used in 6-dot font width mode, SEG97, SEG98, SEG99 and SEG100 must be open.
6-dot 1-line Display
In case of 1-line display with 6-dot font, the address range of DDRAM is 00H-4FH (refer to Figure 5).
Display Position
1
COM1
COM8
10 11 12 13 14 15 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
2
3
4
5
6
10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
SEG1
7
8
9
SEG96 SEG1
S6A0075
DDRAM Address
COM9
COM16
SEG96
S6A0075
1
COM1
COM8
10 11 12 13 14 15 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
2
3
4
5
6
7
8
9
11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20
COM9
COM16
(After Shift Left)
1
COM1
COM8
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
4F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E
COM9
COM16
(After Shift Right)
Figure 5. 1-line × 32ch. Display
6-dot 2-line Display
In case of 2-line display with 6-dot font, the address range of DDRAM is 00H-27H, 40H-67H (refer to Figure 6).
Display Position
1
COM1
COM8
COM17
COM24
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
COM9
COM16
COM25
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F
COM32
SEG1
SEG96
SEG96 SEG1
DDRAM
Address
S6A0075
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
S6A0075
1
COM1
COM8
COM17
COM24
10 11 12 13 14 15 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
2
3
4
5
6
7
8
9
11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20
41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50
COM9
COM16
COM25
51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60
COM32
(After Shift Left)
1
COM1
COM8
COM17
COM24
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E
67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E
COM9
COM16
COM25
4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E
COM32
(After Shift Right)
Figure 6. 2-line × 32ch. Display (6-dot font width)
14
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
6-dot 4-line Display
In case of 4-line display with 6-dot font, the address range of DDARM is 00H-13H, 20H-33H, 40H-53H, 60H-73H
(refer to Figure 7).
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
1
2
3
4
5
6
7
8
10 11 12 13 14 15 16
Display Position
DDRAM Address
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F
60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F
SEG1
1
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
9
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
2
S6A0075
3
4
5
6
7
8
9
SEG96
10 11 12 13 14 15 16
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30
41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50
61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70
(After Shift Left)
1
COM1
COM8
COM9
COM16
COM17
COM24
COM25
COM32
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
13 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
33 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E
53 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E
73 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E
(After Shift Right)
Figure 7. 4-line × 16ch. Display (6-dot Font Width)
15
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
TIMING GENERATION CIRCUIT
Timing generation circuit generates clock signals for the internal operations.
ADDRESS COUNTER (AC)
Address Counter(AC) stores DDRAM/CGRAM/SEGRAM address, transferred from IR. After writing into (reading
from) DDRAM/CGRAM/SEGRAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W =
"High", AC can be read through DB0-DB6
CURSOR/BLINK CONTROL CIRCUIT
It controls cursor/blink ON/OFF and black/white inversion at cursor position.
LCD DRIVER CIRCUIT
LCD Driver circuit has 34 common and 100 segment signals for LCD driving. Data from
SEGRAM/CGRAM/CGROM is transferred to 100-bit segment latch serially, and then it is stored to 100-bit shift
latch. When each com is selected by 34-bit common register, segment data also output through segment driver
from 100-bit segment latch. In case of 1-line display mode, COM0-COM17 have 1/17 duty, and in 2-line or 4-line
mode, COM0-COM33 have 1/33 duty ratio.
16
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
CGROM (CHARACTER GENERATOR ROM)
CGROM has 5 × 8 dots 240 Character Pattern.
CGRAM (CHARACTER GENERATOR RAM)
CGRAM has up to 5 × 8 dots 8 characters. By writing font data to CGRAM, user defined character can be used
(refer to Table 4).
5 × 8 dots Character Pattern
Table 4. Relationship between Character Code(DDRAM) and Character Pattern(CGRAM)
Character Code (DDRAM data)
CGRAM Address
CGRAM Data
D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0
0
0
0
0
x
0
0
0
0
0
0
0
0
0 B1 B0 x
0
1
1
1
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
1
1
.
.
.
0
1
1
1
1
1
1
1
.
.
.
.
.
.
1
0
0
0
0
0
1
1
.
.
.
1
0
1
1
0
0
0
1
.
.
.
1
1
0
1
0
0
0
1
1
.
.
0
0
0
0
.
.
x
.
.
.
.
.
1
1
1
1
1
.
.
.
.
.
1
1
0
.
.
1
0
0
0
0
0
1
1
0
0
1
0
1
0
1
1
1
0
1
1
1
0
1
B1 B0
.
.
.
.
.
x
Pattern 1
0
.
.
.
.
0
0
0
0
1
Pattern
Number
1
0
0
0
1
1
1
0
0
1
0
0
0
1
0
1
1
1
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
Pattern 8
1
1
17
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
6 x 8 Dots Character Pattern
Character Code (DDRAM data)
CGRAM Address
CGRAM Data
D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0
0
0
0
0
x
0
0
0
0
0
0
0
0
0 B1 B0 0
0
1
1
1
0
0
0
1
0
1
0
0
0
1
0
1
0
0
1
0
0
0
1
.
.
.
0
0
1
1
1
1
1
1
1
.
.
.
.
.
.
0
1
0
0
1
0
0
0
1
.
.
.
0
1
0
1
1
0
0
0
1
.
.
.
0
1
1
0
1
0
0
0
1
1
1
1
0
0
0
0
0
0
.
.
0
0
0
0
x
.
.
.
.
.
1.
2
18
.
.
1
1
1
1
1
.
.
.
.
.
.
.
1
.
.
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
B1 B0
.
.
.
.
.
Pattern
Number
Pattern 1
.
.
0
1
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
0
Pattern 8
When BE (Blink Enable bit) = "High", blink is controlled by B1 and B0 bit.
In case of 5-dot font width, when B1 = "1", enabled dots of P0-P4 will blink, and when B1 = "0" and B0 = "1", enabled
dots in P4 will blink, when B1 = "0" and B0 = "0", blink will not happen.
In case of 6-dot font width, when B1 = "1", enabled dots of P0-P5 will blink, and when B1 = "0" and B0 = "1", enabled
dots of P5 will blink, when B1 = "0" and B0 = "0", blink will not happen.
"X": Don't care
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
SEGRAM (SEGMENT ICON RAM)
SEGRAM has segment control data and segment pattern data. During 1-line display mode, COM0 (COM17)
makes the data of SEGRAM enable to display icons. When used in 2/4-line display mode COM0 (COM33) does
that. Its higher 2-bit are blinking control data, and lower 6-bits are pattern data (refer to Table 5 and Figure 8).
Table 5. Relationship between SEGRAM Address and Display Pattern
SEGRAM Data Display Pattern
SEGRAM Address
5-dot Font Width
6-dot Font Width
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
B1
B0
X
S1
S2
S3
S4
S5
B1
B0
S1
S2
S3
S4
S5
S6
0
0
0
1
B1
B0
X
S6
S7
S8
S9
S10
B1
B0
S7
S8
S9
S10
S11
S12
0
0
1
0
B1
B0
X
S11
S12
S13
S14 S15
B1
B0
S13
S14
S15
S16
S17
S18
0
0
1
1
B1
B0
X
S16
S17
S18
S19 S20
B1
B0
S19
S20
S21
S22
S23
S24
0
1
0
0
B1
B0
X
S21
S22
S23
S24 S25
B1
B0
S25
S26
S27
S28
S29
S30
0
1
0
1
B1
B0
X
S26
S27
S28
S29 S30
B1
B0
S31
S32
S33
S34
S35
S36
0
1
1
0
B1
B0
X
S31
S32
S33
S34 S35
B1
B0
S37
S38
S39
S40
S41
S42
0
1
1
1
B1
B0
X
S36
S37
S38
S39 S40
B1
B0
S43
S44
S45
S46
S47
S48
1
0
0
0
B1
B0
X
S41
S42
S43
S44 S45
B1
B0
S49
S50
S51
S52
S53
S54
1
0
0
1
B1
B0
X
S46
S47
S48
S49 S50
B1
B0
S55
S56
S57
S58
S59
S60
1
0
1
0
B1
B0
X
S51
S52
S53
S54 S55
B1
B0
S61
S62
S63
S64
S65
S66
1
0
1
1
B1
B0
X
S56
S57
S58
S59 S60
B1
B0
S67
S68
S69
S70
S71
S72
1
1
0
0
B1
B0
X
S61
S62
S63
S64 S65
B1
B0
S73
S74
S75
S76
S77
S78
1
1
0
1
B1
B0
X
S66
S67
S68
S69 S70
B1
B0
S79
S80
S81
S82
S83
S84
1
1
1
0
B1
B0
X
S71
S72
S73
S74 S75
B1
B0
S85
S86
S87
S88
S89
S90
1
1
1
1
B1
B0
X
S76
S77
S78
S79 S80
B1
B0
S91
S92
S93
S94
S95
S96
1.
B1, B0: Blinking control bit
Control Bit
1.
2.
Blinking Port
BE B1 B0
5-dot font width
6-dot font width
0 X X
No blink
No blink
1 0 0
No blink
No blink
1 0 1
D4
D5
1 1 X
D4 - D0
D5 - D0
S1-S80 : Icon pattern ON/OFF in 5-dot font width
S1-S96 : Icon pattern ON/OFF in 6-dot font width
"X": Don't care.
19
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
SEG9
SEG100
SEG8
SEG99
SEG7
SEG98
SEG6
...
SEG97
SEG5
S96 S97 S98 S99 S100
SEG96
SEG4
SEG85
SEG3
...
S81 S82 S83 S84 S85
SEG84
SEG2
S76 S77 S78 S79 S80
SEG83
S9 S10
SEG82
S8
SEG81
S7
SEG80
S6
SEG79
S5
SEG78
S4
SEG77
S3
SEG76
S2
SEG10
S1
SEG1
5-Dot Font Width (FW = 0)
20
SEG8
SEG9
SEG96
SEG7
SEG95
SEG6
SEG94
SEG5
SEG93
SEG4
Figure 8. Relationship between SEGRAM and Segment Display
SEG92
SEG3
...
SEG91
SEG2
...
S85 S86 S87 S88 S89 S90 S91 S92 S93 S94 S95 S96
SEG90
S9 S10 S11 S12
SEG89
S8
SEG88
S7
SEG87
S6
SEG86
S5
SEG85
S4
SEG12
S3
SEG11
S2
SEG10
S1
SEG1
6-Dot Font Width (FW = 1)
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
INSTRUCTION DESCRIPTION
OUTLINE
To overcome the speed difference between internal clock of S6A0075 and MPU clock, S6A0075 performs
internal operation by storing control information to IR or DR. The internal operation is determined according to the
signal from MPU, composed of read/write and data bus. (refer to Table 6/10) Instruction can be divided largely
four kinds,
•
S6A0075 function set instructions (set display methods, set data length, etc.)
•
Address set instructions to internal RAM
•
Data transfer instructions with internal RAM
•
Others .
The address of internal RAM is automatically increased or decreased by 1.
When IE = "High", S6A0075 is operated according to instruction set 1 (Table 6) and when IE = "Low", S6A0075 is
operated according to instruction set 2 (Table 10).
NOTE: During internal operation, busy flag (DB7) is read high. Busy flag check must precede the next instruction. When an
MPU program with Busy Flag (DB7) checking is made, 1/2 fosc (is necessary) for executing the next instruction by
the falling edge of the “E” signal after the Busy Flag (DB7) goes to “Low”.
21
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
INSTRUCTION DESCRIPTION 1 (IE = "HIGH")
Table 6. Instruction Set 1
Instruction Code
Instruction RE
Clear
display
Return
home
Power
down
mode
X
0
1
0
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
I/D
1
Write "20H" to DDRAM. and
set DDRAM address to "00H"
from AC.
x
Set DDRAM address to "00H"
from AC and return cursor to its
original position if shifted. The
1.53ms
contents of DDRAM are not
changed.
PD
Set power down mode bit.
PD = "1":power down mode set,
PD = "0":power down mode
disable
S
Assign cursor moving direction.
I/D = "1": increment,
I/D = "0": decrement and
display shift enable
bit.
S = "1": make display shift of
the enabled lines by
the DS4
DS1 bits in the shift enable
instruction.
S = "0": display shift disable
Entry
mode set
1
Display
ON/OFF
Control
22
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
D
1
C
Description
Executi
on Time
(fosc =
270kHz)
B/D
Segment bi-direction function.
BID = "0": Seg1 → Seg80,
BID = "1": Seg80 → Seg1.
B
Set display/cursor/blink on/off
D = "1": display on,
D = "0": display off,
C = "1": cursor on,
C = "0": cursor off,
B = "1": blink on,
B = "0": blink off.
1.53ms
39µs
39µs
39µs
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
Table 6. Instruction Set 1 (Continued)
Instruction Code
Instruction RE
Extended
function
set
Cursor or
Display
Shift
Shift
Enable
Scroll
enable
1
0
1
1
Description
Executi
on Time
(fosc =
270kHz)
FW B/W NW
Assign font width, black/white
inverting of cursor, and 4-line
display mode control bit.
FW = "1": 6-dot font width,
FW = "0": 5-dot font width,
B/W = "1": black/white inverting of
cursor enable,
B/W = "0": black/white inverting of
cursor disable
NW = "1": 4-line display mode,
NW = "0": 1-line or 2-line display
mode.
39µs
R/L
Cursor or display shift.
S/C = "1": display shift,
S/C = "0": cursor shift,
R/L = "1": shift to right,
R/L = "0": shift to left.
39µs
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
S/C
x
x
1
(when DH = "1")
Determine the line for display shift.
DS1 = "1/0": 1st line display shift
enable/disable
DS2 = "1/0": 2nd line display shift
DS4 DS3 DS2 DS1
enable/disable
DS3 = "1/0": 3rd line display shift
enable/disable
DS4 = "1/0": 4th line display shift
enable/disable.
39µs
1
(when DH = "0")
Determine the line for horizontal
smooth scroll.
HS1 = "1/0": 1st line dot scroll
enable/disable
HS4 HS3 HS2 HS1 HS2 = "1/0": 2nd line dot scroll
enable/disable
HS3 = "1/0": 3rd line dot scroll
enable/disable
HS4 = "1/0": 4th line dot scroll
enable/disable.
39µs
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S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Table 6. Instruction Set 1 (Continued)
Instruction Code
Instruction RE
0
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
DL
N
RE
(0)
DH
REV
Function
set
1
0
0
0
0
Set
CGRAM
address
0
0
0
0
1
Set
SEGRAM
address
1
0
0
0
1
Set
DDRAM
address
0
0
0
1
Set scroll
quantity
1
0
0
1
1
DL
N
RE
(1)
BE
0
AC5 AC4 AC3 AC2 AC1 AC0
X
X
AC3 AC2 AC1 AC0
AC6 AC5 AC4 AC3 AC2 AC1 AC0
X
QC
5
QC
4
QC
3
QC
2
QC
1
QC
0
Description
Executio
n Time
(fosc =
270kHz)
Set interface data length
(DL = "1": 8-bit, DL = "0": 4-bit),
numbers of display line when
NW = "0", (N = "1": 2-line, N = "0" :
1-line), extension register, RE("0"),
shift/scroll enable
DH = "1": display shift enable
DH = "0": dot scroll enable. reverse
bit REV = "1": reverse display,
REV = "0": normal display.
39µs
Set DL, N, RE("1") and
CGRAM/SEGRAM blink enable
BE)
BE = " 1/0": CGRAM/SEGRAM
blink enable/disable
39µs
Set CGRAM address in address
counter.
39µs
Set SEGRAM address in address
counter.
39µs
Set DDRAM address in address
counter.
39µs
Set the quantity of horizontal dot
scroll.
39µs
Can be known whether during
internal operation or not by
reading BF. The contents of
AC6 AC5 AC4 AC3 AC2 AC1 AC0
address counter can also be read.
BF = "1": busy state
BF = "0": ready state
Read busy
flag and
address
X
0
1
BF
Write data
X
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write data into internal RAM
(DDRAM / CGRAM / SEGRAM).
43µs
Read data
X
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read data from internal RAM
(DDRAM / CGRAM / SEGRAM).
43µs
0µs
NOTES:
1. When an MPU program with busy flag (DB7) checking is made, 1/2 fosc (is necessary) for executing the next instruction
by the "E" signal after the busy flag (DB7) goes to "Low"
2. "X": Don’t care
24
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
Display Clear
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
1
Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H"
into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first
line of the display. Make entry mode increment (I/D = "1").
Return Home: (RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
1
X
Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return
cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change.
Power Down Mode Set: (RE = 1)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
0
0
1
PD
Power down mode enable bit set instruction. When PD = "High", it makes S6A0075 suppress current
consumption except the current needed for data storage by executing next three functions.
•
Make the output value of all the COM/SEG ports VDD
•
Make the COM/SEG output value of extension driver VDD by setting D output to "High" and M output to
"Low"
•
Disable voltage converter to remove the current through the divide resistor of power supply.
You can use this instruction as power sleep mode.
When PD = "Low", power down mode becomes disabled.
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S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Entry Mode Set
(RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
1
I/D
S
Set the moving direction of cursor and display.
I/D:
Increment/decrement of DDRAM address (cursor or blink)
When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1.
When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1.
- CGRAM/SEGRAM operates the same as DDRAM, when read from or write to CGRAM/SEGRAM.
When S = "High", after DDRAM write, the display of enabled line by DS1 - DS4 bits in the shift enable instruction
is shifted to the right (I/D = "0") or to the left (I/D = "1"). But it will seem as if the cursor does not move. When S =
"Low", or DDRAM read, or CGRAM/SEGRAM read/write operation, shift of display like this function is not
performed.
(RE = 1)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
1
1
BID
Set the data shift direction of segment in the application set.
BID:
Data shift direction of segment
When BID = "Low", segment data shift direction is set to normal order from SEG1 to SEG100.
When BID = "High", segment data shift direction is set to reverse from SEG100 to SEG1.
By using this instruction, you can raise the efficiency of application board area.
- The BID setting instruction is recommended to be set at the same time level of function set instruction.
- DB1 bit must be set to "1".
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
Display ON / OFF Control (RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
1
D
C
B
Control display/cursor/blink ON/OFF 1 bit register.
D:
Display ON/OFF control bit
When D = "High", entire display is turned on.
When D = "Low", display is turned off, but display data is remained in DDRAM.
C:
Cursor ON/OFF control bit
When C = "High", cursor is turned on.
When C = "Low", cursor is disappeared in current display, but I/D register remains its data.
B:
Cursor Blink ON/OFF control bit
When B = "High", cursor blink is on, that performs alternate between all the high data and display
character at the cursor position. If fosc has 270kHz frequency, blinking has 370 ms interval.
When B = "Low", blink is off.
Extended Function Set (RE = 1)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
1
FW
B/W
NW
FW:
Font Width control
When FW = "High", display character font width is assigned to 6-dot and execution time becomes 6/5
times than that of 5-dot font width.
The user font, specified in CGRAM, is displayed into 6-dot font width, bit-5 to bit-0,including the leftmost
space bit of CGRAM.(refer to Figure 9)
When FW = "Low", 5-dot font width is set.
B/W:
Black/White Inversion enable bit
When B/W = "High", black/white inversion at the cursor position is set. In this case C/B bit of display
ON/OFF control instruction becomes don't care condition. If fosc has frequency of 270kHz, inversion
has 370 ms intervals.
NW:
4 Line mode enable bit
When NW = "High", 4 line display mode is set. In this case N bit of function set instruction becomes don't
care condition.
6-bit
S
p
a
c
e
CGROM
Characte
Font
(5-dot)
CGROM
6-bit
8-bit
CGRAM
Characte
Font
(6-dot)
8-bit
CGRAM
Figure 9. 6-dot Font Width CGROM/CGRAM
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Cursor or Display Shift (RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
S/C
R/L
X
X
Shift right/left cursor position or display, without writing or reading of display data, this instruction is use to correct
or search display data (refer to Table 7). During 2-line mode display, cursor moves to the 2nd line after 40th digit
of 1st line. When 4-line mode, cursor moves to the next line, only after every 20th digit of the current line. Note
that display shift is performed simultaneously in all the line enabled by DS1-DS4 in the shift enable instruction.
When displayed data is shifted repeatedly, each line shifted individually. When display shift is performed, the
contents of address counter are not changed. During low power consumption mode, display shift may not be
performed normally.
Table 7. Shift Patterns According to S/C and R/L Bits
28
S/C
R/L
Operation
0
0
Shift cursor to the left, address counter is decreased by 1
0
1
Shift cursor to the right, address counter is increased by 1
1
0
Shift all the display to the left, cursor moves according to the display
1
1
Shift all the display to the right, cursor moves according to the display
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
Shift/Scroll Enable (RE = 1)
(DH = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
HS4
HS3
HS2
HS1
HS:
Horizontal scroll per line enable
This instruction makes valid dot shift by a display line unit. HS1, HS2, HS3 and HS4 indicate each line to
be dot scrolled, and each scroll is performed individually in each line.
If you want to scroll the line in 1-line display mode or the 1st line in 2-line display mode, set HS1 and
HS2 to "High".
If the 2nd line scroll is needed in 2-line mode, set HS3 and HS4 to "High". (refer to Table 8)
(DH = 1)
DS:
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
DS4
DS3
DS2
DS1
Display shift per line enable this instruction selects shifting line to be shifted according to each line
mode in display shift right/left instruction. DS1, DS2, DS3 and DS4 indicate each line to be shifted, and
each shift is performed individually in each line.
If you set DS1 and DS2 to "High" (enable) in 2 line mode, only the 1st line is shifted and the 2nd line is
not shifted. When only DS1 = "High", only the half of the 1st line is shifted. If all the DS bits (DS1 to DS4)
are set to "Low" (disable), no display is shifted.
Table 8. Relationship between DS and COM signal
Enable Bit
Enabled Common Signals
During Shift
Description
HS1/DS1
COM1 - COM8
HS2/DS2
COM9 - COM16
The part of display line that corresponds to enabled
HS3/DS3
COM17 - COM24
common signal can be shifted.
HS4/DS4
COM25 - COM32
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S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Function Set
(RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
DL
N
RE(0)
DH
REV
DL:
Interface data length control bit
When DL = "High", it means 8-bit bus mode with MPU.
When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit
bus mode.
When 4-bit bus mode, it needs to transfer 4-bit data by two times.
N:
Display line number control bit
It is variable only when NW bit of extended function set instruction is low.
When N = "Low", it means 1-line display mode.
When N = "High", 2-line display mode is set.
When NW = "High", N bit is invalid, it means 4-line mode independent of N bit.
RE:
Extended function registers enable bit
At this instruction, RE must be "Low".
DH:
Display shift enable selection bit.
When DH = "High", display shift per line becomes enable.
When DH = "Low", smooth dot scroll becomes enable.
This bit can be accessed only when IE pin input is "High".
REV:
Reverse enable bit
When REV = "High", all the display data are reversed. Namely, all the white dots become black and
black dots become white.
When REV = "Low", the display mode set normal display.
(RE = 1)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
DL
N
RE(1)
BE
0
DL:
Interface data length control bit
When DL = "High", it means 8-bit bus mode with MPU.
When DL = "Low", it means 4-bit bus mode with MPU.
So to speak, DL is a signal to select 8-bit or 4-bit bus mode.
When 4-bit bus mode, it needs to transfer 4-bit data by two times.
N:
Display line number control bit
It is variable only when NW bit of extended function set instruction is Low.
When N = "Low", it means 1-line display mode.
When N = "High", 2-line display mode is set.
When NW = "High", N bit is invalid, it means 4-line mode independent of N bit.
RE:
Extended function registers enable bit
When RE = "High", extended function set registers, SEGRAM address set registers, BID bit, HS/DS bits
of shift/scroll enable instruction and BE bits of function set register can be accessed.
BE:
CGRAM/SEGRAM data blink enable bit
If BE is "High", It makes user font of CGRAM and segment of SEGRAM blink. The quantity of blink is
assigned the highest 2 bit of CGRAM/SEGRAM.
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
Set CGRAM Address (RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
AC5
AC4
AC3
AC2
AC1
AC0
Set CGRAM address to AC. This instruction makes CGRAM data available from MPU.
Set SEGRAM Address (RE = 1)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
X
X
AC3
AC2
AC1
AC0
Set CGRAM address to AC. This instruction makes CGRAM data available from MPU.
Set DDRAM Address (RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. When 1-line display mode
(N = 0, NW = 0), DDRAM address is from "00H" to "4FH". In 2-line display mode (N = 1, NW = 0), DDRAM
address in the 1st line is from "00H" - "27H", and DDRAM address in the 2nd line is from "40H" - "67H". In 4-line
display mode (NW = 1), DDRAM address is from "00H" - "13H" in the 1st line, from "20H" to "33H" in the 2nd
line, from "40H" - "53H" in the 3rd line and from "60H" - "73H" in the 4th line.
Set Scroll Quantity (RE = 1)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
X
SQ
SQ4
SQ3
SQ2
SQ1
SQ0
As set SQ5 to SQ0, horizontal scroll quantity can be controlled in dot units (Refer to Table 9). In this case
S6A0075 can show hidden areas of DDRAM by executing smooth scroll from 1 to 48 dots.
Table 9. Scroll Quantity According to HDS bits
SQ5
SQ4
SQ3
SQ2
SQ1
SQ0
Function
0
0
0
0
0
0
No shift
0
0
0
0
0
1
Shift left by 1-dot
0
0
0
0
1
0
Shift left by 2-dot
0
0
0
0
1
1
Shift left by 3-dot
:
:
:
:
:
:
:
1
0
1
1
1
1
Shift left by 47-dot
1
1
X
X
X
X
Shift left by 48-dot
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Read Busy Flag & Address
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
BF
AC6
AC5
AC4
AC3
AC2
AC1
AC0
This instruction shows whether S6A0075 is in internal operation or not. If the resultant BF is High, it means the
internal operation is in progress and you have to wait until BF to be Low, and then the next instruction can be
performed. In this instruction you can read also the value of address counter.
Write Data to RAM
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write binary 8-bit data to DDRAM/CGRAM/SEGRAM. The selection of RAM from DDRAM, CGRAM, or
SEGRAM, is set by the previous address set instruction: DDRAM address set, CGRAM address set, SEGRAM
address set. RAM set instruction can also determines the AC direction to RAM. After write operation, the address
is automatically increased/decreased by 1, according to the entry mode.
Read Data From RAM
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read binary 8-bit data from DDRAM/CGRAM/SEGRAM. The selection of RAM is set by the previous address set
instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is
invalid, because the direction of AC is not determined. If you read RAM data several times without RAM address
set instruction before read operation, you can get correct RAM data from the second, but the first data would be
incorrect, because there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift
instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output data
register. After read operation address counter is automatically increased/decreased by 1 according to the entry
mode. After CGRAM/SEGRAM read operation, display shift may not be executed correctly. In case of RAM write
operation, after this AC is increased/decreased by 1 like read operation. In this time, AC indicates the next
address position, but you can read only the previous data by read instruction.
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
INSTRUCTION DESCRIPTION 2 (IE = "LOW")
Table 10. Instruction Set 2
Instruction Code
Instruction RE
Clear
display
Return
home
Entry
mode set
Display
ON/OFF
control
Extended
function
set
Cursor or
display
shift
X
X
X
0
1
0
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
S/L
Description
Executi
on Time
(fosc =
270kHz)
1
Write "20H" to DDRAM. and set
DDRAM address to "00H" from
AC.
1.53ms
x
Set DDRAM address to "00H" from
AC and return cursor to its original
position if shifted. The contents of
DDRAM are not changed.
1.53ms
S
Assign cursor moving direction.
I/D = "1": increment,
I/D = "0": decrement. and display
shift enable bit.
S = "1": make entire display shift
of all lines during DDRAM write,
S = "0": display shift disable
39µs
B
Set display/cursor/blink on/off
D = "1": display on,
D = "0": display off,
C = "1": cursor on,
C = "0": cursor off,
B = "1": blink on,
B = "0": blink off.
39µs
FW B/W NW
Assign font width, black/white
inverting of cursor, and 4-line
display mode control bit.
FW = "1": 6-dot font width,
FW = "0": 5-dot font width,
B/W = "1": black/white inverting of
cursor enable,
B/W = "0": black/white inverting of
cursor disable
NW = "1": 4-line display mode,
NW = "0": 1-line or 2-line display
mode
39µs
R/L
Cursor or display shift.
S/C = "1": display shift,
S/C = "0": cursor shift,
R/L = "1": shift to right,
R/L = "0": shift to left
39µs
0
0
1
D
0
1
I/D
C
X
X
33
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Table 10. Instruction Set 2 (Continued)
Instruction Code
Instruction RE
Scroll
Enable
1
0
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
1
1
DL
Determine the line for horizontal
smooth scroll.
HS1 = "1/0": 1st line dot scroll
enable/disable
HS2 = "1/0": 2nd line dot scroll
HS4 HS3 HS2 HS1
enable/disable
HS3 = "1/0": 3rd line dot scroll
enable/disable
HS4 = "1/0": 4th line dot scroll
enable/disable
N
RE
(0)
X
0
0
0
0
Set
CGRAM
address
0
0
0
0
1
Set
SEGRAM
address
1
0
0
0
1
Set
DDRAM
address
0
0
0
1
Set scroll
quantity
1
0
0
1
Read busy
flag and
address
34
X
0
1
BF
1
DL
N
RE
(1)
BE
X
39µs
0
Set DL, N, RE("1") and
CGRAM/SEGRAM blink enable
(BE)
BE = " 1/0": CGRAM/SEGRAM
blink enable/disable
39µs
Set CGRAM address in address
counter.
39µs
Set SEGRAM address in address
counter.
39µs
Set DDRAM address in address
counter.
39µs
Set the quantity of horizontal dot
scroll.
39µs
AC5 AC4 AC3 AC2 AC1 AC0
X
X
AC3 AC2 AC1 AC0
AC6 AC5 AC4 AC3 AC2 AC1 AC0
X
SQ5
SQ4
SQ3
SQ2 SQ1
39µs
Set interface data length
DL = "1": 8-bit,
DL = "0": 4-bit
numbers of display line when
NW = "0",
N = "1": 2-line,
N = "0": 1-line
extension register, RE("0")
Function
Set
1
Description
Executi
on Time
(fosc =
270kHz)
SQ0
Can be known whether during
internal operation or not by
reading BF. The contents of
AC6 AC5 AC4 AC3 AC2 AC1 AC0
address counter can also be read.
BF = "1": busy state,
BF = "0": ready state.
0µs
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
Table 10. Instruction Set 2 (Continued)
Instruction Code
Instruction RE
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description
Execution
Time
(fosc =
270kHz)
Write data
X
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write data into internal RAM
(DDRAM / CGRAM / SEGRAM).
43µs
Read data
X
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read data from internal RAM
(DDRAM / CGRAM / SEGRAM).
43µs
Note: 1. When an MPU program with Busy Flag (DB7) checking is made, 1/2 fosc (is necessary) for executing the next
instruction by the falling edge of the “E” signal after the Busy Flag (DB7) goes to “Low”.
2. "X": Don’t care.
35
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Display Clear
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
1
Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H"
into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first
line of the display. And entry mode is set to increment mode (I/D = "1").
Return Home
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
1
X
Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return
cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change.
Entry Mode Set
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
1
I/D
S
Set the moving direction of cursor and display.
I/D:
Increment/decrement of DDRAM address (cursor or blink)
When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1.
When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1.
- CGRAM/SEGRAM operates the same as DDRAM, when read from or write to CGRAM/SEGRAM.
When S = "High", after DDRAM write, the entire display of all lines is shifted to the right (I/D = "0") or to the left
(I/D = "1"). But it will seem as if the cursor does not move. When S = "Low", or DDRAM read, or
CGRAM/SEGRAM read/write operation, shift of entire display is not performed.
36
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
Display ON/OFF Control (RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
1
D
C
B
Control display/cursor/blink ON/OFF 1 bit register.
D:
Display ON/OFF control bit
When D = "High", entire display is turned on.
When D = "Low", display is turned off, but display data is remained in DDRAM.
C:
Cursor ON/OFF control bit
When C = "High", cursor is turned on.
When C = "Low", cursor is disappeared in current display, but I/D register remains its data.
B:
Cursor Blink ON/OFF control bit
When B = "High", cursor blink is on, that performs alternate between all the high data and display
character at the cursor position. If fosc has 270kHz frequency, blinking has 370 ms interval.
When B = "Low", blink is off.
Extended Function Set (RE = 1)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
1
FW
B/W
NW
FW:
Font width control
When FW = "High", display character font width is assigned to 6-dot and execution time becomes 6/5
times than that of 5-dot font width.
The user font, specified in CGRAM, is displayed into 6-dot font width, bit-5 to bit-0,including the leftmost
pace bit of CGRAM.(Refer to Fig-10)
When FW = "Low", 5-dot font width is set.
B/W:
Black/White Inversion enable bit
When B/W = "High", black/white inversion at the cursor position is set. In this case C/B bit of display
ON/OFF control instruction becomes don't care condition. If fosc has frequency of 270kHz, inversion
has 370 ms intervals.
NW:
4 Line mode enable bit
When NW = "High", 4 line display mode is set. In this case N bit of function set instruction becomes don't
care condition.
6-bit
S
p
a
c
e
CGROM
Characte
Font
(5-dot)
CGROM
6-bit
8-bit
CGRAM
Characte
Font
(6-dot)
8-bit
CGRAM
Figure 10. 6-dot font width CGROM/CGRAM
37
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Cursor or Display Shift (RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
S/C
R/L
X
X
Without writing or reading of display data, shift right/left cursor position or display. This instruction is used to
correct
or search display data.(Refer to Table 11) during 2-line mode display, cursor moves to the 2nd line after 40th
digit
of 1st line. When 4-line mode, cursor moves to the next line, only after every 20th digit of the current line. Note
that
display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly, each line
shifted
individually. When display shift is performed, the contents of address counter are not changed.
Table 11. Shift Patterns According to S/C and R/L Bits
S/C
R/L
Operation
0
0
Shift cursor to the left, address counter is decreased by 1
0
1
Shift cursor to the right, address counter is increased by 1
1
0
Shift all the display to the left, cursor moves according to the display
1
1
Shift all the display to the right, cursor moves according to the display
Scroll Enable (RE = 1)
HS:
38
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
HS4
HS3
HS2
HS1
Horizontal scroll per line enable
This instruction makes valid dot shift by a display line unit. HS1, HS2, HS3 and HS4 indicate each line to
be dot scrolled, and each scroll is performed individually in each line.
If you want to scroll the line in 1-line display mode or the 1st line in 2-line display mode, set HS1 and
HS2 to "High". If the 2nd line scroll is needed in 2-line mode, set HS3 and HS4 to "High".
(refer to Table 8)
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
Function Set
(RE = 0)
RS
0
DL:
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
DL
N
RE(0)
X
X
Interface data length control bit
When DL = "High", it means 8-bit bus mode with MPU.
When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit
bus mode.
When 4-bit bus mode, it needs to transfer 4-bit data by two times.
N:
Display line number control bit
It is variable only when NW bit of extended function set instruction is Low.
When N = "Low", it means 1-line display mode.
When N = "High", 2-line display mode is set.
When NW = "High", N bit is invalid, it means 4-line mode independent of N bit.
RE:
Extended function registers enable bit
At this instruction, RE must be "Low".
(RE = 1)
RS
0
DL:
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
DL
N
RE(1)
BE
0
Interface data length control bit
When DL = "High", it means 8-bit bus mode with MPU.
When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit
bus mode.
When 4-bit bus mode, it needs to transfer 4-bit data by two times.
N:
Display line number control bit
It is variable only when NW bit of extended function set instruction is Low.
When N = "Low", it means 1-line display mode.
When N = "High", 2-line display mode is set.
When NW = "High", N bit is invalid, it means 4-line mode independent of N bit.
RE:
Extended function registers enable bit
When RE = "High", extended function set registers, SEGRAM address set registers, HS bits of scroll
enable instruction and BE bits of function set register can be accessed.
BE:
CGRAM/SEGRAM data blink enable bit
If BE is "High", It makes user font of CGRAM and segment of SEGRAM blink. The quantity of blink is
assigned the highest 2 bit of CGRAM/SEGRAM.
39
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Set CGRAM Address (RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
AC5
AC4
AC3
AC2
AC1
AC0
Set CGRAM address to AC. This instruction makes CGRAM data available from MPU.
Set SEGRAM Address (RE = 1)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
X
X
AC3
AC2
AC1
AC0
Set SEGRAM address to AC. This instruction makes SEGRAM data available from MPU.
Set DDRAM Address (RE = 0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Set DDRAM address to AC.
This instruction makes DDRAM data available from MPU. When 1-line display mode (N = 0, NW = 0), DDRAM
address is from "00H" to "4FH". In 2-line display mode (N = 1, NW = 0), DDRAM address in the 1st line is from
"00H" to "27H", and DDRAM address in the 2nd line is from "40H" to "67H". In 4-line display mode (NW = 1),
DDRAM address is from "00H" to "13H" in the 1st line, from "20H" to "33H" in the 2nd line, from "40H" to "53H" in
the 3rd line and from "60H" to "73H" in the 4th line.
40
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
Set Scroll Quantity (RE = 1)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
X
SQ5
SQ4
SQ3
SQ2
SQ1
SQ0
As set SQ5 to SQ0, horizontal scroll quantity can be controlled in dot units (refer to Table 12). In this case
S6A0075 execute dot smooth scroll from 1 to 48 dots.
Table 12. Scroll Quantity According to HDS bits
SQ5
SQ4
SQ3
SQ2
SQ1
SQ0
Function
0
0
0
0
0
0
No shift
0
0
0
0
0
1
Shift left by 1-dot
0
0
0
0
1
0
Shift left by 2-dot
0
0
0
0
1
1
Shift left by 3-dot
:
:
:
:
:
:
:
1
0
1
1
1
1
Shift left by 47-dot
1
1
X
X
X
X
Shift left by 48-dot
Read Busy Flag & Address
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
BF
AC6
AC5
AC4
AC3
AC2
AC1
AC0
This instruction shows whether S6A0075 is in internal operation or not. If the resultant BF is High, it means the
internal operation is in progress and you have to wait until BF to be low, and then the next instruction can be
performed. In this instruction you can read also the value of address counter.
Write Data to RAM
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write binary 8-bit data to DDRAM/CGRAM/SEGRAM. The selection of RAM from DDRAM, CGRAM, or
SEGRAM, is set by the previous address set instruction : DDRAM address set, CGRAM address set, SEGRAM
address set. RAM set instruction can also determines the AC direction to RAM. After write operation, the address
is automatically increased/decreased by 1, according to the entry mode.
41
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Read Data From RAM
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read binary 8-bit data from DDRAM/CGRAM/SEGRAM. The selection of RAM is set by the previous address set
instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is
invalid, because the direction of AC is not determined. If you read RAM data several times without RAM address
set instruction before read operation, you can get correct RAM data from the second, but the first data would be
incorrect, because there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift
instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output data
register. After read operation address counter is automatically increased/decreased by 1 according to the entry
mode. After CGRAM/SEGRAM read operation, display shift may not be executed correctly.
- In case of RAM write operation, after this AC is increased/decreased by 1 like read operation. In this time, AC
indicates the next address position, but you can read only the previous data by read instruction.
42
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
INTERFACE WITH MPU
S6A0075 can transfer data in bus mode (4-bit or 8-bit) or serial mode with MPU. So you can use any type 4 or 8bit MPU.
In case of 4-bit bus mode, data transfer is performed by two times to transfer 1 byte data.
•
When interfacing data length are 4-bit, only 4 ports, from DB4 - DB7, are used as data bus.
•
At first higher 4-bit (in case of 8-bit bus mode, the contents of DB4 - DB7) are transferred, and then lower 4bit (in case of 8-bit bus mode, the contents of DB0 - DB3) are transferred. So transfer is performed by two
times. Busy flag outputs "High" after the second transfer are ended.
•
When interfacing data length are 8-bit, transfer is performed at a time through 8 ports, from DB0 - DB7.
•
If IM is set to "Low", serial transfer mode is set.
43
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
INTERFACE WITH MPU IN BUS MODE
Interface with 8-bit MPU
If 8-bit MPU is used, S6A0075 can connect directly with that. In this case, port E, RS, R/W and DB0 - DB7 need
to interface each other. Example of timing sequence is shown below.
RS
R/W
E
Internal Signal
DB7
Internal Operation
Data
Busy
No
Bus
y
Busy Flag
Check
Busy Flag
Check
Busy
Instruction
Busy Flag
Check
Data
Instruction
Figure 11. Example of 8-bit Bus Mode Timing Sequence
Interface with 4-bit MPU
If 4-bit MPU is used, S6A0075 can connect directly with this. In this case, port E, RS, R/W and DB4 - DB7 need
to interface each other. The transfer is performed by two times. Example of timing sequence is shown below.
RS
R/W
E
Internal Signal
DB7
Internal Operation
D7
D3
Instruction
Busy
AC3
Busy Flag Check
No
Busy
AC3
Busy Flag Check
Figure 12. Example of 4-bit Bus Mode Timing Sequence
44
D7
D3
Instruction
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
INTERFACE WITH MPU IN SERIAL MODE
When IM port input is "Low", serial interface mode is started. At this time, all three ports, SCLK (synchronizing
transfer clock), SID (serial input data), and SOD (serial output data), are used. If you want to use S6A0075 with
other chips, chip select port (CS) can be used. By setting CS to "Low", S6A0075 can receive SCLK input. If CS is
set to "High", S6A0075 reset the internal transfer counter.
Before transfer real data, start byte has to be transferred. It is composed of succeeding 5 "High" bits, read write
control bit (R/W), register selection bit (RS) and end bit that indicates the end of start byte. Whenever succeeding
5 "High" bits are detected by S6A0075, it makes serial transfer counter reset and ready to receive next
information.
The next input data are register selection bit that determine which register will be used, and read write control bit
that determine the direction of data. Then end bit is transferred, which must have "Low" value to show the end of
start byte. (Refer to Figure 13. Figure 14)
Write Operation (R/W = 0)
After start byte is transferred from MPU to S6A0075, 8-bit data is transferred which is divided into 2 bytes, each
byte has 4 bit's real data and 4 bit's partition token data. For example, if real data is "10110001" (D0 - D7), then
serially transferred data becomes "1011 0000 0001 0000" where 2nd and 4th 4 bits must be "0000" for safe
transfer. To transfer several bytes continuously without changing RS bit and RW bit, start byte transfer is needed
only at first starting time. Namely, after first start byte is transferred, real data can be transferred succeeding.
Read Operation (R/W = 1)
After start byte is transferred to S6A0075, MPU can receive 8-bit data through the SOD port at a time from the
LSB. Wait time is needed to insert between start byte and data reading, because internal reading from RAM
requires some delay. Continuous data reading is possible like serial write operation. It also needs only one start
bytes, only if you insert some delay between reading operations of each byte. During the reading operation,
S6A0075 observes succeeding 5 "High" from MPU. If it is detected, S6A0075 restarts serial operation at once
and ready to receive RS bit. So in continuous reading operation, SID port must be "Low".
45
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Serial Write Operation
CS (Input)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCLK (Input)
SID (Input)
"1" "1" "1" "1" "1" R/W RS 0 D0 D1 D2 D3 "0" "0" "0" "0" D4 D5 D6 D7 "0" "0" "0" "0"
Starting Byte
Synchronizing
Bit String
Instruction
Lower Data
Upper Data
1'st Byte
2'nd Byte
Serial Read Operation
CS (Input)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SCLK (Input)
SID (Input)
"1" "1" "1" "1" "1" R/W RS "0" "0" "0" "0" "0" "0" "0" "0" "0"
SOD (Output)
D0 D1 D2 D3 D4 D5 D6 D7
Starting Byte
Synchronizing
Bit String
Busy Flag/
Read Data
Lower
Data
Upper
Data
Figure 13. Timing Diagram of Serial Data Transfer
46
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
Continuous Write Operation
SCLK
SID
Wait
Start Byte
1'st Byte
2'nd Byte
Instruction1
Wait
1'st Byte
2'nd Byte
Instruction2
Instruction1
Execution Time
1'st Byte
2'nd Byte
Instruction3
Instruction2
Execution Time
Instruction3
Execution Time
Continuous Read Operation
SCLK
SID
SOD
Wait
Wait
Wait
Start
Byte
Data
Read1
Instruction1
Execution Time
Data
Read2
Instruction2
Execution Time
Data
Read3
Instruction3
Execution Time
Figure 14. Timing Diagram of Continuous Data Transfer
47
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
APPLICATION INFORMATION ACCORDING TO LCD PANEL
LCD Panel: 40 Character x 1-line Format (5-dot Font,1/17 Duty)
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM17
(COM0)
S6A0075
♠♣
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG98
SEG99
SEG100
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
LCD Panel: 40 Character x 2-line Format (5-dot Font, 1/33 Duty)
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM33
(COM0)
S6A0075
SEG1
SEG2
SEG3
SEG4
SEG5
SEG98
SEG99
SEG100
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
48
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
LCD Panel: 20 Character x 4-line Format (5-dot Font, 1/33 Duty)
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
S6A0075
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
(COM0)
SEG1
SEG2
SEG3
SEG4
SEG5
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG98
SEG99
SEG100
49
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
LCD Panel: 16 Character x 4-line Format (6-dot Font, 1/33 Duty)
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
S6A0075
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
♠♣
COM33
(COM0)
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
50
Open
Open
Open
Open
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
INITIALIZING
INITIALIZING BY INTERNAL RESET CIRCUIT
When the power is turned on, S6A0075 is initialized automatically by power on reset circuit. During the
initialization, the following instructions are executed, and BF(Busy Flag) is kept "High"(busy state) to the end of
initialization.
Display Clear instruction
Write "20H" to all DDRAM
Set Functions instruction
DL = 1: 8-bit bus mode
N = 1: 2-line display mode
RE = 0: Extension register disable
BE = 0: CGRAM/SEGRAM blink OFF
DH = 0: Horizontal scroll enable
REV = 0: Normal display (Not reversed display)
Control Display ON/OFF instruction
D = 0: Display OFF
C = 0: Cursor OFF
B = 0: Blink OFF
Set Entry Mode instruction
I/D = 1: Increment by 1
S = 0: No entire display shift
BID = 0: Normal direction segment port
Set Extension Function instruction
FW = 0: 5-dot font width character display
B/W = 0: Normal cursor (8th line)
NW = 0: Not 4-line display mode, 2-line mode is set because of N("1")
Enable Shift instruction
HS = 0000: Scroll per line disable
DS = 0000: Shift per line disable
Set scroll Quantity instruction
SQ = 000000: Not scroll
INITIALIZING BY HARDWARE RESET INPUT
When RESET pin = "Low", S6A0075 can be initialized like the case of power on reset. During the power on reset
operation, this pin is ignored.
51
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
INITIALIZING BY INSTRUCTION
8-BIT INTERFACE MODE
Power On
Wait for more than 20ms after
VDD rises to 4.5V
Wait for more than 30ms after
VDD rises to 2.7V
Condition: fosc = 270kHz
(DL = "1")
Function Set
0
4-bit interface
1
8-bit interface
0
1-line mode
1
2-line mode
0
Display off
1
Display on
0
Cursor off
1
Cursor on
0
Blink off
1
Blink on
0
Decrement mode
1
Increment mode
0
Entire shift off
1
Entire shift on
DL
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
DL(1)
N
0
x
x
N
Wait for more than 39µs
D
Display ON/OFF Control
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C
0
0
0
0
0
0
1
D
C
B
B
Wait for more than 39µs
Clear Display
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
1
Wait for more than 1.53sms
Entry Mode Set
I/D
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
1
I/D
S
Initialization End
52
S
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
4-BIT INTERFACE MODE
Power On
Wait for more than 20ms after
VDD rises to 4.5V
Wait for more than 30ms after
VDD rises to 2.7V
Condition: fosc = 270kHz
(DL = "0")
Function Set
RS
0
0
4-bit interface
1
8-bit interface
0
1-line mode
1
2-line mode
0
Display off
1
Display on
0
Cursor off
1
Cursor on
0
Blink off
1
Blink on
0
Decrement mode
1
Increment mode
0
Entire shift off
1
Entire shift on
DL
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
DL(0)
x
x
x
x
N
Wait for more than 39µs
Function Set
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
0
x
x
x
x
0
0
N
x
x
x
x
x
x
x
Wait for more than 39µs
D
Display ON/OFF Control
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C
0
0
0
0
0
0
x
x
x
x
0
0
1
D
C
B
x
x
x
x
B
Wait for more than 39µs
Display Clear
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
x
x
x
x
0
0
0
0
0
1
x
x
x
x
Wait for more than 1.53ms
Entry Mode Set
I/D
RS
0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
x
x
x
x
S
0
0
0
1
I/D
SH
x
x
x
x
Initialization End
53
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
EXAMPLE OF INSTRUCTION AND DISPLAY CORRESPONDENCE
IE = "LOW"
1. Power supply on: Initialized by the internal power on reset circuit
RS
LCD DISPLAY
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
2. Function Set: 8-bit, 1-line, RE(0)
RS
0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
1
1
0
X
X
3. Display ON/OFF Control: Display/Cursor on
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
_
0
0
0
0
0
0
1
1
1
0
4. Entry Mode Set: Increment
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
_
0
0
0
0
0
0
0
1
1
0
5. Write Data to DDRAM: Write S
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
S_
1
0
0
1
0
1
0
0
1
1
6. Write Data to DDRAM: Write A
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
SA_
1
0
0
1
0
0
0
0
0
1
7. Write Data to DDRAM: Write M
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
SAM_
1
0
0
1
0
0
1
1
0
1
8. Write Data to DDRAM: Write S
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
SAMS_
1
54
0
0
1
0
1
0
0
1
1
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
9. Write Data to DDRAM: Write U
RS
R/W
1
0
LCD DISPLAY
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
0
1
0
1
0
SAMSU_
1
10. Write Data to DDRAM: Write N
RS
R/W
1
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
0
0
1
1
1
SAMSUN_
0
11. Write Data to DDRAM: Write G
RS
R/W
1
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
0
0
0
1
1
SAMSUNG_
1
12. Cursor or Display Shift: Cursor shift to right
RS
R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
SAMSUNG _
0
0
0
1
0
1
X
X
13. Entry Mode Set: Entire Display Shift Enable
RS
R/W
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
SAMSUNG _
0
0
0
0
0
1
1
1
14. Write Data to DDRAM: Write K
RS
R/W
1
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
AMSUNG K_
0
1
0
0
1
0
1
1
15. Write Data to DDRAM: Write S
RS
R/W
1
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
MSUNG KS_
0
1
0
1
0
0
1
1
16. Write Data to DDRAM: Write 0
RS
R/W
1
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
SUNG KS0_
0
0
1
1
0
0
0
0
55
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
17. Write Data to DDRAM: Write 0
RS
1
R/W DB7
0
0
LCD DISPLAY
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
1
0
0
0
0
UNG KS00_
18. Write Data to DDRAM: Write 7
RS
1
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
1
0
1
1
1
NG KS007_
19. Write Data to DDRAM: Write 3
RS
1
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
1
0
0
1
1
G KS0073_
20. Cursor or Display Shift: Cursor shift left
RS
0
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
0
x
x
G KS0073
21. Write Data to DDRAM: Write 8
RS
1
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
1
0
1
0
1
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
x
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
1
KS0075_
22. Return Home
RS
0
R/W DB7
0
0
SAMSUNG KS0075
23. Clear Display
RS
0
56
R/W DB7
0
0
_
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
IE = "HIGH"
1. Power Supply On: Initialized by the internal power on reset circuit
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
2. Function Set: 8-bit, RE(1)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
1
1
1
0
0
3. Extended Function Set: 5-font, 4-line
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
1
0
0
1
4. Function Set: RE(0)
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
1
1
0
0
0
5. Display ON/OFF Control: Display/Cursor on
_
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
1
1
1
0
6. Write Data to DDRAM: Write S
S_
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
0
1
0
0
1
1
57
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
7. Write Data to DDRAM: Write A
SA_
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
0
0
0
0
0
1
12. Write Data to DDRAM: Write G
SAMSUNG_
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
0
0
0
1
1
1
13. Set DDRAM Address 20H
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
0
0
0
0
14. Write Data to DDRAM: Write K
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
0
0
1
0
1
1
19. Write Data to DDRAM: Write 5
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
1
1
0
1
0
1
20. Set DDRAM Address 40H
58
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
0
0
0
0
0
0
SAMSUNG
_
SAMSUNG
K_
SAMSUNG
KS0075_
SAMSUNG
KS0075
_
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
21. Write Data to DDRAM: Write L
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
0
0
1
1
0
0
30. Write Data to DDRAM: Write R
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
0
1
0
0
1
0
31. Set DDRAM Address 60H
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
0
0
0
0
43. Write Data to DDRAM: Write R
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
0
1
0
0
1
0
44. Function Set: RE("0"), DH("1")
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
1
1
0
1
0
45. Function Set: RE("1")
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
1
1
1
0
0
SAMSUNG
KS0075
L_
SAMSUNG
KS0075
LCD DRIVER_
SAMSUNG
KS0075
LCD DRIVER
_
SAMSUNG
KS0075
LCD DRIVER
& CONTROLLER_
SAMSUNG
KS0075
LCD DRIVER
& CONTROLLER_
SAMSUNG
KS0075
LCD DRIVER
& CONTROLLER_
59
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
46. Shift/Scroll Enable: DS4("1"), DS3/2/1("0")
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
1
0
0
0
47. Function Set: RE("0")
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
1
1
0
1
0
48. Cursor or Display Shift: Display shift to left
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
1
0
x
x
49. Cursor or Display Shift: Display shift to left
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
1
0
x
x
50. Cursor or Display Shift: Display shift to left
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
1
0
x
x
51. Cursor or Display Shift: Display shift to left
60
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
1
0
x
x
SAMSUNG
KS0075
LCD DRIVER
& CONTROLLER_
SAMSUNG
KS0075
LCD DRIVER
& CONTROLLER_
SAMSUNG
KS0075
LCD DRIVER
CONTROLLER_
SAMSUNG
KS0075
LCD DRIVER
CONTROLLER_
SAMSUNG
KS0075
LCD DRIVER
ONTROLLER_
SAMSUNG
KS0075
LCD DRIVER
NTROLLER_
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
52. Return Home
RS
0
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
x
53. Function Set: RE("0), REV("1")
RS
0
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
1
1
0
1
1
54. Cursor or Display Shift: Display shift to right
RS
0
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
x
x
55. Cursor or Display Shift: Display shift to right
RS
0
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
x
x
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
x
56. Return Home
RS
0
R/W DB7
0
0
57. Function Set: RE("0"), REV("0")
RS
0
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
1
1
0
0
0
SAMSUNG
KS0075
LCD DRIVER
& CONTROLLER
SAMSUNG
KS0075
LCD DRIVER
& CONTROLLER
SAMSUNG
KS0075
LCD DRIVER
& CONTROLLER
SAMSUNG
KS0075
LCD DRIVER
& CONTROLLER
SAMSUNG
KS0075
LCD DRIVER
& CONTROLLER
SAMSUNG
KS0075
LCD DRIVER
& CONTROLLER
61
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
58. Function Set: RE("1")
RS
0
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
1
1
1
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
1
1
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
1
0
59. Entry Mode Set: BID("1")
RS
0
R/W DB7
0
0
60. Clear Display
RS
1
R/W DB7
0
0
61. Write Data to DDRAM: Write B
RS
1
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
0
0
1
62. Write Data to DDRAM: Write I
RS
1
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
1
0
0
63. Write Data for DDRAM: Write D
RS
0
62
R/W DB7
0
0
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
1
SAMSUNG
KS0075
LCD DRIVER
& CONTROLLER
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
FRAME FREQUENCY
1/17 DUTY CYCLE
1-line selection period
1
2
3
4
...
16
17
1
2
3
...
16
17
VDD
..
V1
COM1
V4
V5
1 Frame
1 Frame
Display Font Width
Item
5-Dot Font Width
6-Dot Font Width
200 clocks
240 clocks
79.4Hz
66.2Hz
1-line selection period
Frame frequency
fosc = 270kHz (1 clock = 3.7µs)
1/33 DUTY CYCLE
1-line selection period
1
2
3
4
...
32
33
1
2
3
...
32
33
VDD
..
V1
COM1
V4
V5
1 Frame
Item
1-line selection period
Frame frequency
1 Frame
Display Font Width
5-Dot Font Width
6-Dot Font Width
100 clocks
120 clocks
81.8Hz
68.2Hz
fosc = 270kHz (1 clock = 3.7µs)
63
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
POWER SUPPLY FOR DRIVING LCD PANEL
WHEN AN EXTERNAL POWER SUPPLY IS USED
VDD
VDD
V1
V2
V3
V4
V5
R
R
R0
R
R
VEE
WHEN AN INTERNAL BOOSTER IS USED
Boosting Twice
Boosting Three Times
VDD
VDD
VCI
+
1µF +-
1µF +
GND
C1
VDD
V1
C2
V5OUT2
V2
V3
V4
V5OUT3
V5
Can be detached if
not using power
down mode
R
R
R0
R
R
VCI
+
1µF +-
1µF +
1µF +
GND
C1
VDD
V1
C2
V5OUT2
V2
V3
V4
V5OUT3
V5
R
R
R0
R
R
Can be detached if
not using power
down mode
•
Boosted output voltage should not exceed the maximum value (13 V) of the LCD driving voltage.
Especially, a voltage of over 4.3V should not be input to the reference voltage (Vci) when boosting three
times.
•
A voltage of over 5.5V should not be input to the reference voltage (Vci) when boosting twice.
•
The value of resistance, according to the number of lines, duty ratio and the bias, is shown below.
(refer to Table 13)
64
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
Table 13. Duty Ratio and Power Supply for LCD Driving
Item
Data
Number of lines
1
2 or 4
Duty ratio
1/17
1/33
Bias
1/5
1/6.7
R
R
R
R0
R
2.7R
Divided resistance
MAXIMUM ABSOLUTE RATE
Characteristic
Symbol
Value
Unit
Power supply voltage (1)
VDD
-0.3 to +7.0
V
Power supply voltage (2)
VLCD
VDD -15.0 to VDD +0.3
V
VIN
-0.3 to VDD +0.3
V
Operating temperature
TOPR
-30 to +85
°C
Storage temperature
TSTG
-55 to +125
°C
Input voltage
Voltage greater than above may damage to the circuit (VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5)
65
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (VDD = 2.7V to 5.5V, Ta = -30 to + 85°C)
Characteristic
Symbol
Condition
Min
Typ
Max
Unit
Operating voltage
VDD
-
2.7
-
5.5
V
Supply current
IDD
Internal oscillation or external
clock.
(VDD = 3.0V, fosc = 270kHz)
-
0.15
0.3
mA
VIH1
-
0.7VDD
-
VDD
VDD = 2.7 - 3.0
-0.3
-
0.2VDD
VDD = 3.0 - 5.5
-0.3
-
0.6
VIH2
-
0.7VDD
-
VDD
VIL2
-
-
-
0.2VDD
VOH1
IOH = -0.1mA
0.75VDD
-
-
VOL1
IOL = 0.1mA
-
-
0.2VDD
VOH2
IO = -40µA
0.8VDD
-
-
VOL1
IO = 40µA
-
-
0.2VDD
-
-
1
-
-
1
Input voltage (1)
(Except OSC1)
Input voltage (2)
(Osc1)
Output voltage (1)
(DB0 - DB7)
Output voltage (2)
(Except DB0 - DB7)
Voltage drop
Input leakage current
Low input current
Internal clock
(external Rf)
VIL1
VdCOM
VdSEG
IO = ± 0.1mA
V
V
-1
-
1
IIL
VIN = 0V, VDD = 3V (pull up)
-10
-50
-120
f OSC
Rf = 91kΩ ± 2% (VDD = 5V)
190
270
350
kHz
125
270
410
kHz
45
50
55
%
-
-
0.2
µs
-3.0
-4.2
-
-
duty
Voltage converter out2
(Vci = 4.5V)
VOUT2
Voltage converter out3
(Vci = 2.7V)
VOUT3
f OSC = 270kHz
-4.3
-5.1
-
Voltage converter input
Vci
-
1.0
-
4.5
1/5 bias
3.0
-
13.0
1/6.7 bias
3.0
-
13.0
66
V
VIN = 0V - VDD
tr, tf
LCD driving voltage
V
ILKG
f EC
External clock
-
Ta = 25°C, C = 1µF,
IOUT = 0.25mA,
VLCD
VDD-V5
µA
V
V
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
AC CHARACTERISTICS (VDD = 4.5 to 5.5V, Ta = -30 to +85°C)
Table 14. AC Characteristics
Mode
Item
Symbol
Min
Typ
Max
tc
500
-
-
tr, tf
-
-
20
E pulse width (high, low)
tw
230
-
-
R/W and RS setup time
tsu1
40
-
-
R/W and RS hold time
th1
10
-
-
Data setup time
tsu2
60
-
-
Data hold time
th2
10
-
-
tc
500
-
-
tr, tf
-
-
20
E pulse width (high, low)
tw
230
-
-
R/W and RS setup time
tsu
40
-
-
R/W and RS hold time
th
10
-
-
Data output delay time
tD
-
-
160
Data hold time
tDH
5
-
-
tc
0.5
-
20
tr, tf
-
-
50
tw
200
-
-
E cycle time
E rise/fall time
(1) Write mode
(refer to Figure15)
E cycle time
E rise/fall time
(2) Read mode
(refer to Figure 16)
Serial clock cycle time
Serial clock rise/fall time
Serial clock width (high, low)
(3) Serial interface
Chip select setup time
tsu1
60
-
-
mode
Chip select hold time
th1
20
-
-
(refer to Figure 17)
Serial input data setup time
tsu2
100
-
-
Serial input data hold time
th2
100
-
-
Serial output data delay time
tD
-
-
160
Serial output data hold time
tDH
5
-
-
Unit
ns
ns
µs
ns
67
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
TABLE 14. AC CHARACTERISTICS (VDD = 4.5 to 5.5V, Ta = -30 to +85°C)
Mode
Item
Symbol
Min
Typ
Max
tc,
1000
-
-
tr, tf
-
-
25
E pulse width (high, low)
tw
450
-
-
R/W and RS setup time
tsu1
60
-
-
R/W and RS hold time
th1
20
-
-
Data setup time
tsu2
195
-
-
Data hold time
th2
10
-
-
tc
1000
-
-
tr, tf
-
-
25
E pulse width (high, low)
tw
450
-
-
R/W and RS setup time
tsu
60
-
-
R/W and RS hold time
th
20
-
-
Data output delay time
tD
-
-
360
Data hold time
tDH
5
-
-
tc
1
-
20
tr, tf
-
-
50
tw
400
-
-
E cycle time
E rise / fall time
(4) Write mode
(refer to Fig-15)
E cycle time
E rise/fall time
(5) Read mode
(refer to Figure 16)
Serial clock cycle time
Serial clock rise/fall time
Serial clock width (high, low)
(6) Serial interface
Chip select setup time
tsu1
60
-
-
mode
Chip select hold time
th1
20
-
-
(refer to Figure 17)
Serial input data setup time
tsu2
200
-
-
Serial input data hold time
th2
200
-
-
Serial output data delay time
tD
-
-
360
Serial output data hold time
tDH
5
-
-
68
Unit
ns
ns
µs
ns
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
RS
VIH1
VIL1
tsu1
R/W
S6A0075
th1
VIL1
VIL1
th1
tw
tf
VIH1
VIL1
E
VIH1
VIL1
tsu2
tr
VIH1
VIL1
DB0 - DB7
VIL1
th2
VIH1
VIL1
Valid Data
tc
Figure 15. Write Mode
RS
R/W
VIH1
VIL1
tsu
th
VIH1
VIH1
th
tw
tf
tr
DB0 - DB7
VIH1
VIL1
VIH1
VIL1
E
tD
VOH1
VOL1
VIL1
tDH
Valid Data
tc
VOH1
VOL1
Figure 16. Read Mode
69
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
tC
CS
SCLK
VIL1
tsu1
tr
tw
VIL1
th1
tw
tf
VIH1
VIL1
tsu2
VIH1 VIH1
VIL1 VIL1
th2
VIH1
VIL1
SID
tD
tDH
VOH1
VOL1
SOD
Figure 17. Serial Interface Mode
RESET TIMING (VDD = 2.7 to 5.5V, Ta = -30 to +85°° C)
Item
Symbol
Min
Typ
Max
Unit
tRES
10
-
-
ms
Reset low level width (refer to Figure 18)
tRES
RESET
VIL1
VIL1
Figure 18. Reset Timing Diagram
70