S72NS-N Based MCPs Stacked Multi-Chip Product (MCP) MirrorBitTM Flash Memory & DRAM 128 Mb (8 M x 16 bit)/256 Mb (16 M x 16 bit), 110nm CMOS 1.8 Volt-only, Multiplexed, Simultaneous Read/Write, Burst Mode Flash Memory and 128/256-Mb (8/16-M x 16-bit) DDR DRAM ADVANCE INFORMATION Data Sheet Notice to Readers: The Advance Information status indicates that this document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice. Publication Number S72NS128_256ND0_00 Revision B Amendment 1 Issue Date November 9, 2005 A d v a n c e I n f o r m a t i o n Notice On Data Sheet Designations Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets will contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with DC Characteristics table and AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion LLC applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office. ii S72NS128/256ND0 Based MCPs S72NS128_256ND0_00_B1 November 9, 2005 S72NS-N Based MCPs Stacked Multi-Chip Product (MCP) MirrorBitTM Flash Memory & DRAM 128/256 Mb (8/16 M x 16 bit), 110nm CMOS 1.8 Volt-only, Multiplexed, Simultaneous Read/Write, Burst Mode Flash Memory and 128/256-Mb (8/16-M x 16-bit) DDR DRAM ADVANCE INFORMATION Data Sheet General Description This document contains information on the S72NS-N MCP product family. Refer to the S29NS-N data sheet (S29NS256/128N_01, revision A4) for full electrical specifications of the Flash memory component. Refer to the DDR SDRAM Type 1 data sheet (revision A2) for full electrical specifications of the DDR SDRAM component. Refer to the DDR SDRAM Type 5 data sheet (revision A0) for full electrical specifications of the DDR SDRAM component The S72NS Series is a product line of stacked Multi-Chip Product (MCP) products and consists of: One or more NS family multiplexed Flash memory die DDR DRAM The products covered by this document are listed in the table below. DRAM Density Flash Density 128 Mb 256 Mb 128 Mb S72NS128ND0 S72NS256ND0 256 Mb S72NS256ND0 512 Mb S72NS512ND0 S72NS512NE0 Distinctive Characteristics MCP Features Power supply voltage of 1.7 V to 1.95 V Packages, 133-ball FBGA — 11.0 x 10.0 x 1.0 mm Burst Speeds — 8.0 x 8.0 x 1.0 mm — Flash = 66 MHz, 80 MHz Operating Temperature of 25°C to +85°C — DRAM = 133 MHz Product Selector Guide Device- Model# Flash Density DRAM Density S72NS256ND0-7K S72NS256ND0-7J S72NS256ND0-73 Flash Speed (MHz) 256 Mb 128 Mb 66 S72NS256ND0-72 80 66 S72NS128ND0-1J 80 128 Mb 128 Mb S72NS128ND0-12 80 66 S72NS512ND0-7J 80 S72NS512ND0-73 512 Mb 128 Mb 80 S72NS512NE0-7K 66 S72NS512NE0-7J 512 Mb 256 Mb S72NS512NE0-72 Publication Number S72NS128_256ND0_00 80 66 80 Revision B Amendment 1 DRAM Type 5 DRAM Type 1 DRAM Type 5 Package NLC133, 11x10mm NLE133, 8x8mm DRAM Type 1 66 S72NS512ND0-72 S72NS512NE0-73 133 66 S72NS512ND0-7K Supplier DRAM Type 1 80 S72NS128ND0-1K S72NS128ND0-13 DRAM Speed (MHz) 66 133 DRAM Type 5 DRAM Type 1 MTA133 11x10mm DRAM Type 5 Issue Date November 9, 2005 This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice. A d v a n c e I n f o r m a t i o n Contents 1 2 3 4 5 6 2 MCP Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Connection Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 256 Mb Flash + 128 Mb DDR SDRAM Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 512 Mb Flash + 128 Mb DDR SDRAM Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 512 Mb Flash + 256 Mb DDR SDRAM Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4 128 Mb Flash + 128 Mb DDR SDRAM Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1 NLC133—133-ball Fine-Pitch Ball Grid Array (FBGA) 11.0 x 10.0 x 1.0 mm MCP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 5.2 NLE133—133-ball Fine-Pitch Ball Grid Array (FBGA) 8.0 x 8.0 x 1.0 mm MCP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.3 MTA133—133-ball Fine-Pitch Ball Grid Array (FBGA) 10.0 x 11.0 x 1.0 mm MCP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 S72NS-N Based MCPs S72NS128_256ND0_00_B1 November 9, 2005 A d v a n c e 1 I n f o r m a t i o n MCP Block Diagrams F-RST# F-VPP RST# A15-A0 VPP ADQ15-ADQ0 DQ15-DQ0 F-WP# WP# F-CE# CE# F-OE# OE# F-WE# WE# AVD# AVD# F-VSS VSS MUX Flash Memory NS-N CLK F-CLK RDY F-RDY A16-Amax A16-Amax VCC VCCQ F-VCC F-VCCQ CLK D-CLK F2-CE# Second NS-N (if needed) D-RAS# RAS# D-CAS# CAS# D-BA0 BA0 D-BA1 BA1 D-CKE CKE D-WE# WE# DDR DRAM Memory VCC D-VCCQ VCCQ D-CLK# D-LDQS DQS1 D-UDQS LDQM D-LDQM UDQM D-UDQM TEST D-TEST DQ15-DQ0 D-Amax - D-A0 D-VCC CLK# DQS0 D-DQ15 - D-DQ0 VSS D-VSS VSSQ D-VSSQ (Note 3) Notes: 1. 2. 3. Amax indicates highest address bit for memory component: a. Amax = A23 for NS256N, A22 for NS128N b. Amax = A11 for 128 Mb DDR DRAM, A12 for 256-Mb DDR DRAM For Flash, A0 – A15 is tied to DQ0 – DQ15. For the NS512N, two NS-N devices are included. All signals are common to both except for CE#. F-CE# becomes F1-CE#, while the CE# for the second flash is F2-CE#. This way, the two NS-N devices are separately accessed. Figure 1.1. November 9, 2005 S72NS128_256ND0_00_B1 MCP Block Diagram S72NS-N Based MCPs 3 A d v a n c e 2 2.1 I n f o r m a t i o n Connection Diagrams 256 Mb Flash + 128 Mb DDR SDRAM Pinout Legend A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 DNU D-TEST D-VSSQ D-VCCQ D-DQ9 D-DQ8 D-VSS D-VCC D-VCC D-DQ5 D-DQ3 D-VSSQ DNU DNU B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 DNU D-VSS D-DQ13 D-UDQS D-DQ10 D-VSSQ D-VCCQ D-VCCQ D-LDQM D-DQ6 D-DQ4 D-DQ1 D-VCCQ DNU C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 D-VCC D-DQ15 D-DQ14 D-DQ12 D-DQ11 D-UDQM D-VSS D-VCC D-VSSQ D-DQ7 D-LDQS D-DQ2 D-DQ0 D-VSS Do Not Use D1 D2 D3 D4 D12 D13 D14 RFU NC NC INDEX F-OE# ADQ8 D-VCC E1 E2 E3 E12 E13 E14 RFU A22 A17 ADQ9 ADQ1 ADQ0 F1 F2 F3 F12 F13 F14 A23 A19 A18 F-VSS ADQ3 ADQ2 G1 G2 G3 G12 G13 G14 F-CE# F-WP# F-WE# F-VCCQ ADQ11 ADQ10 H1 H2 H3 H12 H13 H14 F-VPP F-VCC F-CLK ADQ13 ADQ12 ADQ4 J1 J2 J3 J12 J13 J14 A16 F-VSS NC F-VSS F-VSS ADQ5 K1 K2 K3 K12 K13 K14 A21 F-AVD# NC NC ADQ7 ADQ6 L1 L2 L3 L12 LA13 L14 A20 F-RST# D-CE# F-VCCQ ADQ15 ADQ14 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 NC NC D-A3 D-A6 D-A9 D-CKE D-VSS D-WE# D-A10 D-A1 RFU NC F-RDY F-VSS N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 DNU D-VSS D-VCC D-A5 D-A8 D-CAS# D-CLK# D-BA1 D-A11 D-A2 RFU RFU F-VCC DNU P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 DNU DNU NC D-A4 D-A7 D-RAS# D-CLK D-VCC D-BA0 D-A0 D-VCC D-VSS DNU DNU Figure 2.1. 4 Code Flash Only DRAM Only Reserved for Future Use No Connect Index Location 133-ball Fine-Pitch Ball Grid Array, 256 Mb Flash + 128 Mb DDR DRAM S72NS-N Based MCPs S72NS128_256ND0_00_B1 November 9, 2005 A d v a n c e 2.2 I n f o r m a t i o n 512 Mb Flash + 128 Mb DDR SDRAM Pinout Legend A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 DNU D-TEST D-VSSQ D-VCCQ D-DQ9 D-DQ8 D-VSS D-VCC D-VCC D-DQ5 D-DQ3 D-VSSQ DNU DNU B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 DNU D-VSS D-DQ13 D-UDQS D-DQ10 D-VSSQ D-VCCQ D-VCCQ D-LDQM D-DQ6 D-DQ4 D-DQ1 D-VCCQ DNU C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 D-VCC D-DQ15 D-DQ14 D-DQ12 D-DQ11 D-UDQM D-VSS D-VCC D-VSSQ D-DQ7 D-LDQS D-DQ2 D-DQ0 D-VSS Do Not Use D1 D2 D3 D4 D12 D13 D14 RFU NC NC INDEX F-OE# ADQ8 D-VCC E1 E2 E3 E12 E13 E14 RFU A22 A17 ADQ9 ADQ1 ADQ0 F1 F2 F3 F12 F13 F14 A23 A19 A18 F-VSS ADQ3 ADQ2 G1 G2 G3 G12 G13 G14 F1-CE# F-WP# F-WE# F-VCCQ ADQ11 ADQ10 H1 H2 H3 H12 H13 H14 F-VPP F-VCC F-CLK ADQ13 ADQ12 ADQ4 J1 J2 J3 J12 J13 J14 A16 F-VSS NC F-VSS F-VSS ADQ5 K1 K2 K3 K12 K13 K14 A21 F-AVD# NC NC ADQ7 ADQ6 L1 L2 L3 L12 LA13 L14 A20 F-RST# D-CE# F-VCCQ ADQ15 ADQ14 Flash Shared Flash 1 Only Flash 2 Only DRAM Only Reserved for Future Use No Connect M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 NC NC D-A3 D-A6 D-A9 D-CKE D-VSS D-WE# D-A10 D-A1 RFU F2-CE# F-RDY F-VSS N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 DNU D-VSS D-VCC D-A5 D-A8 D-CAS# D-CLK# D-BA1 D-A11 D-A2 RFU RFU F-VCC DNU P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 DNU DNU NC D-A4 D-A7 D-RAS# D-CLK D-VCC D-BA0 D-A0 D-VCC D-VSS DNU DNU Figure 2.2. November 9, 2005 S72NS128_256ND0_00_B1 Index Location 133-ball Fine-Pitch Ball Grid Array, 512 Mb Flash + 128 Mb DDR DRAM S72NS-N Based MCPs 5 A d v a n c e 2.3 I n f o r m a t i o n 512 Mb Flash + 256 Mb DDR SDRAM Pinout Legend A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 DNU D-TEST D-VSSQ D-VCCQ D-DQ9 D-DQ8 D-VSS D-VCC D-VCC D-DQ5 D-DQ3 D-VSSQ DNU DNU B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 DNU D-VSS D-DQ13 D-UDQS D-DQ10 D-VSSQ D-VCCQ D-VCCQ D-LDQM D-DQ6 D-DQ4 D-DQ1 D-VCCQ DNU C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 D-VCC D-DQ15 D-DQ14 D-DQ12 D-DQ11 D-UDQM D-VSS D-VCC D-VSSQ D-DQ7 D-LDQS D-DQ2 D-DQ0 D-VSS Do Not Use D1 D2 D3 D4 D12 D13 D14 RFU NC NC INDEX F-OE# ADQ8 D-VCC E1 E2 E3 E12 E13 E14 RFU A22 A17 ADQ9 ADQ1 ADQ0 F1 F2 F3 F12 F13 F14 A23 A19 A18 F-VSS ADQ3 ADQ2 G1 G2 G3 G12 G13 G14 F1-CE# F-WP# F-WE# F-VCCQ ADQ11 ADQ10 H1 H2 H3 H12 H13 H14 F-VPP F-VCC F-CLK ADQ13 ADQ12 ADQ4 J1 J2 J3 J12 J13 J14 A16 F-VSS NC F-VSS F-VSS ADQ5 K1 K2 K3 K12 K13 K14 A21 F-AVD# NC NC ADQ7 ADQ6 L1 L2 L3 L12 LA13 L14 A20 F-RST# D-CE# F-VCCQ ADQ15 ADQ14 Flash Shared Flash 1 Only Flash 2 Only DRAM Only Reserved for Future Use No Connect M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 NC NC D-A3 D-A6 D-A9 D-CKE D-VSS D-WE# D-A10 D-A1 RFU F2-CE# F-RDY F-VSS N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 DNU D-VSS D-VCC D-A5 D-A8 D-CAS# D-CLK# D-BA1 D-A11 D-A2 D-A12 RFU F-VCC DNU P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 DNU DNU NC D-A4 D-A7 D-RAS# D-CLK D-VCC D-BA0 D-A0 D-VCC D-VSS DNU DNU Figure 2.3. 6 Index Location 133-ball Fine-Pitch Ball Grid Array, 512 Mb Flash + 256 Mb DDR DRAM S72NS-N Based MCPs S72NS128_256ND0_00_B1 November 9, 2005 A d v a n c e 2.4 I n f o r m a t i o n 128 Mb Flash + 128 Mb DDR SDRAM Pinout Legend A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 DNU D-TEST D-VSSQ D-VCCQ D-DQ9 D-DQ8 D-VSS D-VCC D-VCC D-DQ5 D-DQ3 D-VSSQ DNU DNU B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 DNU D-VSS D-DQ13 D-UDQS D-DQ10 D-VSSQ D-VCCQ D-VCCQ D-LDQM D-DQ6 D-DQ4 D-DQ1 D-VCCQ DNU C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 D-VCC D-DQ15 D-DQ14 D-DQ12 D-DQ11 D-UDQM D-VSS D-VCC D-VSSQ D-DQ7 D-LDQS D-DQ2 D-DQ0 D-VSS Do Not Use D1 D2 D3 D4 D12 D13 D14 RFU NC NC INDEX F-OE# ADQ8 D-VCC E1 E2 E3 E12 E13 E14 RFU A22 A17 ADQ9 ADQ1 ADQ0 F1 F2 F3 F12 F13 F14 NC A19 A18 F-VSS ADQ3 ADQ2 G1 G2 G3 G12 G13 G14 F-CE# F-WP# F-WE# F-VCCQ ADQ11 ADQ10 H1 H2 H3 H12 H13 H14 F-VPP F-VCC F-CLK ADQ13 ADQ12 ADQ4 J1 J2 J3 J12 J13 J14 A16 F-VSS NC F-VSS F-VSS ADQ5 K1 K2 K3 K12 K13 K14 A21 F-AVD# NC NC ADQ7 ADQ6 L1 L2 L3 L12 LA13 L14 A20 F-RST# D-CE# F-VCCQ ADQ15 ADQ14 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 NC NC D-A3 D-A6 D-A9 D-CKE D-VSS D-WE# D-A10 D-A1 RFU NC F-RDY F-VSS N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 DNU D-VSS D-VCC D-A5 D-A8 D-CAS# D-CLK# D-BA1 D-A11 D-A2 RFU RFU F-VCC DNU P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 DNU DNU NC D-A4 D-A7 D-RAS# D-CLK D-VCC D-BA0 D-A0 D-VCC D-VSS DNU DNU Figure 2.4. November 9, 2005 S72NS128_256ND0_00_B1 Code Flash Only DRAM Only Reserved for Future Use No Connect Index Location 133-ball Fine-Pitch Ball Grid Array, 128 Mb Flash + 128 Mb DDR DRAM S72NS-N Based MCPs 7 A d v a n c e 3 8 I n f o r m a t i o n Input/Output Descriptions A23 – A0 DQ15 – DQ0 F-CE# = = = F-OE# = F-WE# F-VCC F-VCCQ F-VSS F-RDY = = = = = F-CLK = F-AVD# = F-RST# = F-WP# = F-VPP = D-A11 – D-A0 D-DQ15 – D-DQ0 D-CLK D-CE# D-CKE D-BA1 – BA0 D-RAS# D-CAS# D-DM1 – D-DM0 D-WE# D-VSS D-VSSQ D-VCCQ D-VCC D-UDQS = = = = = = = = = = = = = = = D-LDQS = D-CLK# RFU NC D-TEST = = = = Flash Address inputs Flash Data input/output Flash Chip-enable input. Asynchronous relative to CLK for Burst Mode Flash Output Enable input. Asynchronous relative to CLK for Burst mode. Flash Write Enable input Flash device power supply (1.7 V to 1.95 V) Flash Input/Output Buffer power supply Flash Ground Flash ready output. Indicates the status of the Burst read. VOL = data invalid. VOH = data valid. Flash Clock. The first rising edge of CLK in conjunction with AVD# low latches the address input and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low during asynchronous access. Flash Address Valid input. Indicates to device that the valid address is present on the address inputs. VIL = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge of CLK. VIH= device ignores address inputs Flash hardware reset input. VIL= device resets and returns to reading array data Flash hardware write protect input. VIL = disables program and erase functions in the four outermost sectors Flash accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. DRAM Address inputs. DRAM Data input/output DRAM System Clock DRAM Chip Select DRAM Clock Enable DRAM Bank Select DRAM Row Address Strobe DRAM Column Address Strobe DRAM Data Input/Output Mask DRAM Write Enable input DRAM Ground DRAM Input/Output Buffer ground DRAM Input/Output Buffer power supply DRAM device power supply DRAM Upper Data Strobe, output with read data and input with write data DRAM Lower Data Strobe, output with read data and input with write data DDR Clock for negative edge of CLK Reserved for Future Use No Connect. Can be connected to ground or left floating. Internal Test mode pin for DDR DRAM only. Do not apply any signal on this pin. Can be connected to ground or left floating. S72NS-N Based MCPs S72NS128_256ND0_00_B1 November 9, 2005 A d v a n c e 4 I n f o r m a t i o n Ordering Information The order number (Valid Combination) is formed by the following: S72NS 256 N D0 AF W 7 K 0 PACKING TYPE 0 2 3 = Tray = 7-inch Tape and Reel = 13-inch Tape and Reel MODEL NUMBER K J 3 2 = = = = DRAM DRAM DRAM DRAM Type Type Type Type 1, 1, 5, 5, 66 80 66 80 MHz MHz MHz MHz Flash/133 Flash/133 Flash/133 Flash/133 MHz MHz MHz MHz DRAM DRAM DRAM DRAM PACKAGE MODIFIER 7 1 = DDR DRAM, 133-ball, 11x10 mm, FBGA Multi-chip Package = DDR DRAM, 133-ball, 8.0x8.0 mm, FBGA Multi-chip Package TEMPERATURE RANGE = Wireless (-25°C to +85°C) W PACKAGE TYPE AF = Thin profile Fine-pitch BGA Pb-free package (0.5 mm pitch, 1.0 mm height) = Thin profile Fine-pitch BGA Pb-free LF35 package (0.5 mm pitch, 1.0 mm height) = Thin profile Fine-pitch BGA Pb-free LF35 package (0.5 mm pitch, 1.2 mm height) AJ ZJ DRAM AND DATA FLASH DENSITY D0 E0 = 128 Mb DRAM, No Data Flash = 256 Mb DRAM, No Data Flash PROCESS TECHNOLOGY N = 110 nm, MirrorBitTM Technology CODE FLASH DENSITY 512 256 128 = 512 Mb = 256 Mb = 128 Mb PRODUCT FAMILY S72NS Multi-Chip Product (MCP) 1.8 V Multiplexed, SRW, Burst Mode Flash and DDR DRAM on Split Bus Valid Combinations Product Family Code Flash Density (Mb) Process Technology 128 S72NS 256 512 N DRAM Density (Mb) Package Type/ Marking/ Material D0 AF, AJ E0 ZJ Temperature Range Notes: 1. 2. Model Number Packing Type K, J, 2, 3 0, 2, 3 1 W 7 Valid Combinations Packing Type 0 is standard. Specify other options as required. BGA package marking omits leading “S” and packing type designator from ordering part number. November 9, 2005 S72NS128_256ND0_00_B1 Package Modifier Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S72NS-N Based MCPs 9 A d v a n c e 5 5.1 I n f o r m a t i o n Physical Dimensions NLC133—133-ball Fine-Pitch Ball Grid Array (FBGA) 11.0 x 10.0 x 1.0 mm MCP Package NOTES: PACKAGE NLC 133 JEDEC N/A DxE 11.0 mm x 10.00 mm PACKAGE SYMBOL MIN NOM MAX NOTE A 0.90 1.00 1.10 PROFILE A1 0.20 0.25 0.30 BALL HEIGHT A2 0.70 0.76 0.82 BODY THICKNESS D 10.9 11.0 11.1 BODY SIZE E 9.9 10.0 10.1 6.50 BSC. MATRIX FOOTPRINT E1 6.50 BSC. MATRIX FOOTPRINT MD 14 MATRIX SIZE D DIRECTION ME 14 MATRIX SIZE E DIRECTION n 133 0.25 0.30 DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. BODY SIZE D1 Øb 1. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL COUNT 0.35 eE 0.50 BSC. BALL PITCH eD 0.50 BSC BALL PITCH SD / SE 0.25 BSC. SOLDER BALL PLACEMENT D5-D11, E4-E11, F4-F11 G4-G11, H4-H11, J4-J11 K4-K11, L4-L11 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER DEPOPULATED SOLDER BALLS WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3436 \ 16-039.22 \ 12.09.04 10 S72NS-N Based MCPs S72NS128_256ND0_00_B1 November 9, 2005 A d v a n c e 5.2 I n f o r m a t i o n NLE133—133-ball Fine-Pitch Ball Grid Array (FBGA) 8.0 x 8.0 x 1.0 mm MCP Package D D1 A A1 CORNER eD 1.00 +0.20 -0.50 A1 ID. 14 13 12 11 10 9 8 7 6 5 eE 4 3 2 1 0.10 C A +0.20 -0.50 0.50 REF B C D E 1.00 0.50 REF F 7 SE G H E E1 J K L M N P B 6 0.10 C SD 7 φ 0.15 M C A B TOP VIEW C SEATING PLANE BOTTOM VIEW 0.10 C A2 A A1 φb φ 0.08 M C 0.08 C SIDE VIEW NOTES: PACKAGE NLE 133 JEDEC N/A DxE 8.00 mm x 8.00 mm PACKAGE SYMBOL MIN NOM MAX NOTE 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1 SPP-010. A 0.90 1.00 1.10 PROFILE 4. e REPRESENTS THE SOLDER BALL GRID PITCH. A1 0.20 0.25 0.30 BALL HEIGHT 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. A2 0.70 0.76 0.82 BODY THICKNESS D 7.90 8.00 8.10 BODY SIZE E 7.90 8.00 8.10 BODY SIZE D1 6.50 BSC. MATRIX FOOTPRINT MATRIX FOOTPRINT E1 6.50 BSC. MD 14 MATRIX SIZE D DIRECTION ME 14 MATRIX SIZE E DIRECTION n Øb 133 0.25 0.30 n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL COUNT 0.35 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER eE 0.50 BSC. BALL PITCH eD 0.50 BSC BALL PITCH 0.25 BSC. SOLDER BALL PLACEMENT SD / SE SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. D5-D11,E4-E11,F4-F11,G4-G11 DEPOPULATED SOLDER BALLS H4-H11,J4-J11,K4-K11,L4-L11 WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3513 \ 16-038.22 \ 08.09.05 November 9, 2005 S72NS128_256ND0_00_B1 S72NS-N Based MCPs 11 A d v a n c e 5.3 I n f o r m a t i o n MTA133—133-ball Fine-Pitch Ball Grid Array (FBGA) 10.0 x 11.0 x 1.0 mm MCP Package A D PIN A1 CORNER D1 9 INDEX MARK PIN A1 CORNER eD A B C D E F G H E SE 7 E1 J K L eE M N P 0.10 C 14 13 12 11 10 9 8 (2X) TOP VIEW 7 6 5 4 3 2 1 SD B 7 0.10 C BOTTOM VIEW (2X) 0.10 C A A2 A1 C 0.08 C SIDE VIEW 6 b 133X M C A B M C 0.15 0.08 NOTES: PACKAGE MTA 133 JEDEC DXE 11.00 mm x 10.00 mm PACKAGE SYMBOL MIN NOM MAX A --- --- 1.30 A1 0.20 --- --- A2 0.91 --- 1.06 D 11.00 BSC. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JEP95, SECTION 3.0, SPP-010. NOTE PROFILE BALL HEIGHT 10.00 BSC. BODY SIZE 6.50 BSC. MATRIX FOOTPRINT MATRIX FOOTPRINT E1 6.50 BSC. MD 14 MATRIX SIZE D DIRECTION ME 14 MATRIX SIZE E DIRECTION n 133 BALL COUNT N 133 MAXIMUM NUMBER OF BALLS 2 0.25 0.30 e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. BODY SIZE E R 4. BODY THICKNESS D1 Øb 1. N/A n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DATUM C IS THE SEATING PLANE AND IS DEFINED BY THE CROWNS OF THE SOLDER BALLS. 7 NUMBER OF LAND PERIMETERS 0.35 eE 0.50 BSC. BALL PITCH 0.50 BSC BALL PITCH SE SD 0.25 BSC. SOLDER BALL PLACEMENT 4L ~ 4E, 5L ~ 5D, 6L ~ 6D, 7L ~ 7D, 8L ~ 8D, 9L ~ 9D, 10L ~ 10D, 11L ~ 11D DEPOPULATED SOLDER BALL SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER eD DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT. 3529 / 16.038 / 11.08.05 12 S72NS-N Based MCPs S72NS128_256ND0_00_B1 November 9, 2005 A d v a n c e 6 I n f o r m a t i o n Revision Summary MCP Revision History Revision A0 (January 3, 2005) Initial release. Revision A1 (April 25, 2005) Global Updated the flash module Updated the SDRAM Type 1 module Revision A2 (May 20, 2005) Global Data sheet format modularized. Distinctive Characteristics Package description changed from 10.0 x 11.0 x 1.0 to 11.0 x 10.0 x 1.0 MCP Block Diagrams Changed the F-ACC signal to F-VPP Changed the ACC description to VPP Connection Diagrams Changed the F-ACC pin to F-VPP Input/Output Descriptions Updated description for F-RDY Changed the F-ACC description to F-VPP Updated description for NC and D-TEST Product Revision Identification New section added. Revision B0 (August 15, 2005) Global Data sheet revised to include 128/128 MCP details. Distinctive Characteristics Package description changed to include new 128/128 MCP details and update the Product Selector Guide table. Connection Diagrams New 128 Mb Flash + 128 Mb DDR SDRAM Pinout added. Ordering Information New valid combinations added to the table. Physical Dimensions New illustration for 8.0 x 8.0 x 1.0 mm MCP Package added. November 9, 2005 S72NS128_256ND0_00_B1 S72NS-N Based MCPs 13 A d v a n c e I n f o r m a t i o n Revision B1 (November 9, 2005) Added DDR DRAM Type 5 Information Updated General Description, Product Selector Guide, Ordering Information, and Valid Combinations with DDR DRAM Type 5 Information. S29NS-N Flash Module Removed all of the Revision Summary except for A4 (request from customer). SDRAM (Micron) Revision Summary Removed all of the Revision Summary except for A1 (request from customer). SDRAM (Elpida) Revision Summary New SDRAM to be added to MCP S29NS-N Revision Summary Revision A4 Flash Module (April 21, 2005) Global Changes Removed all ordering options and package information listed in revision A4 of the discrete data sheet. Removed 54 MHz speed option. Changed ACC to VPP. Read Access Times Removed burst access for 54MHz. Defined asynchronous random access and synchronous random access to 80 ns for all speed options. DC Characteristics CMOS Compatible Table. Updated ICC3 and ICC6 values from 40 µA to 70 µA. SDRAM Type 1 Revision Summary Revision A2 (November 1, 2005) Features Changed VDD/VDDQ range from 1.7 V-1.9 V to 1.7 V-1.95 V Indicated temperature range (-40°C to 85°C) Stopping the External Clock Removed information that limited the rate of frequency change. IDD Specifications and Conditions table Specifications and conditions updated. Electrical Characteristics and Recommended AC Operating Conditions table Removed tREFC parameter SDRAM Type 5 Revision Summary Revision A0 (September 30, 2005) Initial release. New SDRAM module. 14 S72NS-N Based MCPs S72NS128_256ND0_00_B1 November 9, 2005 A d v a n c e I n f o r m a t i o n Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abovementioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2005 Spansion. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of Spansion. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies. November 9, 2005 S72NS128_256ND0_00_B1 S72NS-N Based MCPs 15