SUMMIT S9318 MICROELECTRONICS, Inc. Nonvolatile DACPOT™ Electronic Potentiometer With Up/Down Counter Interface FEATURES • Digitally Controlled Electronic Potentiometer OVERVIEW • 8-Bit Digital-to-Analog Converter (DAC) – Independent Reference Inputs – Differential Non-Linearity - ±0.5LSB max – Integral Non-Linearity - ±1LSB max • VOUT Value in E2PROM for Power-On Recall – Equivalent to 256-Step Potentiometer • Unity Gain Op Amp Drives up to 1mA The S9318 DACPOT™ trimmer is an 8-bit nonvolatile DAC designed to replace mechanical potentiometers. The S9318 includes a unity-gain amplifier to buffer the DAC output and enables VOUT to swing from rail to rail. The DACPOT trimmer operates over a supply voltage range of 2.7V to 5.5V. The S9318’s simple up/down counter input provides an ideal interface for automatic test equipment to dither and monitor the VOUT voltage. This interface allows for quick and consistent calibration of even the most sophisticated systems. • Simple Trimming Adjustment – Up/Down Counter Style Operation • Low Noise Operation • “Clickless” Transitions between DAC Steps The S9318 is a pin-compatible performance upgrade for other industry nonvolatile potentiometers. The S9318 offers double the resolution of these devices and provides ‘clickless’ transitions of VOUT. • No Mechanical Wearout Problem – 1,000,000 Stores (typical) – 100 Year Data Retention • Operation from +2.7V to +5.5V Supply • Low Power, 1mW max at +5V FUNCTIONAL BLOCK DIAGRAM VDD VH 8-bit E2 PROM - UP/DN INC CS Counter & Write Control AMP 8-bit Data Register 8-bit DAC VOUT + VL GND 2016 ILL2.1 SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 © SUMMIT MICROELECTRONICS, Inc. 1999 2016-04 4/24/99 • Campbell, CA 95008 1 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com Characteristics subject to change without notice S9318 PIN NAMES Symbol INC UP/DN VH PINOUT Description Increment Input, High to Low Edge Trigger Up/Down Input controlling relative VOUT movement V+ reference input GND Analog and Digital Ground VOUT Trimmed Voltage Output VL V- reference input CS Active low chip select input VDD Supply Voltage (2.7V to 5.5V) INC 1 8 VDD UP/DN 2 7 CS VH 3 6 VL GND 4 5 VOUT 2016 ILL1.1 CS Chip Select (CS CS) is an active low input. Whenever CS is high the S9318 is in standby mode and consumes the least power. This mode is equivalent to a potentiometer that is adjusted to the required setting. When CS is low the S9318 will recognize transitions on the INC input and will move the VOUT either toward the VH reference or toward the VL reference depending upon the state of the UP/DN input. Analog Section The S9318 is an 8-bit, voltage output digital-to-analog converter (DAC). The DAC consists of a resistor network that converts an 8-bit value into equivalent analog output voltages in proportion to the applied reference voltage. Reference Inputs The voltage differential between the VL and VH inputs sets the full-scale output voltage range. VL must be equal to or greater than ground (i.e. a positive voltage). VH must be greater than VL and less than or equal to VDD. See table on page 3 for guaranteed operating limits. The host may exit an adjustment routine in two ways: deselecting the S9318 while INC is low will not perform a store operation (a subsequent power cycle will recall the original data); deselecting the S9318 while INC is high will store the current VOUT setting into nonvolatile memory. Output Buffer Amplifier The voltage output is a precision unity-gain follower that can slew up to 1V/µs. INC Increment (INC INC) is an edge triggered input. Whenever CS is low and a high to low transition occurs on the INC input, the VOUT voltage will either move toward VH or VL depending upon the state of the UP/DN input. Digital Interface The interface is designed to emulate a simple up/down counter, but instead of a parallel count output, a ratiometric voltage output is provided. DN UP/Down (UP/DN DN) is an input that will determine the VOUT movement relative to VH and VL. When CS is low, UP/DN is high and there is a high to low transition on INC, the VOUT voltage will move (1/256th x VH-VL) toward VH. When CS and UP/DN are low, and there is a high to low transition on INC, the VOUT will move (1/256th x VH-VL) toward VL. 2016-04 4/24/99 2 S9318 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias Storage Temperature Voltage on pins with reference to GND: Analog Inputs Digital Inputs Analog Outputs Digital Outputs Lead Solder Temperature (10 secs) RECOMMENDED OPERATING CONDITIONS Condition -55°C to +125°C -65°C to +150°C -0.5V to VDD+.5V -0.5V to VDD+.5V -0.5V to VDD+.5V -0.5V to VDD+.5V 300°C *COMMENT Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operation sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Min Max Temperature -40°C +85°C VDD +2.7V +5.5V 2016 PGM T1.1 DAC DC ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, VrefH = VDD, VrefL = 0V, TA = -40°C to +85°C, unless specified otherwise Accuracy Symbol Parameter Conditions Min. Typ. Max. Units INL Integral Non-Linearity ILOAD = 100µA, - 0.5 ±1 LSB DNL Differential Non-Linearity ILOAD = 100µA, Guaranteed but not tested - 0.1 ±0.5 LSB References VH VrefH Input Voltage VrefL - VDD V VL VrefL Input Voltage Gnd - VrefH V RIN VrefH to VrefL Resistance - 38K - Ω TCRIN Temperature Coefficient of RIN VrefH to VrefL - 600 - ppm/°C Analog GEFS Full-Scale Gain Error DATA = FF - - ±1 LSB Output VOUTZS Zero-Scale Output Voltage DATA = 00 0 20 mV TCVOUT VOUT Temperature Coefficient - 50 µV/°C +1000 µA VDD = +5, ILOAD = 50µA, VrefH = +5V, VrefL = 0V Guaranteed but not tested IL Amplifier Output Load Current ROUT Amplifier Output Resistance IL = 100µA PSRR Power Supply Rejection eN - -200 VDD = +5V VDD = +3V Ω Ω - 10 20 ILOAD = 10µA - - 1 Amplifier Output Noise f = 1KHz, VDD = +5V - 90 - THD Total Harmonic Distortion VIN = 1V rms, f = 1KHz - 0.08 - % BW Bandwidth - 3dB VIN = 100mV rms - 300 - kHz LSB/V nV/ HZ 2016 PGM T3.4 2016-04 4/24/99 3 S9318 RELIABILITY CHARACTERISTICS Symbol Parameter Min VZAP ESD Susceptibility ILTH Max Unit Test Method 2000 V MS-883, TM 3015 Latch-Up 100 mA JEDEC Standard 17 TDR Data Retention 100 Years MS-883, TM 1008 NEND Endurance 1,000,000 Stores MS-883, TM 1033 2016 PGM T2.0 DC ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, VH = VDD, VL = 0V, Unless otherwise specified Symbol Parameter Conditions IDD Supply Current during store, note 1 ISB Min Max Units CS = VIL 1.2 mA Supply Standby Current CS = VIH 200 µA IIH Input Leakage Current VIN = VDD 10 µA IIL Input Leakage Current, note 2 VIN = 0V -25 µA VIH High Level Input Voltage 2 VDD V VIL Low Level Input Voltage 0 0.8 V 2016 PGM T4.3 Notes: 1. IDD is the supply current drawn while the EEPROM is being updated. IDD does not include the current that flows through the Reference resistor chain. 2. CS, UP/DN and INC have internal pull-up resistors of approximately 200kΩ. When the input is pulled to ground the resulting output current will be VDD/200kΩ. 2016-04 4/24/99 4 S9318 OPERATIONAL TRUTH TABLE INC CS UP/DN DN Operation HITOLO L H VOUT toward VH HITOLO L L VOUT toward VL H LOTOHI X Store Setting L LOTOHI X Maintain Setting, NO Store VDD VDD VDD Standby 2016 PGM T5.1 AC TIMING CHARACTERISTICS VDD = +4.5V to +5.5V Symbol Parameter Min Max Units tCLIL CS to INC Setup 100 ns tIHDC INC High to UP/DN Change 100 ns tDCIL UP/DN to INC Setup 100 ns tIL INC Low Period 200 ns tIH INC High Period 200 ns tIHCH INC Inactive to CS Inactive 100 ns tWP Write Cycle Time 5 ms tILVOUT INC to VOUT Delay 5 µs 2016 PGM T6.1 CS tCLIL tIL tIH tIHCH tWP INC tIHDC tIHDHLD UP/DN tILVOUT VOUT 2016 ILL3.1 AC TIMING DIAGRAM 2016-04 4/24/99 5 S9318 8 Pin SOIC (Type S) Package JEDEC (150 mil body width) .050 (1.27) TYP. .050 (1.270) TYP. 8 Places .157 (4.00) .150 (3.80) .275 (6.99) TYP. .030 (.762) TYP. 8 Places 1 .196 (5.00) .189 (4.80) FOOTPRINT .061 (1.75) .053 (1.35) .020 (.50) x45° .010 (.25) .0192 (.49) .0138 (.35) .0098 (.25) .004 (.127) .05 (1.27) TYP. .035 (.90) .016 (.40) .244 (6.20) .228 (5.80) 8pn JEDEC SOIC ILL.2 ORDERING INFORMATION S9318 S Package S = 8 Pin SOIC Base Part Number 2016 ILL4.1 NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. © Copyright 1999 SUMMIT Microelectronics, Inc. 2016-04 4/24/99 6