Features •= •= •= •= •= •= •= •= •= •= •= •= •= Saifun NROM™ Cell Serial Peripheral Interface (SPI) Compatible, Supports SPI Modes 0 (0,0) and 3 (1,1) Byte and Page Write Operation: 1024 pages (256 Bytes/Page) Single Byte or Page Write Cycle in 10ms Typical Single Supply Voltage: 2.7V to 3.6V 25MHz Clock Rate Block Write Protection: Protect Quarter, Half or Entire Array Write Protect Pin and Write Disable Instructions of Both Hardware and Software Data Protection 100,000 Erase Cycles (Minimum) More than 20-Year Data Retention Low-power Standby Current (less than 1µA) 8-SOIC Narrow Package MLF Leadless Package Temperature Range: Industrial: -40°C to +85°C Commercial: 0°C to +70°C – – SA25C020 Advanced Information 2Mb EEPROM with 25MHz SPI Bus Interface – – http://www.saifun.com Saifun NROMTM is a trademark of Saifun Semiconductors Ltd. This Data Sheet states Saifun's current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 1911 Rev: 0 Amendment: 0 Issue Date: 20 July 2003 SA25C020 Advanced Information SAIFUN General Description The SA25C020 is available in a space-saving, 8-lead narrow SOIC package The SA25C020 is a 2Mb (512K X 4) CMOS non-volatile serial EEPROM. This device fully conforms to the SPI 4-wire protocol, is enabled through the Chip Select (CSb) pin, and uses Clock (SCK), Data-in (SI) and Data-out (SO) pins to synchronously control data transfer between the SPI microcontroller and the Serial EEPROM. The SA25C020 is part of the SPI EEPROM family. It is designed to work with any SPIcompatible, high-speed microcontroller, and offers both hardware (WPb pin) and Software (“block protect”) data protection. For example, programming a 2-bit code into the status register prevents program with top ¼, top ½ or entire array write protection and enables block write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WPb pin to protect against inadvertent write attempts to the status register. The memory can be written from 1 up to 256 bytes at a time via the Byte / Page Write (PW) instruction. The memory consists of 1024 pages or 262,144 bytes. Each device requires only a 3.0V power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The SA25C020 does not require a VPP supply. The HOLDb pin may be used to suspend any serial communication without resetting the serial sequence. In addition, the serial interface allows a minimal-pin-count packaging designed to simplify PC board layout requirements and offers the designer a variety of low-voltage and low-power options. Saifun’s SPI Serial EEPROM products are designed and tested for applications requiring high endurance and low power consumption for a continuously reliable non-volatile solution for all markets. 2 SA25C020 Advanced Information SAIFUN Table of Contents Features ........................................................................... 1 General Description ........................................................ 2 Memory Organization...................................................... 5 Connection Diagrams ..................................................... 6 Ordering Information ...................................................... 7 Product Specifications ................................................... 8 Absolute Maximum Ratings....................................... 8 ESD/Latch Up Specification (JEDEC 8 Spec) ........... 8 Operating Conditions................................................. 8 DC Characteristics .......................................................... 9 AC Test Conditions ....................................................... 10 Timing Diagrams ........................................................... 11 Signal Description......................................................... 13 Chip Select (CSb).................................................... 13 Serial Clock (SCK) .................................................. 13 Serial Input (SI) ....................................................... 13 Serial Output (SO)................................................... 13 Hold (HOLDb).......................................................... 13 Write Protect (WPb) ................................................ 13 Serial Interface Description .......................................... 14 SPI Modes............................................................... 14 Master ............................................................. 14 Slave ............................................................... 14 Transmitter/Receiver ....................................... 14 Serial Opcode.................................................. 14 Invalid Opcode ................................................ 14 Chip Select (CSb)............................................ 15 Hold Condition................................................. 15 Write Protect ................................................... 16 Functional Description ................................................. 17 Instructions.............................................................. 17 Read Status Register (RDSR) ................................. 18 Write Enable (WREN) ............................................. 20 Write Disable (WRDI).............................................. 20 Write Status Register (WRSR) ................................ 21 Read Data Bytes (READ) ........................................ 23 Byte or Page Write (PW)......................................... 24 Read Electronic Signature (Read_Id) ...................... 26 Powerup and Powerdown ........................................ 27 Physical Dimensions..................................................... 28 Contact Information ...................................................... 31 Life Support Policy........................................................ 31 3 SA25C020 Advanced Information SAIFUN List of Figures Figure 16. Read Electronic Signature (Read Id) Instruction Sequence ............................................................ 26 Figure 1. SA25C020 Block Diagram................................ 5 Figure 17. 8-pin SOIC Package..................................... 28 Figure 2. SOIC 8 (150 mil)/PDIP/MLF Package (Top View) ............................................................. 6 Figure 18. 8-pin MLF Leadless Package ....................... 29 Figure 3. SA25C020 Ordering Information ...................... 7 Figure 19. Molded Dual-in-line Package (N) Package Number N08E...................................................... 30 Figure 4. SPI Mode 0 (0,0) Input Timing........................ 11 Figure 5. SPI Mode 0 (0,0) Output Timing ..................... 11 Figure 6. AC Measurements I/O Waveform................... 12 Figure 7. Supported SPI Modes .................................... 14 Figure 8. Hold Condition................................................ 15 Figure 9. SPI Serial Interface ........................................ 17 List of Tables Table 1. Pin Names......................................................... 6 Table 2. DC Characteristics............................................. 9 Table 3. AC Test Conditions.......................................... 10 Table 4. AC Measurements........................................... 12 Table 5. Instruction Set ................................................. 17 Figure 10. Read Status Register (RDSR) Instruction Sequence ............................................................ 19 Table 6. Status Register Format.................................... 17 Figure 11. Write Enable (WREN) Instruction Sequence 20 Table 7. Read Status Register Definition....................... 18 Figure 12. Write Disable (WRDI) Instruction Sequence. 20 Table 8. Block Write Protect Bits................................... 21 Figure 13. Write Status Register (WRSR) Instruction Sequence ............................................................ 22 Table 9. WPBEN Operation .......................................... 21 Figure 14. Read (READ) Instruction Sequence ............. 23 Figure 15. Byte or Page Write (PW) Instruction Sequence ............................................................ 25 Table 10. Powerup ........................................................ 27 4 SA25C020 Advanced Information SAIFUN Each byte or page can be individually written with the bits programmed from 1 to 0 and from 0 to 1. Memory Organization The memory is organized in the following manner: •= 262,144 bytes (8 bits each) •= 1024 pages (256 bytes each) SRAM PS Logic X D E C Array - L RD Array - R DATA PATH Figure 1. SA25C020 Block Diagram HOLDb WPb Vcc GND SO SI SCK CSb IO 5 SA25C020 Advanced Information SAIFUN Connection Diagrams CSb 1 SO 2 8 VCC 7 HOLDb SA25C020 WPb 3 6 SCK GND 4 5 SI Figure 2. SOIC 8 (150 mil)/PDIP/MLF Package (Top View) Table 1. Pin Names Pin Name CSb Signal Name Chip Select SCK Serial Data Clock SI Serial Data Input SO Serial Data Output GND Ground VCC Power Supply WPb Write Protect HOLDb Suspend Serial Input 6 SA25C020 Advanced Information SAIFUN Ordering Information SA 25 C XX L E PP F X Package Letter Description Blank X Tube Tape and Reel Blank F Non Lead Free Lead Free N MN MLF 8-pin DIP 8-pin SOIC (150 mil) 8-lead MLFo Blank E 0 to 70 C -40 to +85 C L 2.7 V to 3.6 V 020 2 Mb with Write Protect C CMOS 25 SPI-2 Wires SA Saifun Non-Volatile Memory o Temp. Range Voltage Operating Range Density Interface Figure 3. SA25C020 Ordering Information 7 SA25C020 Advanced Information SAIFUN Product Specifications Absolute Maximum Ratings Storage Temperature -65 °C to +150 °C All input or output voltages with respect to Ground 4.5 V to -0.3 V Lead Temperature (Soldering, 10 seconds) +235 °C ESD/Latch Up Specification (JEDEC 8 Spec) Human Body Model Minimum 4 KV Machine Model Minimum 500 V Charge Device Model Minimum 1 KV Latch Up 100 mA on all pins +125°C Operating Conditions Operating Temperature: SA25C020 SA25C020 E 0 °C to +70 °C -40 °C to +85 °C Positive Power Supply: SA25C020 2.7 V to 3.6 V 8 SA25C020 Advanced Information SAIFUN DC Characteristics Applicable over recommended operating range from TAI = -40 ºC to 85 ºC, VCC = 2.7-3.6 V. Table 2. DC Characteristics Symbol Parameter Test Conditions Limits Unit Min Typ* Max 2.7 3 3.6 V 9 12 mA VCC Supply Voltage ICC1 Active Power Supply Current (Read) SCK = 0.1VCC/0.9 VCC @ 25 MHz ICC2 Active Power Supply Current (Page Write) CSb = VCC 15 mA ICC3 Active Power Supply Current (WRSR) CSb = VCC 15 mA ISB Standby Current VCC = 3.6 V, CSb = VCC 1 µA IIL Input Leakage Current VIN = GND to VCC 1 µA IOL Output Leakage Current VIN = GND to VCC 1 µA VIL Input Low Voltage -0.3 0.3 VCC V VIH Input High Voltage 0.7 VCC VCC + 0.5 V VOH Output High Voltage IOH = -0.1 mA VOL Output Low Voltage IOL = 1.6 mA; VCC = 2.7 V *Typical values are at TAI = 25 ºC and 3 V. VCC 0.2 V 0.4 V 9 SA25C020 Advanced Information SAIFUN AC Test Conditions Table 3. AC Test Conditions Symbol Parameter 25 MHz Min Typ D.C. Max 25 Unit FSCK SCK Clock Frequency MHz tCRT Clock Rise Time (Slew Rate) 0.1 V/ns tCFT Clock Fall Time (Slew Rate) 0.1 V/ns tWH SCK High Time 18 ns tWL SCK Low Time 18 ns tCS CSb High Time 100 ns tCSS ** CSb Setup Time 10 ns tCSH ** CSb HOLD Time 10 ns tHD ** HOLDb Setup Time 10 ns tCD ** HOLDb Hold Time 10 ns tV Output Valid 0 15 ns tHO Output Hold Time 0 ns tHD:DAT Data in Hold Time 5 ns tSU:DAT Data in Setup Time 5 ns tLZ ** HOLDb to Output Low Z 15 ns tHZ ** HOLDb to Output High Z 20 ns Output Disable Time 15 ns ** tDIS ** tWPS ** tWPH Write Protect Setup Time 20 Write Protect Hold Time 100 tPW * Byte or Page Write tRES Release SP Mode Endurance ns ns 10 100K * 256 bytes in the checkerboard programming formation. ** Value guaranteed by characterization, not 100% tested in production 15 ms 1000 ns Erase cycles 10 SA25C020 Advanced Information SAIFUN Timing Diagrams All timing diagrams are based on SPI protocol modes 0 and 1. tCS CS tCSH tCSS tCSH tCSS SCK tSU:DAT tHD:DAT SI tCRT tCFT MSB IN LSB IN High Impedance SO Figure 4. SPI Mode 0 (0,0) Input Timing CS tWH SCK tV tHO tV tHO tWL SO tDIS LSB OUT Figure 5. SPI Mode 0 (0,0) Output Timing 11 SA25C020 Advanced Information SAIFUN Input and Output Timing Reference Levels Input Levels 0.8Vcc 0.7Vcc 0.3Vcc 0.2Vcc Figure 6. AC Measurements I/O Waveform Table 4. AC Measurements Symbol CL Parameter Load Capacitance Input Rise and Fall Times Min Max 30 Unit PF 5 ns Input Pulse Voltage 0.2 VCC to 0.8 VCC V Input and Output Timing Reference Voltages 0.3 VCC to 0.7 VCC V 12 SA25C020 Advanced Information SAIFUN Signal Description Chip Select (CSb) This is an active-low input pin to the device that is generated by the master controlling the device. A low level on this pin selects the device, while a high level deselects the device. All serial communications with the device are enabled only when this pin is held low. Serial Clock (SCK) This is an input pin to the device that is generated by the master controlling the device. It is a clock signal that synchronizes the communication between a master and the device. All input information (SI) to the device is latched on the rising edge of this clock input, while output data (SO) from the device is driven after the falling edge of this clock input. Serial Input (SI) This is an input pin to the device that is generated by the master controlling the device. The master transfers input information (instruction, addresses and the data to be programmed) into the device serially via this pin. This input information is latched on the rising edge of the SCK. Serial Output (SO) This is an output pin from the device that is used to transfer output data to the controlling master. Output data is serially shifted out on this pin after the falling edge of the SCK. Hold (HOLDb) This is an active low input pin to the device that is generated by the master controlling the device. When driven low, this pin suspends any current communication with the device. The suspended communication can be resumed by driving this pin high. This feature eliminates the need to re-transmit the entire sequence by enabling the master to resume the communication from where it was left off. This pin should be tied high if this feature is not used. Refer to Hold Condition, page 15, for additional details. Write Protect (WPb) This is an active low input pin to the device. This pin allows enabling and disabling of writes to the device's memory array and status register. When this pin is held low, writes to the memory array and status register are disabled; when it is held high, they are enabled. Refer to Write Protect, page 16, for additional details. 13 SA25C020 Advanced Information SAIFUN Serial Interface Description SPI Modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: •= CPOL=0, CPHA=0 CPHA 0 0 CS 1 1 CS SO •= SCK remains at 0 for CPOL = 0, CPHA = 0 •= SCK remains at 1 for CPOL = 1, CPHA = 1 •= CPOL=1, CPHA=1 CPOL In both of these modes, input data is latched on the rising edge of SCK, and output data is available from the falling edge of SCK. The difference between the two modes, as shown in Figure 7, is the clock polarity when the bus master is in Standby mode and is not transferring data, as follows: MSB SI MSB Figure 7. Supported SPI Modes Master Serial Opcode The device that generates the SCK. As the SCK pin is always an input, the SA25C020 always operates as a slave. The first byte is received after the device is selected. This byte contains the opcode that defines the operation to be performed (for more details, refer to Table 5, page 17). Transmitter/Receiver Invalid Opcode The SA25C020 has separate pins designated for data transmission and reception. If an invalid opcode is received, no data is shifted into the SA25C020, and the serial output pin remains in a high impedance state until a CSb falling edge is detected again, which reinitializes the serial communication. Slave 14 SA25C020 Advanced Information SAIFUN Chip Select (CSb) The SA25C020 is selected when the CSb pin is low. When the device is not selected, data is not accepted via the SI pin, and the SO pin remains in a high impedance state. Hold Condition The HOLDb pin is used in conjunction with the CSb pin to select the SA25C020. When the device is selected and a serial sequence is underway, HOLDb can be used to pause the serial communication with the master device without resetting the serial sequence. To enter the hold condition the device must be selected, with CSb low. As shown in Figure 8, the Hold condition starts on the falling edge of the HOLDb signal, provided that SCK is low. The Hold condition ends on the rising edge of the HOLDb signal, provided that SCK is low. If the falling edge does not coincide with SCK being low, the Hold condition starts only after SCK next goes low. Similarly, if the rising edge does not coincide with SCK being low, the Hold condition ends only after SCK next goes low. During the Hold condition, SO is high impedance, and SI and SCK are Don’t Care. In most cases, the device is kept selected, with CSb driven low, for the entire duration of the Hold condition, which ensures that the internal logic state remains unchanged from the moment it enters the Hold condition. NOTE: Driving CSb high while HOLDb is still low is not a legal operation. SCK HOLD Hold Condition (Standard Use) Figure 8. Hold Condition Hold Condition (Non-Standard Use) 15 SA25C020 Advanced Information SAIFUN Write Protect The WPb pin enables write operations to the status register when held high. When the WPb pin is brought low and the WPBEN bit is 1, all write operations to the status register are inhibited (for more details, refer to Table 9, page 21). If WPb goes low while CSb is still low, the write to the status register is interrupted. If the internal write cycle has already been initiated, WPb going low has no effect on any write operations to the status register. The WPb pin function is blocked when the WPBEN bit in the status register is 0, which enables the user to install the SA25C020 in a system with the WPb pin tied to ground but still able to write to the status register. All WPb pin functions are enabled when the WPBEN bit is set to 1. 16 SA25C020 Advanced Information SAIFUN Functional Description Instructions Figure 9 presents a schematic diagram of the SA25C020 's SPI serial interface. MASTER: MICROCONTROLLER DATA OUT DATA IN SLAVE SA25C020 SI SO SERIAL CLOCK SCK SSO CSb SS1 SS2 The SA25C020 's SPI consists of an 8-bit instruction register that decodes a specific instruction to be executed. Thirteen different instructions (called opcodes) are incorporated in the device for various operations. Table 5 lists the instruction set and the format for proper operation. All opcodes, array addresses and data are transferred in an MSB-first-LSB-last fashion. Detailed information about each of these opcodes is provided for the individual instruction descriptions in the sections that follow. Table 5. Instruction Set SS3 SI SO Instruction Name Instruction Format WREN 0000 0110 Set Write Enable Latch WRDI 0000 0100 Reset Write Enable Latch RDSR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register READ 0000 0011 Read Data from Memory Array Byte or Page Write 0000 0010 Write Data to Memory Array READ_ID 1010 1011 +3 dummy bytes Operation SCK CSb SI SO SCK CSb SI SO Read ID SCK CSb Figure 9. SPI Serial Interface In addition to the instruction register, the device also contains an 8-bit status register that can be accessed by RDSR and WRSR instructions. The byte defines the Block Write Protection (BP1 and BP0) levels, Write Enable (WEN) status, Busy/Rdy (/RDY) status and Hardware Write Protect (WPBEN) status of the device. Table 6 illustrates the format of the status register. Table 6. Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 WPBEN X X X BP1 BP0 WEN /RDY Bit1 Bit 0 17 SA25C020 Advanced Information SAIFUN Read Status Register (RDSR) The RDSR instruction provides read access to the status register. The BUSY/RDY and WREN statuses of the device can also be determined by this instruction. In addition, the Block Write Protection bits indicate the extent of protection employed. In order to determine the status of the device, the value of the /RDY bit can be continuously polled before sending any write instruction. Table 7. Read Status Register Definition Bit Definition Bit 0 (/RDY) Bit 0 = 0 (/RDY) indicates that the device is READY. Bit 0 = 1 indicates that a write cycle is in progress. Bit 1 (WEN) Bit 1 = 0 indicates that the device is not write enabled. Bit 1 = 1 indicates that the device is write enabled. Bit 2 (BP0) Block Write Protect Bit 0 Bit 3 (BP1) Block Write Protect Bit 1 Bit 7 (WPBEN) Write Protect Mode Enable Bit Bit 7 (WPBEN) is Hardware Write Protect mode. If this bit is a 1, this mode is enabled and the status register is write protected. Bits 6 through 4 are always 0. Bit 3 (BP1) and Bit 2 (BP0) together indicate a Block Write Protection previously sent to the device. Bits 0 and 1 are 1 during an internal write cycle. Bit 1 (WEN) indicates the Write Enable status of the device. This bit is read by executing an RDSR instruction. If this bit is 1, the device is write enabled; if it is 0, it is write disabled. Bit 0 (/RDY) indicates the Busy/Ready status of the device. This bit is a read-only bit and is read by executing an RDSR instruction. If this bit is 1, the device is busy doing a Program or Erase cycle; if it is 0, the device is ready. 18 SA25C020 Advanced Information SAIFUN The RDSR command requires the following sequence: 2. The data on the SI pin becomes Don't Care. 1. The CSb pin is pulled low to select the device and the RDSR opcode is transmitted on the SI pin. 3. The data from the status register is shifted out on the SO pins, with the D7 bit first and the D0 bit last, as shown in Figure 10. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 7 6 18 19 20 21 22 23 SCK Instruction SI Status Register Out SO High Impedance 7 MSB 6 5 4 3 2 Status Register Out 1 5 4 3 MSB Figure 10. Read Status Register (RDSR) Instruction Sequence 2 1 0 7 MSB 19 SA25C020 Advanced Information SAIFUN Write Enable (WREN) Write Disable (WRDI) The device powers up in the Write Disable state when VCC is applied. All programming instructions must be preceded by a WREN instruction. The instruction sequence is shown in Figure 11, with SO in high impedance. To protect the device against inadvertent writes, the WRDI instruction disables all programming modes. The WRDI instruction is independent of the WP pin's status. The WREN instruction should be executed after the WRDI instruction to re-enable all programming modes. The instruction sequence is shown in Figure 12, with SO in high impedance. CS 0 1 2 3 4 5 6 7 SCK Instruction SI Figure 11. Write Enable (WREN) Instruction Sequence CS 0 1 2 3 4 5 6 7 SCK Instruction SI Figure 12. Write Disable (WRDI) Instruction Sequence 20 SA25C020 Advanced Information SAIFUN Table 9. WPBEN Operation Write Status Register (WRSR) The WRSR instruction enables the user to select one of four levels of protection. The SA25C020 is divided into four array segments. The top quarter, top half or all of the memory segments can be protected (for more details, refer to Table 8). The data within a selected segment is therefore read-only. Table 8. Block Write Protect Bits Level Status Register Bits WPb WPBEN WEN X 0 0 UnProtected Status protected Blocks Register Blocks Protected Protected Protected X 0 1 Protected Writeable Writeable Low 1 0 Protected Protected Protected Low 1 1 Protected Writeable Protected High X 0 Protected Protected Protected High X 1 Protected Writeable Writeable The WRSR instruction is enabled: Array Addresses Protected BP1 BP0 0 0 0 None 1/4 0 1 30000 - 3FFFF 1/2 1 0 20000 - 3FFFF All 1 1 00000 - 3FFFF The WRSR instruction (as shown in Table 9) also allows the user to enable or disable the WPb pin via the WPBEN bit. Hardware write protection is enabled when the WPb pin is low and the WPBEN bit is 1, and disabled when either the WP pin is high or the WPBEN bit is 0. When the device is hardware write protected, writes to the status register are disabled. NOTE: When the WPBEN bit is hardware write protected, it cannot be changed back to 0 while the WPb pin is held low. 1. When the WPb pin is held high and the device has been previously write enabled via the WREN instruction. 2. When the WPb pin is held low, the WPBEN bit is 0 and the device has been previously write enabled via the WREN instruction. 21 SA25C020 Advanced Information SAIFUN The WRSR command following sequence: requires the 2. The WRSR opcode is then transmitted on the SI pin, followed by the data to be programmed. 1. The CSb pin is pulled low to select the device. The instruction sequence is shown in Figure 13. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction SI Status Register In 7 6 5 4 3 2 1 MSB SO High Impedance Figure 13. Write Status Register (WRSR) Instruction Sequence 0 22 SA25C020 Advanced Information SAIFUN If only one byte is to be read, the CSb line should be driven high after the data comes out. The READ sequence can be continued, as the byte address is automatically incremented and data continues to shift out. When the highest address is reached, the address counter rolls over to the lowest address, enabling the entire memory to be read in one continuous READ cycle. The instruction sequence is shown in Figure 14. Read Data Bytes (READ) Reading the memory via the serial SPI link requires the following sequence: 1. After the CSb line is pulled low to select the device, the READ opcode is transmitted via the SI line, followed by the 3-byte address to be read (address bits A23 to A18 are Don’t Care). 2. Upon completion, any data on the SI line is ignored. Driving CSb high terminates the READ instruction, which can be done at any time during data output. Any READ instruction executed while an Erase, Program or WRSR cycle is in progress is rejected without having any effect on the cycle in progress. 3. The data (D7-D0) at the specified address is then shifted out onto the SO line. Each bit is shifted out at a maximum SCK frequency of FSCK. CS 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 2 1 0 32 33 34 7 6 5 35 36 37 38 39 SCK 24-Bit Address Instruction 23 22 21 SI 3 DATA OUT 1 SO High Impedance MSB Figure 14. Read (READ) Instruction Sequence 4 3 2 DATA OUT 2 1 0 7 MSB 23 SA25C020 Advanced Information SAIFUN Byte or Page Write (PW) The Byte or Page Write instruction allows bytes to be programmed and erased in the memory (changing bits from 1 to 0 and from 0 to 1). In order to program to the SA25C020, two separate instructions must be executed. The device must first be write enabled via the WREN instruction, and then a Byte or Page Write sequence (which consists of four bytes plus data) may be executed. The address of the memory locations to be written must be outside the protected address field location selected by the Block Write Protection level. During an internal Write cycle, all commands are ignored except the RDSR instruction. A Byte or Page Write instruction requires the following sequence: After the CSb line is pulled low to select the device, the WRITE opcode is transmitted via the SI line, followed by the byte address and the data (D7-D0) to be written. Programming starts after the CSb pin is brought high. The CSb pin's low-to-high transition must occur during the SCK low time, immediately after the clock in the D0 (LSB) data bit. The instruction sequence is shown in Figure 15, page 25. As soon as CSb is driven high, the self-timed Write cycle (whose duration is defined as TPW ) is initiated. While the Page Write cycle is in progress, the status register may be read to check the value of the Write in Progress (/RDY) bit. The /RDY bit is 1 during the self-timed Page Write cycle, and 0 when it is completed. The Write Enable Latch (WEN) bit is reset at some unspecified time before the cycle is completed. The SA25C020's PW operation is capable of up to a 256-byte writing, from 1 to 256 bytes at a time (changing bits from 1 to 0 and from 0 to 1), provided that they lie in consecutive addresses on the same page of memory. After each byte is received, the eight low-order address bits are internally incremented by one. If more than 256 bytes of data are transmitted, the address counter rolls over and the previously written data is overwritten. The SA25C020 is automatically returned to the write disable state at the completion of a Write cycle. NOTES: 1. If the device is not write enabled, the device ignores the PW instruction and returns to the standby state when CSb is brought high. A new CSb falling edge is required to re-initiate the serial communication. 2. A PW instruction applied to a page that is protected by the Block Protect (BP1, BP0) bits (as described in Table 7, page 18, and Table 8, page 21) is not executed. 24 SA25C020 Advanced Information SAIFUN CS 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCK 24-Bit Address Instruction SI 23 22 21 Data Byte 1 3 2 1 0 MSB 7 6 5 4 3 2 1 0 MSB 2078 2079 2077 2076 2075 2074 2073 40 41 42 43 44 45 46 47 48 49 59 51 52 53 54 55 2072 CS 1 0 SCK Data Byte 2 SI 7 MSB 6 5 4 3 Data Byte 3 2 1 0 7 MSB 6 5 4 3 2 Data Byte 256 1 0 7 6 5 4 MSB Figure 15. Byte or Page Write (PW) Instruction Sequence 3 2 25 SA25C020 Advanced Information SAIFUN The 8-bit Electronic Signature, which stored in the memory, is then shifted out on SO, with each bit being shifted out during the falling edge of SCK. The instruction sequence is shown in Figure 16. Read Electronic Signature (Read_Id) The device features an 8-bit Electronic Signature, whose value for the SA25C020 is 11h. This can be read using the RES instruction. Driving CSb high after the Electronic Signature has been read at least once terminates the Read Id instruction. Sending additional clock cycles on SCK, while CSb is driven low causes the Electronic Signature to be output repeatedly. The Read Id instruction always provides access to the Electronic Signature of the device (except while a Byte/Page Write or Write Status Register cycle is in progress). Any Read Id instruction executed while a Byte/Page Write or Write Status Register cycle is in progress is not decoded, and has no effect on the cycle in progress. When CSb is driven high, the device is put into Standby mode. The transition to Standby mode is delayed by tRES, and CSb must remain high for at least tRES(max), as specified in Table 3 on page 10. Once in Standby mode, the device waits to be selected, so that it can receive, decode and execute instructions. The device is first selected by driving CSb low. The instruction code is followed by three dummy bytes, each bit being latched in on SI during the rising edge of SCK. CS 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCK 23 22 21 SI tRES 3 Dummy Bytes Instruction 3 2 1 0 MSB SO High Impedance Electonic ID 7 6 5 4 3 2 1 0 MSB Software Protect Mode Figure 16. Read Electronic Signature (Read Id) Instruction Sequence Standby Mode 26 SA25C020 Advanced Information SAIFUN Powerup and Powerdown The device must not be selected at powerup or powerdown (that is, CSb must follow the voltage applied on VCC) until VCC reaches the correct value, as follows: •= VCC(min) at powerup, and then for a further delay of tPU (as described in Table 10) •= VSS at powerdown A simple pull-up resistor on CSb can usually be used to insure safe and proper powerup and powerdown. To avoid data corruption and inadvertent write operations during powerup, a Power On Reset (POR) circuit is included. The logic inside the device is held at reset while VCC is less than the POR threshold value (VPOR), all operations are disabled and the device does not respond to any instructions. The device ignores all instructions until a time delay of tPU has elapsed after the moment that VCC rises above the VWI threshold. However, correct operation of the device is not guaranteed if by this time VCC is still below VCC(min). No Write Status Register, Program or Erase instructions should be sent until tPU reaches the minimum VCC threshold after VCC. At powerup, the device is in Standby mode (not SP mode) and the WEN bit is reset. Normal precautions must be taken for supply rail decoupling to stabilize the VCC feed. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package pins (this capacitor is generally of the order of 0.1 µF). All operations are disabled and the device does not respond to any instructions when VCC drops at powerdown from the operating voltage to below the VPOR threshold. (The designer must be aware that if a powerdown occurs while a Write, Program or Erase cycle is in progress, data corruption can result.) Table 10. Powerup Symbol Parameter Min. Max. Unit VPOR POR Threshold Value 2.2 2.4 V tPU VCC(min) to CS low 2 ms 27 SA25C020 Advanced Information SAIFUN Physical Dimensions All measurements are in inches (millimeters), unless otherwise specified. Figure 17. 8-pin SOIC Package 28 SA25C020 Advanced Information SAIFUN Figure 18. 8-pin MLF Leadless Package 29 SA25C020 Advanced Information SAIFUN Figure 19. Molded Dual-in-line Package (N) Package Number N08E 30 SA25C020 Advanced Information SAIFUN Contact Information International Headquarters United States Saifun Semiconductors Ltd. ELROD Building 45 Hamelach St. Sappir Industrial Park Netanya 42504 Israel Saifun Semiconductors Inc. 2350 Mission College Blvd. Suite 1070 Santa Clara, CA 95054 U.S.A. Tel.: +972-(0) 9-892-8444 Fax: +972- (0) 9-892-8445 Tel: +1-408-982-5888 Fax: +1-408-982-5890 Email: [email protected] http://www.saifun.com Revision History Rev 0.0 Date Description of Change 20-July-03 Initial Release © Saifun Semiconductors Ltd. 2003 Saifun reserves the right, without notice, to change any of the products described in this guide, in order to improve functionality, reliability or design. Saifun assumes no liability arising from the application or use of any product described in this guide; and under its patent rights, gives no authorization for the use of this product or associated products. The Buyer will not hold Saifun responsible for direct or indirect damages and expenses, as well as any claim of injury or death, associated with the unauthorized use, including claims of manufacture or design negligence. Saifun and Saifun NROM are trademarks or registered trademarks of Saifun Semiconductors Ltd. Other company and brand products and service names are trademarks or registered trademarks of their respective holders. Life Support Policy Saifun's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Saifun Semiconductors Ltd. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 31