INTEGRATED CIRCUITS SA7025 Low-voltage 1GHz fractional-N synthesizer Product specification IC17 Data Handbook 1996 Aug 6 Philips Semiconductors Product specification 1GHz low-voltage Fractional-N synthesizer DESCRIPTION SA7025 PIN CONFIGURATION The SA7025 is a monolithic low power, high performance dual frequency synthesizer fabricated in QUBiC BiCMOS technology. Featuring Fractional-N division with selectable modulo 5 or 8 implemented in the Main synthesizer to allow the phase detector comparison frequency to be five or eight times the channel spacing. This feature reduces the overall division ratio yielding a lower noise floor and faster channel switching. The phase detectors and charge pumps are designed to achieve phase detector comparison frequencies up to 5MHz. A triple modulus prescaler (divide by 64/65/72) is integrated on chip with a maximum input frequency of 1.04GHz. Programming and channel selection are realized by a high speed 3-wire serial interface. DK Package CLOCK 1 20 VDD DATA 2 19 TEST STROBE 3 18 LOCK VSS 4 17 RF RFIN 5 16 RN RFIN 6 15 VDDA VCCP 7 14 PHP REFIN 8 13 PHI RA 9 12 VSSA AUXIN 10 11 PHA FEATURES • Operation up to 1.04GHz • Fast locking by “Fractional-N” divider • Auxiliary synthesizer • Digital phase comparator with proportional and integral charge SR00600 pump output Figure 1. Pin Configuration • High speed serial input • Low power consumption • Programmable charge pump currents • Supply voltage range 2.7 to 5.5V • Excellent input sensitivity: VRF_IN = –20dBm APPLICATIONS • NADC (North American Digital Cellular) • PDC (Personal Digital Cellular) • Cellular radio • Spread-spectrum receivers ORDERING INFORMATION DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG # –40 to +85°C SA7025DK SOT266-1 20-Pin Plastic Shrink Small Outline Package (SSOP) ABSOLUTE MAXIMUM RATINGS SYMBOL V VIN TSTG TA PARAMETER RATING UNITS -0.3 to +6.0 V -0.3 to (VDD + 0.3) V Storage temperature range -65 to +150 °C Operating ambient temperature range -40 to +85 °C Supply voltage, VDD, VDDA, VCCP Voltage applied to any other pin NOTE: Thermal impedance (θJA) = 117°C/W. This device is ESD sensitive. 1996 Aug 6 2 853-1786 17157 Philips Semiconductors Product specification 1GHz low-voltage Fractional-N synthesizer SA7025 PIN DESCRIPTIONS Symbol Pin Description CLOCK 1 Serial clock input DATA 2 Serial data input STROBE 3 Serial strobe input VSS 4 Digital ground RFIN 5 Prescaler positive input RFIN 6 Prescaler negative input VCCP 7 Prescaler positive supply voltage. This pin supplies power to the prescaler and RF input buffer REFIN 8 Reference divider input RA 9 Auxiliary current setting; resistor to VSSA AUXIN 10 Auxiliary divider input PHA 11 Auxiliary phase detector output VSSA 12 Analog ground PHI 13 Integral phase detector output PHP 14 Proportional phase detector output VDDA 15 Analog supply voltage. This pin supplies power to the charge pumps, Auxiliary prescaler, Auxiliary and Reference buffers. RN 16 Main current setting; resistor to VSSA RF 17 Fractional compensation current setting; resistor to VSSA LOCK 18 Lock detector output TEST 19 Test pin; connect to VDD VDD 20 Digital supply voltage. This pin supplies power to the CMOS digital part of the device 1996 Aug 6 3 Philips Semiconductors Product specification 1GHz low-voltage Fractional-N synthesizer SA7025 BLOCK DIAGRAM CLOCK VDD SERIAL INPUT + PROGRAM LATCHES DATA STROBE VSS EM FB PR 2 NM1 NM2 NM3 12 2 FB FMOD 8 RFIN PRESCALER MODULUS CONTROL FRACTIONAL 64/65/72 PRESCALER RFIN 3 NF MAIN DIVIDERS ACCUMULATOR RF FRD 8 EM TEST RN CN MAIN PHASE DETECTOR NORMAL OUTPUT CHARGE PUMP 2 CL 2 VCCP EM+EA SPEED-UP OUTPUT CHARGE PUMP MAIN REFERENCE SELECT NR PHP 2 SM 12 CK ÷2 REFERENCE DIVIDER REFIN ÷2 4 ÷2 INTEGRAL OUTPUT CHARGE PUMP SA AUXILIARY REFERENCE SELECT 2 RA EA PA AUXILIARY PHASE DETECTOR NA EA PHI 2 AUXILIARY OUTPUT CHARGE PUMP PHA 12 LOCK AUXIN 1/4 PRESCALER AUXILIARY DIVIDER VDDA VSSA SR00601 Figure 2. Block Diagram 1996 Aug 6 4 Philips Semiconductors Product specification 1GHz low-voltage Fractional-N synthesizer SA7025 DC ELECTRICAL CHARACTERISTICS VDD = VDDA = VCCP = 3V; TA = 25°C, unless otherwise specified. SYMBOL PARAMETER VSUPPLY Recommended operating conditions ISTANDBY Total standby supply currents TEST CONDITIONS VCCP = VDD, VDDA ≥ VDD LIMITS MIN TYP 2.7 EM = EA = 0, IRN = IRF = IRA = 0 50 MAX UNITS 5.5 V 500 µA Operational supply currents: I = IDD + ICCP + IDDA; IRN = 25µA, IRA = 25µA, (see Note 5) IAUX Operational supply currents EM = 0, EA = 1 3.5 mA IMAIN Operational supply currents EM = 1, EA = 0 5.5 mA ITOTAL Operational supply currents EM = EA = 1 7.5 mA Digital inputs CLK, DATA, STROBE VIH High level input voltage range 0.7xVDD VDD V VIL Low level input voltage range 0 0.3xVDD V 0.4 V Digital outputs LOCK VOL Output voltage LOW IO = 2mA VOH Output voltage HIGH IO = –2mA VDD–0.4 V Charge pumps: VDDA = 3V / IRX = 25µA or VDDA = 5V / IRX = 62.5µA, VPHX in range, unless otherwise specified. (See Note 16) |IRX| VPHOUT Setting g current range g for anyy setting g resistor 2.7V < VDDA < 5.5V 25 4.5V < VDDA < 5.5V 62.5 Output voltage range 0.7 µA VDDA–0.8 V Charge pump PHA |IPHA| I PHP_A | I PHP_A| ∆IPHA_M Output current PHA Relative output current variation PHA Output current matching PHA pump IRA = –62.5µA; VPHA = VDDA/213 400 500 600 IRA = –25µA; VPHA = VDDA/2 160 200 240 2 6 IRA = –62.5µA2, 13 VDDA = 3V, IRA = 25µA ±50 VDDA = 5V, IRA = 62.5µA ±65 µA % µA Charge pump PHP, normal mode1, 4, 6 VRF = VDDA |IPHP_N| I PHP_N I PHP_N ∆IPHP_N_M Output current PHP Relative output current variation PHP Output current matching g PHP normal mode IRN = –62.5µA; VPHP = VDDA/213 440 550 660 IRN = –25µA; VPHP = VDDA/2 175 220 265 2 6 IRN = –62.5µA2, 13 VDDA = 3V, IRA = 25µA ±50 VDDA = 5V, IRA = 62.5µA ±65 µA % µA Charge pump PHP, speed-up mode 1, 4, 7 VRF = VDDA |IPHP_S S| I PHP_S I PHP_S ∆IPHP_S_M S Output current PHP Relative output current variation PHP Output current matching g PHP speed-up mode IRN = –62.5µA; VPHP = VDDA/213 2.20 2.75 3.30 IRN = –25µA; VPHP = VDDA/2 0.85 1.1 1.35 2 6 IRN = –62.5µA2, 13 VDDA = 3V, IRA = 25µA ±250 VDDA = 5V, IRA = 62.5µA ±300 mA % µA Charge pump PHI, speed-up mode 1, 4, 8 VRF = VDDA |IPHI| Output current PHI I PHI I PHI Relative output current variation PHI ∆IPHI_M Output current matching PHI pump IRN = –62.5µA; VPHI = VDDA/213 4.4 5.5 6.6 IRN = –25µA; VPHI = VDDA/2 1.75 2.2 2.65 2 8 IRN = –62.5µA2, 13 VDDA = 3V, IRA = 25µA ±500 VDDA = 5V, IRA = 62.5µA ±600 mA % µA Fractional compensation PHP, normal mode 1, 9 VRN = VDDA, VPHP = VDDA/2 IPHP_F_N 1996 Aug 6 Fractional compensation output current PHP vs FRD3 IRF = –62.5µA;FRD = 1 to 713 –625 –400 –250 IRF = –25µA;FRD = 1 to 7 –250 –180 –100 5 nA Philips Semiconductors Product specification 1GHz low-voltage Fractional-N synthesizer SA7025 DC ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PARAMETER TEST CONDITIONS LIMITS MIN TYP MAX IRF = –62.5µA;FRD = 1 to 713 –3.35 –2.0 –1.1 IRF = –25µA;FRD = 1 to 7 –1.35 –1.0 –0.5 UNITS Fractional compensation PHP, speed up mode 1, 10 VPHP = VDDA, VRN = VDDA IPHP_F_S S Fractional compensation output current PHP vs FRD3 Pump leakage –20 20 µA nA Fractional compensation PHI, speed up mode 1, 11 VPHP = VDDA/2, VRN = VDDA IPHI_F Fractional compensation output current PHI vs FRD3 IRF = –62.5µA;FRD = 1 to 713 –5.4 –4.0 –2.6 IRF = –25µA;FRD = 1 to 7 –2.15 –1.6 –1.05 µA Charge pump leakage currents, charge pump not active IPHP_L Output leakage current PHP; normal mode1 VPHP = 0.7 to VDDA – 0.8 0.1 10 nA IPHI_L Output leakage current PHI; normal mode1 VPHI = 0.7 to VDDA – 0.8 0.1 10 nA IPHA_L Output leakage current PHA VPHA = 0.7 to VDDA – 0.8 0.1 10 nA AC ELECTRICAL CHARACTERISTICS VDD = VDDA = VCCP = 3V; TA = 25°C; fRF_IN = 1GHz, input level = –20dBm; unless otherwise specified. Test Circuit, Figure 4. The parameters listed below are tested using automatic test equipment to assure consistent electrical characteristics. The limits do not represent the ultimate performance limits of the device. Use of an optimized RF layout will improve many of the listed parameters. SYMBOL PARAMETER TEST CONDITIONS LIMITS MIN TYP MAX UNITS Main divider fRF_IN Input signal frequency VRF_IN Input sensitivity Direct coupled input14 1.04 1000pF input coupling 1.04 1040MHz –20 0 GHz dBm Reference divider (VDD = VDDA = 3V or VDD = 3V / VDDA = 5V) fREF_IN Input signal frequency VREF_IN Input signal range, range AC coupled ZREF_IN Reference divider input impedance15 2.7 < VDD and VDDA < 5.5V 25 2.7 < VDD and VDDA < 4.5V 30 2.7 < VDD and VDDA < 5.5V 500 2.7 < VDD and VDDA < 4.5V 300 MHz mVP-P 100 kΩ 3 pF Auxiliary divider Input signal frequency fAUX_IN PA = “0”, prescaler enabled Input signal frequency PA = “1”, prescaler disabled VAUX_IN ZAUX_IN 4.5V ≤ VDDA ≤ 5.5V 4.5V ≤ VDDA ≤ 5.5V Input signal range, AC coupled 0 50 0 150 0 30 0 40 200 Auxiliary divider input impedance MHz mVP-P 100 kΩ 3 pF Serial interface15 fCLOCK Clock frequency 10 MHz tSU Set-up time: DATA to CLOCK, CLOCK to STROBE 30 ns tH Hold time; CLOCK to DATA 30 ns Pulse width; CLOCK 30 tW Pulse width; STROBE B, C, D, E words ns 30 In-Loop Performance17 VDDA = 5V, VDD = 2.7V RMM 1996 Aug 6 Main loop residual FM FVCO = 1030MHz 6 300 600 Hz Philips Semiconductors Product specification 1GHz low-voltage Fractional-N synthesizer SA7025 AC ELECTRICAL CHARACTERISTICS (continued) SYMBOL PARAMETER LIMITS TEST CONDITIONS MIN Pulse width width; STROBE A word, PR = ‘10’ MAX 1 (NM2 65) t W f VCO A word, PR = ‘01’ tSW TYP 1 f VCO [(NM2 65) (NM3 1) 72] t UNITS ns W NOTES: 1. When a serial input “A” word is programmed, the main charge pumps on PHP and PHI are in the “speed up mode” as long as STROBE = H. When this is not the case, the main charge pumps are in the “normal mode”. 2. The relative output current variation is defined thus: I OUT (I I 1) 2 2 ; with V1 = 0.7V, V2 = VDDA – 0.8V (see Figure 3). |(I 2 I 1)| I OUT 3. FRD is the value of the 3 bit fractional accumulator. 4. Monotonicity is guaranteed with CN = 0 to 255. 5. Power supply current measured with VDD = VCCP = 3V, VDDA = 5V, fRF IN = 915.99MHz, XTAL at 21.36MHz, AUX at 85.92MHz (PA = ‘0’), Main comp frequency = 240kHz, Auxiliary comp frequency = 120kHz, CN = 160, CL = 0, CK = 0. Internal registers NM1 = 52, NM2 = 0, NM3 = 4, PR = ‘10’, SM = ‘00’, SA = ‘01’, NA = 179, NF = 5, FMOD = 8, NR = 89, PA = 0, IRN = IRA = IRF = 25µA, lock condition, normal mode. Operational supply current = IDDA + IDD + ICCP. 6. Specification condition: CN = 255 7. Specification conditions: 1) CN = 255; CL = 1, or 2) CN = 75; CL = 3 8. Typical output current | IPHI | = –IRN x CN x 2(CL+1) x CK/32: 1) CN = 160; CL = 3; CK = 1, or 2) CN = 160; CL = 2; CK = 2, or 3) CN = 160; CL = 1; CK = 4, or 4) CN = 160; CL = 0; CK = 8 9. Any RFD, CL = 1 for speed-up pump. The integral pump is intended for switching only and the fractional compensation is not guaranteed. 10. Specification conditions: FRD = 1 to 7; CL = 1. 11. Specification conditions: 1) FRD = 1 to 7; CL = 1; CK = 2, or 2) FRD = 1 to 7; CL = 2; CK = 1. 12. The matching is defined by the sum of the P and the N pump for a given output voltage. 13. Limited analog supply voltage range 4.5 to 5.5V. 14. For fIN < 50MHz, low frequency operation requires DC-coupling and a minimum input slew rate of 32V/µs. 15. Guaranteed by design. 16. Close in noise for the charge pumps is tested on a sample basis in a typical application in order to eliminate parts outside the normal distribution. 17. FXTAL = 14.4MHz, VXTAL = 500mVP-P, comparison frequency = 200kHz, Loop bandwidth = 5kHz, Audio filter = 300Hz to 15kHz. 1996 Aug 6 7 Philips Semiconductors Product specification 1GHz low-voltage Fractional-N synthesizer SA7025 CURRENT I2 I1 V1 VOLTAGE V2 I2 I1 SR00602 Figure 3. Relative Output Current Variation 22nF CLOCK 1 CLOCK DATA 2 STROBE 22nF 10K 10µF VDD 20 DATA TEST 19 TEST 3 STROBE LOCK 18 LOCK 4 VSS RF 17 150k RN RFIN RN 6 RFIN VDDA 15 7 VCCP PHP 14 8 REFIN PHI 13 9 RA VSSA 12 10 AUXIN PHA 11 5 RFIN RF 150k SA7025 50 VDD 16 10µF 22nF 50 RFIN 10µF 22nF A VCCP 1k 22nF REFIN 50 150k VPH 100 22nF AUXIN VDD 22nF P VPHI 1k VPH A 50 SR00603 Figure 4. Test Circuit 1996 Aug 6 8 Philips Semiconductors Product specification 1GHz low-voltage Fractional-N synthesizer SA7025 AC TIMING CHARACTERISTICS DATA D0 D22, D30 D1 D23, D31 D0 tH tSU tSU 50% CLOCK FIRST CLOCK LAST CLOCK FIRST CLOCK tSU STROBE CLOCK ENABLED SHIFT IN DATA CLOCK DISABLED STORE DATA tSW tW CLOCK 50% 50% STROBE STROBE (B, C, D, E) WORDS (A WORD) SR00604 Figure 5. Serial Input Timing Sequence values. Therefore, the new A word will be correctly loaded provided that the STROBE signal has been at an active high value for at least a minimum number of VCO input cycles at RFIN or RFIN. FUNCTIONAL DESCRIPTION Serial Input Programming The serial input is a 3-wire input (CLOCK, STROBE, DATA) to program all counter ratios, DACs, selection and enable bits. The programming data is structured into 24 or 32 bit words; each word includes 1 or 4 address bits. Figure 5 shows the timing diagram of the serial input. When the STROBE = L, the clock driver is enabled and on the positive edges of the CLOCK the signal on DATA input is clocked into a shift register. When the STROBE = H, the clock is disabled and the data in the shift register remains stable. Depending on the 1 or 4 address bits the data is latched into different working registers or temporary registers. In order to fully program the synthesizer, 4 words must be sent: D, C, B and A. Figure 6 and Table 1 shows the format and the contents of each word. The E word is for testing purposes only. The E (test) word is reset when programming the D word. The data for CN and PR is stored by the B word in temporary registers. When the A word is loaded, the data of these temporary registers is loaded together with the A word into the work registers which avoids false temporary main divider input. CN is only loaded from the temporary registers when a short 24 bit A0 word is used. CN will be directly loaded by programming a long 32 bit A1 word. The flag LONG in the D word determines whether A0 (LONG = “0”) or A1 (LONG = “1”) format is applicable. The A word contains new data for the main divider. 1 (NM @ 65) ) t for PR + ‘01Ȁ 2 W f VCO t_strobe_min + 1 [NM @ 65 ) (NM ) 1) @ 72] ) t for PR + ‘10Ȁ 2 3 W f VCO Programming the A word means also that the main charge pumps on output PHP and PHI are set into the speed-up mode as long as the STROBE is H. Auxiliary Divider The input signal on AUX_IN is amplified to logic level by a single-ended CMOS input buffer, which accepts low level AC coupled input signals. This input stage is enabled if the serial control bit EA = “1”. Disabling means that all currents in the input stage are switched off. A fixed divide by 4 is enabled if PA = “0”. This divider has been optimized to accept a high frequency input signal. If PA = “1”, this divider is disabled and the input signal is fed directly to the second stage, which is a 12-bit programmable divider with standard input frequency (40MHz). The division ratio can be expressed as: if PA = “0”: N = 4 x NA if PA = “1”: N = NA; with NA = 4 to 4095 Main Divider Synchronization Reference Divider The A word is loaded only when a main divider synchronization signal is also active in order to avoid phase jumps when reprogramming the main divider. The synchronization signal is generated by the main divider. The signal is active while the NM1 divider is counting down from the programmed value. The new A word will be loaded after the NM1 divider has reached its terminal count; also, at this time a main divider output pulse will be sent to the main phase detector. The loading of the A word is disabled while the NM2 or NM3 dividers are counting up to their programmed 1996 Aug 6 t_strobe_min + The input signal on REF_IN is amplified to logic level by a single-ended CMOS input buffer, which accepts low level AC coupled input signals. This input stage is enabled by the OR function of the serial input bits EA and EM. Disabling means that all currents in the input stage are switched off. The reference divider consists of a programmable divider by NR (NR = 4 to 4095) followed by a three bit binary counter. The 2 bit SM register (see Figure 7) determines which of the 4 output pulses is selected as the main 9 Philips Semiconductors Product specification 1GHz low-voltage Fractional-N synthesizer accumulator works modulo Q. Q is preset by the serial control bit FMOD to 8 when FMOD = “1”. Each time the accumulator overflows, the feedback to the prescaler will select one cycle using prescaler ratio R2 instead of R1. phase detector input. The 2 bit SA register determines the selection of the auxiliary phase detector signal. Main Divider The differential inputs are amplified (to internal ECL logic levels) and provide excellent sensitivity (–20dBm at 1GHz) making the prescaler ideally suited to directly interface to a VCO as integrated on the SA620 RF gain stage, VCO and mixer device. The internal triple modulus prescaler feedback loop FB controls the selection of the divide by ratios 64/65/72, and reduces the minimum system division ratio below the typical value required by standard dual modulus (64/65) devices. As shown above, this will increase the overall division ratio by 1 if R2 = R1 + 1. The mean division ratio over Q main divider will then be NQ N NF Q Programming a fraction means the prescaler with main divider will divide by N or N + 1. The output of the main divider will be modulated with a fractional phase ripple. This phase ripple is proportional to the contents of the fractional accumulator FRD, which is used for fractional current compensation. This input stage is enabled when serial control bit EM = “1”. Disabling means that all currents in the prescaler are switched off. The main divider is built up by a 12 bit counter plus a sign bit. Depending on the serial input values NM1, NM2, NM3, and the prescaler select PR, the counter will select a prescaler ratio during a number of input cycles according to Table 2 and Table 3. Phase Detectors The auxiliary and main phase detectors are a two D-type flip-flop phase and frequency detector shown in Figure 8. The flip-flops are set by the negative edges of output signals of the dividers. The rising edge of the signal, L, will reset the flip-flops after both flip-flops have been set. Around zero phase error this has the effect of delaying the reset for 1 reference input cycle. This avoids non-linearity or deadband around zero phase error. The flip-flops drive on-chip charge pumps. A source current from the charge pump indicates the VCO frequency will be increased; a sink current indicates the VCO frequency will be decreased. The loading of the work registers NM1, NM2, NM3 and PR is synchronized with the state of the main counter, to avoid extra phase disturbance when switching over to another main divider ratio as explained in the Serial Input Programming section. At the completion of a main divider cycle, a main divider output pulse is generated which will drive the main phase comparator. Also, the fractional accumulator is incremented with NF. The 1996 Aug 6 SA7025 10 Philips Semiconductors Product specification 1GHz low-voltage Fractional-N synthesizer LAST IN WORD SA7025 MSB LSB D31 D0 FIRST IN NM2 A1 0 NF NM1 CN NM3 NM2 D0 D23 PR = “01” NM2 A0 0 NF NM1 NM3 B 1 0 0 0 0 0 0 0 C 1 0 0 1 NA P A D 1 0 1 0 NR SM E 1 1 1 1 0 0 0 CN CK T T 1 NM2 CL PR = “10” PR 0 E M SA F L E M O A O N D G 0 0 D23 D0 ADDRESS BITS TEST BITS SR00605 Figure 6. Serial Input Word Format |I PHA| + 8 @ I RA Current Settings The SA7025 has 3 current setting pins: RA, RN and RF. The active charge pump currents and the fractional compensation currents are linearly dependent on the current connected between the current setting pin and VSS. The typical value R (current setting resistor) can be calculated with the formula: R + V DDA * 0.9 * 150 Main Output Charge Pumps and Fractional Compensation Currents The main charge pumps on pin PHP and PHI are driven by the main phase detector and the current value is determined by the current at pin RN and via a number of DACs which are driven by registers of the serial input. The fractional compensation current is determined by the current at pin RF, the contents of the fractional accumulator FRD and a number of DACs driven by registers from the serial input. The timing for the fractional compensation is derived from the reference divider. The current is on during 1 input reference cycle before and 1 cycle after the output signal to the phase comparator. Figure 9 shows the waveforms for a typical case. ǸIR IR The current can be set to zero by connecting the corresponding pin to VDDA. Auxiliary Output Charge Pumps The auxiliary charge pumps on pin PHA are driven by the auxiliary phase detector and the current value is determined by the external resistor RA at pin RA. The active charge pump current is typically: 1996 Aug 6 11 Philips Semiconductors Product specification 1GHz low-voltage Fractional-N synthesizer SA7025 Table 1. Function Table Symbol Bits Function NM1 12 Number of main divider cycles when prescaler modulus = 64* NM2 8 if PR = “01” 4 if PR = “10” Number of main divider cycles when prescaler modulus = 65* NM3 4 if PR = “10” Number of main divider cycles when prescaler modulus = 72* PR 2 Prescaler type in use PR = “01”: modulus 2 prescaler (64/65) PR = “10”: modulus 3 prescaler (64/65/72) NF 3 Fractional-N increment FMOD 1 Fractional-N modulus selection flag “1”: modulo 8 “0”: modulo 5 LONG 1 A word format selection flag “0”: 24 bit A0 format “1”: 32 bit A1 format CN 8 Binary current setting factor for main charge pumps CL 2 Binary acceleration factor for proportional charge pump current CK 4 Binary acceleration factor for integral charge pump current EM 1 Main divider enable flag EA 1 Auxiliary divider enable flag SM 2 Reference select for main phase detector SA 2 Reference select for auxiliary phase detector NR 12 Reference divider ratio NA 12 Auxiliary divider ratio PA 1 Auxiliary prescaler mode: PA = “0”: divide by 4 PA = “1”: divide by 1 *Not including reset cycles and Fractional-N effects. MAIN SELECT SM = “00” SM = “01” SM = “10” MAIN PHASE DETECTOR SM = “11” REFERENCE INPUT DIVIDE BY NR ÷2 ÷2 ÷2 AUXILIARY SELECT SA = “11” SA = “10” SA = “01” AUXILIARY PHASE DETECTOR SA = “00” Figure 7. Reference Divider Table 2. Prescaler Ratio The total division ratio from prescaler to the phase detector may be expressed as: if PR = “01” N = (NM1 + 2) x 64 + NM2 x 65 N’ = (NM1 + 1) x 64 + (NM2 + 1) x 65 (*) if PR = “10” N = (NM1 + 2) x 64 + NM2 x 65 + (NM3 + 1) x 72 N’ = (NM1 + 1) x 64 + (NM2 + 1) x 65 + (NM3 + 1) x 72 (*) (*) When the fractional accumulator overflows the prescaler ratio = 65 (64 + 1) and the total division ratio N’ = N + 1 1996 Aug 6 12 SR00606 Philips Semiconductors Product specification 1GHz low-voltage Fractional-N synthesizer SA7025 Table 3. PR Modulus In “speed-up mode” the current in output PHI is: PR Modulus Prescaler Bit Capacity NM1 NM2 NM3 01 2 12 8 – 10 3 12 4 4 I PHI_S + I PHI ) I PHI_comp where: |I PHI| + When the serial input A word is loaded, the output circuits are in the “speed-up mode” as long as the STROBE is H, else the “normal mode” is active. In the “normal mode” the current output PHP is: :charge pump current |I PHP_comp| + FRD @ where: Q = fVCO = fINM × N, FINR = In “speed-up mode” the current in output PHP is: I PHP_S + I PHP ) I PHP_comp ǒ Ǔ ǒ fractional-N modulus input frequency of the prescaler input frequency of the reference divider PHI pump is meant for switching only. Current and compensation are not as accurate as PHP. CN @ I RN (2 CL)1 ) 1) 32 |I PHP_comp| + Ǔ I RF FRD (2 CL)1) CK 128 (Q @ f VCO) I RN + I RF (3 @ CN @ F INR) I RF :fractional comp. 128 current The current in PHI is zero in “normal mode”. |I PHP| + ǒ Figure 9 shows that for proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output. This means that the current setting on the input RN, RF is approximately: where: CN @ I RN 32 Ǔ I RNCN (2 CL)1) CK 32 |I PHI_comp| + I PHP_N + I PHP ) I PHP_comp |I PHP| + ǒ Ǔ FRD @ I RF (2 CL)1 ) 1) 128 L REFERENCE DIVIDER REF_IN “1” R D Q C VDDA R P “1” AUX/MAIN DIVIDER D P-TYPE CHARGE PUMP PH R C X N-TYPE CHARGE PUMP Q N VSSA REF_IN L R X P N IP H SR00607 Figure 8. Phase Detector Structure with Timing 1996 Aug 6 13 Philips Semiconductors Product specification 1GHz low-voltage Fractional-N synthesizer SA7025 REFERENCE R TIME MAIN N VCO CYCLES N N N+1 N N+1 DETECTOR OUTPUT 2 4 1 3 0 CONTENTS ACCUM. FRACTIONAL COMPENSATION CURRENT PULSE-WIDTH MODULATION mA OUTPUT ON PHP, PHI µA PULSE-LEVEL MODULATION SR00608 Figure 9. Waveforms for NF = 2, Fraction = 0.4 PA registers. The fAUX signal can be used to verify the divide ratio of the Auxiliary divider. Lock Detect The output LOCK is H when the auxiliary phase detector AND the main phase detector indicates a lock condition. The lock condition is defined as a phase difference of less than +1 cycle on the reference input REF_IN. The lock condition is also fulfilled when the relative counter is disabled (EM = “0” or respectively EA = “0”) for the main, respectively auxiliary counter. If T1 = High and T0 = High, the lock output is configured as fMAIN. The signal is the buffered output of the MAIN divider. The fMAIN signal appears as normally high and pulses low whenever the divider reaches terminal count from the value programmed into the NM1, NM2 or NM3 registers. The fMAIN signal can be used to verify the divide ratio of the MAIN divider and the prescaler. Test Modes The lock output is selectable as fREF, fAUX, fMAIN and lock. Bits T1 and T0 of the E word control the selection (see Figures 6 and 10). If T1 = T0 = Low, or if the E-word is not sent, the lock output is configured as the normal lock output described in the Lock Detect section. If T1 = Low and T0 = High, the lock output is configured as fREF. The signal is the buffered output of the reference divider NR and the 3-bit binary counter SM. The fREF signal appears as normally low and pulses high whenever the divider reaches terminal count from the value programmed into the NR and SM registers. The fREF signal can be used to verify the divide ratio of the Reference divider. If T1 = High and T0 = Low, the lock output is configured as fAUX. The signal is normally high and pulses low whenever the divider reaches terminal count from the value programmed into the NA and 1996 Aug 6 14 Philips Semiconductors Product specification 1GHz low-voltage Fractional-N synthesizer SA7025 Test Pin MAIN DIVIDER The Test pin, Pin 19, is a buffered logic input which is exclusively ORed with the output of the prescaler. The output of the XOR gate is the input to the MAIN divider. The Test pin must be connected to VDD during normal operation as a synthesizer. This pin can be used as an input for verifying the divide ratio of the MAIN divider; while in this condition the input to the prescaler, RFIN, may be connected to VCCP through a 10kΩ resistor in order to place prescaler output into a known state. REF DIVIDER SM AUX DIVIDER φMAIN φAUX T1 SELECT T0 LOGIC LOCK SR00609 Figure 10. Test Mode Diagram PIN FUNCTIONS PIN PIN DC V No. MNEMONIC 1 CLOCK –– 2 DATA –– 3 STROBE –– 19 TEST –– PIN PIN DC V No. MNEMONIC EQUIVALENT CIRCUIT VDD 9 RA 1.35 16 RN 1.35 1 EQUIVALENT CIRCUIT VDDA = 3V 9 25µA 17 RF 1.35 VSS VSSA VCCP = 3V 5 RFIN 5 6 RFIN 11 PHA –– 13 PHI –– 14 PHP –– 2.1 2.1 6 2.5k 2.5k VDDA 11 VSSA VSS VDDA = 3V 8 REFIN VDD 1.8 ENABLE 18 10 LOCK –– 18 100k 10 AUXIN 1.8 VSS Figure 11. Pin Functions 1996 Aug 6 15 VSS SR00610 Philips Semiconductors Product specification 1GHz low-voltage Fractional-N synthesizer SA7025 TYPICAL PERFORMANCE CHARACTERISTICS 8.5 11 8 VCCP = VDDA = VDD VCCP = VDDA = VDD 10 7.5 EM = EA = 1, Note5 7 I TOTAL (mA) 9 I TOTAL (mA) EA=0, EM=1, Note5 8 6.5 6 5.5 7 t = –40°C t = 25°C t = 85°C 6 5 2.7 3.5 4.5 t = –40°C t = 25°C t = 85°C 5 4.5 4 2.7 5.5 3.5 4.5 5.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SR00611 SR00614 Figure 12. Operational Supply Current vs Supply Voltage and Temperature Figure 15. Main Operational Supply Current vs Supply Voltage and Temperature 7 3.5 VDD = 3V, VDDA = 5V Pin = –10dBm, ref divider halted VCCP = VDDA = VDD 6 3 EA=0, EM=1, Note5 I TOTAL (mA) 4 3 t = –40°C t = 25°C t = 85°C 2 2.5 2 t = –40°C t = 25°C t = 85°C 1.5 1 1 2.7 3.5 4.5 5.5 50 100 AUXILIARY INPUT FREQUENCY (MHz) SUPPLY VOLTAGE (V) 150 SR00612 SR00615 Figure 13. Auxiliary Operational Supply Current vs Supply Voltage and Temperature Figure 16. Auxiliary Operational Supply Current vs Frequency and Temperature 20 20 VDD = VCCP 0 INPUT POWER (dBm) 2.7V 3.5V 4.5V 5.5V –20 –40 TA = 25°C, N = 3971.625 t=–40°C t=25°C t=85°C –20 –40 VDD = VCCP = 3V N=3971.625 –60 Figure 14. Main Divider Input Power vs frequency and Supply 1996 Aug 6 1150 1050 950 900 850 800 750 700 650 600 500 1100 1050 1000 1150 FREQUENCY (MHz) SR00613 1000 FREQUENCY (MHz) 950 900 850 800 750 700 650 600 550 500 –60 550 INPUT POWER (dBm) 0 1100 I TOTAL (mA) 5 SR00616 Figure 17. Main Divider Input Power vs Frequency and Temperature 16 Philips Semiconductors Product specification 1GHz low-voltage Fractional-N synthesizer SA7025 TYPICAL PERFORMANCE CHARACTERISTICS (continued) 5 0 VDD= 3V, MINIMUM INPUT POWE (dBm) INPUT POWER (dBm) –5 –10 –15 VDD/VDDA –20 VDDA= 5V, N = 100 –5 –10 3/3V 3/5V 5/5V –25 0 t = –40°C t = 25°C t = 85°C –15 N=100 –30 –20 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) 55 10 25 30 35 40 SR00631 Figure 21. Reference Divider Minimum Input Power vs Frequency and Temperature 0 –10 VDD/VDDA TA =amb, PA=1, N=100 –10 VDD =3V, 3/3V 3/5V 5/5V MINIMUM INPUT POWER (dBm) –5 MINIMUM INPUT POWER (dBm) 20 FREQUENCY (dBm) Figure 18. Reference Divider Minimum Input Power vs frequency and Supply –15 –20 –25 –30 t = –40°C t = 25°C t = 85°C VDDA=5V, PA=1, N=100 –15 –20 –25 30 50 70 90 110 FREQUENCY (MHz) 130 150 30 50 SR00618 Figure 19. Auxiliary Divider Minimum Input Power vs Frequency and Supply 70 FREQUENCY (MHz) 90 SR00632 Figure 22. Auxiliary Divider Minimum Input Power vs Frequency and Temperature 0 0 VDD/VDDA VDD=3V, MINIMUM INPUT POWER (dBm) TA = amb, PA=0, N=25 –5 MINIMUM INPUT POWER (dBm) 15 SR00617 –10 –15 3/3V 3/5V 5/5V –20 VDDA=5V PA=0, N=25 –5 t = –40°C t = 25°C t = 85°C –10 –15 –25 –20 –30 50 100 150 FREQUENCY (MHz) 200 50 250 Figure 20. Auxiliary Divider Minimum Input Power vs Frequency and Supply 1996 Aug 6 100 150 FREQUENCY (MHz) 200 SR00619 Figure 23. Auxiliary Divider Minumum Input Power vs Frequency and Temperature 17 Philips Semiconductors Product specification 1GHz low-voltage Fractional-N synthesizer SA7025 j1 j0.5 j2 VCCP = VDD = 3V TA = 25°C R3 1Ω L4 2nH 1 0 50 C2 0.1pF R1 C1 3000Ω 0.85pF 300 600 900 Equivalent Input Impedance 1100 –j2 –j0.5 –j1 SR00620 Figure 24. Typical RFIN Input Impedance 1996 Aug 6 18 Philips Semiconductors Product specification 1GHz low-voltage Fractional-N synthesizer SA7025 TOP SILK SCREEN TOP VIEW BOTTOM VIEW Figure 25. SA7025DK Demoboard Layout (NOT ACTUAL SIZE) 1996 Aug 6 19 SR00621 Philips Semiconductors Product specification 1GHz low-voltage Fractional-N synthesizer SA7025 SR00622 Figure 26. SA7025DK Application Circuit 1996 Aug 6 20 Philips Semiconductors Product specification 1GHz low-voltage Fractional-N synthesizer SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm 1996 Aug 6 21 SA7025 SOT266-1 Philips Semiconductors Product specification Low-voltage 1GHz fractional-N synthesizer SA7025 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A. print code Document order number: