INTEGRATED CIRCUITS SA8026 2.5GHz low voltage fractional-N dual frequency synthesizer Product specification Supersedes data of 1999 Apr 16 1999 Nov 04 Philips Semiconductors Product specification 2.5GHz low voltage fractional-N dual frequency synthesizer SA8026 GENERAL DESCRIPTION The SA8026 BICMOS device integrates programmable dividers, charge pumps and a phase comparator to implement a phase-locked loop. The device is designed to operate from 3 NiCd cells, in pocket phones, with low current and nominal 3 V supplies. The synthesizer operates at VCO input frequencies up to 2.5 GHz. The synthesizer has fully programmable main, auxiliary and reference dividers. All divider ratios are supplied via a 3-wire serial programming bus. Separate power and ground pins are provided to the analog and digital circuits. The ground leads should be externally short-circuited to prevent large currents flowing across the die and thus causing damage. VDDCP must be greater than or equal to VDD. LOCK 1 20 PON TEST 2 19 STROBE VDD 3 18 DATA GND 4 17 CLOCK RFin+ 5 16 REFin+ RFin– 6 15 REFin– GNDCP 7 14 RSET PHP 8 13 VDDCP PHI 9 12 AUXin 11 PHA GNDCP 10 SR01649 The charge pump current (gain) is set by an external resistance at RSET pin. Passive loop filters could be used; the charge pump operates within a wide voltage compliance range to provide a wider tuning range. Figure 1. Pin Configuration APPLICATIONS FEATURES • 350 to 2500 MHz wireless equipment • Cellular phones (all standards) • WLAN • Portable battery-powered radio equipment. • Low phase noise • Low power • Fully programmable main and auxiliary dividers • Normal & Integral charge pumps outputs • Fast Locking Adaptive mode design • Internal fractional spurious compensation • Hardware and software power down • Split supply for VDD and VDDCP QUICK REFERENCE DATA SYMBOL PARAMETER VDD Supply voltage VDDCP Analog supply voltage IDDCP+IDD Total supply current IDDCP+IDD CONDITIONS MIN. TYP. MAX. UNIT 2.7 – 5.5 V VDDCP w VDD 2.7 – 5.5 V Main and Aux. on – 10 12 mA Total supply current in power-down mode – 1 – µA fVCO Input frequency 350 – 2500 MHz fAUX Input frequency 20 – 550 MHz fREF Crystal reference input frequency 5 – 40 MHz fPC Maximum phase comparator frequency – 4 MHz Tamb Operating ambient temperature –40 +85 °C – ORDERING INFORMATION PACKAGE TYPE NUMBER SA8026DH 1999 Nov 04 NAME DESCRIPTION VERSION TSSOP20 Plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360–1 2 853–2141 22633 Philips Semiconductors Product specification 2.5GHz low voltage fractional-N dual frequency synthesizer SA8026 VDDCP VDD 13 3 17 2–BIT SHIFT REGISTER 22–BIT SHIFT REGISTER ADDRESS DECODER CONTROL LATCH CLOCK DATA STROBE 18 19 PUMP CURRENT SETTING 14 PUMP BIAS RSET LOAD SIGNALS LATCH COMP 5 RFin+ RFin– MAIN DIVIDER 6 8 PHASE DETECTOR PHP AMP SM 9 LATCH PHI 16 REFin+ REFERENCE DIVIDER REFin– 2 2 22 15 1 SA LATCH AUXin PHASE DETECTOR 12 AUX DIVIDER LOCK 11 PHA 20 PON AMP TEST 2 4 GND 7, 10 GNDCP SR01496 Figure 2. Block Diagram PINNING SYMBOL PIN DESCRIPTION SYMBOL PIN DESCRIPTION LOCK 1 Lock detect output PHA 11 Auxiliary charge pump output TEST 2 Test (should be either grounded or connected to VDD) AUXin 12 Input to auxiliary divider VDDCP 13 Charge pump supply voltage RSET 14 External resistor from this pin to ground sets the charge pump current VDD 3 Digital supply GND 4 Digital ground RFin+ 5 RF input to main divider REFin– 15 Reference input RFin– 6 RF input to main divider REFin+ 16 Reference input GNDCP 7 Charge pump ground CLOCK 17 Programming bus clock input PHP 8 Main normal charge pump DATA 18 Programming bus data input PHI 9 Main integral charge pump STROBE 19 Programming bus enable input GNDCP 10 Charge pump ground PON 20 Power down control 1999 Nov 04 3 Philips Semiconductors Product specification 2.5GHz low voltage fractional-N dual frequency synthesizer SA8026 Limiting values SYMBOL PARAMETER MIN. MAX. UNIT VDD Digital supply voltage –0.3 +5.5 V VDDCP Analog supply voltage –0.3 +5.5 V ∆VDDCP–VDD Difference in voltage between VDDCP and VDD (VDDCP ≥ VDD) –0.3 +2.8 V Vn Voltage at pins 1, 2, 5, 6, 12, 15 to 20 –0.3 VDD + 0.3 V Vn Voltage at pin 8, 9, 11 –0.3 VDDCP + 0.3 V ∆VGND Difference in voltage between GNDCP and GND (these pins should be connected together) –0.3 +0.3 V Tstg Storage temperature –55 +125 _C Tamb Operating ambient temperature –40 +85 _C Tj Maximum junction temperature 150 _C Handling Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. Thermal characteristics SYMBOL Rth j–a 1999 Nov 04 PARAMETER Thermal resistance from junction to ambient in free air 4 VALUE UNIT 135 K/W Philips Semiconductors Product specification 2.5GHz low voltage fractional-N dual frequency synthesizer SA8026 CHARACTERISTICS VDDCP = VDD = +3.0V, Tamb = +25°C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply; pins 3, 13 VDD Digital supply voltage VDDCP Analog supply voltage VDDCP w VDD 2.7 – 5.5 V 2.7 – 5.5 V IDDTotal Synthesizer operational total supply current VDD = +3.0V (with main and aux on) – 10 12 mA IStandby Total supply current in power-down mode logic levels 0 or VDD – 1 – µΑ 350 – 2500 MHz –18 – 0 dBm RFin main divider input; pins 5, 6 fVCO VCO input frequency VRFin(rms) AC-coupled input signal level Rin (external) = Rs = 50Ω; single-ended drive; max. limit is indicative @ 500 to 2500 MHz ZIRFin Input impedance (real part) fVCO = 2.4 GHz – 300 – Ω CIRFin Typical pin input capacitance fVCO = 2.4 GHz – 1 – pF Nmain Main divider ratio 512 – 65535 fPCmax Maximum loop comparison frequency – – 4 MHz indicative, not tested AUX reference divider input; pin 12 fAUXin Input frequency range Rin (external) ( ) = RS = 50Ω; max. limit is indicative 20 – 550 MHz –18 – 0 dBm 80 – 632 mVPP VAUXin AC coupled input signal level AC-coupled ZAUXin Input impedance (real part) fVCO = 500 MHz – 3.9 – kΩ CAUXin Typical pin input capacitance fVCO = 500 MHz – 0.5 – pF NAUX Auxiliary division ratio 128 – 16383 5 – 40 MHz 360 – 1300 mVPP Reference divider input; pins 15, 16 fREFin Input frequency range from TCXO VRFin AC-coupled input signal level single-ended drive; max. limit is indicative ZREFin Input impedance (real part) fREF = 20 MHz – 10 – kΩ CREFin Typical pin input capacitance fREF = 20 MHz – 1 – pF RREF Reference division ratio SA = SM = ”000” 4 – 1023 6 7.5 15 kΩ – 1.25 – V Charge pump current setting resistor input; pin 14 RSET External resistor from pin to ground VSET Regulated voltage at pin RSET = 7.5 kΩ Charge pump outputs (including fractional compensation pump); pins 8, 9, 11; RSET = 7.5 kΩ, FC = 80 ICP Charge pump current ratio to ISET1 IMATCH Sink-to-source current matching IZOUT Output current variation versus VPH ILPH Charge pump off leakage current VPH Charge pump voltage compliance 1999 Nov 04 2 Current gain = IPH/ISET –15 +15 % VPH = 1/2 VDDCP –10 +10 % VPH in compliance range –10 +10 % VPH = 1/2 VDDCP –10 +10 nA VDDCP–0.8 V 0.7 5 – Philips Semiconductors Product specification 2.5GHz low voltage fractional-N dual frequency synthesizer SA8026 CHARACTERISTICS (continued) SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT GSM – –90 – dBc/Hz – –83 – dBc/Hz – –85 – dBc/Hz – –77 – dBc/Hz Phase noise (condition RSET = 7.5 kΩ, CP = 00) Synthesizer’s contribution to close-in phase noise of 900 MHz RF signal at 1 kHz offset. Synthesizer’s contribution to close-in phase noise of 1800 MHz RF signal at 1 kHz offset. L(f) Synthesizer’s contribution to close-in phase noise of 800 MHz RF signal at 1 kHz offset. Synthesizer’s contribution to close-in phase noise of 2100 MHz RF signal at 1 kHz offset. fREF = 13MHz, TCXO, fCOMP = 1MHz indicative, not tested TDMA fREF = 19.44MHz, TCXO, fCOMP = 240kHz indicative, not tested Interface logic input signal levels; pins 2, 17, 18, 19, 20 VIH HIGH level input voltage 0.7*VDD – VDD+0.3 V VIL LOW level input voltage –0.3 – 0.3*VDD V ILEAK Input leakage current –0.5 – +0.5 µA – – 0.4 V VDD–0.4 – – V logic 1 or logic 0 Lock detect output signal (in push/pull mode); pin 1 VOL LOW level output voltage Isink = 2mA VOH HIGH level output voltage Isource = –2mA NOTES: 1. ISET = V SET bias current for charge pumps. R SET 2. The relative output current variation is defined as: DI OUT (I 2–I 1) + 2. ; with V 1 + 0.7V, V 2 + V DDCP –0.8V (See Figure 3.) I(I 2 ) I 1)I I OUT CURRENT IZOUT I2 I1 V1 V2 VPH I2 I1 SR00602 Figure 3. Relative Output Current Variation 1999 Nov 04 6 Philips Semiconductors Product specification 2.5GHz low voltage fractional-N dual frequency synthesizer SA8026 FUNCTIONAL DESCRIPTION Main Fractional-N divider Auxiliary divider The RFin inputs drive a pre-amplifier to provide the clock to the first divider stage. For single ended operation, the signal should be fed to one of the inputs while the other one is AC grounded. The pre-amplifier has a high input impedance, dominated by pin and pad capacitance. The circuit operates with signal levels from –18 dBm to 0 dBm, and at frequencies as high as 2.5 GHz. The divider consists of a fully programmable bipolar prescaler followed by a CMOS counter. Total divide ratios range from 512 to 65536. The AUXin input drives a pre-amplifier to provide the clock to the first divider stage. The pre-amplifier has a high input impedance, dominated by pin and pad capacitance. The circuit operates with signal levels from –18dBm to 0 dBm (80 to 636 mVpp), and at frequencies as high as 550 MHz. The divider consists of a fully programmable bipolar prescaler followed by a CMOS counter. Total divide ratios ranges from 128 to 16383. Reference divider At the completion of a main divider cycle, a main divider output pulse is generated which will drive the main phase comparator. Also, the fractional accumulator is incremented by the value of NF. The accumulator works with modulo Q set by FMOD. When the accumulator overflows, the overall division ratio N will be increased by 1 to N + 1, the average division ratio over Q main divider cycles (either 5 or 8) will be The reference divider consists of a divider with programmable values between 4 and 1023 followed by a three bit binary counter. The 3 bit SM (SA) register (see figure 4) determines which of the 5 output pulses are selected as the main (auxiliary) phase detector input. Phase detector (see Figure 5) NF Nfrac + N ) Q The reference and main (aux) divider outputs are connected to a phase/frequency detector that controls the charge pump. The pump current is set by an external resistor in conjunction with control bits CP0 and CP1 in the C-word (see Charge Pump table). The dead zone (caused by finite time taken to switch the current sources on or off) is cancelled by forcing the pumps ON for a minimum time at every cycle (backlash time) providing improved linearity. The output of the main divider will be modulated with a fractional phase ripple. The phase ripple is proportional to the contents of the fractional accumulator and is nulled by the fractional compensation charge pump. The reloading of a new main divider ratio is synchronized to the state of the main divider to avoid introducing a phase disturbance. SM=”000” SM=”001” SM=”010” SM=”011” TO MAIN PHASE DETECTOR SM=”100” REFERENCE INPUT DIVIDE BY R /2 /2 /2 /2 SA=”100” SA=”011” SA=”010” TO AUXILIARY PHASE DETECTOR SA=”001” SA=”000” SR01415 Figure 4. Reference Divider 1999 Nov 04 7 Philips Semiconductors Product specification 2.5GHz low voltage fractional-N dual frequency synthesizer SA8026 VCC “1” fREF REF DIVIDER P–TYPE CHARGE PUMP P D Q CLK R R τ “1” AUX/MAIN DIVIDER D IPH R N–TYPE CHARGE PUMP CLK Q X N GND fREF R X τ P τ N IPH SR01451 Figure 5. Phase Detector Structure with Timing 1999 Nov 04 8 Philips Semiconductors Product specification 2.5GHz low voltage fractional-N dual frequency synthesizer Main Output Charge Pumps and Fractional Compensation Currents (see Figure 6) SA8026 The compensation is done by sourcing a small current, ICOMP, see Figure 7, that is proportional to the fractional error phase. For proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the fractional charge pump ripple. The width of the fractional compensation pulse is fixed to 128 VCO cycles, the amplitude is proportional to the fractional accumulator value and is adjusted by FDAC values (bits FC7–0 in the B-word). The fractional compensation current is derived from the main charge pump in that it follows all the current scaling through external resistor setting, RSET, programming or speed-up operation. For a given charge pump, The main charge pumps on pins PHP and PHI are driven by the main phase detector and the charge pump current values are determined by the current at pin RSET in conjunction with bits CP0, CP1 in the C-word (see table of charge pump ratios). The fractional compensation is derived from the current at RSET, the contents of the fractional accumulator FRD and by the program value of the FDAC. The timing for the fractional compensation is derived from the main divider. The main charge pumps will enter speed up mode after the A-word is set and strobe goes High. When strobe goes Low, charge pump will exit speed up mode. Principle of Fractional Compensation ICOMP = ( IPUMP / 128 ) * ( FDAC / 5*128) * FRD The fractional compensation is designed into the circuit as a means of reducing or eliminating fractional spurs that are caused by the fractional phase ripple of the main divider. If ICOMP is the compensation current and IPUMP is the pump current, then for each charge pump: FRD is the fractional accumulator value. The target values for FDAC are: 128 for FMOD = 1 (modulo 5) and 80 for FMOD = 0 (modulo 8). IPUMP_TOTAL = IPUMP + ICOMP. REFERENCE R MAIN M DIVIDE RATIO N DETECTOR OUTPUT N 2 N+1 N 4 1 N+1 3 0 ACCUMULATOR FRACTIONAL COMPENSATION CURRENT PULSE WIDTH MODULATION mA OUTPUT ON PUMP µA PULSE LEVEL MODULATION SR01416 NOTE: For a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output. Figure 6. Waveforms for NF = 2 Modulo 5 → fraction = 2/5 fRF FRACTIONAL ACCUMULATOR MAIN DIVIDER ICOMP IPUMP fREF Σ LOOP FILTER & VCO SR01800 Figure 7. Current Injection Concept 1999 Nov 04 9 Philips Semiconductors Product specification 2.5GHz low voltage fractional-N dual frequency synthesizer SA8026 Auxiliary Output Charge Pumps The auxiliary charge pump on pin PHA are driven by the auxiliary phase detector and PHP, PHI are driven by the main phase detector. The current value is determined by the external resistor attached to pin RSET. Main and auxiliary charge pump currents CP1 CP0 IPHA IPHP IPHP–SU IPHI 0 0 1.5xlSET 3xISET 15xlSET 36xlSET 0 1 0.5xlSET 1xlSET 5xlSET 12xlSET 1 0 1.5xlSET 3xlSET 15xlSET 0 1 1 0.5xlSET 1xlSET 5xlSET 0 NOTES 1. ISET = VSET/RSET: bias current for charge pumps. 2. CP1 is used to disable the PHI pump, IPHP–SU is the total current at pin PHP during speed up condition. Lock Detect Power-down mode The output LOCK maintains a logic ‘1’ when the auxiliary phase detector ANDed with the main phase detector indicates a lock condition. The lock condition for the main and auxiliary synthesizers is defined as a phase difference of less than "1 period of the frequency at the input REFin+, –. One counter can fulfill the lock condition when the other counter is powered down. Out of lock (logic ’0’) is indicated when both counters are powered down. The power-down signal can be either hardware (PON) or software (PD). The PON signal is exclusively ORed with the PD bits in B-word. If PON = 0, then the part is powered up when PD = 1. PON can be used to invert the polarity of the software bit PD. When the synthesizer is reactivated after power-down, the main and reference dividers are synchronized to avoid possibility of random phase errors on power-up. 1999 Nov 04 10 Philips Semiconductors Product specification 2.5GHz low voltage fractional-N dual frequency synthesizer SA8026 data is latched into different working registers or temporary registers. In order to fully program the synthesizer, 3 words must be sent: C, B, and A. Table 1 shows the format and the contents of each word. The D word is normally used for testing purposes. When sending the B-word, data bits FC7–0 for the fractional compensation DAC are not loaded immediately. Instead they are stored in temporary registers. Only when the A-word is loaded, these temporary registers are loaded together with the main divider ratio. Serial programming bus The serial input is a 3-wire input (CLOCK, STROBE, DATA) to program all counter divide ratios, fractional compensation DAC, selection and enable bits. The programming data is structured into 24 bit words; each word includes 2 or 3 address bits. Figure 8 shows the timing diagram of the serial input. When the STROBE goes active HIGH, the clock is disabled and the data in the shift register remains unchanged. Depending on the address bits, the Serial bus timing characteristics. See Figure 8. VDD = VDDCP =+3.0V; Tamb = +25°C unless otherwise specified. PARAMETER SYMBOL MIN. TYP. MAX. UNIT Serial programming clock; CLK tr Input rise time – 10 40 ns tf Input fall time – 10 40 ns Tcy Clock period 100 – – ns 40 – – ns 1/fCOMP – – ns 20 – – ns Enable programming; STROBE tSTART Delay to rising clock edge tW Minimum inactive pulse width tSU;E Enable set-up time to next clock edge Register serial input data; DATA tSU;DAT Input data to clock set-up time 20 – – ns tHD;DAT Input data to clock hold time 20 – – ns Application information tSU;DAT tHD;DAT tr Tcy tf tSU;E CLK DATA ADDRESS MSB LSB STROBE tw tSTART SR01417 Figure 8. Serial Bus Timing Diagram 1999 Nov 04 11 Philips Semiconductors Product specification 2.5GHz low voltage fractional-N dual frequency synthesizer SA8026 Data format Table 1. Format of programmed data Last In MSB p23 p22 Serial Programming Format p21 p20 ../.. First In LSB ../.. p1 p0 Table 2. A word, length 24 bits Last In MSB Address 0 fmod 0 Fractional-N LSB First In Main Divider ratio Spare FM NF2 NF1 NF0 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 SK1 SK2 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 Default A word select Fixed to 00. Fractional Modulus select FM 0 = modulo 8, 1 = modulo 5. Fractional-N Increment NF2..0 Fractional N Increment values 000 to 111. N-Divider N0..N15, Main divider values 512 to 65535 allowed for divider ratio. Table 3. B word, length 24 bits Address 0 Reference Divider 1 Default Lock PD Fractional Compensation DAC R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 L1 L0 Main Aux FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 0 0 0 1 0 1 0 0 0 1 0 0 1 1 0 1 0 1 0 0 0 0 B word select Fixed to 01 R-Divider R0..R9, Reference divider values 4 to 1023 allowed for divider ration. Lock detect output L1 L0 0 0 Combined main, aux. lock detect signal present at the LOCK pin (push/pull). 0 1 Combined main, aux, lock detect signal present at the LOCK pin (open drain). 1 0 Main lock detect signal present at the LOCK pin (push/pull). 1 1 Auxiliary loop lock detect signal present at the LOCK pin (push/pull). When auxiliary loop and main loop are in power down mode, the lock indicator is low. Power down Main = 1: power to N-divider, reference divider, main charge pumps, Main = 0 to power down. Aux = 1: power to Aux divider, reference divider, aux charge pump, Aux = 0 to power down. Fractional Compensation FC7..0 Fractional Compensation charge pump current DAC, values 0 to 255. Table 4. C word, length 24 bits Address 1 Auxiliary Divider 0 CP SM SA A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CP1 CP0 SM2 SM1 SM0 SA2 SA1 SA0 0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 1 0 0 0 0 0 0 Default C word select Fixed to 10 A-Divider A0..A13, Auxiliary divider values 128 to 16383 allowed for divider ratio. Charge pump current Ratio CP1, CP0: Charge pump current ratio, see table of charge pump currents. Main comparison select SM comparison divider select for main phase detector. Aux comparison select SA Comparison divider select for auxiliary phase detector. Table 5. D word, length 24 bits Address 1 1 Default Synthesizer Test Bits 0 – – – – – Tspu – – – – – – – – – – – – – – – 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Tspu: Speed up = 1 1999 Nov 04 Synthesizer Test Bits Forces the main charge pumps in speed-up mode all the time. NOTE: All test bits must be set to 0 for normal operation. 12 Philips Semiconductors Product specification 2.5GHz low voltage fractional-N dual frequency synthesizer SA8026 TYPICAL PERFORMANCE CHARACTERISTICS 3000 2500 ISET = 206.67 mA 2000 2000 1500 ISET = 165.33 mA 1000 ISET = 103.33 mA ISET = 51.67 mA 0 ISET = 51.67 mA –1000 –2000 +85_C +25_C –40_C 500 Icp (uA) ICP (uA) 1000 0 –500 ISET = 103.33 mA –1000 ISET = 165.33 mA –1500 –2000 –2500 ISET = 206.67 mA –3000 0 0.25 0.5 0.75 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 SR01856 SR01855 Figure 10. PHI Charge Pump Output vs. Temperature (CP = 01; VDD = 3.0 V; ISET = 165.33 mA) 8000 ISET = 206.67 mA 8000 6000 ISET = 165.33 mA 6000 4000 ISET = 103.33 mA 4000 2000 ISET = 51.67 mA 0 ISET = 51.67 mA ISET = 103.33 mA 0 –2000 –4000 ISET = 165.33 mA –6000 +85_C +25_C –40_C 2000 Icp (uA) Icp (uA) Figure 9. PHI Charge Pump vs. ISET (CP = 01; Temp = 25_C) –4000 –6000 ISET = 206.67 mA –8000 –8000 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 COMPLIANCE VOLTAGE (V) COMPLIANCE VOLTAGE (V) SR01858 SR01857 Figure 11. PHI Charge Pump vs. ISET (CP = 00; TEMP = 25_C) Figure 12. PHI Charge Pump Output vs. Temperature (CP = 00; VDD = 3.0 V; ISET = 165.33 mA) 800 600 ISET = 206.67 mA 600 400 ISET = 165.33 mA 200 ISET = 103.33 mA 400 ISET = 51.67 mA 0 –200 ISET = 51.67 mA –400 ISET = 103.33 mA –600 ISET = 165.33 mA –400 ISET = 206.67 mA 0.25 0.5 0.75 0 –200 –800 0 +85_C +25_C –40_C 200 Icp (uA) Icp (uA) 3.25 3.5 COMPLIANCE VOLTAGE (V) COMPLIANCE VOLTAGE (V) –2000 3 3 1 1.25 1.5 1.75 2 2.25 2.5 2.75 –600 3 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 COMPLIANCE VOLTAGE (V) COMPLIANCE VOLTAGE (V) SR01859 SR01860 Figure 13. PHP Charge Pump Output vs. ISET (CP = 10; Temp = 25_C) 1999 Nov 04 Figure 14. PHP Charge Pump Output vs. Temperature (CP = 10; VDD = 3.0 V; ISET = 165.33 mA) 13 Philips Semiconductors Product specification 2.5GHz low voltage fractional-N dual frequency synthesizer SA8026 TYPICAL PERFORMANCE CHARACTERISTICS (Continued) 250 200 150 200 ISET = 165.33 mA 150 ISET = 103.33 mA 100 ISET = 51.67 mA 50 0 –50 ISET = 51.67 mA –100 –150 –200 0 0 –50 ISET = 103.33 mA –100 ISET = 165.33 mA –150 ISET = 206.67 mA –250 +85_C +25_C –40_C 50 Icp (uA) Icp (uA) 100 ISET = 206.67 mA –200 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3 COMPLIANCE VOLTAGE (V) COMPLIANCE VOLTAGE (V) SR01861 SR01862 Figure 15. PHP Charge Pump Output vs. ISET (CP = 11; Temp = 25_C) Figure 16. PHP Charge Pump Output vs. Temperature (CP = 11; VDD = 3.0 V; ISET = 165.33 mA) 1000 1500 1000 600 ISET = 165.33 mA 500 ISET = 51.67 mA 0 ISET = 51.67 mA –500 +85_C +25_C –40_C 400 ISET = 103.33 mA Icp (uA) Icp (uA) 800 ISET = 206.67 mA 200 0 ISET = 103.33 mA –200 ISET = 165.33 mA –400 –600 –1000 ISET = 206.67 mA –800 –1500 –1000 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2 2.25 2.5 2.75 3 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 COMPLIANCE VOLTAGE (V) COMPLIANCE VOLTAGE (V) SR01863 SR01864 Figure 17. PHP–SU Charge Pump Output vs. ISET (CP = 01; Temp = 25_C) 3500 Figure 18. PHP–SU Charge Pump Output vs. Temperature (CP = 01; VDD = 3.0 V; ISET = 165.33 mA) 3000 ISET = 206.67 mA ISET = 165.33 mA 2500 2000 ISET = 103.33 mA 1500 Icp (uA) Icp (uA) 500 0 –500 ISET = 51.67 mA –1500 +85_C +25_C –40_C 1000 ISET = 51.67 mA 0 –1000 ISET = 103.33 mA –2500 –2000 ISET = 165.33 mA ISET = 206.67 mA –3500 0 0.25 0.5 0.75 1 1.25 –3000 1.5 1.75 2 2.25 2.5 2.75 3 0 COMPLIANCE VOLTAGE (V) 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 COMPLIANCE VOLTAGE (V) SR01870 SR01865 Figure 19. PHP–SU Charge Pump Output vs. ISET (CP = 00; Temp = 25_C) 1999 Nov 04 0.25 0.5 0.75 Figure 20. PHP–SU Charge Pump Output vs. Temperature (CP = 00; VDD = 3.0 V; ISET = 165.33 mA) 14 Philips Semiconductors Product specification 2.5GHz low voltage fractional-N dual frequency synthesizer SA8026 TYPICAL PERFORMANCE CHARACTERISTICS (Continued) 150 100 ISET = 206.67 mA 100 80 60 ISET = 165.33 mA ISET = 51.67 mA 0 ISET = 51.67 mA –50 +85_C +25_C –40_C 40 ISET = 103.33 mA Icp (uA) Icp (uA) 50 20 0 ISET = 103.33 mA –20 ISET = 165.33 mA –40 –100 –60 ISET = 206.67 mA –80 –150 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 –100 3 0 0.25 0.5 0.75 COMPLIANCE VOLTAGE (V) 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 COMPLIANCE VOLTAGE (V) SR01866 SR01867 Figure 21. PHA Charge Pump Output vs. ISET (CP = 11; Temp = 25_C) Figure 22. PHA Charge Pump Output vs. Temperature (CP = 11; VDD = 3.0 V; ISET = 165.33 mA) 400 300 ISET = 206.67 mA ISET = 165.33 mA 200 ISET = 103.33 mA 100 ISET = 51.67 mA 200 0 –100 ISET = 51.67 mA –200 ISET = 103.33 mA –300 ISET = 165.33 mA 0 0 –100 –200 ISET = 206.67 mA –400 +85_C +25_C –40_C 100 Icp (uA) Icp (uA) 300 –300 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 0 0.25 0.5 0.75 1 COMPLIANCE VOLTAGE (V) 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 COMPLIANCE VOLTAGE (V) SR01869 SR01868 Figure 23. PHA Charge Pump Output vs. ISET (CP = 10; Temp = 25_C) Figure 24. PHA Charge Pump Output vs. Temperature (CP = 10; VDD = 3.0 V; ISET = 165.33 mA) 5.00 MINIMUM SIGNAL INPUT LEVEL (dBm) MINIMUM SIGNAL INPUT LEVEL (dBm) 10.00 VDD = 5.00 V VDD = 3.75 V VDD = 3.00 V VDD = 2.70 V 0.00 –5.00 –10.00 –15.00 –20.00 –25.00 –30.00 –35.00 –40.00 0.00 –5.00 –10.00 –15.00 +85_C –20.00 –40_C +25_C –25.00 –30.00 –35.00 –40.00 –45.00 –45.00 1300 1500 1700 1900 2100 2300 2500 2700 2900 3100 1300 3300 FREQUENCY (MHz) 1700 1900 2100 2300 2500 2700 2900 3100 FREQUENCY (MHz) SR01878 SR01879 Figure 25. Main Divider Input Sensitivity vs. Frequency and Supply Voltage (Temp = 25_C) 1999 Nov 04 1500 Figure 26. Main Divider Input Sensitivity vs. Frequency and Temperature (VDD = 3.00 V) 15 Philips Semiconductors Product specification 2.5GHz low voltage fractional-N dual frequency synthesizer SA8026 TYPICAL PERFORMANCE CHARACTERISTICS (Continued) –5.00 MINIMUM SIGNAL POWER LEVEL (dBm) MINIMUM SIGNAL POWER LEVEL (dBm) 0.00 VDD = 5.00 V VDD = 3.75 V VDD = 3.00 V VDD = 2.70 V –10.00 –15.00 –20.00 –25.00 –30.00 –35.00 –40.00 0.00 –5.00 –10.00 –15.00 –20.00 +85_C –40_C +25_C –25.00 –30.00 –35.00 –40.00 –45.00 –45.00 0 40 0 80 120 160 200 240 280 320 360 400 440 480 520 560 40 80 120 160 200 240 280 320 360 400 440 480 520 560 600 640 FREQUENCY (MHz) FREQUENCY (MHz) SR01880 SR01881 Figure 28. Auxiliary Divider Input Sensitivity vs. Frequency and Temperature (Supply = 3.00 V) 0.00 MINIMUM SIGNAL POWER LEVEL (dBm) MINIMUM SIGNAL POWER LEVEL (dBm) Figure 27. Auxiliary Divider Input Sensitivity vs. Frequency and Supply Voltage (Temp = 25_C) –5 VDD = 5.00 V VDD = 3.75 V VDD = 3.00 V VDD = 2.70 V –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 0 5 10 15 20 25 30 35 40 45 50 55 60 65 I TOTAL (mA) 12 11 10 +85_C +25_C –40_C 9 4 4.5 5 5.5 6 SUPPLY VOLTAGE (V) SR01854 Figure 31. Current Supply Over VDD 1999 Nov 04 –25 –30 –35 –40 –45 –50 –55 5 10 15 20 25 30 35 40 45 50 55 60 65 Figure 30. Reference Divider Input Sensitivity vs. Frequency and Temperature (VDD = 3.00 V) 13 3.5 –20 70 SR01891 Figure 29. Reference Divider Input Sensitivity vs. Frequency and Supply Voltage (Temp = 25_C) 3 –15 FREQUENCY (MHz) SR01890 2.5 Temp = –40_C Temp = +85_C Temp = +25_C –10 0 70 FREQUENCY (MHz) 2 0 –5 16 Philips Semiconductors Product specification 2.5GHz low voltage fractional–N dual frequency synthesizer TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm 1999 Nov 04 17 SA8026 SOT360-1 Philips Semiconductors Product specification 2.5GHz low voltage fractional–N dual frequency synthesizer SA8026 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 11-99 Document order number: 1999 Nov 04 18 9397 750 06567