INTEGRATED CIRCUITS SA1630 IF quadrature transceiver Product specification IC17 Data Handbook 1998 Jul 21 Philips Semiconductors Product specification IF quadrature transceiver SA1630 • Internal IF PLL for synthesizing the local IF oscillator signal. • Bandwidth of baseband Tx inputs is 20 MHz and that of baseband DESCRIPTION The SA1630 is a 70–400 MHz I/Q transceiver for wireless LAN. The Receive Path contains a digitally gain controlled linear IF amplifier, a pair of quadrature down conversion mixers and a pair of baseband amplifiers. The transmit path contains a pair of quadrature up conversion mixers that transposes a quadrature baseband input signal up to IF frequency. An external VCO signal is divided internally and provides quadrature local oscillator signals for the mixers. Another divider chain, reference divider and phase detector are provided to avoid the need for an external synthesizer. To keep power consumption to a minimum the transmit, receive and local oscillator functions can be powered down under digital control. Rx outputs is 8.5MHz. • Designed for IEEE 802.11 wireless LAN using Direct Sequence Spread Spectrum modulation. • Control registers power up in a default state. • Only a standard reference input frequency required, choice of 8, 11, 22 or 44 MHz. • Digital gain control of 70 dB in steps of 2 dB. • Rx Baseband amplifiers are capable of driving 1k ||15pF • Rx Baseband o/p’s clamp symmetrically, above 1Vp–p in order to FEATURES • Low supply voltage operation of 2.7V for main chip and 2.9V for prevent dc bias shift under overdrive conditions. charge pump. • Package: LQFP–48, PCMCIA compatible • Low current consumption: 33.5 mA in RX, 26.5 mA in TX, typical at 3V. • Flexible power up/down options. • Optional 2.5V regulated reference voltage available during APPLICATIONS • IF circuitry for IEEE 802.11 DSSS wireless LAN. • Applications for high speed wireless data. transmit. • Input IF frequency range of 70–400 MHz. 48 47 46 45 44 43 42 I REF VCC TxRx V REF 2.5 GNDTxRx GNDTxRx IFOUT TxIFOUTX Tx GNDRX RxIF INX RxIF IN GNDRx GNDRx BE Package 41 40 39 38 37 36 VCC Rx 1 GNDCP 35 CP VCC Rx 3 34 V CC CP PLL_ON 4 33 DATA 5 32 CLOCK GNDRX 2 Rx_ON GNDHDR 6 GC0 7 GC1 8 GC2 9 GC3 10 GC4 11 GC5 12 31 STROBE 30 LOCK 29 LO_INX 28 LO_IN 27 GNDRx 26 CLK IN 25 CLK INX GNDDIG Tx_ON VCC _DIG Q_Tx IN Q_Tx INX I_Tx_INX I_Tx_IN I_RXOUT Q_RxOUT VCC _BB GND_BB GND_BB 13 14 15 16 17 18 19 20 21 22 23 24 SR01549 Figure 1. Pin Configuration ORDERING INFORMATION DESCRIPTION 48–Pin Plastic Low Profile Quad Flat package 1998 Jul 21 2 TEMPERATURE RANGE ORDER CODE DWG # –40 to +85°C SA1630BE SOT313–2 853–2049 19763 Philips Semiconductors Product specification IF quadrature transceiver SA1630 (4) (1,3) (38) VREF 2.5 PLL–ON VCCRX (39) VCCTXRX GND_BB (5) RXON 2.5V REGULATOR VCC_BB MODE CONTROL (23) TxON (13, 14) (15) I_Tx IN (18) I_Tx INX (43) (42) TxIFOUT (19) TxIFOUTX Q_Tx IN (20) Q_Tx INX (7) GC0 (8) (9) GC1 GC2 I_RxOUT 1 (21) (17) (46) RxIFIN (45) RxIFINX (10) GC3 (11) GC4 (12) GC5 (28) (29) (34) Q_RxOUT 1 LO IN ÷2 LO INX BUFFERS VCCCP ÷N DAC (35) (37) (30) CP IREF CHARGE PHASE SYNTH PUMP DETECTOR REGISTER GND HDR LOCK GNDTXRX GNDCP (36) (16) ÷ 8, 11, 22, 44 CLKIN (26) (6) (40, 41) SERIAL TEST REGISTER INPUT CLKINX (25) VCCDIG (22) GND DIG (24) DATA CLOCK STROBE (33) (32) (31) GND RX (2, 27, 44, 47, 48) SR01551 Figure 2. 1998 Jul 21 Block Diagram 3 Philips Semiconductors Product specification IF quadrature transceiver SA1630 PIN DESCRIPTIONS Pin No. Pin Name Description 1, 3 VCCRx Supply Pin for Rx section (IF circuits) 2, 27, 44,47, 48 GNDRx Ground pins for Rx section (IF circuits) 4 PLL_ON One of the three digital CMOS logic control inputs to the mode control section 5 Rx_ON One of the three digital CMOS logic control inputs to the mode control section 6 GNDHDR Substrate ground 7 GCO Control bit 0 for IF VGA gain control, CMOS input 8 GC1 Control bit 1 for IF VGA gain control, CMOS input 9 GC2 Control bit 2 for IF VGA gain control, CMOS input 10 GC3 Control bit 3 for IF VGA gain control, CMOS input 11 GC4 Control bit 4 for IF VGA gain control, CMOS input 12 GC5 Control bit 5 for IF VGA gain control, CMOS input 13, 14 GND_BB Ground pin for Rx baseband circuits 15 VCC_BB Supply Pin for Rx Baseband circuits 16 Q_RXOUT Quadrature–phase Rx baseband output, single–ended 17 I_RxOUT In–phase Rx baseband output, single–ended 18 I_Tx IN In–phase differential Tx baseband input, positive 19 I_Tx INX In–phase differential Tx baseband input, negative 20 Q_Tx IN Quadrature differential Tx baseband input, positive 21 Q_Tx INX Quadrature differential Tx baseband input, negative 22 VCC_DIG Supply for digital circuits 23 Tx_ON One of the Three digital CMOS logic control inputs to the mode control section 24 GNDDIG Digital ground 25 CLK INX Differential reference input for synthesizer, negative 26 CLK IN Differential reference input for synthesizer, positive 28 LO_IN Differential LO input,positive 29 LO INX Differential LO input, negative 30 LOCK Test control output and synthesizer lock indicator 31 STROBE Serial bus strobe input 32 CLOCK Serial bus clock input 33 DATA Serial bus data input 34 VCCCP Supply for charge pump circuits 35 CP Charge pump output 36 GNDCP Ground for charge pump circuits 37 IREF Charge pump reference current 38 VREF2.5 Reference voltage of 2.5V available for external use 39 VCCTxRx Supply pin used by Tx circuits 40,41 GNDTxRx Ground pins used by Tx circuits 42 TxIFOUTX Differential transmitter IF output (open collector), positive 43 TxIFOUT Differential transmitter IF output (open collector), negative 45 RxIF INX Differential receiver IF input, negative 46 RxIF IN Differential receiver IF input, positive 1998 Jul 21 4 Philips Semiconductors Product specification IF quadrature transceiver SA1630 ABSOLUTE MAXIMUM RATINGS SYMBOL VCCXX PARAMETER VIN Voltage applied to any other pin ∆VG Any GND pin to any other GND pin PD RATING UNITS -0.3 to +6.0 V -0.3 to VCCXX+0.3 V 0 V mW Supply voltages Power dissipation, TA = 25°C (still air) 300 TJMAX Maximum operating junction temperature 150 °C PMAX Maximum power input/output +20 dBm TSTG Storage temperature range –65 to +150 °C RECOMMENDED OPERATING CONDITIONS SYMBOL VCCXXXX VCCCP TA RATING UNITS Supply voltages: PARAMETER 2.7 to 3.6 V Charge pump supply voltage 2.7 to 3.6 V Operating ambient temperature range -40 to +85 °C NOTES: 1. There are no ESD protection diodes between pins 42, 43 and VCC to allow higher AC peak voltage. The ESD protection level has thus been reduced. Proper ESD handling precautions should be followed. MODE CONTROL NO: PLL_ON RX_ON TX_ON STATE DESCRIPTION MODE 2.5V REF 1 0 X X SLEEP mode SLEEP Off 2 1 0 1 Synthesizer ON, Rx STDBY, Tx OFF WAIT Off 3 1 1 1 Synthesizer ON, Rx STDBY, Tx ON TRANSMIT On 4 1 1 0 Synthesizer ON, Rx ON, Tx OFF RECEIVE Off 5 1 0 0 Synthesizer ON, Rx OFF, Tx ON TRANSMIT Off ’0’ – LOGIC LOW ’1’ – LOGIC HIGH ’X’ – DON’T CARE In this mode everything is switched off except the 3–wire digital bus. As long as the digital supply is still on, the programmed values are active and the 3–wire bus will continue to be programmable. except for the bias and baseband circuits needed to hold the baseband output voltages in the active state. This mode is useful if the Rx baseband outputs are AC coupled via a large capacitor and the application demands quick turn–on for the Rx, from Tx. 2. Wait Mode (Tx Off, Rx Standby) 4. Receive Mode (Tx Off) PLL is on. Receiver is in the reduced current standby mode and the transmitter is completely switched off. This mode maybe useful if the PLL is to be kept on and is waiting for a quick turn–on to either transmit or receive modes, especially when Rx outputs are AC coupled. The Transmitter is completely shut–off. The PLL and receiver sections are operating. 1. Sleep mode (PLL OFF, Rx OFF, Tx OFF) 5. Transmit Mode (Rx OFF) PLL and Transmit sections are on. However, the Receiver is completely shut–down. This mode is useful if the Rx baseband outputs are DC coupled to the external world. 3. Transmit mode (Rx standby) The PLL and transmitter are on. The receive section is in a reduced current mode wherein most of the Rx circuitry is powered down 1998 Jul 21 5 Philips Semiconductors Product specification IF quadrature transceiver SA1630 RX VGA CONTROL TABLE GC5 GC4 GC3 GC2 GC1 GC0 DECIMAL NUMBER REDUCTION FROM Gmax 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 –2 0 0 0 0 1 0 2 –4 0 0 0 0 1 1 3 –6 0 0 0 1 0 0 4 –8 0 0 0 1 0 1 5 –10 0 0 0 1 1 0 6 –12 0 0 0 1 1 1 7 –14 0 0 1 0 0 0 8 –16 0 0 1 0 0 1 9 –18 0 0 1 0 1 0 10 –20 0 0 1 0 1 1 11 –22 0 0 1 1 0 0 12 –24 0 0 1 1 0 1 13 –26 0 0 1 1 1 0 14 –28 0 0 1 1 1 1 15 –30 0 1 0 1 1 1 23 –32 0 1 1 0 0 0 24 –34 0 1 1 0 0 1 25 –36 0 1 1 0 1 0 26 –38 0 1 1 0 1 1 27 –40 0 1 1 1 0 0 28 –42 0 1 1 1 0 1 29 –44 0 1 1 1 1 0 30 –46 0 1 1 1 1 1 31 –48 1 1 0 1 0 0 52 –50 1 1 0 1 0 1 53 –52 1 1 0 1 1 0 54 –54 1 1 0 1 1 1 55 –56 1 1 1 0 0 0 56 –58 1 1 1 0 0 1 57 –60 1 1 1 0 1 0 58 –62 1 1 1 0 1 1 59 –64 1 1 1 1 0 0 60 –66 1 1 1 1 0 1 61 –68 1 1 1 1 1 0 62 –70 1998 Jul 21 6 Philips Semiconductors Product specification IF quadrature transceiver SA1630 DC ELECTRICAL CHARACTERISTICS VCCXXX=+3V; VEEXXX = 0V; TA=25°C, unless otherwise stated. SYMBOL PARAMETER ICC–4 Supply Current, Receive (mode #4) ICC–2 Supply Current, Wait (mode #2) ICC–3 Supply Current, Transmit (mode #3) ICC–1 Supply Current, Sleep mode (mode #1) ICC–5 Supply current transmit (mode 5) VREF_2.5 ZOUT_VREF Reference voltage (mode 3, enabled) Output impedance of reference voltage TEST CONDITION LIMITS MIN UNITS TYP MAX PLL_ON=Rx_ON=Hi Tx_ON = Low 33.5 41.5 mA Wait mode (2) PLL_ON = Hi Tx_ON = Hi Rx_ON = Low 17 23 mA PLL_ON = TX_ON = Hi RX_ON = Hi 26.5 34.5 mA PLL_ON = Low RX_ON = DC TX_ON = DC 0.012 0.1 mA PLL_ON = Hi TX_ON = RX_ON = Low 22 28.5 mA Load = 1.5mA 2.5 V ∆I = 1.4 to 1.6mA 15 CMOS LOGIC INPUTS (DATA, CLOCK, STROBE) VIH Input logic 1 level 2.0 VCCD VIL Input logic 0 level 0 0.8 V V II Input logic current 1 µA CI Input logic capacitance 4 pF CMOS Logic output (LOCK) VOH Output logic 1 level IO = –2mA VOL Output logic 0 level IO = 2mA VCCD–0.4 V 0.4 V V CMOS Logic Inputs (PLL_ON, RX_ON, TX_ON) VIH Input logic 1 level 2.0 VCCTXRX VIL Input logic 0 level 0 0.8 V II Input logic current 1 µA 1998 Jul 21 7 Philips Semiconductors Product specification IF quadrature transceiver SA1630 AC ELECTRICAL CHARACTERISTICS IF TRANSMIT MODULATOR (Mode #3, Tx ON Rx Standby) VCCXXX = +3V; GNDXXX = 0V; LO_in = 100 mV peak at 704 MHz, CLKin = 100mV peak at 22 MHz, Tamb = 25°C, unless otherwise stated. SYMBOL BW4,5 VIN PARAMETER Input modulation bandwidth Input signal amplitude, Differential1 TEST CONDITION 500 ohms source impedance LIMITS MIN TYP 22 1 Third harmonic distortion5 Input signal amplitude = 1 VPP, 8 MHz, VCM = 1.5 –55 RINTx Input resistance Between pins I_TXIN, I_TXINX Q_TXIN, Q_TXINX 98 CINTx4 Input Capacitance Between pins I_TXIN, I_TXINX Q_TXIN, Q_TXINX Minimum Tx output DC voltage IO DC CS SBS G4 tON 4 TOFF4 Mean output DC current VCC–0.3 At TXIFOUT and TXIFOUTX 2 Mismatch at TXIFOUT and TXIFOUTX Output current available2 At TXIFOUT and TXIFOUTX Vpp –45 dBc kΩ 2 VIN = IVPP VCMI = VCMQ = VCC/2 Output current DC offset4 UNITS MHz Voltage common mode = 1 to 2V THD_3 MAX pF V 2.75 40 mA µA 0.475 mA rms Output differential voltage1,2 400 Ω tuned load2 190 mV rms Carrier suppression1,3 Differential output 30 36 dBc SB Suppression 1,3 fOUT = 352 MHz 35 47 dBc Noise floor offset = 10 MHz 156 dBc/Hz Gain stability6 0.5 2.0 dB Turn–on time TX_ON, RX_ON transition to transmit signal at 90% level 4 µs Turn–off time TX_ON, RX_ON transition to transmit signal at 10% level 4 µs NOTES: 1. Tx inputs are differential sine wave, 0.5 V peak, with quadrature relationship between I and Q Tx input. The output spectrum will be SSB. The tone is at a frequency of 1 MHz. 2. The output current in each arm is the same but 180 degrees out of phase with each other. Also the tuned load of 400 ohms differential, is assumed. The power delivered to 400 ohms will be –10.4 dBm (typ.). The output current measurement is indirect based on output power measurement according to P = 10 log I2rms (400)/IMV. See typical performance characteristic curve. 3. This is measured with respect to the SSB output. 4. Guaranteed by design and or characterization but not final tested. 5. The input bandwidth may be verified by measuring the output THD and signal level using a DSB spectrum where I = Q. 6. Measured over temperature and supply. 1998 Jul 21 8 Philips Semiconductors Product specification IF quadrature transceiver SA1630 AC ELECTRICAL CHARACTERISTICS IF RECEIVER DEMODULATOR (Mode #4, Rx_ON, Tx_OFF) VCCXXX = +3V = GNDXXX = 0V; LO IN = 100 mVpeak at 704 MHz, CLKIN = 100mVpeak, at 22 MHz, Ta = 25°C, unless otherwise stated. SYMBOL RInRx VG NF PARAMETER Differential input impedance Voltage gain Input noise figure1 TEST CONDITION LIMITS MIN fIN = 352 MHz AGC at maximum gain 81 VGA at maximum gain AGC range 67 AGC step size TYP kΩ||pF 88 dB 7.5 dB 70 dB 2 any AGC step Channel matching gain phase Output DC offset between IRx Out and QRx Out OVS Output voltage swing Maximum Gain, Output at 1 MHz Total Harmonic Distortion BW5 Rx Bandwidth 4 tOFF4 tON dB 200 nS dB deg 6 mV Vp–p AGC GMIN, into load2 0.9 1.15 1.0 1.4 1.9 Output impedance THD3 dB 2 0.1 0.25 AGC Gain, except GMIN Output common mode voltage Max. Gain, rated output at 1 MHz 7 UNITS 6.6K||0.7 AGC differential error AGC settling time MAX V 7 Ω 3 % 10 MHz Turn–on time RX_ON, TX_ON transition to baseband signal out 8.5 2 µs Turn–off time RX_ON, TX_ON transition to no baseband signal out 2 µs NOTES: 1. The Receive input is to be differential (using a balun or a differential source such as a differential SAW filter) and matched to external generator’s impedance (ex: 50 ohms). The balun may or may not provide any impedance transformation depending on availability. An external L–C matching circuit can provide the rest of the impedance transformation and absorb the input capacitance of the receiver input. Such a differential input scheme is mandatory to avoid pickup, and keep the noise figure low. A shunt resistor across the input (value TBD) will be used to set the input impedance as a compromise between the matching ease in production versus the noise figure of the receiver. The system board layout has to keep the isolation between the receive inputs and the LO signal as high as possible. Otherwise the LO leakage will overload the receiver. 2. The load is 1000 ohms in parallel with 15pF of capacitor. 3. THD is total harmonic distortion. We measure harmonics 2, 3, 4. 4. Guaranteed by design. 5. 3dB bandwidth relative to a passband measurement taken at 1MHz. 1998 Jul 21 9 Philips Semiconductors Product specification IF quadrature transceiver SA1630 AC ELECTRICAL CHARACTERISTICS IF SYNTHESIZER VCCXXX = RX_ON = TX_ON = PLL_ON = +3V, VEEXXX = 0V; LO_IN = 100 mVpeak at 704 MHz, CLKIN = 100mVpeak at 22 MHz, Ta = 25°C, unless otherwise stated. SYMBOL fLO PARAMETER TEST CONDITION Local oscillator input frequency range3 Differential input impedance Between LO_IN and LO_INX VLOIN LO input sensitivity4 Single ended Referred to 50Ω ZCLKIN Reference clock maximum frequency3 1 fCMAX Phase detector maximum comparison freq Between ClkIN and ClkINX Referred to 50Ω MHz Ω||pF 350 mVpk 511 50 44 MHz 10|| 1.0 kΩ pF 200 400 mVpk 1 MHz Ref Divider = 44 2.5 MHz REXT = 50KΩ 31.25 µA IREF Charge pump reference current |ICP| Charge pump output current: C0...C2 = 000 C0...C2 = 111 step size IREF = 31.25 µA VCP = VCCCP/2 ICP ICP Relative output current variation1 IREF = 31.25 µA Output current matching2 IREF = 31.25 µA VCP = VCCCP/2 ICP_M UNITS 1 CLK input sensitivity4 fCMIN 800 50 64 Phase detector minimum comparison frequency MAX. 276||0.6 Programmable divider: division range step size Differential input impedance TYP 140 ZLOIN fCLK LIMITS MIN 0.160 0.320 0.023 0.200 0.400 0.029 0.240 0.480 0.035 mA mA mA 1.3 8 % 12 % 15 nA Output leakage current 0.2 Output current tolerance with temperature with output voltage 1 5 % Serial Interface3 fCLOCK Clock frequency 10 MHz tSU Set–up time; DATA to clock, CLOCK to STROBE 30 ns tH Hold time: CLOCK to DATA 30 ns Pulse width: CLOCK 30 ns Pulse width: STROBE 30 ns tW NOTES: 1. The relative output current variation is defined thus: I OUT 2 I OUT . I 2 – I 1 II 2 1 1 ; WITH V 1 0.7V, V 2 V CCCP – 0.8V (see Figure 3). 2. The output current matching is measured when both (positive current and negative current) sections of the output charge pumps are on 3. Guaranteed by design. 4. Maximum level guaranteed by design. 1998 Jul 21 10 Philips Semiconductors Product specification IF quadrature transceiver SA1630 The baseband amplifiers can interface directly to the Track/Hold switch/capacitor combination with capacitance values up to 15 pF. When sampled at 22MHz the output can settle to within 1/4 LSB when swinging 1V p–p. CURRENT I2 I1 The chip has a unique mode in which the Rx is on standby while the Tx is ON. In this mode the Rx Baseband circuits are idling at reduced currents and all Rx I/O outputs retain their DC bias unchanged from their values when the Rx was fully ON. This mode is very essential if ac coupling through a large capacitor, such as, 10nF is used. From this mode the chip can quickly be switched to the Rx ON mode (Tx OFF) without worrying about charging/discharging the large AC coupling capacitor. VOLTAGE V1 V2 I2 I1 The VGA can be programmed in 2 ways: 1) Directly programming external control pins. 2) programming over the serial 3–wire bus. The former method can switch gain in less than 200 ns. SR00526 Figure 3. Relative Output Current Variation APPLICATION DESCRIPTION The Rx baseband section also incorporates simple low pass active filters of the Sallen key type. The Rx bandwidth is mainly set by these filters. The function of these filters is twofold: 1) attenuate high frequency signals from the Rx mixers. 2) act as anti–aliasing filters for any A to D converters following this chip. General IF synthesizer The 1630 performs the IF modulator and demodulator functionality for high–speed wireless data transceivers. The design is optimized for IEEE 802.11 wireless LAN using 11 chips/symbol Direct Sequence Spread Spectrum. The SA1630 has an integrated synthesizer that uses an external VCO operating on twice the IF frequency. It is internally divided by 2 for obtaining quadrature signals. The divided VCO signal is not externally available. This minimizes the LO feedthrough to the IF input port and hence minimizes output dc glitches when the IF gain is switched. Transmitter The IF quadrature transmitter baseband modulator input is driven differentially by the D/A converters in the DSP chip. The baseband signals are DC coupled for fast turn–on and turn–off and for constant carrier testing. The typical common–mode input voltage is VCC/2. The open collector outputs of the mixers are biased by two inductors, which are part of an LC tank. The LC tank matches the output impedance of the mixers to the input impedance of the upconverter chip (or any filter in between) and suppresses IF harmonics. The PLL reference clock is derived from the 22 MHz DSP clock. The available divider ratios facilitate both 1 and 2 MHz phase comparison frequency from a 22 MHz and an optional 44 MHz clock respectively. In essence the reference divider will have programmable dividers ratios of 8, 11, 22 and 44. The VCO shall be fed from a stabilized supply. Such a stabilized supply is necessary in order to prevent oscillator jitters due to Rx/Tx switching. The effect of oscillator jitters is further minimized when using a high PLL loop bandwidth, which on its turn requires a high phase comparison frequency (1 MHz, preferably 2 MHz). An optional 2.5V reference is available during mode (3) and (5), the transmit mode with Rx in standby. This reference can be enabled or disabled via the 3 wire bus (in this mode). This voltage is provided for use by an external current DAC if needed. If the IF Synthesizer is not used, the CLKIN pins should be terminated to ac ground. Serial Programming Input Receiver The serial input is a 3–wire input (CLOCK, STROBE, DATA) to program the counter ratios, charge pump current, status– and DC–offset register, mode select and test register. The programming data is structured into two 21–bit words; each word includes 4 chip address bits and 1 subaddress bit. Figure 2 shows the timing diagram of the serial input. When the STROBE = L, the clock driver is enabled and on the positive edges of the CLOCK the signal on DATA input is clocked into a shift register. When the STROBE = H, the clock is disabled and the data in the shift register remains stable. Depending on the value of the subaddress bit the data is latched into different working registers. Table 3 shows the contents of each word. The receiver part of the SA1630 consists of an IF Variable gain amplifier, a quadrature demodulator and a pair of baseband amplifiers. The IF amplifier has its gain controlled by the DSP chip. This ensures linear operation of the receiver chain over a wide dynamic range of input signals. Linear operation is essential for resolving echo’s due to multipath reception. The digital controlled AGC is meant for fast level training for the receiver. The high gain receiver, which is distributed between the IF and baseband part facilitates interfacing with the RF front–end chip, which normally have moderate gains (up to 20 dB), and SAW IF filters, which mostly have considerable loss (up to 8 dB) without external amplifiers. Default States Upon power up (VCCDIG is applied) a reset signal is generated, which sets all registers to a default state. The logic level at the The baseband amplifiers have a high drive capability (1 Vpp into 1kΩ, 15 pF for VCC = 3V) that facilitates direct interfacing to the A/D converter without active external elements. 1998 Jul 21 11 Philips Semiconductors Product specification IF quadrature transceiver SA1630 The current can be set to zero by connecting the pin IREF to VCCCP. STROBE pin should be low during power up to guarantee a proper reset. These default states are shown in Table 2. Charge Pumps Reference Divider The charge pumps at pin CP are driven by the phase detector and the current value is determined by the binary value of the charge pumps register CN = c2, c1, c0, default .4mA. The active charge pump current is typically: The reference divider can be programmed to four different division ratios (:8, :11, :22, :44), see registers r0, r1; default setting: divide by 22. |I CP| (c0 2c1 4c2) 29A 200A Main Divider The external VCO signal, applied to the LOIN and LOINX inputs, is divided by two and then fed to the main divider (:N). The main divider is a programmable 9 bit divider, the minimum division ratio is divide by 64. The division ratio is binary coded and set in the registers n0 to n8. The default setting is a divide by 352. Lock Detect The output LOCK is H when the phase detector indicates a lock condition. This condition is defined as a phase difference of less than ±1 cycle on the reference input CLKIN, CLKINX. At the completion of a main divider cycle, a main divider output is generated which will drive the phase detector. Test Modes (Synthesizer, Transmit Mixer) The LOCK output is selectable as a test output. Bits x0, x1 control the selection, the default setting is normal lock output as described in the Lock detect section. The selection of a Bit x0, x1 combination has a twofold effect: First it routes a divider output signal to the LOCK pin, second it disables mixer stages in the transmit path. Setting x0,1 = 11 disables both transmit path mixers. This mode can be used to prevent the transmitter from producing an IF output signal even if the transmit part is powered on. This can be used to simplify the control timing while commanding the transmit and receive simultaneously without the transmit part causing interference. Phase Detector The phase detector is a D-type flip-flop phase and frequency detector shown in Figure 5. The flip-flops are set by the negative edges of the output signals of the dividers. The rising edge of the signal L will reset the flip-flops after both flip-flops have been set. Around zero phase error this has the effect of delaying the reset for 1 reference input cycle. This avoids non-linearity or deadband around zero phase error. The flip-flops drive on-chip charge pumps. A source current from the charge pump acts to increase the VCO frequency; a sink current acts to decrease the VCO frequency. Table 1. Test Modes Current Setting The charge pump current is defined by the current set between the pin IREF and VEECP. The current value to be set there is 31.2µA. This current can be set by an external resistor to be connected between the pin IREF and VEECP. The typical value REXT (current setting resistor) can be calculated with the formula R EXT 1998 Jul 21 V CCCP–1.6V (44.87K for 3V) 31.2A Q-mixer I-mixer 0 normal lock detect on on 1 0 CLKIN divided by reference divider ratio off on 0 1 LOIN ÷ 2 * (main divider ratio) on off 1 main divider output, that goes to the phase detector off off x1 0 1 12 Transmit Mixer Synthesizer y Signal g at LOCK Pin x0 Philips Semiconductors Product specification IF quadrature transceiver SA1630 Table 2. Definition of SA1630 Serial Registers First data word: (shown with default values) Sub Adr Address SA1630 Reference Divider N-Divider Charge-Pump Test MSB LSB a0 a1 a2 a3 sa 1 1 1 0 0 Address: Sub:Address: N-Divider: Reference Divider Register: Charge-Pump Register: Test Register: n0 n1 n2 n3 n4 n5 n6 n7 n8 r0 r1 c0 c1 c2 x0 x1 1 0 1 1 0 0 0 0 0 1 0 1 1 1 0 0 4 bits, a0...a3, fixed to 1110 1 bit, sa, fixed to 0 for first data word 9 bits, n0...n8, values 64 (00100 0000) to 511 (11111 1111) allowed for IF choice, default 352 (assuming LO input frequency is 704 MHz). 2 bits, r0...r1, 00 = /8, 01 = 11, 10 = /22, 11 = /44. Default: 10 3 bits, c0...c2, Binary setting factor for charge pumps, values 000 = minimum current to 111 = maximum current, default is maximum charge pump current (111) 2 bits, x0...x1, default 00, see functional description for details Second data word: (shown with default values) Sub Adr Address SA1630 LLL Mode Control Q Offset Register I Offset Register Misc Control bits VGA Gain Control MSB LSB a0 a1 a2 a3 sa s0 s1 i0 i1 i2 q0 q1 q2 b0 b1 b2 b3 b4 b5 bc vc 1 1 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 Address: Sub:Address: LLL Mode control: I Offset Register: 1 bit, sa, fixed to 1 for second data word 2 bits, s0, s1 Not used, always set to 0, 0 3 bits, i0...i2 .10 Not used, always set to 0, 0, 0 Q Offset Register: 3 bits, q0...q2. q0. Currently not being used, always set to 0, 0, 0 VGA Gain Control 6 bits, b0...b5. 000 000 corresponds to maximum gain and 111 111 to minimum gain in 2 dB increments. Check control table contained elsewhere in this document. VGA Control Enable Regulator Disable 1998 Jul 21 4 bits, a0...a3, fixed to 1110 1 bit, bc. When bc=0 the VGA is controlled by external pins. When bc=1 then bits b0...b5 control the VGA. Default bc=0, control by external pins 1 bit, Vc. When Vc=0 the 2.5V reference output is completely powered down. When Vc=1 the reference voltage is enabled (provided Tx_ON=HIGH). Default: Vc = 1, enable the 2.5 reference. 13 Philips Semiconductors Product specification IF quadrature transceiver SA1630 LSB DATA MSB X1 or t5 a1 X0 or t4 a0 tH tSU tSU 50% CLOCK FIRST CLOCK LAST CLOCK FIRST CLOCK tSU STROBE CLOCK ENABLED SHIFT IN DATA CLOCK DISABLED STORE DATA tW 50% CLOCK SR00527 STROBE Figure 4. Serial Input Timing Sequence L “1” CLKIN REFERENCE DIVIDER D Q C VCCCP R R P P-TYPE CHARGE PUMP “1” LOIN ÷2 MAIN DIVIDER D CP R C X N-TYPE CHARGE PUMP Q N VSS CLKIN L R X P N ICP SR00528 Figure 5. 1998 Jul 21 Phase Detector Structure with Timing 14 Philips Semiconductors Product specification IF quadrature transceiver SA1630 10m 1 100n VCCRx GNDRX GNDRx GNDRX 2 3V SUPPLY 48 47 1.8p 3 VCCRx RxIF IN 46 100n 4 PLL_ON RxIF INX Rx_ON GNDRX 45 RxIN 5K 44nH PLL_ON 5 1n Rx_ON 6 1n 7 GC0 TxIFOUT 8 GC1 9 GC2 GNDTxRx GC3 VCCTXRX 10 GC3 11 GC4 12 GC5 TxOUT 294 294 GC0 GNDTxRx GC2 17.4 43 GNDHDR TxIFOUTX GC1 1.8p 44 42 41 1n 40 39 I0n 20Ω 38 GC4 VREF2.5 GC5 IREF 37 36 VREF 10n 13 GND_BB GNDCP 14 GND_BB CP 15 VCC__BB VCCCP 100n 16 15P 15P CP 34 100n DATA 33 CLOCK 32 STROBE 31 LOCK 30 LO INX 29 Q_RXOUT 1K 17 35 I_RxOUT 1K 3 WIRE SERIAL BUS LOCK 10n LO IN W 10n 18 I_TX IN I/Q GEN 1MHZ FOR SSB TESTING 19 I_Tx INX (8MHZ FOR DSB TESTING) 20 Q_Tx IN 21 Q_Tx INX LO_IN 28 GNDRx 27 CLK IN 26 CLK INX 25 GNDDIG 24 Tx_ON 22 10n 10n 23 CLKIN 50W TX_ON 1n VCC DIG 100nF SR01550 Figure 6. 1998 Jul 21 Typical SA1630 Test Circuit 15 Philips Semiconductors Product specification IF quadrature transceiver 22 SA1630 Supply Current Sleep Mode 1 Supply Current Wait Mode 2 Vs. Temperature and Supply Vs. Temperature and Supply 20 20 19 3.6 V 18 Supply Current mA Supply Current uA 18 3V 16 2.7 V 14 12 3.6 V 17 3V 2.7 V 16 15 10 –50 0 Temperature °C 50 14 100 –50 0 Supply Current Transmit Mode 3 Vs. Temperature and Supply Temperature °C 50 100 Supply Current Receive Mode 4 Vs. Temperature and Supply 30 40 29 38 28 Supply Current mA Supply Current mA 36 27 3.6 V 26 3V 25 2.7 V 24 34 3.6 V 32 2.7 V 30 23 28 22 26 –50 0 Temperature °C 50 –50 100 0 Supply Current Transmit Mode 5 Vs. Temperature and Supply Temperature °C 50 100 Receiver Third Harmonic Distortion Vs. Temperature and Supply 26 40 dB below signal with Rx input IVPP at maximum gain 38 22 Third Harmonic dB Supply Current mA 24 3.6 V 3V 2.7 V 20 36 34 2.7 V 3V 3.6 V 32 30 18 28 –50 16 –50 0 Temperature °C 50 0 50 100 Temperature °C 100 SR01601 Figure 7. 1998 Jul 21 16 Philips Semiconductors Product specification IF quadrature transceiver SA1630 Receiver AGC Gain Range Receiver Maximum Gain Vs. Temperature and Supply Vs. Temperature and Supply 100 75 90 Gain Range dB Gain dB 95 3.6 V 3V 2.7 V 3V 3.6 V 70 2.7 V 85 80 65 –50 0 50 100 –50 Temperature °C 0 50 100 Temperature °C Transmitter Carrier and Sideband Suppression Vs. Temperature and Supply Transmitter Third Harmonic Distortion Vs. Temperature and Supply –50 –30 –32 –55 Carrier Suppression 3.6 3 2.7 V Suppression dB –36 –38 Distortion dBc –34 –40 –42 –44 –46 –48 3.6 3 2.7 V Sideband Suppression –50–50 0 –60 2.7 V 3 3.6 –65 50 –70 –50 100 0 50 100 Temperature °C Temperature °C Transmitter AC Output Current Vs. Temperature and Supply P Charge Pump Current 000 Vs. Temperature and Supply 0.5 –190 Average output at 353MHz Input 1VPP Current uA Current mA –195 0.4 2.7V to 3,6 V 3.6 –200 3 2.7 V 0.3 –205 –210 –50 0.2 –50 0 Temperature °C 50 100 0 50 Temperature °C 100 SR01600 Figure 8. 1998 Jul 21 17 Philips Semiconductors Product specification IF quadrature transceiver SA1630 N Charge Pump Current 000 Vs. Temperature and Supply P Charge Pump Current 111 Vs. Temperature and Supply 205 –390 200 –400 Current uA Current uA –395 3.6 –405 3 –410 3.6 3 2.7 V 195 2.7 V –415 –420 –50 0 50 190 100 –50 Temperature °C 0 50 100 Temperature °C Charge Pump Match 111 Vs. Temperature and Supply N Charge Pump Current 111 Vs. Temperature and Supply 5 410 0 3.6 V Current uA Current uA 405 3 V 2.7 V 400 –5 2.7 V 3V 3.6 V –10 395 –15 390 –50 0 50 –50 100 0 50 100 Temperature °C Temperature °C N Charge Pump Step Size Vs. Temperature and Supply 35 P Charge Pump Step Size Vs. Temperature and Supply –25 33 Current uA Current uA –27 2.7 V –29 3V 3.6 V –31 31 29 3.6 V 3V 2.7 V 27 –33 –35 25 –50 0 50 Temperature 100 –50 C 0 50 100 Temperature °C SR01599 Figure 9. 1998 Jul 21 18 Philips Semiconductors Product specification IF quadrature transceiver SA1630 Transmitter Input Modulation Bandwidth Vs. Frequency 3.0 –21 85°C 25°C –40°C 2.8 Output Level dBm Reference Voltage V 2.5 Reference Voltage Vs. Load and Temperature 2.6 2.4 –2.0 –1.2 –0.4 0.4 1.2 2.0 –22 –23 –24 –25 –26 0 Load Current mA Vcc= 3V 4 8 RMS Output mA rms –14 Output Level dBm –16 –18 –20 –40°C –22 25°C 85°C –26 0 3 6 9 12 20 24 28 32 36 0.6 0.5 0.4 0.3 0.2 0.50 15 0.70 0.90 1.10 1.30 1.50 Single Ended Input Vpp V Output Frequency MHz Vcc= 3V Gain= –70 16 Transmitter RMS Output Current Vs. Input Voltage Receiver Filter Bandwidth Vs. Frequency and Temperature –24 12 Frequency MHz Vcc = 3V Vcc= 3V Charge Pump Relative Variation Vs. Temperature and Supply 3 Variation % Vcm – 0.7V to VCC–0.8V 2 2.7 V P Pump 1 3V 3.6 V N Pump 2.7V to 3.6V 0 –50 0 50 100 Temperature °C SR01602 Figure 10. 1998 Jul 21 19 Philips Semiconductors Product specification IF quadrature transceiver SA1630 LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm 1998 Jul 21 20 SOT313-2 Philips Semiconductors Product specification IF quadrature transceiver SA1630 NOTES 1998 Jul 21 21 Philips Semiconductors Product specification IF quadrature transceiver SA1630 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: 1998 Jul 21 22 Date of release: 07-98 9397 750 04166